Modulator

Abstract

The present application relates to an analog-to-digital converter (ADC) circuit (200). A time-coded modulator (TEM201) has: a comparator (104); a loop filter (105) configured to respond to an input signal (S IN ) and feedback signal (S FB ) generates a pulse width modulation (PWM) signal (S PWM A controlled oscillator (e.g., VCO (202)) receives the PWM signal and generates an output oscillating signal (S) having a frequency that varies based on a drive signal at a drive node (109) (e.g., a drive node of a ring oscillator (107)). OSC The controlled oscillator (202) includes at least one control switch (112) controlled by a switch control signal (S1) generated from the received PWM signal, thereby controlling the drive strength of the drive signal applied to the drive node (109). The feedback signal (S1) for the TEM (201) FB ) is derived from the controlled oscillator (202) and thus includes any timing errors between the PWM signal and the switch control signal (S1) applied to the controlled switch.

Description

Technical Field

[0001] The field of representative embodiments of the present disclosure relates to methods, apparatus, and / or embodiments relating to or associated with modulators for signal modulation, and in particular to time coded modulators, such as modulators for generating pulse width modulated signals. Background Art

[0002] Signal modulators are utilized in many applications, for example as part of the conversion from analog to digital signals (or vice versa).A time coded modulator is a modulator that encodes an input signal into a time coded data stream.

[0003] One specific form of time encoding is pulse width modulation (PWM). In a PWM signal, the input value is encoded by comparing a given output signal level (e.g., the duration or width of a pulse of a first signal level) with the duration of any period of any other signal level within a cycle. For a conventional two-level PWM signal, the input signal value can be encoded by the duty cycle of the pulse of the first signal level within the cycle (i.e., the proportion of the cycle spent at the first output signal level).

[0004] One specific application of a time coded modulator is as part of an analog-to-digital converter (ADC) having a controlled oscillator, such as a voltage controlled oscillator (VCO).

[0005] In a VCO-based ADC, an input analog signal may be used to control the VCO so that the frequency of an oscillating signal output by the VCO depends on the value of the input signal. The frequency of the oscillating signal may be determined, for example, by counting the number of cycles of the oscillating signal in a defined frame period to provide a digital output indicative of the value of the input signal. The VCO may be implemented by a relatively simple ring oscillator that is relatively low power, and thus a VCO-based ADC may be relatively efficient in terms of power requirements and circuit area compared to alternative ADC structures such as continuous-time or discrete-time sigma-delta ADCs.

[0006] However, VCOs (especially those based on ring oscillators) typically have relatively poor linearity. Therefore, if the VCO is directly controlled by an analog input signal, the resulting digital output signal may have poor linearity. Although this is acceptable for some applications, poor linearity is disadvantageous for many audio applications.

[0007] A time-coded modulator (e.g., a PWM modulator) can be used to improve the linearity of a VCO-based ADC by modulating the input analog signal into a time-coded signal that changes between two voltage states, where the value of the input signal is encoded by the relative duration of each state. The time-coded signal is then used to control the VCO. Since the VCO operates with only two input voltage levels, the output is linear in nature. The average frequency of the oscillating signal in the frame period depends on the proportion of time spent at each voltage level, and thus on the value of the input signal.

[0008] However, especially for audio applications, the demand for better static audio performance (eg, for low levels of distortion such as THD) continues to increase, and other sources of non-linearity associated with the operation of the VCO may affect the distortion performance. Summary of the invention

[0009] Embodiments of the present disclosure are directed to improved time coded modulators that alleviate at least some of these problems.

[0010] According to some embodiments, there is provided an analog-to-digital converter circuit comprising:

[0011] a time coded modulator comprising a comparator and a loop filter and configured to generate a pulse width modulated (PWM) signal in response to an input signal and a feedback signal;

[0012] a controlled oscillator configured to receive a pulse width modulated (PWM) signal and generate an output oscillating signal having a frequency that varies based on a drive signal at a drive node;

[0013] wherein the controlled oscillator comprises at least one control switch, the at least one control switch being configured to be controlled by a switch control signal so as to control the driving strength of the driving signal applied to the driving node, the switch control signal being generated by the received PWM signal;

[0014] Wherein the feedback signal for the time coded modulator is derived from the controlled oscillator and thereby includes any timing errors between a PWM signal and the switch control signal applied to the control switch.

[0015] In some embodiments, the feedback signal for the time coded modulator may be tapped from the switch control signal applied to the control switch.A buffer may be configured to receive a signal tapped from the switch control signal applied to the control switch and output the feedback signal.

[0016] In some embodiments, the feedback signal for the time coded modulator may be derived from the controlled oscillator to include an indication of any timing error between the drive signal applied to the drive node and the PWM signal. In such embodiments, the feedback signal may thereby indicate any timing error between the drive signal applied to the drive node and the PWM signal due to timing errors in the switch control signal and possibly other timing errors associated with driving the drive node.

[0017] The circuit may include a monitor for monitoring the signal level at the monitored node against a defined reference, thereby providing the feedback signal, wherein the monitored node exhibits a change in the signal level with a duty cycle corresponding to the duty cycle of the driving node. In some cases, the monitored node may be the driving node itself. However, in some embodiments, the monitored node may be some other node, such as a replica driving node for driving a load synchronously with the driving node. The monitor may include a comparator configured to compare the first signal with a reference voltage.

[0018] In some embodiments, the controlled oscillator may include a ring oscillator configured to be driven by a drive current signal at the drive node. The first current source may be configured to provide a first drive current to the drive node, and the at least one control switch may be controlled by the switch control signal to selectively connect the second current source to the drive node to provide a second drive current.

[0019] In some embodiments, the loop filter of the time-coded modulator can be configured to filter the feedback signal to provide a filtered feedback signal. In some embodiments, the comparator can be configured to compare the input signal received at the first comparator input with the filtered feedback signal received at the second comparator input. In other embodiments, the filtered feedback signal can be combined with the input signal and applied to the first comparator input of the comparator. In this case, the comparator can be configured to compare the signal at the first comparator input with a reference voltage. In some embodiments, the input signal can be applied to a first signal path of the time-coded modulator, which is coupled to the first comparator input of the comparator. A reference voltage can be applied to a second signal path of the time-coded modulator, which is coupled to the second comparator input of the comparator. The filtered feedback signal can be applied to both the first signal path and the second signal path as a differential signal.

[0020] In some implementations, the loop filter may include a first current source and a second current source controlled to source current or sink current based on the feedback signal.

[0021] In some embodiments, the comparator may be a hysteresis comparator.

[0022] The analog-to-digital converter circuit may be implemented as an integrated circuit.

[0023] The analog to digital converter circuit may be configured to receive an analog audio signal as the input signal.In some embodiments, the input node for receiving the input signal is coupled to a microphone node for receiving the analog audio signal from a microphone in use.

[0024] Embodiments also relate to an electronic device comprising an analog-to-digital converter circuit as discussed in any of the above variations. In some cases, the electronic device may include a microphone transducer, wherein the analog-to-digital converter circuit is configured to receive a signal from the microphone transducer as the input signal. An electronic device comprising an analog-to-digital converter circuit as discussed in any of the above variations, the device may be at least one of the following: a portable device; a battery-powered device; an audio device; a communication device; a mobile phone or a cellular phone or a smart phone; a computing device; a notebook computing device, a laptop computing device, or a tablet computing device; a gaming device; a wearable device; a smart watch; a voice-activated device or a voice-controlled device; an electrical appliance.

[0025] In another aspect, there is provided a time coded modulator circuit comprising:

[0026] a time coded modulator configured to generate a time coded signal based on an input analog signal and a feedback signal;

[0027] a processing module configured to receive the time-coded signal and generate at least one control signal based on the time-coded signal, wherein in at least some operating conditions of the processing module, the control signal may exhibit a timing error relative to the time-coded signal;

[0028] Wherein the feedback signal for the time coded modulator is derived from a downstream processing module such that the feedback signal includes the effects of any such timing errors.

[0029] In another aspect, there is provided a pulse width modulation (PWM) modulator, comprising:

[0030] a comparator configured to generate a PWM signal in response to an input signal and a filtered feedback signal;

[0031] An output node, used to output the PWM signal to a downstream processing module;

[0032] a feedback node, configured to receive a feedback signal from the downstream processing module; and

[0033] A loop filter is configured to receive and filter the feedback signal from the feedback node and generate the filtered feedback signal.

[0034] In another aspect, an analog-to-digital converter circuit is provided, comprising:

[0035] a time coded modulator comprising a comparator and a loop filter and configured to generate a pulse width modulated (PWM) signal in response to an input signal and a feedback signal;

[0036] a controlled oscillator configured to receive the pulse width modulated (PWM) signal and generate an output oscillating signal having a frequency that varies based on a drive signal at a drive node;

[0037] wherein the controlled oscillator comprises at least one control switch, the at least one control switch being configured to be controlled by a switch control signal so as to control a driving strength of the driving signal applied to the driving node, wherein the switch control signal is generated from the received PWM signal;

[0038] wherein the feedback signal for the time coded modulator is derived from the controlled oscillator thereby including any delay between signal transitions of the PWM signal and corresponding signal transitions of the switch control signal applied to the control switch.

[0039] Any of the various features of the various embodiments discussed herein may be implemented with any one or more of the other described features, in any suitable combination, unless explicitly indicated to the contrary. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] For a better understanding of the embodiments of the present disclosure, and to more clearly show how these embodiments may be effectively carried out, reference will now be made, by way of example only, to the accompanying drawings, in which

[0041] In the figure:

[0042] Figure 1 An embodiment of an ADC with a TEM and a VCO is illustrated;

[0043] Figure 2 An ADC with a TEM and a VCO according to one embodiment is illustrated;

[0044] Figure 3 Another embodiment of an ADC with a TEM and a VCO is illustrated;

[0045] Figure 4 One embodiment of a suitable TEM is illustrated;

[0046] Figure 5 Another embodiment of a suitable TEM is illustrated;

[0047] Figure 6 A TEM with adaptive cycle frequency control is illustrated; and

[0048] Figure 7 A TEM with pseudo differential input is illustrated. DETAILED DESCRIPTION

[0049] The following description sets forth example embodiments according to the present disclosure. Other example embodiments and implementations will be apparent to those of ordinary skill in the art. In addition, those of ordinary skill in the art will recognize that a variety of equivalent technologies may be applied in place of or in conjunction with the embodiments discussed below, and all such equivalents are considered to be encompassed by the present disclosure.

[0050] Embodiments of the present disclosure relate to a time coded modulator (TEM), and in particular to a PWM (pulse width modulation) modulator. Some embodiments also relate to a signal processing circuit including such a time coded modulator (TEM), such as an ADC (analog to digital converter) based on a controlled oscillator. In embodiments of the present invention, a time coded signal output from the TEM is used to generate at least one control signal to control a downstream component, and a feedback signal for the TEM is derived, the feedback signal representing the timing of the control signal, such as being tapped from a node to which the control signal is applied or otherwise responsive to the control signal.

[0051] As described above, one application of a time coded modulator, specifically a two-level PWM modulator, is for use in the input stage of a controlled oscillator based ADC.

[0052] Figure 1 One embodiment of an ADC 100 having a controlled oscillator driven by a TEM is generally illustrated. Figure 1 The input signal S is shown as an example. IN is received by TEM 101, which in this case is used to generate a two-level PWM signal S PWM The PWM modulator, the two-level PWM signal S PWM Based on the input signal S INThe duty cycle of the PWM signal S PWM is input to a controlled oscillator 102, which in this case is a VCO 102, which depends on the PWM signal S PWM The level of the output oscillation signal S OSC , the oscillation signal S OSC The downstream decoder (such as the counter 103) may be arranged to detect the oscillation signal S OSC The number of pulses or signal transitions in the input signal S is counted (e.g., within a series of defined frame periods) to provide an indication of the input signal S IN The value of the digital output D OUT .

[0053] The TEM 101 is arranged as a self-oscillating modulator having a comparator 104 and a loop filter 105. The comparator 104 may be, for example, a hysteresis comparator, such as an operational amplifier comparator configured to provide hysteresis, as will be understood by those skilled in the art. Figure 1 In the embodiment illustrated in FIG. 1 , the TEM 101 is arranged so that the input signal S IN The feedback signal S is applied to the first comparator input of the hysteresis comparator 104 and tapped from the output of the hysteresis comparator 104. FB The feedback signal S is filtered by the loop filter 105. FB ' is applied to the second comparator input of the hysteresis comparator 104. In this case, the loop filter 105 may include a passive low-pass RC filter, although other filter arrangements may be implemented, as will be described in more detail later. However, in some cases, the filtered feedback signal S FB 'With the input signal S IN The combined signal is applied to the input of the hysteresis comparator 104 and compared with a reference value (which may be supplied exclusively to another comparator input of the hysteresis comparator 104 or defined by the structure of the hysteresis comparator 104). Such a TEM 101 may be implemented as a small size and low power PWM modulator, which is advantageous in some applications. However, other forms of TEM 101 may be used. For example, in some embodiments, the TEM 101 may include a more conventional asynchronous Σ-Δ modulator (ASDM). As will be appreciated by those skilled in the art, in a conventional ASDM, the input signal S IN Usually with the feedback signal S FB The combined input / feedback signal is input to a loop filter 105 including at least one integrator.

[0054] In any case, the feedback signal S FBUsually, the output of the comparator 104 (ie, the PWM signal S output by the receiving hysteresis comparator 104) is PWM The hysteresis comparator 104 responds to the input signal S IN and feedback signal S FB These two generate a duty cycle along with the input signal S IN The level of the output PWM signal S changes PWM Therefore, in TEM101, the PWM signal S output from TEM101 is PWM Internally tap the feedback signal S FB .

[0055] The PWM signal S output from the TEM 101 PWM is supplied as an input to the VCO 102 for controlling the switching of the VCO 102 to generate an oscillation signal S OSC In some embodiments, the VCO 102 includes a ring oscillator 107, for example, having a plurality of inverters 108 connected in series in a ring configuration, and having a circuit for providing an oscillation signal S OSC The drive strength of the inverter 108 and thus the propagation delay associated with each inverter is controlled by the drive signal at the drive node 109. The received PWM signal S PWM It is used to control the switching of the driving node 109 between two different driving strengths.

[0056] In some embodiments, the ring oscillator 107 may include a current controlled oscillator (ICO), and the PWM signal S PWM is used to control the switching of the driving current supplied to the driving node 109, thereby controlling the output oscillation signal S OSC For example, the driving node 109 may be arranged to be continuously driven by the first current source 110, and the PWM signal S PWM can be used to depend on the PWM signal S PWM The state of the PWM signal S can be used to selectively control whether the second current source 111 contributes to the current at the driving node 109. PWM To switch at least the first control switch 112 to selectively connect the second current source 111 to the driving node. Figure 1 In the embodiment illustrated in FIG. 1 , the second control switch 113 is also switched in anti-phase with the first control switch 112, thereby providing an alternative path for the current from the second current source 111, such as diverting the current to ground, when the second current source 111 is not used to provide current to the drive node 109. Figure 1As illustrated in the figure, the first control switch 112 and the second control switch 113 can be driven by corresponding switch drivers. In this embodiment, the corresponding switch drivers include a buffer / driver 114 and an inverter / driver 115. The buffer / driver 114 and the inverter / driver 115 are arranged to generate buffer control signals S1 and S2 with suitable polarities for driving the first control switch 112 and the second control switch 113.

[0057] Therefore, depending on the received PWM signal S PWM The ICO ring oscillator 107 may be driven by the driving current from the first current source 110 alone or by the combined driving current from the first current source 110 and the second current source 111. In some embodiments, the current output from the second current source 111 may be significantly higher than the current output from the first current source 110, thereby providing a high level of PWM signal S for the received ICO ring oscillator 107. PWM The two states provide significantly different output frequencies. The output oscillation signal S generated by the ICO ring oscillator 107 is OSC The output of the VCO 102 can be sent to the counter 103. The counter 103 counts the oscillation signal S in each of the consecutive counting cycles. OSC The number of oscillations is counted and a digital output D is generated based on the count value. OUT .

[0058] Such an arrangement can provide a relatively low power and small size ADC circuit with good audio performance.By driving the ring oscillator with only two drive current strengths and controlling the average time spent at each frequency, the nonlinearity of the ring oscillator 107 in the relationship between output frequency and drive current strength is mitigated.

[0059] However, there is a growing demand for better distortion performance, especially for audio applications.

[0060] An additional source of possible error and thus distortion comes from non-linearities associated with the operation of the first control switch 112 and / or the second control switch 113. Figure 1 In the embodiment illustrated in FIG. 1 , based on the PWM signal S PWM , driving the first control switch and the second control switch through corresponding switch drivers 114 and 115. However, the control switches have associated capacitances, such as Figure 1 The capacitor C shown in FIG. 1 as illustrated together with the first control switch 112 P The parasitic capacitance represented by (a similar capacitance will also be associated with the second control switch 113, but for the sake of clarity, Figure 1 omitted).

[0061] The effect of such a capacitor may be the PWM signal S PWM The timing error is introduced between the generated switch control signal (for example, S1), that is, the duty cycle of the switch control signal is different from that of the PWM signal S PWM For example, the asymmetric drive strength encountered when driving these switch capacitances high or low may result in differences between the rising and falling edges of the gate voltage of the control switch. That is, the slew rate of the gate voltage of the control switch may be different when transitioning from low to high than when transitioning from high to low. In practice, this may introduce a delay between the transition of the PWM signal output from TEM 101 and the corresponding transition of the switch control signal, where the delay for the transition from high to low varies compared to the delay for the transition from low to high. This can be seen as a difference in the PWM signal S PWM An error is introduced in the duty cycle of the compared switch control signals, or an error is introduced in the timing fidelity of the switch control signals.

[0062] Such timing errors in the switch control signals applied to the control switches may result in errors in the timing of applying drive currents of different strengths to the drive node 109. This effect may therefore result in a timing error with respect to the proportion of time that the drive node 109 is driven by a high strength drive current compared to a low strength drive current, thus causing an error, i.e., distortion, in the frequency output produced. It will be appreciated that the extent of the error will vary depending on the period of the PWM signal, and thus the error may be considered a distortion associated with the signal.

[0063] Ideally, the driver circuits would be balanced to provide exactly equal propagation delays in each direction, but in practice it is impossible to maintain an adequate balance in normal variations in manufacturing tolerances, temperature, and supply voltage to achieve this goal.

[0064] In an embodiment of the present disclosure, the feedback signal S for the TEM FB Indicating at least some of this unavoidable nonlinear effect, the feedback signal may represent the PWM signal S PWM The timing of the derived downstream control signal may be affected by this nonlinearity. Therefore, the effect of this nonlinearity is included in the feedback loop of the TEM and in generating the PWM signal S PWM Therefore, the non-linear effects are mitigated when the control loop of the TEM responds to the actual timing (ie, duty cycle) of the associated control signal.

[0065] Figure 2 An ADC 200 according to one embodiment of the present disclosure is illustrated, wherein Figure 1 Components similar to those discussed are identified by the same reference numerals. Figure 2 The TEM 201 is again illustrated, and is arranged to receive an input signal S IN , and generates a PWM signal S for the controlled oscillator 202 (in this case, the VCO) PWM As described above, in this embodiment, the PWM signal S PWM The current source 111 is received by the VCO 202 and applied to successive switch drivers 114 and 115 to generate switch control signals S1 and S2 for controlling respective first and second control switches 112 and 113 to selectively couple the current source 111 to the driving node 109 of the ring oscillator 107 .

[0066] However, in this embodiment, the feedback signal S for TEM 201 is FB is tapped off from one of the switch control signals, thereby including the effects of any nonlinearity associated with driving the switch capacitance. FB The feedback signal S is tapped from the control signal S1 applied to the first control switch 112. FB 1 provides an indication of the relative timing of the operation of switch S1, which controls when current source 111 is coupled to the drive node. Thus, this signal is indicative of the timing error that will be present at the drive node 109. However, it should be noted that the feedback signal may alternatively be tapped off from the control signal S2 applied to the second control switch 113. Typically, the first control switch 112 and the second control switch 113 will have substantially the same design as each other and will have similar capacitances. Thus, the nonlinearity associated with the drive switch 113 will be substantially the same as the nonlinearity of switch 112 and thus either switch may be included in the feedback loop for the TEM 201 to enable such nonlinearity to be compensated for, wherein appropriate polarity matching enables the feedback signal S2 to be applied to the drive node 109. FB The total ratio of time spent in the two states represents the duty cycle at the driver node.

[0067] Feedback signal S FB is provided to the TEM 201. The TEM 201 may process the feedback signal S in the same manner as discussed above. FB For example, regarding Figure 1 As discussed, the feedback signal may be buffered and filtered by the loop filter 105 as needed, and the filtered signal S FB ' is applied to a comparator input of the hysteresis comparator 104, and the input signal S IN is applied to the other comparator input.

[0068] therefore, Figure 2The embodiment illustrated in includes non-linear effects associated with driving the control switch 112 or 113. Therefore, the switching of the hysteresis comparator 104 is controlled based on the actual timing of the switch control signal S1 or S2, and the feedback loop takes into account any non-linearity experienced in use, which causes the switch control signal S1 or S2 to be different from the PWM signal S1 or S2. PWM In the embodiments of the present disclosure, there will still be nonlinear effects that cause the relevant control signal (e.g., S1) to be inconsistent with the PWM signal S PWM However, feedback ensures that the hysteresis comparator 104 of TEM 201 switches so that compared to Figure 1 In the case of the embodiment illustrated in FIG. 1 , the duty cycle of the switch control signal (eg, S1) more accurately corresponds to the input signal S IN Therefore, the oscillation signal S output from the VCO 102 to the counter 103 is OSC More accurately reflects the input signal S IN .and Figure 1 This can significantly improve the distortion performance of ADC 200 compared to the method illustrated in .

[0069] Another possible source of error, and thus distortion, may arise due to the capacitance associated with the drive node 109 . Figure 3 It is illustrated that there may be a capacitance C associated with the driving node D This capacitor C D This may include parasitic capacitance associated with the drive node 109, and / or some capacitance intentionally introduced to reduce the effect of any power supply noise that feeds through to the controlled oscillator and causes jitter. In any case, the capacitance C associated with the drive node 109 is D Different rise and fall times (i.e., slew rates) may result, which are associated with switching between different drive strengths in a manner similar to that discussed above with respect to the drive voltage for controlling the switch. For example, when switching to a higher drive strength, the drive node 109 may exhibit a relatively fast rise time, but when switching back to a lower drive strength, the fall time may be longer and may vary with the PWM signal S. PWM The rise time and fall time that vary with the period of the controlled oscillator 107 will vary with the input signal. This represents an error in the timing of the drive signal applied to the controlled oscillator 107 (ie, a duty cycle error), thereby generating an output signal D OUT Another possible source of distortion.

[0070] To alleviate this problem, in some embodiments, the feedback signal S FBcan be derived to indicate the timing of the drive control signal applied to the drive node, including the effect of any capacitance associated with the drive node 109. Therefore, Figure 3 A signal is illustrated, which indicates that the driving signal at the driving node 109 can be tapped as the feedback signal S FB Provide a foundation.

[0071] exist Figure 3 In the illustrated embodiment, the signal level, such as the voltage at the drive node 109, can be monitored by a monitor 301. The monitor in this embodiment includes a comparator 301 for comparing the voltage at the drive node with a reference to act as a level detector. In some cases, the reference can be a reference voltage selected to correspond to a suitable voltage between the expected voltages at two different drive strengths (in a stable state). The output of the comparator 301 will be a two-level signal indicating the timing of the drive signal at the drive node 109 crossing the relevant threshold. This can be used as a feedback signal S for the TEM 201. FB , and will include at least some of any duty cycle timing errors associated with the drive node 109, and at least some of any timing errors associated with the control components used to generate the drive signal (such as, controlling switches 112 and 113). It should be understood that the monitor (i.e., comparator 301) itself may introduce some timing errors, but such errors may generally be less severe than the timing errors or fidelity losses associated with the capacitance of the drive node 109, thereby improving distortion performance.

[0072] Figure 3 It is illustrated that the driving node 109 itself may be monitored by the comparator 301 and compared to a reference. However, in some embodiments, it may be advantageous not to tap the signal from the ICO driving node 109 directly. For example, in some embodiments, there may be a load impedance or virtual ICO that is selectively driven by a current source 111 that is synchronized with the driving node 109 (e.g., in phase with the driving node 109 or otherwise synchronized so that the duty cycle of the monitored node represents the duty cycle of the driving node). This arrangement may have some advantages with respect to switching of the ICO 107 between different drive strengths. Therefore, a replica driving node used to drive such a load impedance or virtual ICO may be monitored to provide an indication of the timing of the drive signal applied to the driving node 109. Such a replica driving node will experience timing errors similar to the timing errors of the duty cycle of the drive signal applied to the ICO 107, so that such a monitored node (e.g., a replica driving node) can be used to derive an appropriate feedback signal.

[0073] Therefore, the feedback signal S can usually be generated or derived by monitoring the actual driving node used to drive the ICO 107 (which provides the output oscillating signal). FB However, in some cases, the feedback signal S may be generated or derived by monitoring some other monitored node (e.g., a replica node configured to provide similar load and driving conditions as the driving node, thereby accurately following the timing of the transitions at the driving node). FB .

[0074] It will be appreciated that the embodiments have been described above with ICO as the ring oscillator 107 so that the drive signal corresponds to the drive current. However, the voltage at the drive node will vary with the strength of the drive current so that the signal level at the drive node can be monitored in this way.

[0075] In some embodiments, the ring oscillator may be a ring oscillator driven by a voltage at a driving node, i.e., a VCO ring oscillator. Such a VCO ring oscillator may be driven by controlling a control switch to couple the driving node to different defined voltages, and the control switch may be subject to similar nonlinearities as discussed above. Such a VCO ring oscillator may additionally or alternatively include some type of buffer to drive a filter capacitor or provide a supply current, which may also be subject to asymmetric rise and fall times that affect the duty cycle of the resulting oscillator. Thus, embodiments may be implemented with any type of ring oscillator.

[0076] Thus, embodiments of the present disclosure utilize a TEM to generate a time-coded signal (specifically, a PWM signal) based on an input signal, wherein the time-coded signal is output for use by a downstream module to derive a control signal, and a timing error may be introduced between the PWM signal and the resulting control signal due to components of the downstream module reducing the fidelity of the control signal compared to the PWM signal. In embodiments of the present disclosure, the TEM generates a time-coded signal in response to the input signal and a feedback signal, and the feedback signal is derived from the downstream control signal. Specifically, in some embodiments, the downstream module may be a controlled oscillator (such as a VCO), and the associated control signal may be a switch control signal for controlling the switching of a drive element (such as a current source) of the VCO, or the associated control signal may be a drive signal applied to a drive node of a ring oscillator. Thus, the effect of at least some timing or duty cycle fidelity error between the time-coded signal and the associated control signal is contained in the feedback loop of the TEM, which mitigates the effect of such error, thereby improving distortion performance compared to a feedback signal derived internally in the TEM (e.g., directly from the time-coded signal).

[0077] As described above, TEM 201 may be a device for generating a time-coded signal (eg, a PWM signal S PWM ) and may in particular be arranged as a self-oscillating topology, but deriving the feedback signal S from the downstream control signal FB , the downstream control signal may include a duty cycle timing error as discussed above.

[0078] Figure 4 One embodiment of a suitable TEM 201 is illustrated. As previously discussed, in this embodiment, the comparator 104 converts the input signal S received at the first comparator input IN The filtered feedback signal S received at the second comparator input FB 'Compare and generate a TEM output signal S based on the comparison PWM In this embodiment, the comparator is a hysteresis comparator 104 which is operable to apply hysteresis to the comparison.

[0079] The hysteresis comparator 104 compares the signal at the first comparator input with the signal at the second comparator input (ie, the input signal S IN and the filtered feedback signal S FB ') and outputs two output states (e.g., high state V H With low state V L ) in one of the first comparator inputs. The hysteresis comparator 104 is operable to apply hysteresis to the comparison so that the signal S at the first comparator input IN The signal S at the second comparator input FB The differential voltage between the output states must be greater (i.e., more positive or less negative) to transition from one output state to another (e.g., from output state V L Transition to output state V H ) but must be lower (i.e., less positive or more negative) for the opposite transition to occur (e.g., from output state V H Switch to output state V L ). The difference between these first thresholds and the second threshold corresponds to the amount of hysteresis applied. In some embodiments, the first threshold and the second threshold can be equal in magnitude and opposite in polarity, that is, the input signal S IN The filtered feedback signal S FB The difference between the two must be greater than the amount +H to transition to one state (e.g., V H ), and must be below -H to transition to the other state. In this case, the magnitude of H can be considered as a measure of the hysteresis applied by the hysteresis comparator 104.

[0080] The loop filter 105 provides a certain signal average over time. FB From low state to high state (due to PWM signal S PWM becomes high), the filtered feedback signal S FB ' will increase in value, that is, become more positive, but it will take some time. IN The input signal S is relatively constant during this period. IN The filtered feedback signal S FB The difference between them will decrease, i.e. the positive value becomes smaller / the negative value becomes larger, until the relevant threshold is reached and the PWM signal S PWM The feedback signal S FB At the appropriate time, it will also turn low, and the filtered feedback signal S FB ' will begin to decrease. The hysteresis comparator 104 will maintain a low state V L , until the input signal S IN The filtered feedback signal S FB 'The difference between increases (ie, negative values ​​become smaller / positive values ​​become larger) until a second threshold value is reached.

[0081] Therefore, if the input signal S IN Keeping a relatively constant level, the output of the hysteresis comparator 104 will be in the high output state V H With low output state V L Relative to the input signal S IN The maximum expected rate of change of the input signal S IN In this case, the time spent in each output state will depend on the filtered feedback signal S FB 'Change the amount defined by hysteresis (e.g., from equal to S IN -H value to S value IN +H, or from value S IN +H to equal S IN Obviously, this will depend on the amount of hysteresis and the filtered feedback signal S FB ' rate of change. However, the filtered feedback signal S FB The rate of change of ' will depend on the filtered feedback signal S FB ' (which in turn depends on the input signal S IN level) and the feedback signal S FB The difference between its own values.

[0082] exist Figure 4In the illustrated embodiment, loop filter 105 comprises a passive RC low-pass filter including: a resistor 401 in a feedback path; and a capacitor 402 coupled between the feedback path and a reference voltage (e.g., ground). Although filter 105 may be implemented using resistors and capacitors as illustrated, in some implementations, other RC components, such as FET-based resistors and / or capacitors, may be used.

[0083] The feedback loop of TEM 201 acts as a high state V H Output PWM signal S PWM , so that the feedback signal S FB Charge capacitor 402 to a temperature equal to S IN +H voltage, and then switches to the low state V L , until the capacitor 402 is discharged to a value equal to S IN -H voltage, etc. However, the charging rate and discharging rate of capacitor 402 depend on the feedback signal S FB The difference between the level of the feedback signal S and the current voltage of the capacitor 402. If the input signal is at a relatively high level, the voltage value of the capacitor 402 will be relatively high. FB When the feedback signal S is high, there will be a relatively low voltage difference across the resistor 401, and the capacitor will charge relatively slowly. FB When the input signal S is low, the difference across the resistor 401 will be relatively high, and the capacitor 402 will discharge faster. IN When compared to changing capacitor 402 from S IN +H discharge to S IN -H is the time it takes for capacitor 402 to change from S IN -H charges to S IN +H takes longer. Therefore, at higher input signal levels, the PWM signal S PWM will spend longer in the high output state. For low signal levels, the reverse is true. For signals at mid-level voltages (which, for an audio signal, would correspond to an input signal of zero amplitude), the time spent charging and discharging between the hysteresis thresholds will be the same, resulting in the high output state lasting the same amount of time as the low output state in one cycle.

[0084] Therefore, the proportion of time that TEM 201 spends in the high output state compared to the low output state (ie, the time that PWM signal S PWM duty cycle) to the input signal S IN The level is encoded.

[0085] Figure 4A simple first order RC filter is illustrated, but second order or higher order filters may be implemented in some arrangements.

[0086] Figure 5 An alternative arrangement is illustrated in which the loop filter arrangement 105 comprises a current generator 501 configured to generate a current signal having a current value that depends on the feedback signal S FB The current changes with the state. Figure 5 In the illustrated embodiment, the current generator includes: a first current source 5021 for generating a defined positive current +i; and a second current source 5022 for generating a defined negative current -i, that is, the second current source 5022 is used as a current sink. The first current source 5021 and the second current source 5022 are controlled to depend on the feedback signal S FB state to generate positive or negative current, that is, when the feedback signal S FB When the feedback signal S FB In another state (eg, low), a negative current -i is generated. The current signal output from the current generator 501 is supplied to a node coupled to the feedback capacitor 503. Therefore, the current signal charges or discharges the feedback capacitor 503 depending on the polarity of the current signal.

[0087] In order to provide a variable charging rate or discharging rate based on the value of the input signal, in some embodiments, the feedback capacitor may also be coupled to a voltage source via resistor 504. In some embodiments, the voltage source may be a defined reference voltage V R , the reference voltage V R It can be conveniently the voltage corresponding to the zero amplitude input signal, such as the midpoint voltage. Then, the input signal S IN is provided as a separate input to the hysteresis comparator 104. In such an embodiment, the charging and discharging rates of the feedback capacitor 503 depend not only on the magnitude of the current produced by the current generator, but also on the current through the impedance 504, which in turn depends on the voltage of the feedback capacitor 503 (as discussed above, the voltage of the feedback capacitor 503 will correspond to the input signal S IN Therefore, the voltage of the feedback capacitor provides a filtered feedback signal S for the hysteresis comparator 104. FB '.

[0088] Alternatively, the input signal S IN can be applied to resistor 504, thereby contributing a value that depends on the input signal S INIn this case, one input of the hysteresis comparator 104 is actually based on the filtered feedback signal S FB 'With the input signal S IN The combined signal and a reference voltage V R For comparison, the combined signal may be provided explicitly to another comparator input or may be effectively defined by the structure of the hysteresis comparator 104 .

[0089] As discussed, reference Figure 4 and Figure 5 The TEM 201 described provides a PWM signal S PWM As the output of the TEM, in the TEM, the value of the input signal is encoded as the duty cycle of the PWM signal, that is, with an output state (e.g., a low state V L ) compared to the other output state (such as high state V H ), or equivalently as a ratio of the cycle period. The encoding is similar to a conventional ASDM in some respects. As mentioned above, for an input signal equal to the mid-level voltage (which, for an audio signal, may correspond to a zero amplitude signal), the duty cycle will be 50%, i.e., within each cycle, the duration spent in the high output state will be the same as the time spent in the low output state. As the amplitude of the input signal increases (i.e., the value of the input signal moves further away from the mid-level voltage), the duration of the cycle of one output state will increase, and the duration of the cycle of the other output state will decrease, but not by the same amount. Therefore, the entire period of the PWM cycle will also vary with the input signal. When the signal is at the mid-level voltage (e.g., zero input signal amplitude), the shortest cycle period and thus the maximum PWM cycle frequency occurs, which is called the limit cycle frequency. As the amplitude of the input signal increases, the PWM cycle frequency decreases. For example, at a signal amplitude of nine-tenths of the maximum signal level, the PWM cycle frequency will be less than one-fifth of the limit cycle frequency. PWM signal S PWM Such relatively large variations in the cycle frequency or cycle period may be disadvantageous in some embodiments.

[0090] To avoid these problems, Figure 6 An embodiment is illustrated in which the TEM 201 includes a controller 601 for controlling the PWM cycle period (or equivalently, the PWM cycle frequency), for example to keep the PWM cycle period within defined limits. In some embodiments, the cycle period controller 601 is operable to apply adaptive hysteresis control, i.e., based on the input signal S IN The amount of hysteresis applied by the hysteresis comparator 104 is controlled based on an indication of the signal level of

[0091] The amount of hysteresis applied affects the cycle period and therefore the frequency, since it determines the filtered feedback signal S FB ' (or the combined filtered feedback signal / input signal) must change to switch from one output state to another. Therefore, reducing the amount of applied hysteresis will tend to reduce the PWM cycle period, thereby increasing the PWM cycle frequency, and increasing the amount of applied hysteresis will have the opposite effect. Therefore, the cycle period controller 601 can controllably vary the value of the applied hysteresis H X , thereby reducing the amount of hysteresis applied as the amplitude of the input signal increases, thereby keeping the cycle period within a defined range. As will be appreciated by those skilled in the art, there are a variety of ways to vary the hysteresis applied by the hysteresis comparator 104 .

[0092] Additionally or alternatively, in some embodiments, the cycle controller 601 may control at least one parameter F of the loop filter 105. X For example, the loop filter 105 includes a reference Figure 5 In the case of the described current generator 501, the current sources 5021 and 5022 can be configured to provide a variable output current. Therefore, the cycle controller 601 can control the output current from the current sources 5021 and 5022 as the filter parameter F X The higher current will result in a filtered feedback signal S FB ' changes faster, resulting in a shorter cycle, and vice versa.

[0093] In some embodiments, the digital output signal D OUT can be used as the input signal S IN Therefore, the cycle controller 601 can be configured to receive the digital output signal D OUT , and based on the digital output signal D OUT The PWM cycle period can be controlled by changing the applied hysteresis H X and / or filter parameter F X However, in some embodiments, the TEM 201 may monitor the PWM signal S PWM And the PWM cycle period is controlled based on the PWM signal.

[0094] Therefore, the TEM 201 may include a time decoding converter (TDC) 602 that receives the PWM signal S PWM A type of PWM signal S PWM The time parameter T X Time parameter T X It can be a PWM signal SPWM Any parameter that varies in a known manner with the input signal amplitude. In this embodiment, the time parameter T X This can be the current cycle period T, although the time parameter can also be the duration or duty cycle of a pulse of an output state. X It can therefore be provided to the cycle controller 601 .

[0095] To control the PWM cycle period, a relatively precise or accurate indication of the level of the input signal may not be required, and a relatively rough determination of the cycle period T may be sufficient. In some embodiments, the TDC 602 may include a counter 603 clocked by a reference clock signal CLK. The counter 603 may be configured to determine at least one count value of the number of reference clock cycles in a period corresponding to a relevant time parameter. For example, the counter 603 may be configured to determine the number of reference clock cycles in a period corresponding to a relevant time parameter. PWM The number of reference clock cycles in each cycle between successive rising edges in is counted and a cycle-by-cycle count value is provided as a measure of the cycle period T. X As mentioned, for PWM cycle period control, a high level of accuracy may not be required, so that the reference clock signal CLK only needs to be fast enough to provide the required time resolution of the period or pulse length of the PWM signal.

[0096] In some cases, control of the PWM cycle period may be performed during normal operation of the ADC. However, in some cases, control of the PWM cycle period may be performed as an initial step in ADC startup (e.g., as an initial calibration step for current operating conditions). This initial step may set the hysteresis value H to X and / or the parameter F of the loop filter 105 X Sets the limit cycle period to a limited value or a value within a limited range, and then latches the value for subsequent operation.

[0097] The above discussion has focused on receiving a single-ended input signal S IN , the single-ended input signal S IN The reference voltage varies relative to some static mid-level voltage reference (e.g., ground). However, any noise on the reference voltage (e.g., ground noise) can cause problems. One way to provide ground noise cancellation is to use an inverting amplifier to generate an inverted version of the input signal and use the original input signal and the inverted version as components of the differential input signal. However, this does require an additional inverting amplifier with associated size and power requirements.

[0098] Figure 7Another embodiment of a TEM 201 is illustrated that uses a pseudo-differential input arrangement to provide noise cancellation (e.g., ground noise cancellation) without requiring an initial inverting amplifier. Figure 7 In the embodiment of the present invention, an input signal S is received at the first signal path. IN , the first signal path leads to the first comparator input of the hysteresis comparator 104, and the related reference voltage V R (eg, ground) is applied to a second signal path leading to a second input of the hysteresis comparator 104. The loop filter arrangement 105 comprises a first current source 5021 and a second current source 5022 for providing a current with the same current as above. Figure 5 The positive current and the negative current are generated in a similar manner as described above, such as providing a limited current and absorbing a limited current. The current sources 5021 and 5022 are based on the feedback signal S FB However, in Figure 7 In the embodiment of the present invention, the current sources 5021 and 5022 are also arranged to supply current to the second signal path in anti-phase. Therefore, the switches 7011 and 7012 are arranged to couple the first current source 5021 to the first signal path and the second signal path, respectively, and are configured to be driven by the feedback signal S FB The generated control signals Φ1 and Φ2 are switched in anti-phase. Similarly, switches 7021 and 7022 are arranged to couple the second current source 5022 to the first signal path and the second signal path, respectively, and are also switched in anti-phase by the control signals Φ2 and Φ1, so that each of the first signal path and the second signal path is connected to one of the first current source 5021 and the second current source 5022. Therefore, the filtered feedback signal S FB ' is actually applied to the first signal path, and the filtered feedback signal S FB The inverted version of ' is applied to the second signal path, that is, the feedback is applied differentially to the two inputs. Capacitor 703 is connected between the first signal path and the second signal path and is charged and discharged by the feedback signal, but is also based on the input signal S IN With reference V R Since this embodiment uses the current signal for feedback, the input signal S IN With reference V R is applied to the input resistor 704. Such an arrangement can provide good ground noise cancellation.

[0099] Of course, it will be appreciated that other designs of TEMs are known and may be implemented in embodiments of the present invention.

[0100] Therefore, an ADC according to an embodiment of the present disclosure can provide good quality for audio applications and can be implemented in a relatively small circuit area with relatively low power consumption. The embodiments have been described mainly with respect to the ADC, and in general, an ADC according to one embodiment can include a TEM and a controlled oscillator, the TEM being configured to generate a PWM signal based on an input signal and a feedback signal, and the controlled oscillator being used to generate an oscillation signal having a frequency that varies depending on the strength of the drive signal at the drive node. The PWM signal generated by the TEM is received by the controlled oscillator and is used to control the switching of at least one control switch, thereby controlling the drive strength of the drive signal applied to the drive node of the controlled oscillator. The feedback signal for the TEM is derived from the controlled oscillator, thereby including any duty cycle timing error between the control signal applied to the control switch and the PWM signal.

[0101] However, the same principles can be applied to other applications of TEM, in which a time-coded signal generated by the TEM is applied to downstream components and used to generate control signals in a manner such that the control signals may experience timing errors relative to the time-coded signal due to components of the downstream modules.

[0102] Embodiments may be implemented in a range of applications, and are particularly suited for audio applications.

[0103] The embodiment may be implemented as an integrated circuit, which in some embodiments may be a codec or an audio DSP or the like. The embodiment may be incorporated into an electronic device, which may be, for example, a portable device and / or a device that can be operated by battery power. The device may be a communication device, such as a mobile phone or a smart phone or the like. The device may be a computing device, such as a notebook computing device, a laptop computing device, or a tablet computing device. The device may be a wearable device, such as a smart watch. The device may be a device with voice control or activation functionality. In some cases, the device may be an accessory device used with some other product, such as a headset receiver or the like.

[0104] The skilled person will recognize that some aspects of the apparatus and methods described above (e.g., discovery methods and configuration methods) may be embodied as processor control code, for example, located on a non-volatile carrier medium (such as a disk, CD-ROM or DVD-ROM), a programmed memory (such as a read-only memory (firmware) or on a data carrier (such as an optical signal carrier or an electrical signal carrier). For many applications, the embodiments will be implemented on a DSP (digital signal processor), an ASIC (application specific integrated circuit) or an FPGA (field programmable gate array). Thus, the code may include conventional program code or microcode, or, for example, code for setting up or controlling an ASIC or FPGA. The code may also include code for dynamically configuring a reconfigurable apparatus (such as a reprogrammable logic gate array). Similarly, the code may include code for a hardware description language (such as Verilog TM The code may be distributed among multiple coupled components that communicate with each other, as will be appreciated by the skilled person. Where appropriate, the embodiments may also be implemented using code that runs on a field (re)programmable analog array or similar device to configure analog hardware.

[0105] It should be noted that the embodiments mentioned above illustrate rather than limit the present invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in the claims, "a" or "an" does not exclude a plurality, and a single feature or other unit may perform the functions of several units recited in the claims. Any reference numerals or annotations in the claims should not be interpreted as limiting their scope.

Claims

1. Analog-to-digital converter circuit, including: a time-coded modulator, the time-coded modulator comprising a comparator and a loop filter, and configured to generate a pulse width modulated (PWM) signal in response to an input signal and a feedback signal; a controlled oscillator configured to receive the pulse width modulated (PWM) signal and generate an output oscillating signal having a frequency that varies based on a drive signal at a drive node; wherein the controlled oscillator comprises at least one control switch, the at least one control switch being configured to be controlled by a switch control signal so as to control the driving strength of the driving signal applied to the driving node, the switch control signal being generated from the received PWM signal; wherein the feedback signal for the time coded modulator is derived from the controlled oscillator and thereby includes any timing error between the PWM signal and the switch control signal applied to the control switch.

2. The analog-to-digital converter circuit of claim 1, wherein the feedback signal for the time-coded modulator is tapped off from the switch control signal applied to the control switch. 3 . The analog-to-digital converter circuit according to claim 2 , comprising a buffer configured to receive a signal tapped from the switch control signal applied to the control switch and output the feedback signal.

4. An analog-to-digital converter circuit according to claim 1, wherein the feedback signal for the time-coded modulator is derived from the controlled oscillator to include an indication of any timing error between the drive signal applied to the drive node and the PWM signal.

5. An analog-to-digital converter circuit according to claim 4, comprising a monitor for monitoring the signal level at a monitored node against a defined reference to provide the feedback signal, wherein the monitored node exhibits a change in the signal level with a duty cycle corresponding to the duty cycle of the driving node.

6. The analog-to-digital converter circuit of claim 5, wherein the monitored node is the driving node.

7. The analog-to-digital converter circuit of claim 5, wherein the monitored node is a replica driving node for driving a load in synchronization with the driving node.

8. The analog-to-digital converter circuit of claim 5, wherein the monitor comprises a comparator that compares the first signal to a reference voltage.

9. The analog-to-digital converter circuit of claim 1, wherein the controlled oscillator comprises a ring oscillator configured to be driven by a drive current signal at the drive node.

10. The analog-to-digital converter circuit of claim 9, wherein the first current source is configured to provide a first driving current to the driving node, and the at least one control switch is controlled by the switch control signal to selectively connect the second current source to the driving node to provide a second driving current.

11. The analog-to-digital converter circuit of claim 1, wherein the loop filter of the time-coded modulator is configured to filter the feedback signal to provide a filtered feedback signal.

12. The analog-to-digital converter circuit of claim 11, wherein the comparator is configured to compare the input signal received at a first comparator input with the filtered feedback signal received at a second comparator input.

13. The analog-to-digital converter circuit of claim 11, wherein the filtered feedback signal is combined with the input signal and applied to a first comparator input of the comparator.

14. The analog-to-digital converter circuit of claim 13, wherein the comparator is configured to compare the signal at the first comparator input with a reference voltage.

15. The analog-to-digital converter circuit of claim 11, wherein the input signal is applied to a first signal path of the time-coded modulator, the first signal path is coupled to a first comparator input of the comparator, and a reference voltage is applied to a second signal path of the time-coded modulator, the second signal path is coupled to a second comparator input of the comparator, and wherein the filtered feedback signal is applied to both the first signal path and the second signal path as a differential signal. 16 . The analog-to-digital converter circuit of claim 1 , wherein the loop filter comprises a first current source and a second current source, the first current source and the second current source being controlled to source current or sink current based on the feedback signal.

17. The analog-to-digital converter circuit of claim 1, wherein the comparator is a hysteresis comparator.

18. An electronic device comprising the analog-to-digital converter circuit according to claim 1, wherein the device is a portable device.

19. An electronic device comprising the analog-to-digital converter circuit of claim 1, wherein the device is a battery-powered device.

20. An electronic device comprising the analog-to-digital converter circuit of claim 1, wherein the device is an audio device.

21. An electronic device comprising the analog-to-digital converter circuit according to claim 1, wherein the device is a communication device.

22. An electronic device comprising the analog-to-digital converter circuit according to claim 1, wherein the device is a mobile phone or a cellular phone or a smart phone.

23. An electronic device comprising the analog-to-digital converter circuit of claim 1, wherein the device is a computing device.

24. An electronic device comprising the analog-to-digital converter circuit of claim 1, wherein the device is a notebook computing device or a tablet computing device.

25. An electronic device comprising the analog-to-digital converter circuit of claim 1, wherein the device is a gaming device.

26. An electronic device comprising the analog-to-digital converter circuit of claim 1, wherein the device is a wearable device.

27. An electronic device comprising the analog-to-digital converter circuit according to claim 1, wherein the device is a smart watch.

28. An electronic device comprising the analog-to-digital converter circuit of claim 1, wherein the device is a voice activated device or a voice controlled device.

29. An electronic device comprising the analog-to-digital converter circuit according to claim 1, wherein the device is an electrical appliance.

30. Analog-to-digital converter circuit, comprising: a time-coded modulator, the time-coded modulator comprising a comparator and a loop filter, and configured to generate a pulse width modulated (PWM) signal in response to an input signal and a feedback signal; a controlled oscillator configured to receive the pulse width modulated (PWM) signal and generate an output oscillating signal having a frequency that varies based on a drive signal at a drive node; wherein the controlled oscillator comprises at least one control switch, the at least one control switch being configured to be controlled by a switch control signal so as to control a driving strength of the driving signal applied to the driving node, wherein the switch control signal is generated from the received PWM signal; wherein the feedback signal for the time coded modulator is derived from the controlled oscillator thereby including any delay between signal transitions of the PWM signal and corresponding signal transitions of the switch control signal applied to the control switch.

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