Wire-saving encoder and processing method thereof

Abstract

The present invention discloses a line-saving encoder and a processing method thereof. A line-saving encoder processing method includes step S1: passing the input voltage of the line-saving encoder into a voltage stabilizing circuit and a photocell respectively, so that the input voltage input to the voltage stabilizing circuit is stabilized at a reference voltage, and the reference voltage is sequentially input into a first driving chip after passing through a first delay circuit and a second delay circuit; step S2: the second driving chip outputs a first signal or a second signal generated by the photocell, and realizes switching between the first signal and the second signal through a first element or a second element. The line-saving encoder and the processing method thereof disclosed by the present invention stabilize the input voltage at a reference voltage through a voltage stabilizing circuit and a delay circuit to prevent the delay time from changing due to an external voltage change, and at the same time, this reference voltage is also used to ensure the stability and reliability of the power-on threshold voltage Va of the line-saving encoder.

Description

Technical Field

[0001] The invention belongs to the technical field of line-saving encoders, and in particular relates to a line-saving encoder processing method and a line-saving encoder. Background Art

[0002] The pulse encoder is an optical position detection element. The encoding disk is fixedly connected to the rotating shaft to measure the rotation angle position and speed change of the shaft. Its output signal is an electrical pulse. It is a commonly used angular displacement sensor and can also be used as a speed detection device.

[0003] A non-line-saving encoder is one that outputs six signals, A, B, Z, U, V, and W. After reaching the threshold voltage Va at power-on, a line-saving encoder first maintains a high impedance (or high level) time of Ta, then generates three signals, U, V, and W, and after maintaining the time Tb, finally outputs A, B, and Z signals. Therefore, U, V, W and A, B, and Z share the same transmission cable, which can save three pairs of transmission cables (U+ / U-, V+ / V-, W+ / W-), so it is called a line-saving encoder. Its power-on timing diagram can be seen in Fig. 9 .

[0004] The advantage of the wire-saving pulse encoder over the non-wire-saving encoder is that the number of cables required is small and the cable installation cost is relatively low. The wire-saving pulse encoder on the market also has disadvantages, which are mainly manifested as follows:

[0005] First, the delay times Ta and Tb of common encoders on the market change with the input voltage. When the external voltage changes slightly, it is very easy to cause fluctuations in the power-on timing of the product, which in turn causes the external detection device (such as a servo drive) to fail to detect the U, V, and W signals within the specified time.

[0006] Secondly, in order to realize the non-line-saving function, existing products often add a selection chip (such as SN74HC157) to select the output signal. This requires additional chips to be placed on the PCB that needs to be compatible with the non-line-saving linear encoder, which is not conducive to the miniaturization of the encoder.

[0007] Therefore, further improvements are made to the above problems. Summary of the invention

[0008] The main purpose of the present invention is to provide a line-saving encoder and a processing method thereof, which stabilizes the input voltage at a reference voltage through a voltage stabilizing circuit and a delay circuit to prevent the delay time from changing due to changes in the external voltage. At the same time, this reference voltage is also used to ensure the stability and reliability of the power-on threshold voltage Va of the line-saving encoder; it can also realize the switching between the signals generated by the photocell without adding a chip, and can also realize the control delay, waveform output and switching between signals through a single-chip microcomputer, and realize the time-sharing selection transmission function of data through resistor isolation without the need for additional data selection chips.

[0009] To achieve the above objectives, the present invention provides a line-saving encoder processing method, which realizes voltage stabilization and signal switching through the line-saving encoder, comprising the following steps:

[0010] Step S1: The input voltage of the line-saving encoder is respectively passed through the voltage stabilizing circuit and the photocell, so that the input voltage of the voltage stabilizing circuit is stabilized at the reference voltage (to prevent the external input voltage from changing and causing the delay time to change. At the same time, this reference voltage is also used to ensure the stability and reliability of the power-on threshold voltage Va of the line-saving encoder), and the reference voltage is sequentially passed through the first delay circuit and the second delay circuit and then input into the first driving chip (the voltage stabilizing circuit makes the RC charging delay time not change due to the change of the external voltage);

[0011] Step S2: the second driving chip outputs the first signal or the second signal generated by the photocell, and switches between the first signal and the second signal through the first element or the second element.

[0012] As a further preferred technical solution of the above technical solution, step S1 is specifically implemented as follows:

[0013] Step S1.1: The input voltage (VCC) generates a reference voltage (VREF) after passing through the voltage regulator chip U1 of the voltage regulator circuit;

[0014] Step S1.2: When the input voltage reaches the threshold voltage, the reference voltage starts to charge the reverse end (RC) of the first comparator (U6-B), and after the charging is completed, the level of the reverse end is greater than the same direction end, and the first level (WKUP, and at this time it is a low level, the first level can be used to control whether the first driver chip is output or in a high impedance state (high impedance state, theoretically the output impedance is infinite at this time), the above is the first delay circuit);

[0015] Step S1.3: The output end (pin 7) of the first comparator inputs the first level to the second comparator (U2-B), and the second comparator outputs the second level (WKUP1);

[0016] Step S1.4: The output end of the second comparator (pin 7) inputs the second level to the third comparator (U2-A), and the third comparator outputs the third level (EN, when the high and low levels of the first level change, the second level changes, thereby controlling the third level, and the third level controls the first driver chip. Since the charging voltage is precise, the RC charging time does not change with the supply voltage. Steps S1.3 and S1.4 are the second delay circuit).

[0017] As a further preferred technical solution of the above technical solution, step S2 is specifically implemented as the following steps:

[0018] Step S2.1: inputting the first signal generated by the photocell into the second driving chip through the resistor network, inputting the second signal generated by the photocell into the first driving chip, and inputting the third signal generated by the second signal passing through the first driving chip into the second driving chip, the second driving chip outputting the first signal or the second signal according to the state, thereby realizing the switching between the first signal and the second signal;

[0019] Step S2.2: The first signal generated by the photocell is input into the second driver chip through the resistor network, the second signal generated by the photocell is input into the single-chip microcomputer, and the fourth signal generated after the second signal passes through the single-chip microcomputer is input into the second driver chip. The second driver chip outputs the first signal or the second signal according to the state of the single-chip microcomputer to realize the switching between the first signal and the second signal.

[0020] As a further preferred technical solution of the above technical solution, step S2.1 is specifically implemented as the following steps:

[0021] Step S2.1.1: The first signal including three signals A, B and Z generated by the photocell (photocell: when light passes through the grating and shines on the photocell, the photocell will generate six signals U, V, W, A, B and Z) is input into the second drive chip through the resistor network, the second signal including three signals U, V and W generated by the photocell is input into the first drive chip, and the third signal including three signals U+, V+ and W+ generated by the second signal after passing through the first drive chip is input into the second drive chip; the electrical start reaches the gate on the line-saving encoder During the first time (Td) of the voltage limiting and the second time (Ta) after the threshold voltage is reached, the second driver chip maintains the output high impedance state, and after the second time ends, the second driver chip is set by the first driver chip to output the second signal including the three-way signals of U, V and W; after the third time (Tb), the first driver chip maintains the output high impedance state, and the second driver chip outputs the first signal including the three-way signals of A, B and Z, so as to realize the switching between the first signal including the three-way signals of A, B and Z and the second signal including the three-way signals of U, V and W;

[0022] Step S2.1: The first signal including three signals U, V and W generated by the photocell (photocell: when light passes through the grating and shines on the photocell, the photocell will generate six signals U, V, W, A, B and Z) is input into the second driving chip through the resistor network, the second signal including three signals A, B and Z generated by the photocell is input into the first driving chip, and the third signal including three signals A+, B+ and Z+ generated by the second signal after passing through the first driving chip is input into the second driving chip; within the first time (Td) when the threshold voltage is reached and the second time (Ta) after the threshold voltage is reached when the line-saving encoder is powered on, the second driving chip maintains an output high-impedance state, and after the second time ends, the second driving chip is set by the first driving chip to output the first signal including the three signals U, V and W; after the third time (Tb), the first driving chip maintains an output high-impedance state, and the second driving chip outputs a second signal including the three signals A, B and Z, thereby realizing the switching between the second signal including the three signals A, B and Z and the first signal including the three signals U, V and W.

[0023] As a further preferred technical solution of the above technical solution, step S2.2 is specifically implemented as the following steps:

[0024] Step S2.2.1: The first signal including three signals A, B and Z generated by the photocell is input into the second driving chip through the resistor network, the second signal including three signals U, V and W generated by the photocell is input into the single-chip microcomputer, and the fourth signal including three signals U+, V+ and W+ generated after the second signal passes through the single-chip microcomputer is input into the second driving chip, the enable end of the second driving chip is controlled by the single-chip microcomputer and the second driving chip enters a high impedance state until time point t2, and no signal is output; between time points t3-t4, the single-chip microcomputer controls the second driving chip to enter a normal output state, and outputs a second signal including three signals U, V and W; after time point t4, the single-chip microcomputer stops outputting the fourth signal including three signals U+, V+ and W+, and maintains a high impedance state, outputs the first signal including three signals A, B and Z, and realizes the switching of the first signal including three signals A, B and Z and the second signal including three signals U, V and W (therefore, the time-sharing selection transmission function of data is realized through resistor isolation without the need to add an additional data selection chip).

[0025] The present invention also provides a line-saving encoder, comprising a coding disc and a rotating shaft, wherein the coding disc and the rotating shaft are fixedly connected, and further comprising:

[0026] A voltage stabilizing circuit, a photocell and a first driving chip, the input voltage of the input line-saving encoder is respectively passed into the voltage stabilizing circuit and the photocell, the voltage stabilizing circuit is used to stabilize the input voltage at a reference voltage and the voltage stabilizing circuit is electrically connected to the first driving chip through a first delay circuit and a second delay circuit in sequence;

[0027] A second driving chip, a first element (preferably including a resistor network) and a second element (preferably a single chip microcomputer), the second driving chip is electrically connected to the first element or the second element, and the second driving chip is used to output the first signal or the second signal generated by the photocell.

[0028] As a further preferred technical solution of the above technical solution, the voltage stabilizing circuit includes a voltage stabilizing chip U1, wherein pin 1 of the voltage stabilizing chip U1 is connected to the input voltage (VCC) through resistors R6 and R7 in sequence, and resistors R4 are connected to both ends of the resistor R7, and pin 1 of the voltage stabilizing chip U1 is electrically connected to pin 3 in another way, and pin 2 of the voltage stabilizing chip U1 is connected to a reference voltage (VREF) through the common terminal of the resistors R6 and R7, and the common terminal of the resistors R6 and R7 is also grounded through a capacitor C10;

[0029] The voltage stabilizing circuit also includes resistor R2, resistor R3, resistor R22, resistor R24, resistor R15 and resistor R16. The reference voltage VREF_3.0V is grounded through resistor R2 and resistor R3 in sequence, and the common end of resistor R2 and resistor R3 outputs the reference voltage VREF_2.573V. The reference voltage VREF_3.0V is grounded through resistor R22 and resistor R24 ​​in sequence, and the common end of resistor R22 and resistor R24 ​​outputs the reference voltage VREF_1V. The reference voltage VREF_3.0V is grounded through resistor R15 and resistor R16 in sequence, and the common end of resistor R15 and resistor R16 outputs the reference voltage VREF_2.573V.

[0030] As a further preferred technical solution of the above technical solution, the first delay circuit includes a first comparator U6-B, pin 7 of the first comparator U6-B is connected to a reference voltage through a resistor R28, and a resistor R27 is connected in series between pin 7 and pin 5 of the first comparator U6-B, and pin 6 of the first comparator U6-B is grounded through a capacitor C9;

[0031] The second delay circuit includes a second comparator U2-B and a third comparator U2-A. Pin 6 of the second comparator U2-B is electrically connected to pin 7 of the first comparator U6-B. Pin 7 of the first comparator U6-B outputs a first level WKUP. Pin 7 of the second comparator U2-B is connected to a reference voltage through a resistor R41. Pin 7 of the second comparator U2-B is electrically connected to pin 2 of the third comparator U2-A through a resistor R23. Pin 7 of the second comparator U2-B outputs a second level WKIP1. Pin 2 of the third comparator U2-A is also grounded through a capacitor C17. A resistor R39 is connected in series between pins 3 and 1 of the third comparator U2-A. Pin 1 of the third comparator U2-A outputs a third level EN through a resistor R50. Pin 1 of the third comparator U2-A is also connected to a reference voltage through a resistor R52.

[0032] As a further preferred technical solution of the above technical solution, pin 1 of the first driver chip U3 is connected to signal U1 through one path, pin 1 of the first driver chip U3 is connected to signal A1- through resistor R31 through another path, resistor R32 is connected in parallel at both ends of resistor R31, pin 7 of the first driver chip U3 is connected to signal V1 through one path, pin 7 of the first driver chip U3 is connected to signal B1- through resistor R42 through another path, resistor R43 is connected in parallel at both ends of resistor R42, pin 9 of the first driver chip U3 is connected to signal W1 through one path, pin 9 of the first driver chip U3 is connected to signal Z1- through resistor R44 through another path, resistor R45 is connected in parallel at both ends of resistor R44.

[0033] As a further preferred technical solution of the above technical solution, pin 1 of the second driver chip U5 is connected to signal U, a pin of the second driver chip U5 is connected to the third level EN, pin 7 of the second driver chip U5 is connected to signal W, pin 9 of the second driver chip U5 is connected to signal V, pin 16 of the second driver chip U5 is grounded through capacitor C41 and another pin 16 is connected to the input voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 The invention discloses a wire-saving encoder and a processing method thereof.

[0035] Figure 2 It is a signal switching diagram of the line-saving encoder and its processing method of the present invention (setting ABZ from UVW).

[0036] Figure 3 It is a signal switching diagram of the line-saving encoder and its processing method of the present invention (setting UVW by ABZ).

[0037] Figure 4 The present invention discloses a single chip microcomputer control signal switching diagram of a line-saving encoder and a processing method thereof.

[0038] Figure 5 The invention discloses a voltage stabilizing circuit diagram of a line-saving encoder and a processing method thereof.

[0039] Figure 6 It is a first delay circuit and a second delay circuit diagram of a line-saving encoder and a processing method thereof of the present invention.

[0040] Figure 7 The invention discloses a first driving chip and a peripheral circuit diagram of a line-saving encoder and a processing method thereof.

[0041] Figure 8 The invention discloses a second driving chip and a peripheral circuit diagram of a line-saving encoder and a processing method thereof.

[0042] Fig. 9 It is a power-on timing diagram of the line-saving encoder and the processing method thereof of the present invention. DETAILED DESCRIPTION

[0043] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the present invention defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the present invention.

[0044] See attached figure Figure 1 , Figure 1 is a schematic structural diagram of a line-saving encoder and a processing method thereof of the present invention, Figure 2 It is a signal switching diagram of the line-saving encoder and its processing method of the present invention (UVW sets ABZ), Figure 3 It is a signal switching diagram of the line-saving encoder and its processing method of the present invention (set UVW by ABZ), Figure 4 It is a single chip control signal switching diagram of the line-saving encoder and its processing method of the present invention, Figure 5 It is a voltage stabilizing circuit diagram of the line-saving encoder and the processing method thereof of the present invention, Figure 6 The first delay circuit and the second delay circuit diagram of the line-saving encoder and the processing method thereof of the present invention are shown. Figure 7 The first driving chip and the peripheral circuit diagram of the line-saving encoder and the processing method thereof of the present invention are shown. Figure 8 The second driving chip and the peripheral circuit diagram of the line-saving encoder and the processing method thereof of the present invention are shown. Fig. 9 It is a power-on timing diagram of the line-saving encoder and the processing method thereof of the present invention.

[0045] In the preferred embodiment of the present invention, those skilled in the art should note that the input voltage, the encoding disc and the rotating shaft involved in the present invention can be regarded as prior art.

[0046] Preferred embodiments.

[0047] The present invention discloses a wire-saving encoder processing method, which realizes voltage stabilization and signal switching through the wire-saving encoder, comprising the following steps:

[0048] Step S1: The input voltage of the line-saving encoder is respectively passed through the voltage stabilizing circuit and the photocell, so that the input voltage of the voltage stabilizing circuit is stabilized at the reference voltage (to prevent the external input voltage from changing and causing the delay time to change. At the same time, this reference voltage is also used to ensure the stability and reliability of the power-on threshold voltage Va of the line-saving encoder), and the reference voltage is sequentially passed through the first delay circuit and the second delay circuit and then input into the first driving chip (the voltage stabilizing circuit makes the RC charging delay time not change due to the change of the external voltage);

[0049] Step S2: the second driving chip outputs the first signal or the second signal generated by the photocell, and switches between the first signal and the second signal through the first element or the second element.

[0050] Specifically, step S1 is implemented as follows:

[0051] Step S1.1: The input voltage (VCC) generates a reference voltage (VREF) after passing through the voltage regulator chip U1 of the voltage regulator circuit;

[0052] Step S1.2: When the input voltage reaches the threshold voltage, the reference voltage starts to charge the reverse end (RC) of the first comparator (U6-B), and after the charging is completed, the level of the reverse end is greater than the same direction end, and the first level (WKUP, and at this time it is a low level, the first level can be used to control whether the first driver chip is output or in a high impedance state (high impedance state, theoretically the output impedance is infinite at this time), the above is the first delay circuit);

[0053] Step S1.3: The output end (pin 7) of the first comparator inputs the first level to the second comparator (U2-B), and the second comparator outputs the second level (WKUP1);

[0054] Step S1.4: The output end of the second comparator (pin 7) inputs the second level to the third comparator (U2-A), and the third comparator outputs the third level (EN, when the high and low levels of the first level change, the second level changes, thereby controlling the third level, and the third level controls the first driver chip. Since the charging voltage is precise, the RC charging time does not change with the supply voltage. Steps S1.3 and S1.4 are the second delay circuit).

[0055] More specifically, step S2 is implemented as follows:

[0056] Step S2.1: inputting the first signal generated by the photocell into the second driving chip through the resistor network, inputting the second signal generated by the photocell into the first driving chip, and inputting the third signal generated by the second signal passing through the first driving chip into the second driving chip, the second driving chip outputting the first signal or the second signal according to the state, thereby realizing the switching between the first signal and the second signal;

[0057] Step S2.2: The first signal generated by the photocell is input into the second driver chip through the resistor network, the second signal generated by the photocell is input into the single-chip microcomputer, and the fourth signal generated after the second signal passes through the single-chip microcomputer is input into the second driver chip. The second driver chip outputs the first signal or the second signal according to the state of the single-chip microcomputer to realize the switching between the first signal and the second signal.

[0058] Furthermore, step S2.1 is specifically implemented as the following steps:

[0059] Step S2.1.1: The first signal including three signals A, B and Z generated by the photocell (photocell: when light passes through the grating and shines on the photocell, the photocell will generate six signals U, V, W, A, B and Z) is input into the second drive chip through the resistor network, the second signal including three signals U, V and W generated by the photocell is input into the first drive chip, and the third signal including three signals U+, V+ and W+ generated by the second signal after passing through the first drive chip is input into the second drive chip; the electrical start reaches the gate on the line-saving encoder During the first time (Td) of the voltage limiting and the second time (Ta) after the threshold voltage is reached, the second driver chip maintains the output high impedance state, and after the second time ends, the second driver chip is set by the first driver chip to output the second signal including the three-way signals of U, V and W; after the third time (Tb), the first driver chip maintains the output high impedance state, and the second driver chip outputs the first signal including the three-way signals of A, B and Z, so as to realize the switching between the first signal including the three-way signals of A, B and Z and the second signal including the three-way signals of U, V and W;

[0060] Step S2.1: The first signal including three signals U, V and W generated by the photocell (photocell: when light passes through the grating and shines on the photocell, the photocell will generate six signals U, V, W, A, B and Z) is input into the second driving chip through the resistor network, the second signal including three signals A, B and Z generated by the photocell is input into the first driving chip, and the third signal including three signals A+, B+ and Z+ generated by the second signal after passing through the first driving chip is input into the second driving chip; within the first time (Td) when the threshold voltage is reached and the second time (Ta) after the threshold voltage is reached when the line-saving encoder is powered on, the second driving chip maintains an output high-impedance state, and after the second time ends, the second driving chip is set by the first driving chip to output the first signal including the three signals U, V and W; after the third time (Tb), the first driving chip maintains an output high-impedance state, and the second driving chip outputs a second signal including the three signals A, B and Z, thereby realizing the switching between the second signal including the three signals A, B and Z and the first signal including the three signals U, V and W.

[0061] Furthermore, step S2.2 is specifically implemented as the following steps:

[0062] Step S2.2.1: The first signal including three signals A, B and Z generated by the photocell is input into the second driving chip through the resistor network, the second signal including three signals U, V and W generated by the photocell is input into the single-chip microcomputer, and the fourth signal including three signals U+, V+ and W+ generated after the second signal passes through the single-chip microcomputer is input into the second driving chip, the enable end of the second driving chip is controlled by the single-chip microcomputer and the second driving chip enters a high impedance state until time point t2, and no signal is output; between time points t3-t4, the single-chip microcomputer controls the second driving chip to enter a normal output state, and outputs a second signal including three signals U, V and W; after time point t4, the single-chip microcomputer stops outputting the fourth signal including three signals U+, V+ and W+, and maintains a high impedance state, outputs the first signal including three signals A, B and Z, and realizes the switching of the first signal including three signals A, B and Z and the second signal including three signals U, V and W (therefore, the time-sharing selection transmission function of data is realized through resistor isolation without the need to add an additional data selection chip).

[0063] The present invention also discloses a wire-saving encoder, comprising a coding disc and a rotating shaft, wherein the coding disc and the rotating shaft are fixedly connected, and further comprising:

[0064] A voltage stabilizing circuit, a photocell and a first driving chip, the input voltage of the input line-saving encoder is respectively passed into the voltage stabilizing circuit and the photocell, the voltage stabilizing circuit is used to stabilize the input voltage at a reference voltage and the voltage stabilizing circuit is electrically connected to the first driving chip through a first delay circuit and a second delay circuit in sequence;

[0065] A second driving chip, a first element (preferably including a resistor network) and a second element (preferably a single chip microcomputer), the second driving chip is electrically connected to the first element or the second element, and the second driving chip is used to output the first signal or the second signal generated by the photocell.

[0066] Specifically, the voltage stabilizing circuit includes a voltage stabilizing chip U1, wherein pin 1 of the voltage stabilizing chip U1 is connected to an input voltage (VCC) through resistors R6 and R7 in sequence, and resistors R4 are connected to both ends of the resistor R7, and pin 1 of the voltage stabilizing chip U1 is electrically connected to pin 3 in another way, and pin 2 of the voltage stabilizing chip U1 is connected to a reference voltage (VREF) through a common terminal of resistors R6 and R7, and the common terminal of resistors R6 and R7 is also grounded through a capacitor C10;

[0067] The voltage stabilizing circuit also includes resistor R2, resistor R3, resistor R22, resistor R24, resistor R15 and resistor R16. The reference voltage VREF_3.0V is grounded through resistor R2 and resistor R3 in sequence, and the common end of resistor R2 and resistor R3 outputs the reference voltage VREF_2.573V. The reference voltage VREF_3.0V is grounded through resistor R22 and resistor R24 ​​in sequence, and the common end of resistor R22 and resistor R24 ​​outputs the reference voltage VREF_1V. The reference voltage VREF_3.0V is grounded through resistor R15 and resistor R16 in sequence, and the common end of resistor R15 and resistor R16 outputs the reference voltage VREF_2.573V.

[0068] More specifically, the first delay circuit includes a first comparator U6-B, pin 7 of the first comparator U6-B is connected to a reference voltage via a resistor R28 and a resistor R27 is connected in series between pin 7 and pin 5 of the first comparator U6-B, and pin 6 of the first comparator U6-B is grounded via a capacitor C9;

[0069] The second delay circuit includes a second comparator U2-B and a third comparator U2-A. Pin 6 of the second comparator U2-B is electrically connected to pin 7 of the first comparator U6-B. Pin 7 of the first comparator U6-B outputs a first level WKUP. Pin 7 of the second comparator U2-B is connected to a reference voltage through a resistor R41. Pin 7 of the second comparator U2-B is electrically connected to pin 2 of the third comparator U2-A through a resistor R23. Pin 7 of the second comparator U2-B outputs a second level WKIP1. Pin 2 of the third comparator U2-A is also grounded through a capacitor C17. A resistor R39 is connected in series between pins 3 and 1 of the third comparator U2-A. Pin 1 of the third comparator U2-A outputs a third level EN through a resistor R50. Pin 1 of the third comparator U2-A is also connected to a reference voltage through a resistor R52.

[0070] Furthermore, pin 1 of the first driver chip U3 is connected to signal U1 in one way, and pin 1 of the first driver chip U3 is connected to signal A1- through resistor R31 in another way, and resistor R32 is connected in parallel at both ends of resistor R31. Pin 7 of the first driver chip U3 is connected to signal V1 in one way, and pin 7 of the first driver chip U3 is connected to signal B1- through resistor R42 in another way, and resistor R43 is connected in parallel at both ends of resistor R42. Pin 9 of the first driver chip U3 is connected to signal W1 in one way, and pin 9 of the first driver chip U3 is connected to signal Z1- through resistor R44 in another way, and resistor R45 is connected in parallel at both ends of resistor R44.

[0071] Furthermore, pin 1 of the second driver chip U5 is connected to signal U, a pin of the second driver chip U5 is connected to the third level EN, pin 7 of the second driver chip U5 is connected to signal W, pin 9 of the second driver chip U5 is connected to signal V, pin 16 of the second driver chip U5 is grounded through capacitor C41 and another pin 16 is connected to the input voltage.

[0072] Preferably, the first driving chip U3 and the second driving chip U5 can input any signal generated by the photocell.

[0073] Preferably, signal A, signal A+, signal A- and signal A1- are all signals A in different forms, and so on.

[0074] It is worth mentioning that the technical features such as input voltage, encoding disk and rotating shaft involved in the patent application of this invention should be regarded as prior art. The specific structure, working principle and possible control method and spatial layout method of these technical features can be selected according to the conventional selection in the field, and should not be regarded as the inventive point of the patent of this invention. The patent of this invention will not be further elaborated.

[0075] For those skilled in the art, it is still possible to modify the technical solutions described in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for processing a line-saving encoder, which realizes voltage stabilization and signal switching through a line-saving encoder, characterized in that: The following steps are involved: Step S1: passing the input voltage of the line-saving encoder into the voltage stabilizing circuit and the photocell respectively, so that the input voltage of the voltage stabilizing circuit is stabilized at a reference voltage, and the reference voltage is input into the first driving chip after passing through the first delay circuit and the second delay circuit in sequence; Step S2: The second driving chip outputs the first signal or the second signal generated by the photocell, and switches between the first signal and the second signal through a resistor network or a single chip microcomputer; A first signal including three signals A, B and Z generated by a photocell is input into a second driving chip through a resistor network, a second signal including three signals U, V and W generated by the photocell is input into the first driving chip, and a third signal including three signals U+, V+ and W+ generated after the second signal passes through the first driving chip is input into the second driving chip; during a first time when a threshold voltage is reached after power-on of the line-saving encoder and a second time after the threshold voltage is reached, the second driving chip maintains an output high-impedance state, and after the second time ends, the second driving chip is set by the first driving chip to output a second signal including three signals U, V and W; after the third time, the first driving chip maintains an output high-impedance state, and the second driving chip outputs a first signal including three signals A, B and Z, thereby realizing switching between the first signal including three signals A, B and Z and the second signal including three signals U, V and W; Or a first signal including three signals U, V and W generated by the photocell is input into a second driving chip through a resistor network, a second signal including three signals A, B and Z generated by the photocell is input into the first driving chip, and a third signal including three signals A+, B+ and Z+ generated after the second signal passes through the first driving chip is input into the second driving chip; during a first time when the threshold voltage is reached after the line-saving encoder is powered on and a second time after the threshold voltage is reached, the second driving chip maintains an output high-impedance state, and after the second time ends, the second driving chip is set by the first driving chip to output a first signal including three signals U, V and W; after the third time, the first driving chip maintains an output high-impedance state, and the second driving chip outputs a second signal including three signals A, B and Z, thereby realizing switching between the second signal including three signals A, B and Z and the first signal including three signals U, V and W; Alternatively, the first signal including the three signals A, B and Z generated by the photocell is input into the second driver chip through the resistor network, the second signal including the three signals U, V and W generated by the photocell is input into the single chip microcomputer, and the fourth signal including the three signals U+, V+ and W+ generated by the second signal passing through the single chip microcomputer is input into the second driver chip, the enable end of the second driver chip is controlled by the single chip microcomputer and the second driver chip enters a high impedance state until time point t2, and no signal is output; between time points t3-t4, the single chip microcomputer controls the second driver chip to The single-chip microcomputer enters a normal output state and outputs a second signal including three signals of U, V and W; after time point t4, the single-chip microcomputer stops outputting the fourth signal including three signals of U+, V+ and W+, and maintains a high impedance state, outputs the first signal including three signals of A, B and Z, and realizes the switching between the first signal including three signals of A, B and Z and the second signal including three signals of U, V and W. Time point t2 is the moment of starting to output the signal, time point t3 is the moment of stabilizing the output signal, and time point t4 is the moment of starting to output the A, B and Z signals.

2. A line-saving encoder processing method according to claim 1, characterized in that: Step S1 is specifically implemented as follows: Step S1.1: The input voltage generates a reference voltage after passing through the voltage stabilizing chip U1 of the voltage stabilizing circuit; Step S1.2: When the input voltage reaches the threshold voltage, the reference voltage starts to charge the reverse end of the first comparator, and after the charging is completed, the reverse end level is greater than the same direction end, and the first level is output; Step S1.3: the output end of the first comparator inputs the first level to the second comparator, and the second comparator outputs the second level; Step S1.4: The output terminal of the second comparator inputs the second level to the third comparator, and the third comparator outputs a third level.

3. A line-saving encoder for implementing the line-saving encoder processing method according to claim 1, comprising an encoder disk and a rotating shaft, wherein the encoder disk and the rotating shaft are fixedly connected, characterized in that: Also includes: A voltage stabilizing circuit, a photocell and a first driving chip, the input voltage of the input line-saving encoder is respectively passed into the voltage stabilizing circuit and the photocell, the voltage stabilizing circuit is used to stabilize the input voltage at a reference voltage and the voltage stabilizing circuit is electrically connected to the first driving chip through a first delay circuit and a second delay circuit in sequence; A second driving chip, a first element and a second element, the second driving chip is electrically connected to the first element or the second element, and the second driving chip is used to output the first signal or the second signal generated by the photocell.

4. A line-saving encoder according to claim 3, characterized in that: The voltage stabilizing circuit includes a voltage stabilizing chip U1, wherein pin 1 of the voltage stabilizing chip U1 is connected to the input voltage through resistors R6 and R7 in sequence, and resistors R4 are connected to both ends of the resistor R7, and pin 1 of the voltage stabilizing chip U1 is electrically connected to pin 3 in another way, and pin 2 of the voltage stabilizing chip U1 is connected to a reference voltage through the common terminal of the resistors R6 and R7, and the common terminal of the resistors R6 and R7 is also grounded through a capacitor C10; The voltage stabilizing circuit also includes resistor R2, resistor R3, resistor R22, resistor R24, resistor R15 and resistor R16. The reference voltage VREF_3.0V is grounded through resistor R2 and resistor R3 in sequence, and the common end of resistor R2 and resistor R3 outputs the reference voltage VREF_2.573V. The reference voltage VREF_3.0V is grounded through resistor R22 and resistor R24 ​​in sequence, and the common end of resistor R22 and resistor R24 ​​outputs the reference voltage VREF_1V. The reference voltage VREF_3.0V is grounded through resistor R15 and resistor R16 in sequence, and the common end of resistor R15 and resistor R16 outputs the reference voltage VREF_2.573V.

5. A line-saving encoder according to claim 4, characterized in that: The first delay circuit includes a first comparator U6-B, wherein the pin 7 of the first comparator U6-B is connected to a reference voltage via a resistor R28, a resistor R27 is connected in series between the pin 7 and the pin 5 of the first comparator U6-B, and the pin 6 of the first comparator U6-B is grounded via a capacitor C9; The second delay circuit includes a second comparator U2-B and a third comparator U2-A. Pin 6 of the second comparator U2-B is electrically connected to pin 7 of the first comparator U6-B. Pin 7 of the first comparator U6-B outputs a first level WKUP. Pin 7 of the second comparator U2-B is connected to a reference voltage through a resistor R41. Pin 7 of the second comparator U2-B is electrically connected to pin 2 of the third comparator U2-A through a resistor R23. Pin 7 of the second comparator U2-B outputs a second level WKIP1. Pin 2 of the third comparator U2-A is also grounded through a capacitor C17. A resistor R39 is connected in series between pins 3 and 1 of the third comparator U2-A. Pin 1 of the third comparator U2-A outputs a third level EN through a resistor R50. Pin 1 of the third comparator U2-A is also connected to a reference voltage through a resistor R52.

6. A line-saving encoder according to claim 5, characterized in that: Pin 1 of the first driver chip U3 is connected to signal U1 on one path, and pin 1 of the first driver chip U3 is connected to signal A1- through resistor R31 on another path, and resistor R32 is connected in parallel at both ends of resistor R31. Pin 7 of the first driver chip U3 is connected to signal V1 on one path, and pin 7 of the first driver chip U3 is connected to signal B1- through resistor R42 on another path, and resistor R43 is connected in parallel at both ends of resistor R42. Pin 9 of the first driver chip U3 is connected to signal W1 on one path, and pin 9 of the first driver chip U3 is connected to signal Z1- through resistor R44 on another path, and resistor R45 is connected in parallel at both ends of resistor R44.

7. A line-saving encoder according to claim 6, characterized in that: Pin 1 of the second driver chip U5 is connected to signal U, pin 4 of the second driver chip U5 is connected to the third level EN, pin 7 of the second driver chip U5 is connected to signal W, pin 9 of the second driver chip U5 is connected to signal V, pin 16 of the second driver chip U5 is grounded through capacitor C41 and another pin 16 is connected to the input voltage.

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