Integrated circuit including vertical capacitor

Abstract

In some examples, an integrated circuit includes a first plate (167), a second plate (168), and a dielectric layer (262) disposed between the first plate (167) and the second plate (168). The first plate (167), the second plate (168), and the dielectric layer (262) are disposed on an isolation region (250) of the integrated circuit, and they form a vertical capacitor (252).

Description

Background Art

[0001] A nonvolatile memory (NVM) bit cell is an electronic component configured to store information. The electrical state (e.g., threshold voltage) of a bit cell can be used to define a logic level, such as a logic low level (meaning a digital low or 0) or a logic high level (meaning a digital high or 1). This defined logic level can sometimes be referred to as the information (or bit) stored in the bit cell. Summary of the invention

[0002] According to at least one example, an integrated circuit includes a first plate, a second plate, and a dielectric layer disposed between the first plate and the second plate, wherein the first plate, the second plate, and the dielectric layer form a vertical capacitor, wherein the first plate, the second plate, and the dielectric layer of the vertical capacitor are disposed on an isolation region of the integrated circuit.

[0003] According to another example, an integrated circuit includes a floating gate flash memory bit cell, the floating gate flash memory bit cell includes at least a control gate layer, a word line gate layer and a dielectric layer. The integrated circuit also includes a vertical capacitor disposed on a shallow trench isolation (STI) region, the vertical capacitor includes the control gate layer, the word line gate layer and the dielectric layer, the dielectric layer is located between the control gate layer and the word line gate layer.

[0004] According to another example, a method of manufacturing an integrated circuit having at least one vertical capacitor on a shallow trench isolation (STI) region on a substrate includes depositing a first dielectric layer on the STI region; depositing a first polysilicon layer on the first dielectric layer; patterning the first polysilicon layer to form a first plate of the vertical capacitor having a sidewall; depositing a second dielectric layer so that the second dielectric layer contacts the sidewall; and depositing a second polysilicon layer so that the second polysilicon layer contacts the second dielectric layer, the second polysilicon layer forming a second plate of the vertical capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] FIG. 1( a ) depicts a portion of an illustrative layout of a floating gate flash bitcell memory array according to various examples.

[0006] FIG. 1( b ) depicts a side cross-section of a pair of illustrative bit cells according to various examples.

[0007] FIG. 1( c ) depicts an illustrative layout of a vertical capacitor array according to various examples.

[0008] FIG. 1( d ) depicts a side cross-section of a pair of illustrative vertical capacitors according to various examples.

[0009] Figure 2 Illustrative methods of performing fabrication of vertical capacitors according to various examples are depicted.

[0010] Figure 3(a)-3(g)Depicted is the fabrication of an illustrative bit cell according to various examples.

[0011] Figure 4(a)-4(g) Depicted is the fabrication of at least one vertical capacitor according to various examples. DETAILED DESCRIPTION

[0012] Flash memory is a non-volatile storage medium that can store information in an array of bit cells. This stored information (or "bit") can be electrically erased, programmed, and read. In some cases, an array of floating gate transistor bit cells can be used in flash memory. A floating gate transistor bit cell is similar to a standard metal oxide field effect transistor (MOSFET), except that the floating gate transistor bit cell contains multiple gates, such as a control gate and a floating gate. As described above, the electrical state of the bit cell can be used to define a logic level, which can be referred to as a bit stored in the bit cell. This can be performed using a threshold voltage change of the bit cell. The threshold voltage of a floating gate transistor bit cell may change due to the presence or absence of trapped charge in its floating gate, which further changes the threshold voltage of the floating gate transistor bit cell (relative to the old threshold voltage). When electrons are trapped in a floating gate transistor bit cell, the threshold voltage (or electrical state of the floating gate transistor bit cell) can be characterized as a digital low or "0", which is stored as a bit in the bit cell. Conversely, the electrical state when electrons are depleted in the floating gate can be referred to as a digital high or "1", which is stored as a bit in the bit cell.

[0013] As described above, the characteristics of the bit stored in the floating gate bit cell (e.g., digital high or low) depend on the presence or absence of charge in the floating gate. In some cases, the charge is stored / depleted in the floating gate by applying a voltage potential (e.g., greater than or equal to 10V) at the control gate of the floating gate transistor bit cell. In some cases, the voltage potential is applied using a charge pump circuit. An example charge pump circuit boosts the input charge to provide a higher voltage than the voltage supplied to it. In some cases, the charge pump circuit is capacitor-based, and typically, capacitor-based charge pump circuits employ capacitors such as metal-over-semiconductor (MOS).

[0014] MOS capacitors typically include a layer of metal (e.g., metal contacts), a layer of insulating material (e.g., silicon dioxide), and a layer of semiconductor material (e.g., silicon). These layers are typically fabricated laterally, and the manufacturing design of these capacitors results in parasitic capacitance between the substrate (e.g., a p-type silicon substrate) and the plate of the capacitor (e.g., an n-well), which interferes with the capacitance of the MOS capacitor and degrades its performance. To avoid parasitic capacitance interference, planar poly-to-poly capacitors or metal-to-poly capacitors are used in charge pumps. However, the manufacture of such capacitors requires additional masks, which increases the overall manufacturing cost. Therefore, an alternative design of a capacitor that can be used in a charge pump circuit and alleviate the above-mentioned problems is desired.

[0015] Therefore, at least some examples in this specification are directed to systems and methods for manufacturing vertical capacitors that can be used in floating gate flash memory bit cell technology. In at least some examples, the vertical capacitors described herein are manufactured on the same die as the floating gate flash memory bit cell without an additional mask. The vertical capacitors in this specification are located in an isolation region, such as a shallow trench isolation (STI) region. Providing a vertical capacitor on the STI region prevents interference from the above-mentioned parasitic capacitance (e.g., n-well to p-substrate). In at least some examples, the vertical capacitors utilize the word line gate layer and the control gate layer of the flash memory bit cell as their capacitor plates. In at least some examples, the control gate layer and the word line gate layer are separated by a dielectric layer that can include a multilayer structure.

[0016] FIG. 1( a) shows a portion of an illustrative layout 100 of a floating gate flash memory bit cell memory array (or floating gate bit cell) according to various examples. Layout 100 depicts at least some of the layers that form the floating gate bit cell array. Layout 100 includes bit line (BL) layers 106, 108, 110, 112, 114, and 116 and source line (SL) layers 124. Layout 100 also includes word line (WL) gate layers 118, 122, erase gate (EG) layers 120, and control gate (CG) layers 102, 104. The area occupied by BL layers 106, 108, 110, 112, 114, and 116 is sometimes referred to as an active area. Layout 100 also depicts at least some of the layers (e.g., WL gate layers 118, 122 and CG layers 102, 104) that form vertical capacitors to be utilized in charge pump circuits. This description is not limited to floating gate bit cell arrays that include the aforementioned gate layers. The following description of the vertical capacitor is valid for other types of floating gate bit cells, including floating gate bit cells that do not employ an erase gate layer.

[0017] Figure 1(a) also shows a coordinate system 1, wherein the X-axis and Y-axis of the coordinate system 1 are each located in the page of the drawing, and the Z-axis is away from (outward from) the page of the drawing. For example, from the perspective of layout 100 (as shown in Figure 1(a)), one or more bit cells are located on line 50 aligned with the Y axis; however, from the perspective of manufacturing (as shown in Figure 1(b)), a side view of a cross section of one or more bit cells can be observed in the YZ plane along line 50.

[0018] At least in part, layout 100 is used as a layout (or blueprint) to fabricate a floating gate bit cell array and a vertical capacitor array that are implemented with a CMOS logic array (not explicitly depicted). In some instances, layout 100 can be used to fabricate a bit cell array that is implemented as a standalone memory device (e.g., implemented on its own semiconductor die, packaged within its own chip package, etc.). In some instances, layout 100 can be used to fabricate a bit cell array that is implemented in an integrated circuit (IC) (e.g., implemented on a semiconductor die that includes additional circuitry).

[0019] 1(b), a side cross-section of a pair of illustrative bit cells 70, 80 can be observed in the YZ plane along line 50 (FIG. 1(a)) through bit line layer 112. Other bit cells can be observed in the YZ plane along other bit lines 106, 108, 110, 114, and 116 present on the Y axis.

[0020] The bit cells 70 and 80 are substantially similar in structure. The bit cell 70 includes a bit line layer 112 disposed in a substrate 126. The bit cell 70 also includes a word line (WL) gate layer 118, a control gate layer 102, a floating gate layer 132, and an erase gate layer 120 (also shared by the bit cell 80). A dielectric layer 142 is located above the control gate layer 102. The bit cell 70 further includes dielectric layers 138, 140. These dielectric layers are manufactured to provide isolation between the word line gate layer 118, the control gate layer 102, the floating gate layer 132, and the erase gate layer 120. In some examples, the substrate 126 may include silicon. In such examples, the dielectric layer 140 may include silicon dioxide, and the dielectric layer 138 may include silicon nitride. The bit cell 70 also includes a dielectric layer 111, which acts as a floating gate dielectric and provides isolation between the floating gate 132 and the substrate 126. The bit cell 70 forms a WL transistor, which includes a WL gate layer 118 (similar to the gate of a MOSFET), a bit line layer 112 (similar to the drain of a MOSFET), and a source line layer 124 (similar to the source of a MOSFET). The bit cell 70 also includes an implant layer 128 disposed below the word line gate layer 118 in the substrate 126. In some examples, the implant layer 128 can be used to change the threshold voltage of the WL transistor. In some examples, the substrate 126 also includes additional implant layers, such as an anti-punch-through layer 136 formed by implanting dopants (e.g., boron) in the substrate 126. Although the bit cell 70 (or an array of such bit cells) depicted in FIG. 1( b) includes an erase gate layer 120, a control gate layer 102, a word line gate layer 118, and a floating gate layer 132, this description is not limited to a floating gate bit cell 70 including the aforementioned gate layers. This description is valid for a floating gate bit cell array, where each floating gate bit cell includes a word line gate layer 118 , a control gate layer 102 , and a floating gate layer 132 .

[0021] Similar to bit cell 70, bit cell 80 includes a bit line layer 112, a source line layer 124, an erase gate layer 120, a floating gate layer 134, a control gate layer 104, and a word line gate layer 122. A dielectric layer 144 is located above the control gate layer 104, and an injection layer 130 is located below the word line gate layer 122. Bit cell 80 also includes dielectric layers 146, 148, which isolate the word line gate layer 122, the control gate layer 104, the floating gate layer 134, and the erase gate layer 120 from each other. Bit cell 80 also includes a dielectric layer 111, which acts as a floating gate 134 dielectric and provides isolation between the floating gate 132 and the substrate 126. In some examples, the substrate 126 may include silicon. In such examples, the dielectric layer 146 may include silicon dioxide, and the dielectric layer 148 may include silicon nitride. In some examples, the word line gate layers 118 , 122 and the control gate layers 102 , 104 include polysilicon.

[0022] In some examples, the bitcells 70 , 80 may be fabricated in an integrated circuit (IC) (eg, implemented on a semiconductor die that includes additional circuitry).

[0023] As described above, vertical capacitors are formed with word line gate layers and control gate layers on the same die as the floating gate bit cell array. Unlike the bit cells 70, 80 fabricated on the substrate 126, the vertical capacitors are fabricated on an isolation region (e.g., STI region) to prevent parasitic capacitance interference. Although the present specification generally describes vertical capacitors on a single STI region, in some examples, multiple vertical capacitors are distributed across multiple isolation regions (e.g., STI regions).

[0024] 1( c ) depicts an illustrative layout 160 of a vertical capacitor array formed with control gate layers 167, 169, 171 ... 237 and word line gate layers 166, 168, 170 ... 236 of a bit cell (not explicitly shown) disposed in the same die as the vertical capacitor. The layout 160 includes a contact layer 162 coupled to each of the control gate layers 167, 169, 171 ... 237. The layout 160 also includes a contact layer 164 coupled to each of the word line gate layers 166, 168, 170 ... 236. In some examples, the word line gate layers 166, 168, 170 ... 236 and the control gate layers 167, 169, 171, 237 include polysilicon.

[0025] In some examples, layout 160 can be used with layout 100 to fabricate a vertical capacitor and bitcell array that is implemented in an integrated circuit (IC) (eg, implemented on a semiconductor die that includes additional circuitry).

[0026] FIG. 1( d ) shows a side cross-section of a vertical capacitor disposed along a portion of line 165 ( FIG. 1( c )). FIG. 1( d ) depicts vertical capacitors 251-260 disposed on an STI region 250 located on a substrate 126. The capacitor depicted in FIG. 1( d ) includes wordline gate layers 166, 168, 170, 172, 174, and 176 and control gate layers 167, 169, 171, 173, and 175. For example, the wordline gate layer 166 acts as one of the plates of the vertical capacitor 251, while the control gate layer 167 acts as another of the plates. In some instances, a dielectric layer 261 is disposed between the wordline gate layer 166 and the control gate layer 167. In some instances, such a dielectric layer 261 may include a three-layer structure. In some instances, such a three-layer structure includes two dielectric layers 271 as oxide layers and a dielectric layer 272 as a nitride layer. In the example where the substrate comprises silicon, dielectric layer 271 comprises silicon dioxide, and dielectric layer 272 comprises silicon nitride. Other materials may also be used.

[0027] Similar to the vertical capacitor 251 formed between the word line gate 166 and the control gate 167, a vertical capacitor 252 is formed between the control gate layer 167 and the word line gate layer 168, and a dielectric layer 262 is disposed therebetween. Similar to the vertical capacitor 251, a vertical capacitor 252 is also disposed on the STI region 250. In some examples, the dielectric layer 262 includes a three-layer structure. In some examples, the three-layer structure includes two dielectric layers 296 as oxide layers and a dielectric layer 297 as a nitride layer. In an example where the substrate includes silicon, the dielectric layer 296 includes silicon dioxide, and the dielectric layer 297 includes silicon nitride. Similar to vertical capacitors 251, 252, vertical capacitors 253-260 are formed between word line gate layers 168, 170, 172, 174 and 176 and control gate layers 169, 171, 173 and 175 on STI region 250, wherein each of vertical capacitors 253-260 includes a dielectric layer, which may include a three-layer structure.

[0028] Reference Figure 2 , the illustrative method 300 may be performed to fabricate a vertical capacitor located on an STI region. Figure 3(a)-3(g) and Figure 4(a)-4(g) 3(a)-3(g) depict the fabrication of an illustrative bit cell including at least one control gate layer and a word line gate layer, and FIGS. 4(a)-4(g) depict the fabrication of at least one vertical capacitor that employs the control gate layer and word line gate layer of the bit cell mentioned above to form its parallel plates.

[0029] Figure 3(a)-3(g) The steps depicted in FIG. 1( a ) can be viewed along line 50 ( FIG. 1( a )), and Figure 4(a)-4(g) The steps depicted in can be observed along line 165 (Figure 1(c)).

[0030] For simplicity, the steps for fabricating a single bit cell are depicted in FIGS. 3(a)-3(g), and the steps for fabricating at least one vertical capacitor formed using the control gate layer and word line gate layer of the bit cell are depicted in FIGS. 4(a)-4(g). However, in other examples, the description may be applicable to the fabrication of multiple bit cells and vertical capacitors.

[0031] Method 300 begins by obtaining a substrate 126 (step 310) including STI regions, such as STI region 401 (FIG. 4(a)), which includes silicon dioxide. In semiconductor device manufacturing, STI regions are created before forming other electronic components (e.g., transistors, bit cells). In some examples, the fabrication of STI regions includes etching a pattern of trenches ( Figure 3(a)-3(g)4(a)-4(g)). Further steps in the fabrication of the STI regions include depositing one or more dielectric materials (e.g., silicon dioxide) to fill the trenches and then removing excess dielectric material using a planarization technique (e.g., chemical mechanical planarization).

[0032] In some examples, additional steps (not explicitly included in method 300) may be performed after step 310. The additional steps may include depositing a dielectric layer 405 and a floating gate layer 410 to form a portion of a bit cell (see Figures 3(a) and 3(b) respectively). The deposition of the floating gate layer 410 can be observed in Figure 4(b); however, the deposition of the dielectric layer 405 is masked to include it in the fabrication of the bit cell. In some examples, the dielectric layer 405 can be fabricated such that the dielectric layer 405 is disposed on the STI region 401 (not explicitly depicted in Figure 4(b)). In some examples, the floating gate layer 410 includes polysilicon. In some examples, the aforementioned deposition steps may be performed using chemical vapor deposition.

[0033] In some examples, from the perspective of the vertical capacitor, the method 300 may further include removing the floating gate layer 410 from the STI region 401 ( FIG. 4( c )). The floating gate layer 410 may be removed using a masking technique and a dry / wet etching technique, such that the floating gate layer 410 is removed from the STI region 401 ( FIG. 4( c )), rather than from the dielectric layer 405 of FIG. 3( c ). In some examples, the floating gate layer 410 may be removed from the STI region 401 using a chemical mechanical polishing technique.

[0034] After removing the floating gate layer 410 from the STI region 401, the method 300 can proceed to step 320, which can include depositing a dielectric layer 413. From the perspective of the vertical capacitor, the dielectric layer 413 is deposited on the STI region 401 (Figure 4(c)), and from the perspective of the bit cell, the dielectric layer 413 is deposited on the floating gate layer 410 (Figure 3(c)). In some examples, the dielectric layer 413 can include a three-layer structure. In some examples, this three-layer structure includes two dielectric layers 412, 416 including silicon dioxide and a dielectric layer 414 including silicon nitride. In some examples, step 320 can also include implanting dopants (e.g., boron) into the substrate 126 to form an anti-punch-through layer 136 (Figure 3(c)).

[0035] Then, the method 300 moves to step 330, which includes depositing a control gate layer 420 on the dielectric layer 413. The control layer 420 can be viewed from the perspective of the vertical capacitor (FIG. 4(c)) and the bit cell (FIG. 3(c)). In some examples, step 330 can also include depositing a dielectric layer 430 on the control gate layer 420. Again, the dielectric layer 430 can be viewed from the perspective of the vertical capacitor (FIG. 4(c)) and the bit cell (FIG. 3(c)). In some examples, the deposition of the control gate layer 420 and the dielectric layer 430 can be performed using chemical vapor deposition. In some examples, the control gate layer 420 includes polysilicon and the dielectric layer 430 includes silicon nitride.

[0036] Then, the method 300 may move to step 340, which includes placing the control gate layer 420 ( Figure 3(d) and 4(d) ) patterning. The patterning can be performed using photolithography and dry plasma etching. From the perspective of the vertical capacitor, after step 340, the control gate layer 420 or at least some portion of the control gate layer 420 forms the first plate of the vertical capacitor. As described above, for simplicity, method 300, Figure 3(a)-3(g) and Figure 4(a)-4(g) The formation of a single bit cell and at least one vertical capacitor is described. In other examples, patterning may be performed such that multiple bit cells and vertical capacitors may be formed. FIG. 4( d ) shows the sidewalls 2 , 3 of the patterned control gate layer 420 .

[0037] The method 300 may proceed to step 350, which includes depositing a dielectric layer 417 on the sidewalls 2, 3 of the control gate layer 420 (FIG. 4(e)). The deposition of the dielectric layer 417 may also be observed in FIG. 3(e). Although FIG. 4(e) depicts the dielectric layer 417 adjacent to the control gate layer 420 and the dielectric layer 430 (e.g., the deposition of the dielectric layer 417 may extend from the top of the dielectric layer 416 to the top of the dielectric layer 430), in some examples, the dielectric layer 417 is adjacent only to the control gate layer 420. In some examples, after the deposition of the dielectric layer 417, a portion of the floating gate layer 410 may be etched / removed, followed by further implantation of dopants (such as boron) into the substrate 126. In some examples, the dielectric layer 417 has a three-layer structure, which includes dielectric layers 421, 422, 423. In some examples, dielectric layers 421 , 423 include silicon dioxide, and dielectric layer 422 includes silicon nitride.

[0038] Then, method 300 may proceed to step 360, which includes depositing polysilicon layer 424 such that polysilicon layer 424 is disposed on top of dielectric layer 416, dielectric layers 421, 422, 423, and dielectric layer 430 ( Figure 3(f) , 3(g), 4(f) and 4(g)). Step 360 may also include etching a portion of polysilicon layer 424 to form two separate polysilicon layers 415 and 418 ( Figure 3(g) and 4(g) ), which are called word line gate layer and erase gate layer respectively.

[0039] Certain modifications may be made to the described embodiments and other embodiments within the scope of the claims.

Claims

1. An integrated circuit, comprising: First board; Second board; Third board; a first dielectric layer disposed between the first plate and the second plate; as well as a second dielectric layer disposed between the second plate and the third plate, The first plate, the second plate and the first dielectric layer form a first vertical capacitor, and the second plate and the third plate are used for a second vertical capacitor, wherein the first plate, the second plate and the third plate and the first dielectric layer and the second dielectric layer are arranged on the same isolation region of the integrated circuit, and wherein the first plate and the third plate contact the upper surface of the isolation region and the second plate is separated from the upper surface by the third dielectric layer. 2 . The integrated circuit of claim 1 , wherein the integrated circuit further comprises a flash memory bit cell, the flash memory bit cell comprising at least the first plate and the second plate.

3. The integrated circuit of claim 1, wherein the first and second dielectric layers comprise a first silicon dioxide layer, a second silicon dioxide layer, and a silicon nitride layer. The integrated circuit according to claim 1 , wherein the isolation region is disposed on a silicon substrate. 5 . The integrated circuit of claim 1 , wherein the isolation region comprises a shallow trench isolation (STI) region.

6. The integrated circuit of claim 1 wherein the isolation region comprises silicon dioxide.

7. An integrated circuit comprising: A first floating gate flash memory bit cell including at least a first control gate layer, a first word line gate layer, and a first dielectric layer; A second floating gate flash memory bit cell including at least a second control gate layer, a second word line gate layer, and a second dielectric layer; A first vertical capacitor is disposed on a shallow trench isolation (STI) region, wherein the first vertical capacitor comprises the first control gate layer, the first word line gate layer and the first dielectric layer, wherein the first dielectric layer is located between the first control gate layer and the first word line gate layer; as well as a second vertical capacitor disposed on the STI region, the second vertical capacitor comprising the second control gate layer, the second word line gate layer and the second dielectric layer, the second dielectric layer being located between the second control gate layer and the second word line gate layer; The first word line gate layer and the second word line gate layer contact an upper surface of the STI region, and the first control gate layer and the second control gate layer are separated from the upper surface by a third dielectric layer. 8 . The integrated circuit of claim 7 , wherein the first and second control gate layers and the first and second word line gate layers comprise polysilicon.

9. The integrated circuit of claim 7 wherein the STI regions comprise silicon dioxide.

10. The integrated circuit of claim 7, wherein the STI region is disposed on a silicon substrate. 11 . The integrated circuit of claim 7 , further comprising a first floating gate layer, the first dielectric layer being located between the first control gate layer and the first floating gate layer.

12. The integrated circuit of claim 7, wherein the first dielectric layer comprises at least one silicon dioxide layer.

13. The integrated circuit of claim 7, wherein the first dielectric layer comprises a first silicon dioxide layer, a second silicon dioxide layer, and a silicon nitride layer.

14. A method of manufacturing an integrated circuit having at least a first vertical capacitor and a second vertical capacitor on a shallow trench isolation (STI) region on a substrate, comprising: depositing a first dielectric layer on the STI region; depositing a first polysilicon layer on the first dielectric layer; patterning the first polysilicon layer to form a first plate of the first vertical capacitor having a first sidewall and a first plate of the second vertical capacitor having a second sidewall; depositing a second dielectric layer such that the second dielectric layer contacts the first sidewall and the second sidewall; as well as depositing a second polysilicon layer such that the second polysilicon layer contacts the second dielectric layer, the second polysilicon layer forming a second plate of the first vertical capacitor and a second plate of the second vertical capacitor; The first plate of the first vertical capacitor and the first plate of the second vertical capacitor contact an upper surface of the STI region and the second plate is spaced apart from the upper surface by a third dielectric layer.

15. The method of claim 14, wherein the first dielectric layer comprises a first silicon dioxide layer, a second silicon dioxide layer, and a silicon nitride layer.

16. The method of claim 14, wherein the second dielectric layer comprises a first silicon dioxide layer, a second silicon dioxide layer, and a silicon nitride layer. The method of claim 14 , wherein the STI region comprises silicon dioxide.

Images