Display device

Abstract

A display device is provided. The display device includes: a display panel including a plurality of connection signal wirings having different voltage values; a flexible circuit board attached to a side surface of the display panel, including a base film and a plurality of guiding wirings disposed on the base film; and an anisotropic conductive film disposed between the plurality of connection signal wirings and the plurality of guiding wirings. When a potential difference between two adjacent connection signal wirings among the plurality of connection signal wirings is equal to or greater than a first voltage value, at least one bump wiring having a predetermined voltage value is disposed between the two adjacent connection signal wirings.

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] With the development of multimedia, the importance of display devices is increasing. In response to this, various display devices such as liquid crystal display devices (Liquid Crystal Display, LCD) and organic light emitting display devices (Organic Light Emitting Display, OLED) are being used.

[0003] Among display devices, a liquid crystal display device is one of the most widely used flat panel display devices at present, including two substrates formed with electric field generating electrodes such as pixel electrodes and common electrodes, and a liquid crystal layer inserted therebetween. A voltage is applied to the electric field generating electrodes to generate an electric field in the liquid crystal layer, and the orientation of liquid crystal molecules in the liquid crystal layer is determined by this electric field and the polarization of incident light is controlled to display an image.

[0004] On the other hand, a printed circuit board including a plurality of signal wirings for driving a display device and a plurality of guiding wirings connected to the plurality of signal wirings is also required. A display device includes a display area for displaying an image and a portion surrounding the display area and not displaying an image, that is, a bezel. In order to achieve a bezel-less, the signal wirings and the guiding wirings can be side-bonded on the side surface of the display device. Summary of the Invention

[0005] The problem that the present invention wants to solve is to provide a display device that can use bump wirings to reduce the phenomenon of wiring corrosion.

[0006] The problems of the present invention are not limited to the above-mentioned technical problems, and those skilled in the art should clearly understand other technical problems not mentioned through the following description.

[0007] An embodiment of the present invention relates to a display device, including: a display panel including a plurality of connection signal wirings having different voltage values; a flexible circuit board attached to a side surface of the display panel, including a base film and a plurality of guiding wirings disposed on the base film; and an anisotropic conductive film disposed between the plurality of connection signal wirings and the plurality of guiding wirings. When the potential difference between two adjacent connection signal wirings among the plurality of connection signal wirings is equal to or greater than a first voltage value, at least one bump wiring having a predetermined voltage value is disposed between the two adjacent connection signal wirings.

[0008] The display device according to an embodiment of the present invention can use bump wirings to reduce the phenomenon of wiring corrosion.

[0009] The effects according to the present invention are not limited to those exemplified above, and more effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a perspective view of a display device according to an embodiment of the present invention.

[0011] Figure 2 It is a block diagram of a display device according to an embodiment of the present invention.

[0012] Figure 3 It is a diagram showing Figure 1 an example of pixels.

[0013] Figure 4 It is a diagram showing Figure 1 other examples of pixels.

[0014] Figure 5 It is Figure 2 a block diagram of a gate driving IC.

[0015] Figure 6 It is a cross-sectional view taken along the I-I' line of Figure 1 ...

[0016] Figure 7 It is a diagram showing Figure 1 an enlarged cross-sectional view of a portion taken by cutting the bonding portion between the flexible circuit board and the display panel of the display device in a plane parallel to the display panel.

[0017] Figure 8 It is a diagram showing Figure 1 a side view of the conductive paste portion of the display device.

[0018] Figure 9 It is Figure 1 an exploded perspective view of the display device.

[0019] Figure 10 It is a diagram showing Figure 9 a pad portion.

[0020] Figure 11 It is a diagram showing the configuration relationship of connection signal wirings, pad electrodes, and guiding wirings according to an embodiment.

[0021] Figure 12 It is a diagram showing the configuration relationship of connection signal wirings, pad electrodes, and guiding wirings according to another embodiment.

[0022] Figure 13 It is a diagram showing the configuration relationship of connection signal wirings, pad electrodes, and guiding wirings according to still another embodiment.

[0023] Figure 14It is a diagram showing the configuration relationship of the connection signal wiring, pad electrodes, and guiding wiring related to another embodiment.

[0024]

Symbol Explanation

[0025] 100: Lower substrate; 200: Upper substrate; 120: Connection part; 310: ACF film; 400: Flexible circuit board; PDE: Pad electrode; LE: Guiding wiring; BL1, BL2, BL3: First bump wiring to third bump wiring. Detailed Embodiment

[0026] Figure 1 It is a perspective view of a display device according to an embodiment of the present invention.

[0027] Referring to Figure 1 , the display device 1 may include a display panel DP and a flexible circuit board 400 attached to the side surface of the display panel DP. The display panel DP may include a lower substrate 100 and an upper substrate 200. The flexible circuit board 400 may include a base film 410 and a driving circuit unit DIC disposed on the base film 410.

[0028] An image can be displayed in the display area DA on the upper substrate 200 of the display panel DP. The display panel DP can display an image in the display area DA on a plane formed by a first direction D1 and a second direction D2 perpendicular to the first direction D1. No image is displayed in the peripheral area NDA surrounding the display area DA. That is, the peripheral area NDA corresponds to the bezel of the display device 1.

[0029] The flexible circuit board 400 can be attached to the side surface of the display panel DP. That is, the flexible circuit board 400 is attached to the side surfaces of the lower substrate 100 and the upper substrate 200, so that a display device 1 with a minimized width of the area where no image is displayed, that is, the bezel, can be realized. The flexible circuit board 400 extends in a third direction D3 perpendicular to the first direction D1 and the second direction D2 and is bent toward the back surface of the display panel DP, so that the driving circuit unit DIC can be configured to overlap with the upper substrate 200 and the lower substrate 100.

[0030] The driving circuit unit DIC can generate signals for driving the display panel DP of the display device 1. The driving circuit unit DIC can be electrically connected to the display panel DP through the conductive pattern (refer to Figure 6 420) of the flexible circuit board 400. For example, the driving circuit unit DIC can be an integrated circuit IC mounted on the base film 410.

[0031] Figure 2 It is a block diagram showing the display device 1 according to an embodiment of the present invention.Figure 3 is an exemplary diagram of a pixel representing Figure 1 . Figure 4 is another exemplary diagram of a pixel representing Figure 1 .

[0032] Referring to Figure 2 , the display device 1 according to an embodiment of the present invention includes a gate driving unit GD, a data driving unit DD, and a timing control unit TC.

[0033] The display device 1 according to an embodiment of the present invention may include any display device 1 that provides data voltages to pixels through line-by-line scanning by sequentially providing gate signals to gate lines G1 to Gn. For example, the display device 1 according to an embodiment of the present invention may be implemented by any one of a liquid crystal display device, an organic light emitting display device, a field emission display device, and an electrophoresis display device.

[0034] The display panel DP includes an upper substrate 200 and a lower substrate 100. In the lower substrate 100, a pixel array PA including data lines D1 to Dm (m is a positive integer of 2 or more), gate lines G1 to Gn (n is a positive integer of 2 or more), and pixels P is formed. The pixel P may be connected to any one of the data lines D1 to Dm and any one of the gate lines G1 to Gn. Thus, when a gate signal is provided to the gate lines G1 to Gn, the pixel P receives the supply of data voltages of the data lines D1 to Dm and emits light with a predetermined brightness according to the received data voltages.

[0035] In the case where the display device 1 is implemented by a liquid crystal display device, each pixel P may respectively include a transistor T, a pixel electrode PE, and a storage capacitor Cst as Figure 3 shown. The transistor T supplies the data voltage of the j-th (j is a positive integer satisfying 1 ≤ j ≤ m) data line Dj to the pixel electrode PE in response to the gate signal of the k-th (k is a positive integer satisfying 1 ≤ k ≤ n) gate line Gk. Thus, each pixel P drives the liquid crystal molecules of the liquid crystal layer LC according to the electric field generated by the potential difference between the data voltage supplied to the pixel electrode PE and the common voltage supplied to the common electrode CE, and thus may adjust the amount of light transmitted from the backlight unit. The common electrode CE receives the supply of the common voltage from the common voltage line VcomL, and the backlight unit is disposed below the display panel DP and irradiates uniform light to the display panel DP. In addition, the storage capacitor Cst is provided between the pixel electrode PE and the common electrode CE to maintain a certain level of voltage difference between the pixel electrode PE and the common electrode CE.

[0036] In the case where the display device 1 is implemented by an organic light-emitting display device, each pixel P may include an organic light-emitting diode OLED, a scanning transistor ST, a driving transistor DT, and a storage capacitor Cst as shown below. The scanning transistor ST supplies the data voltage of the j-th data line Dj to the gate electrode of the driving transistor DT in response to the scanning signal of the k-th scanning line Sk. The driving transistor DT controls the driving current flowing from the high potential voltage line VDDL to the organic light-emitting diode OLED according to the data voltage supplied to its gate electrode. The organic light-emitting diode OLED is provided between the driving transistor DT and the low potential voltage line VSSL, and emits light with a predetermined luminance according to the driving current. The storage capacitor Cst may be provided between the gate electrode of the driving transistor DT and the high potential voltage line VDDL in order to maintain the voltage of the gate electrode of the driving transistor DT at a certain level. Figure 4 As shown, the gate driving unit GD may include a plurality of gate driving integrated circuits (hereinafter referred to as "ICs") GIC1, GIC2, GIC3. The gate driving ICs GIC1, GIC2, GIC3 are connected to the gate lines G1 to Gn. The gate driving ICs GIC1, GIC2, GIC3 receive the input of the gate control signal GCS from the timing control unit TC, and generate gate signals according to the gate control signal GCS and supply them to the gate lines G1 to Gn.

[0037] As shown in Figure 2 and Figure 5 The data driving unit DD may include a plurality of source driving ICs. The source driving ICs are connected to the data lines D1 to Dm. The source driving ICs receive the input of the digital video data DATA and the data control signal DCS from the timing control unit TC, and convert the digital video data DATA into an analog data voltage according to the data control signal DCS. The source driving ICs supply the data voltage to the data lines D1 to Dm.

[0038] The timing control unit TC receives the input of the digital video data DATA and the timing signal from an external system board (not shown). The timing signal may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock. The timing control unit TC generates a gate control signal GCS for controlling the operation timing of the gate driving unit GD and a data control signal DCS for controlling the operation timing of the data driving unit DD based on the timing signal.

[0039]

[0040] The gate control signal GCS includes a gate start signal (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), a selection signal (SEL), etc. The gate start signal is a signal for controlling the output timing of the first gate pulse during one frame. The gate shift clock is a clock signal for shifting the gate start signal. The gate output enable signal is a signal for controlling the output width of each gate signal. The selection signal is a signal for controlling the output of the start feedback signal and the carry signal of the gate driver IC.

[0041] The data control signal DCS includes a source start signal, a source sampling clock, a source output enable signal, a polarity control signal, etc. The source start signal is a signal for controlling the data sampling start time point of the data driver DD. The source sampling clock is a clock signal for controlling the sampling operation of the data driver DD based on the rising edge or the falling edge. The polarity control signal is a signal for reversing the polarity of the data voltage output from the data driver DD at a period of L (L is a natural number) levels. The source output enable signal is a signal for controlling the output of the data driver DD.

[0042] The timing control unit TC supplies digital video data DATA and the data control signal DCS to the data driver DD. The timing control unit TC supplies the gate control signal GCS to the gate driver GD.

[0043] The gate driver ICs GIC1, GIC2, and GIC3 can be fabricated using driver chips respectively. The gate driver ICs GIC1, GIC2, and GIC3 can be mounted on a gate flexible film respectively. The gate flexible film can be implemented by a tape carrier package or a chip on film respectively. The chip on film can include a base film such as polyimide and a plurality of conductive guiding lines disposed on the base film. The gate flexible film can be bent or folded respectively. The gate flexible film can be attached to the lower substrate 100 in a TAB (tape automated bonding) manner using an anisotropic conductive film, whereby the gate driver ICs GIC1, GIC2, and GIC3 can be connected to the gate lines G1 to Gn.

[0044] The source driver ICs can also be fabricated using driver chips respectively. The source driver ICs can be mounted on a source flexible film respectively. The source flexible film can be implemented by a tape carrier package or a chip on film respectively. The source flexible film can be bent or folded respectively. The source flexible film can be attached to the lower substrate 100 in a TAB manner using an anisotropic conductive film, whereby the source driver ICs can be connected to the data lines D1 to Dm.

[0045] In addition, although not shown, the source flexible film can be attached to a source printed circuit board. The source printed circuit board can be implemented by a flexible printed circuit board that can be bent or folded.

[0046] The timing control unit TC is mounted on a control printed circuit board. The control printed circuit board and the source printed circuit board can be connected by a flexible circuit board such as an FFC (flexible flat cable) or an FPC (flexible printed circuit). In addition, the control printed circuit board and the flexible circuit board can be omitted, and in this case, the timing control unit TC can be mounted on the source printed circuit board.

[0047] Figure 5 is a block diagram of Figure 2 the gate driver IC.

[0048] In Figure 5 an example is shown in which the display device 1 includes three gate driver ICs GIC1, GIC2, and GIC3 connected in a slave manner, but it should be noted that this is not limited thereto. That is, the display device 1 can include s (s is a positive integer of 2 or more) gate driver ICs connected in a slave manner.

[0049] Reference Figure 5 As shown in Figure 5 , the first gate driving ICGIC1 is connected to the gate start signal line GSPL, the gate shift clock line GSCL, and the gate output enable signal line GOEL. In addition, the first gate driving ICGIC1 is connected to the first gate line G1 to the p-th gate line Gp (p is a positive integer greater than or equal to 2). In addition, the first gate driving ICGIC1 is connected to the first carry signal line CL1.

[0050] The first gate driving ICGIC1 generates the first gate signal to the p-th gate signal that are sequentially output according to the gate start signal input through the gate start signal line GSPL, the gate shift clock input through the gate shift clock line GSCL, and the gate output enable signal input through the gate output enable signal line GOEL. The first gate driving ICGIC1 outputs the first gate signal to the p-th gate signal to the first gate line G1 to the p-th gate line Gp. The first gate driving ICGIC1 outputs a carry signal to the first carry signal line CL1.

[0051] The second gate driving ICGIC2 is connected to the first carry signal line CL1, the gate shift clock line GSCL, and the gate output enable signal line GOEL. In addition, the second gate driving ICGIC2 is connected to the (p + 1)-th gate line Gp+1 to the 2p-th gate line G2p. In addition, the second gate driving ICGIC2 is connected to the second carry signal line CL2.

[0052] The second gate driving ICGIC2 generates the (p + 1)-th gate signal to the 2p-th gate signal that are sequentially output according to the previous-stage carry signal input through the first carry signal line CL1, the gate shift clock input through the gate shift clock line GSCL, and the gate output enable signal input through the gate output enable signal line GOEL. The previous-stage carry signal input through the first carry signal line CL1 indicates the carry signal of the first gate driving ICGIC1. The second gate driving ICGIC2 outputs the (p + 1)-th gate signal to the 2p-th gate signal to the (p + 1)-th gate line Gp+1 to the 2p-th gate line G2p. The second gate driving ICGIC2 outputs a carry signal to the second carry signal line CL2.

[0053] The third gate driving ICGIC3 is connected to the second carry signal line CL2, the gate shift clock line GSCL, and the gate output enable signal line GOEL. In addition, the third gate driving ICGIC3 is connected to the (2p + 1)-th gate line G2p+1 to the 3p-th gate line G3p.

[0054] The third gate driving ICGIC3 generates the (2p + 1)-th gate signal to the 3p-th gate signal that are sequentially output according to the previous carry signal input through the second carry signal line CL2, the gate shift clock input through the gate shift clock line GSCL, and the gate output enable signal input through the gate output enable signal line GOEL. The previous carry signal input through the second carry signal line CL2 indicates the carry signal of the second gate driving ICGIC2. The third gate driving ICGIC3 outputs the (2p + 1)-th gate signal to the 3p-th gate signal to the (2p + 1)-th gate line G2p+1 to the 3p-th gate line G3p.

[0055] In an embodiment of the present invention, the previous stage gate driving IC of the r-th (r is a positive integer satisfying 2 ≤ r ≤ s) gate driving IC indicates the first gate driving IC to the (r - 1)-th gate driving IC. The subsequent stage gate driving IC of the r-th gate driving IC indicates the (r + 1)-th gate driving IC to the s-th gate driving IC. Thus, the previous carry signal input to the r-th gate driving IC indicates the carry signal of the previous stage gate driving IC of the r-th gate driving IC. For example, the previous carry signal input to the second gate driving ICGIC2 through the first carry signal line CL1 indicates the carry signal of the first gate driving ICGIC1.

[0056] As described above, the first gate driving ICGIC1 to the third gate driving ICGIC3 are connected in a subordinate manner and generate outputs sequentially, so that gate signals can be sequentially supplied to the first gate line G1 to the n-th gate line Gn.

[0057] The level shifter LVSH is connected to the gate driving ICGIC1, GIC2, GIC3 and receives the input of the output signals of the gate driving ICGIC1, GIC2, GIC3. In addition, the level shifter LVSH is connected to the gate on-voltage line VonL and receives the supply of the gate on-voltage Von, and the level shifter LVSH is connected to the gate off-voltage line VoffL and receives the supply of the gate off-voltage Voff.

[0058] The level shifter LVSH changes the voltage swing amplitude of each output signal of the gate driving ICGIC1, GIC2, GIC3 into a swing amplitude at which each transistor provided in the display panel DP can perform an operation. That is, the level shifter LVSH can change the voltage swing amplitude of the output signals of the gate driving ICGIC1, GIC2, GIC3 into a swing amplitude from the gate off-voltage Voff to the gate on-voltage Von. The gate on-voltage Von is equivalent to the on-voltage that can turn on the transistor provided in the display panel DP, and the gate off-voltage Voff is equivalent to the off-voltage that can turn off the transistor provided in the display panel DP. As Figure 3 and Figure 4As shown, when the transistors provided in the display panel DP are formed of N-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), the gate-on voltage Von can be set to a high gate voltage, and the gate-off voltage Voff can be set to a low gate voltage lower than the high gate voltage.

[0059] Figure 6 is a cross-sectional view taken along the Figure 1 I-I' line. Figure 7 is an enlarged cross-sectional view of a portion taken by cutting the bonding portion between the flexible circuit board of the display device Figure 1 and the display panel in a plane parallel to the display panel. Figure 8 is a side view showing the Figure 1 conductive paste portion of the display device.

[0060] Referring to Figure 1 , Figures 6 to 8 , the display device 1 may include a lower substrate 100, an upper substrate 200, and a liquid crystal layer LC located between the lower substrate 100 and the upper substrate 200. The lower substrate 100 may include a lower base substrate 110, a gate pattern, a first insulating layer 130, an active pattern ACT, a data pattern, a second insulating layer 140, and a pixel electrode PE in a display area DA. The upper substrate 200 may include an upper base substrate 210, a black matrix BM, a color filter CF, a protective coating 220, and a common electrode CE in the display area DA.

[0061] The lower base substrate 110 may include a transparent insulating substrate. For example, the lower base substrate 110 may be composed of a glass substrate, a quartz substrate, a transparent resin substrate, etc. In this case, the transparent resin substrate may include polyimide-based resins, acrylic-based resins, polyacrylate-based resins, polycarbonate-based resins, polyether-based resins, sulfonic acid-based resins, polyethylene terephthalate-based resins, etc.

[0062] The gate pattern may be disposed on the lower base substrate 110. The gate pattern may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. The gate pattern may include a gate electrode GE, a connection portion 120, and signal wirings for driving the display device 1.

[0063] The first insulating layer 130 may be disposed on the lower substrate 110 on which the gate pattern is formed. The first insulating layer 130 may include an inorganic insulating material. For example, the first insulating layer 130 insulates the gate pattern and may be formed of silicon oxide, metal oxide, or the like.

[0064] The active pattern ACT may be disposed on the first insulating layer 130. The active pattern ACT may include a semiconductor layer formed of amorphous silicon (a-Si:H) and a resistive contact layer formed of n + amorphous silicon (n + a-Si:H).

[0065] In addition, the active pattern ACT may include an oxide semiconductor. For example, the oxide semiconductor includes at least one of indium (In), zinc (Zn), gallium (Ga), tin (Sn), or hafnium (Hf) and may be formed of an amorphous oxide. The active pattern ACT may include a source region and a drain region doped with impurities, respectively, and include a channel region provided between the source region and the drain region.

[0066] The data pattern may be disposed on the active pattern ACT and the first insulating layer 130. The data pattern may be formed of metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, or the like. The data pattern may include a source electrode SE, a drain electrode DE, and signal wirings for driving the display device 1.

[0067] The gate electrode GE, the active pattern ACT, the source electrode SE, and the drain electrode DE may be included as components of the thin film transistor TFT.

[0068] The second insulating layer 140 may be disposed on the active pattern ACT, the data pattern, and the first insulating layer 130. The second insulating layer 140 may include an inorganic insulating material or an organic insulating material. For example, the second insulating layer 140 may include photoresist, acrylic resin, polyimide resin, polyamide resin, siloxane-based resin, or the like.

[0069] According to an exemplary embodiment, the second insulating layer 140 may have a substantially flat upper surface while sufficiently covering the active pattern ACT and the data pattern. According to other exemplary embodiments, the second insulating layer 140 may be formed with a substantially uniform thickness on the first insulating layer 130 on which the active pattern ACT and the data pattern are disposed.

[0070] The pixel electrode PE may be disposed on the second insulating layer 140. The pixel electrode PE may be electrically connected to the drain electrode DE of the thin film transistor TFT through a contact hole formed through the second insulating layer 140. The pixel electrode PE may include a transparent conductive material. For example, the pixel electrode PE may include indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0071] The upper substrate 210 may be configured to face the lower substrate 110. The upper substrate 210 may include a transparent insulating substrate. For example, the upper substrate 210 may be made of a glass substrate, a quartz substrate, a transparent resin substrate, etc. In this case, the transparent resin substrate may include polyimide-based resins, acrylic-based resins, polyacrylate-based resins, polycarbonate-based resins, polyether-based resins, sulfonic acid-based resins, polyethylene terephthalate-based resins, etc.

[0072] The black matrix BM may be disposed on the upper substrate 210. The black matrix BM may include a light-blocking material. The black matrix BM may be disposed to overlap the thin film transistor TFT.

[0073] The color filter CF may be disposed on the upper substrate 210 on which the black matrix BM is disposed. The color filter CF is used to provide color to the light that has passed through the liquid crystal layer LC. The color filter CF may be a red color filter, a green color filter, and a blue color filter. The color filter CF is provided corresponding to the pixels, and between adjacent pixels, the color filter CF may be configured to have mutually different colors. The color filter CF may be overlapped or separated from each other by the color filters of partially adjacent pixels at the boundaries of adjacent pixels.

[0074] The protective coating 220 may be formed on the color filter CF and the black matrix BM. The protective coating 220 serves to flatten the color filter CF while protecting the color filter CF and to perform an insulating function, and may be formed using an acrylic-based epoxy resin material.

[0075] The common electrode CE can be disposed on the protective coating 220. The common electrode CE can be configured to face the pixel electrode PE. The common electrode CE can include a transparent conductive material. For example, the common electrode CE can include indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0076] The liquid crystal layer LC can include liquid crystal molecules having optical anisotropy. The liquid crystal molecules are driven by an electric field and can transmit or block the light passing through the liquid crystal layer LC to display an image. The liquid crystal layer LC can be sealed in the peripheral region NDA by a sealing member 250 disposed between the lower substrate 110 and the upper substrate 210.

[0077] The display device 1 can include a lower substrate 110, a connection portion 120 disposed on the lower substrate 110, and an upper substrate 210 in the peripheral region NDA.

[0078] The connection portion 120 can include a plurality of signal wirings. The ends of the signal wirings are exposed on the side surface of the display device 1, and each signal wiring can be formed to be separated from each other along the second direction D2. That is, each signal wiring can be configured to be separated from each other along the extending direction of the side surface of the display panel.

[0079] The pad electrode PDE can be physically electrically connected to the connection portion 120. The pad electrode PDE can include a conductive paste. For example, the conductive paste can include a metal such as silver (Ag). Each pad electrode PDE can be formed to correspond to each signal wiring of the plurality of connection portions 120 respectively. The conductive paste lines can be formed to be separated from each other along the second direction D2. That is, the conductive paste lines can be configured to be separated from each other along the extending direction of the side surface of the display panel.

[0080] The pad electrode PDE can be formed by directly performing an inkjet method on the conductive paste on the side surface of the display panel or by using a patterning method such as a laser patterning method after applying the conductive paste on the side surface of the display panel, but is not limited thereto, and various known methods can be used to form it.

[0081] Each signal wiring can be electrically connected to the driving circuit unit DIC through the pad electrode PDE, the conductive beads 312 of the ACF film 310, and the guiding wiring. Thus, a plurality of electrical signals for driving the display device 1 can be respectively applied to the plurality of signal wirings. At this time, the driving circuit unit DIC can include a gate driving unit GD, a data driving unit DD, a timing control unit TC, and a power management integrated circuit, etc.

[0082] On the side surfaces of the lower base substrate 110 and the upper base substrate 210, a pad electrode PDE, an ACF film 310, and a flexible circuit substrate 400 can be sequentially disposed. The flexible circuit substrate 400 can include a base film 410 and a conductive pattern 420 disposed on the base film 410.

[0083] The ACF film 310 can be an anisotropic conductive film. That is, the ACF film 310 can have a structure including a plurality of conductive beads in a resin film. The conductive beads can have a structure in which a metal such as nickel (Ni) or gold (Au) is coated on the surface of a polymer particle. The resin film can include a thermosetting resin or a thermoplastic resin.

[0084] Preferably, the ACF film 310 can be a non-random array anisotropic conductive film. For example, the ACF film 310 can have a structure including a plurality of conductive beads 312, where the plurality of conductive beads 312 are arranged in a layer in a resin film having an adhesive force. At this time, the conductive beads 312 can be arranged in a matrix shape at regular intervals on a plane formed by a second direction D2 and a third direction D3. At this time, it is preferable that the thickness of the resin film of the ACF film 310 is equal to or less than the diameter of the conductive beads 312. Since the conductive beads 312 have a structure in which a metal is coated on the surface of a polymer particle, they have elasticity. Thus, even if the thickness of the resin film of the ACF film 310 is equal to or less than the diameter of the conductive beads 312, the resin film can adhere to the pad electrode PDE and the conductive pattern 420 of the flexible circuit substrate 400.

[0085] The higher the resolution of the display device 1 is, the finer the signal wirings of the connection portion 120 are formed, and the contact area between each pad electrode PDE connected to the signal wirings and the ACF film 310 becomes smaller, so that poor contact may occur. Only when the conductive beads 312 of the ACF film 310 are small enough, uniformly arranged, and the thickness of the resin film is equal to or less than the diameter of the conductive beads 312, can electrical contact failure be prevented.

[0086] The non-random array anisotropic conductive film can be manufactured by various methods. For example, after forming micro-cavities on a film by using a laser interference lithography method, the conductive beads can be arranged in a certain shape in the micro-cavities, and a non-random array anisotropic conductive film can be formed through a coating or lamination process. In addition, other known methods can also be used to form a non-random array anisotropic conductive film.

[0087] The base film 410 of the flexible circuit board 400 may be a flexible film. The conductive pattern 420 of the flexible circuit board 400 may be formed on the base film 410 to correspond to a plurality of pad electrodes PDE respectively.

[0088] Hereinafter, when the flexible circuit board 400 is connected to the side surface of the display panel DP, the problems that may occur will be examined, and the configuration of the present embodiment for solving these problems will be described.

[0089] Figure 9 is Figure 1 exploded perspective view of the display device. Figure 10 represents Figure 9 the pad portion of. Figure 11 is a diagram showing the configuration relationship of the connection signal wiring, the pad electrode, and the guiding wiring according to an embodiment.

[0090] Referring to Figures 9 to 11 , the display panel DP may include a lower substrate 100, an upper substrate 200 opposed to the lower substrate 100, a connection portion 120 disposed between the lower substrate 100 and the upper substrate 200, a plurality of pad electrodes PDE of a pad portion P_PA disposed on the side surfaces of the lower substrate 100 and the upper substrate 200, and a flexible circuit board 400.

[0091] As Figure 9 shown, the connection portion 120 may include a plurality of connection signal wirings SL disposed on the lower substrate 100. The connection signal wirings SL may be electrically connected to the pad electrodes PDE. The connection signal wirings SL may be electrically connected to the pixels P of the display panel DP. The connection signal wirings SL may be disposed so as to straddle the pad portion P_PA and the pixels P of the display panel DP. The connection portion 120 may include a plurality of transistors T and storage capacitors Cst.

[0092] The connection signal wiring SL may be one or more of the plurality of gate lines G1 to Gn of the pixel P and / or a gate conductive layer provided with a gate electrode, or may be a source / drain conductive layer provided with the plurality of data lines D1 to Dm of the pixel P, but is not limited thereto.

[0093] The connection signal wiring SL may include one or more metals selected from copper (Cu), molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), and tungsten (W).

[0094] The lower substrate 100 may include a plurality of side surfaces 100s1 to 100s4. A pad portion P_PA may be provided on the first side surface 100s1 of the lower substrate 100. The upper substrate 200 may include a plurality of side surfaces 200s1 to 200s4. The side surfaces 200s1 to 200s4 of the upper substrate 200 may be substantially aligned with the side surfaces 100s1 to 100s4 of the lower substrate 100 in the third direction D3. A pad portion P_PA may be provided on the first side surface 200s1 of the upper substrate 200.

[0095] When the side surfaces 200s1 to 200s4 of the upper substrate 200 are aligned with the side surfaces 100s1 to 100s4 of the lower substrate 100 in the third direction D3, the upper surface of the connection signal wiring SL disposed between the side surfaces 200s1 to 200s4 of the upper substrate 200 and the side surfaces 100s1 to 100s4 of the lower substrate 100 is not exposed, and only a part of the side surface is exposed. A part of the side surface of the exposed connection signal wiring SL is connected to the pad electrode PDE, which can increase the contact surface with the guiding wiring LE. The pad electrode PDE may be formed to protrude on the upper surfaces of the side surfaces 200s1 to 200s4 of the upper substrate 200 and the side surfaces 100s1 to 100s4 of the lower substrate 100.

[0096] In the previous embodiments, a part of the upper surface of the connection signal wiring SL formed on the lower substrate 100 may be exposed without being covered by the upper substrate 200. In this case, a moisture-proof agent for preventing moisture is applied to the area near the connection signal wiring SL exposed on the upper surface and the lower surface of the lower substrate 100, thereby preventing the exposed connection signal wiring SL from being affected by moisture. However, in this embodiment, the side surfaces 200s1 to 200s4 of the upper substrate 200 and the side surfaces 100s1 to 100s4 of the lower substrate 100 are aligned in the third direction D3, and the pad electrode PDE is formed to protrude on the upper surfaces of the side surfaces 200s1 to 200s4 of the upper substrate 200 and the side surfaces 100s1 to 100s4 of the lower substrate 100, so it is difficult to ensure a space for applying the moisture-proof agent. Therefore, each pad electrode PDE may be prone to moisture absorption.

[0097] On the other hand, as Figure 6 shown, the display panel DP may further include a sealing member 250 that joins the upper substrate 200 and the lower substrate 100 to each other. The sealing member 250 is provided along the edge position portion or the edge region of the upper substrate 200 and the lower substrate 100. That is, the sealing member 250 may be in a four-sided frame shape disposed along the edge region formed on the side surface of the upper substrate 200 and the side surface of the lower substrate 100, but is not limited thereto.

[0098] A plurality of pad electrodes PDE can be electrically connected to a partial side surface of the connection signal wiring SL and are connected to a guiding wiring LE of a flexible circuit board 400 described later. In Figure 9 and Figure 10 14 pad electrodes PDE are shown, but it is not limited thereto.

[0099] The pad electrode PDE can include at least one of silver (Ag), molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The pad electrode PDE can be a single film formed of the exemplified substances. However, it is not limited thereto, and the pad electrode PDE can also be a laminated film. For example, the pad electrode PDE can be formed of a laminated structure such as Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu.

[0100] The pad electrode PDE can be disposed across a first side surface 100s1 of the lower substrate 100 and a first side surface 200s1 of the upper substrate 200. The pad electrode PDE covers the first side surface 100s1 of the lower substrate 100 in a third direction D3 and covers at least a part of the first side surface 200s1 of the upper substrate 200 in the third direction D3, and a part of an upper end portion of the first side surface 200s1 of the upper substrate 200 can be exposed. However, it is not limited thereto, and the pad electrode PDE can cover at least a part of the first side surface 100s1 of the lower substrate 100 in the third direction D3, and a part of a lower end portion of the first side surface 100s1 of the lower substrate 100 can be exposed.

[0101] According to an embodiment, the pad electrode PDE can have a first thickness T1 in the third direction D3. The first thickness T1 of the pad electrode PDE can be substantially proportional to a second thickness T2 in the third direction D3 of the lower substrate 100 and can be substantially proportional to a third thickness T3 in the third direction D3 of the upper substrate 200. Recently, with the trend of thinning of the display panel DP, the second thickness T2 of the lower substrate 100 and the third thickness T3 of the upper substrate 200 have a tendency to gradually decrease, and the first thickness T1 of the pad electrode PDE also has a tendency to decrease. Moisture absorption from the outside generally may start from a lower surface area of the lower substrate 100 or may start from an upper surface area of the upper substrate 200. That is, when the first thickness T1 of the pad electrode PDE decreases, it may be easy to absorb moisture from the outside.

[0102] The flexible circuit board 400 may include a conductive pattern 420 disposed on a base film 410. The conductive pattern 420 may include a plurality of guiding wirings LE. The plurality of guiding wirings LE may be disposed on one surface of the flexible circuit board 400. The plurality of guiding wirings LE may be connected to a plurality of pad electrodes PDE of the display panel DP.

[0103] The guiding wiring LE may contain a metallic substance. The guiding wiring LE may respectively contain one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0104] The flexible circuit board 400 may include an insulating layer 430 covering the base film 410 and the conductive pattern 420. In one embodiment, the insulating layer 430 is treated with a solder resist which is an insulating substance formed to protect the conductive pattern 420 on the flexible circuit board 400, and an exposed portion OPN for inputting a signal to the liquid crystal display device may be formed at a predetermined position of the insulating layer 430. For example, the exposed portion OPN of the solder resist may be formed to overlap with the pad portion P_PA and the ACF film 310 in a first direction D1.

[0105] According to one embodiment, the exposed portion OPN of the insulating layer 430 may be formed to have a larger area than the area of the portion where the pad electrode PDE and the guiding wiring LE are connected for connection margin. Thus, a partial region of the guiding wiring LE not covered by the insulating layer 430 may be prone to moisture absorption.

[0106] As Figure 10 shown, the plurality of connection signal wirings SL may sequentially include a gate displacement clock line GSCL, a gate cut-off voltage line VoffL, a ground voltage line GND, a gate integrated circuit drive voltage line VDD, a gate start signal line GSPL, a gate output enable signal line GOEL, a gate conduction voltage line VonL, a common voltage line VcomL, etc. from left to right. For ease of explanation, first, a case where the first bump wiring BL1 to the third bump wiring BL3 are not configured (when not particularly distinguished, it may also be denoted as BL) will be described first, and then the effects when the first bump wiring BL1 to the third bump wiring BL3 are configured will be described.

[0107] According to an embodiment, the gate displacement clock line GSCL may have a voltage range of 0V to 8.6V, and the gate cut-off voltage line VoffL may have a voltage range of -9.4V to -2V. The ground voltage line GND may be 0V, and the gate integrated circuit drive voltage line VDD, the gate start signal line GSPL, and the gate output enable signal line GOEL may be 3.3V. The gate on-voltage line VonL may have a voltage range of 15V to 29V, and the common voltage line VcomL may be 6.3V.

[0108] In the case of a display panel DP according to an embodiment undergoing a reliability test of being exposed to a high-temperature and high-humidity environment for a certain period of time or more, an abnormal phenomenon of unable to display the screen normally may occur. In other words, when moisture and / or impurities penetrate into the pad electrode PDE and / or the lead wiring LE, the wiring may be corroded.

[0109] Specifically, when moisture and / or impurities penetrate into the pad portion P_PA, there is a large difference in the voltages applied to the adjacent gate displacement clock line GSCL and the gate cut-off voltage line VoffL, so galvanic corrosion, which is an electrochemical reaction, may cause the wiring to be corroded. Here, the galvanic corrosion occurs when an electric field is applied to the moisture or impurity ions through the pad electrode PDE connected to the gate displacement clock line GSCL with a relatively higher voltage among the two wirings.

[0110] Since there is also a problem of a large difference in the voltages applied between the adjacent gate cut-off voltage line VoffL and the ground voltage line GND, galvanic corrosion may also occur between these two wirings. And there is also a problem of a large difference in the voltages applied between the adjacent gate output enable signal line GOEL and the gate on-voltage line VonL, so galvanic corrosion may also occur between these two wirings.

[0111] On the other hand, between the adjacent ground voltage line GND, the gate integrated circuit drive voltage line VDD, the gate start signal line GSPL, and the gate output enable signal line GOEL, there is no large difference in the voltages applied, so galvanic corrosion does not occur between two adjacent wirings.

[0112] In addition, although there is also a large difference in the voltages applied between the gate on-voltage line VonL and the common voltage line VcomL, it belongs to the case where the two wirings are sufficiently separated, so galvanic corrosion does not occur between the two wirings.

[0113] That is, the greater the voltage difference between two wirings, the more frequently galvanic corrosion occurs, and the farther the distance between two wirings, the less frequently it occurs. For example, when the potential difference between adjacent pad electrodes PDE is about 7V or more, the occurrence of galvanic corrosion may increase, and when two wirings are separated by a width of one or more pad electrodes PDE in the second direction D2, the occurrence of galvanic corrosion may decrease.

[0114] Refer to Figure 10 and Figure 11 , when the potential difference between adjacent connection signal wirings SL arranged adjacent to each other is equal to or greater than a certain magnitude, at least one bump wiring BL can be arranged between the adjacent connection signal wirings SL arranged adjacent to each other.

[0115] The bump wiring BL can be a pad electrode PDE without an electrical output object. The first bump wiring BL1 may not be connected to any connection signal wiring SL.

[0116] The bump wiring BL can have a voltage of a certain magnitude. When a bump wiring BL having a specific voltage between the voltages of two connection signal wirings SL is arranged between connection signal wirings SL having a potential difference equal to or greater than a certain magnitude, the potential difference between two adjacent wirings can be reduced. According to an embodiment, the bump wiring BL can receive a supply of a voltage of a certain magnitude from the drive circuit unit DIC through the guiding wiring LE.

[0117] According to an embodiment, a first bump wiring BL1 including two first sub-bump wirings BL1_1 and BL1_2 can be arranged between the adjacent gate cut-off voltage line VoffL and the gate displacement clock line GSCL. For example, assuming that the voltage of the gate cut-off voltage line VoffL is -9.4V and the voltage of the gate displacement clock line GSCL is 7.6V, the potential difference between two connection signal wirings SL is 17V. When the potential difference between adjacent pad electrodes PDE is about 7V or more, the occurrence of galvanic corrosion increases. Therefore, the first sub-bump wirings BL1_1 and BL1_2 are respectively set to -3V and 2.6V so that the potential difference between adjacent pad electrodes PDE can be maintained below 7V.

[0118] A second bump wiring BL2 can be disposed between the adjacent gate cut-off voltage lines VoffL and the ground voltage line GND. For example, assuming that the voltage of the gate cut-off voltage line VoffL is -9.4V and the voltage of the ground voltage line GND is 0V, the potential difference between the two connection signal wirings SL is 9.4V. When the potential difference between adjacent pad electrodes PDE is about 7V or more, the occurrence of galvanic corrosion increases. Therefore, the second bump wiring BL2 is set to -4.7V so that the potential difference between adjacent pad electrodes PDE can be maintained below 7V.

[0119] A third bump wiring BL3 including three third sub-bump wirings BL3_1, BL3_2, and BL3_3 can be disposed between the adjacent gate output enable signal lines GOEL and the gate conduction voltage line VonL. For example, assuming that the voltage of the gate output enable signal line GOEL is 3.3V and the voltage of the gate conduction voltage line VonL is 29V, the potential difference between the two connection signal wirings SL is 25.7V. When the potential difference between adjacent pad electrodes PDE is about 7V or more, the occurrence of galvanic corrosion increases. Therefore, the third sub-bump wirings BL3_1, BL3_2, and BL3_3 are set to 10V, 16.5V, and 23V respectively so that the potential difference between adjacent pad electrodes PDE can be maintained below 7V.

[0120] The magnitudes of the voltages of the first bump wiring BL1 to the third bump wiring BL3 are not limited to the above values and can be changed according to the potential difference between two adjacent connection signal wirings SL.

[0121] Refer to Figure 11 , a third bump wiring BL3 including three third sub-bump wirings BL3_1, BL3_2, and BL3_3 can be disposed between the adjacent gate output enable signal lines GOEL and the gate conduction voltage line VonL. For the first pitch D1' to the fifth pitch D5' between the pad electrodes PDE, except for the fifth pitch D5' between the pad electrode PDE connected to the gate conduction voltage line VonL and the pad electrode PDE connected to the common voltage line VcomL, they can be of equal pitch.

[0122] When a high voltage is applied to the pad electrode PDE, in order to reduce the risk of burning occurring between the pad electrode PDE and the guiding wiring LE, the widths W1' to W6' of the pad electrode PDE can be greater than the widths W1 to W6 of the first guiding wiring LE1 to the sixth guiding wiring LE6.

[0123] The widths W1 to W6 of the first guiding wiring LE1 to the sixth guiding wiring LE6 may all be the same, and the center lines of the first guiding wiring LE1 to the sixth guiding wiring LE6 may be configured to overlap with the center line of the pad electrode PDE based on the second direction D2. That is, except for the fifth pitch D5 between the fifth guiding wiring LE5 and the sixth guiding wiring LE6, the first pitch D1 to the fourth pitch D4 between the first guiding wiring LE1 to the fifth guiding wiring LE5 may be equal pitches.

[0124] It is possible not to dispose the bump wiring BL between the gate conduction voltage line VonL and the common voltage line VcomL that are adjacently disposed. That is, when the fifth pitch D5' between the pad electrode PDE connected to the gate conduction voltage line VonL and the pad electrode PDE connected to the common voltage line VcomL is sufficiently separated, galvanic corrosion may not occur between the two connection signal wirings SL.

[0125] Hereinafter, other embodiments will be described. In the following embodiments, descriptions of the same configurations as those of the embodiments already described will be omitted or simplified, and the description will be mainly focused on the differences.

[0126] Figure 12 It is a diagram showing the configuration relationship of the connection signal wiring, the pad electrode, and the guiding wiring according to another embodiment.

[0127] Refer to Figure 12 , different from Figure 11 the embodiment shown in that, in the second direction D2, based on the center line of the pad electrode PDE, the center line of the first guiding wiring LE1_1 is moved to the left, and the center line of the fifth guiding wiring LE5_1 is moved to the right for configuration.

[0128] More specifically, the first width D1_1 between the first guiding wiring LE1_1 connected to the gate output enable signal line GOEL and the third sub-bump wiring BL3_1 and the fourth width D4_1 between the fifth guiding wiring LE5_1 connected to the gate conduction voltage line VonL and the third sub-bump wiring BL3_3 may be greater than Figure 11 the first width D1 between the first guiding wiring LE1 connected to the gate output enable signal line GOEL and the third sub-bump wiring BL3_1 and the fourth width D4 between the fifth guiding wiring LE5 connected to the gate conduction voltage line VonL and the third sub-bump wiring BL3_3 shown in. Thereby, the occurrence of galvanic corrosion can be further prevented.

[0129] Although the fifth width D5_1 between the fifth guiding wiring LE5_1 connected to the gate turn-on voltage line VonL and the sixth guiding wiring LE6_1 connected to the common voltage line VcomL may be reduced, when the fifth pitch D5' between the pad electrode PDE connected to the gate turn-on voltage line VonL and the pad electrode PDE connected to the common voltage line VcomL is sufficiently separated, galvanic corrosion may not occur between the two connection signal wirings SL.

[0130] Figure 13 FIG. is a diagram showing the configuration relationship of connection signal wirings, pad electrodes, and guiding wirings according to another embodiment.

[0131] Referring to Figure 13 , and Figure 11 The difference from the embodiment shown in is that the widths W1_1 to W5_1 of the first guiding wiring LE1_2 to the fifth guiding wiring LE5_2 are smaller than Figure 11 the widths W1 to W5 of the first guiding wiring LE1 to the fifth guiding wiring LE5 shown in.

[0132] More specifically, the first width D1_2 between the first guiding wiring LE1_2 connected to the gate output enable signal line GOEL and the third sub-bump wiring BL3_1 and the fourth width D4_2 between the fifth guiding wiring LE5_2 connected to the gate turn-on voltage line VonL and the third sub-bump wiring BL3_3 can be greater than Figure 11 the first width D1 between the first guiding wiring LE1 connected to the gate output enable signal line GOEL and the third sub-bump wiring BL3_1 and the fourth width D4 between the fifth guiding wiring LE5 connected to the gate turn-on voltage line VonL and the third sub-bump wiring BL3_3 shown in. Thus, the occurrence of galvanic corrosion can be further prevented.

[0133] Figure 14 FIG. is a diagram showing the configuration relationship of connection signal wirings, pad electrodes, and guiding wirings according to another embodiment.

[0134] Referring to Figure 14 , and Figure 13 The difference from the embodiment shown in is that in the second direction D2, with the center line of the pad electrode PDE as a reference, the center line of the first guiding wiring LE1_3 is arranged to move to the left, and the center line of the fifth guiding wiring LE5_3 is arranged to move to the right.

[0135] More specifically, a first width D1_3 between a first guiding wiring LE1_3 connected to a gate output enable signal line GOEL and a third sub bump wiring BL3_1, and a fourth width D4_3 between a fifth guiding wiring LE5_3 connected to a gate conduction voltage line VonL and a third sub bump wiring BL3_3 may be greater than Figure 13 a first width D1_2 between a first guiding wiring LE1_2 connected to the gate output enable signal line GOEL and the third sub bump wiring BL3_1, and a fourth width D4_2 between a fifth guiding wiring LE5_2 connected to the gate conduction voltage line VonL and the third sub bump wiring BL3_3 as shown. Thereby, the occurrence of galvanic corrosion can be further prevented.

Claims

1. A display device, comprising: A display panel, including a plurality of connection signal wirings having different voltage values; A flexible circuit board, attached to a side surface of the display panel, including a base film and a plurality of guiding wirings disposed on the base film; And An anisotropic conductive film, disposed between the plurality of connection signal wirings and the plurality of guiding wirings, When the potential difference between two adjacent connection signal wirings among the plurality of connection signal wirings is equal to or higher than a first voltage value, two or more bump wirings having a predetermined voltage value are disposed between the two adjacent connection signal wirings, The two adjacent connection signal wirings include a first signal wiring located on one side of the two or more bump wirings and a second signal wiring located on the other side of the two or more bump wirings, The two or more bump wirings include an adjacent first bump wiring and a second bump wiring, the first bump wiring is located between the first signal wiring and the second bump wiring, and the second bump wiring is located between the first bump wiring and the second signal wiring, The voltage value of the first bump wiring has a magnitude between the voltage value of the first signal wiring and the voltage value of the second bump wiring, The voltage value of the second bump wiring has a magnitude between the voltage value of the first bump wiring and the voltage value of the second signal wiring, A plurality of pad electrodes are separately disposed along an extending direction of a side surface of the display panel, The central axis of one guiding wiring connected to one pad electrode connected to the first signal wiring adjacent to the two or more bump wirings is configured to be separated from the central axis of the one pad electrode in a direction away from the two or more bump wirings, and the central axis of another guiding wiring connected to another pad electrode connected to the second signal wiring adjacent to the two or more bump wirings is configured to be separated from the central axis of the another pad electrode in another direction away from the two or more bump wirings, The central axes of the remaining guiding wirings among the plurality of guiding wirings, other than the one guiding wiring and the another guiding wiring, coincide with the central axis of the pad electrode serving as the two or more bump wirings.

2. The display device according to claim 1, wherein The difference between the voltage value of the first bump wiring and the voltage value of the second bump wiring is less than the first voltage value.

3. The display device according to claim 1, wherein The flexible circuit board is provided with a driving circuit, and the driving circuit includes a gate driving unit, a data driving unit, a timing control unit, and a power management integrated circuit.

4. The display device according to claim 3, wherein The two or more bump wirings receive a supply of a voltage of a predetermined magnitude from the driving circuit through the guiding wirings.

5. The display device according to claim 1, wherein The number of the two or more bump wirings is determined according to a value obtained by dividing the potential difference between the two adjacent connection signal wirings by the first voltage value.

6. The display device according to claim 1, wherein The flexible circuit board includes an insulating layer in a region that does not overlap with the anisotropic conductive film.

7. The display device according to claim 1, wherein the anisotropic conductive film includes a resin film and a plurality of conductive beads arranged in a matrix in the resin film in one layer.

8. The display device according to claim 7, wherein the thickness of the anisotropic conductive film is less than or equal to the diameter of the conductive beads.

9. The display device according to claim 1, wherein the ends of the plurality of connection signal wirings are exposed on the side surface of the display panel, and are respectively connected to a plurality of pad electrodes.

10. The display device according to claim 9, wherein the pad electrodes are made of silver, and the connection signal wirings and the guiding wirings are made of copper.

11. The display device according to claim 1, wherein in the extending direction of the side surface of the display panel, the widths of the guiding wirings connected to the pad electrodes that are not adjacent to the two or more bump wirings are the same as the widths of the guiding wirings connected to the pad electrodes that are adjacent to the two or more bump wirings.

12. The display device according to claim 11, wherein the width of the pad electrodes is greater than the width of the guiding wirings.

13. The display device according to claim 1, wherein in the extending direction of the side surface of the display panel, the widths of the guiding wirings connected to the pad electrodes that are not adjacent to the two or more bump wirings are different from the widths of the guiding wirings connected to the pad electrodes that are adjacent to the two or more bump wirings.

14. The display device according to claim 13, wherein the width of the guiding wirings connected to the pad electrodes that are not adjacent to the two or more bump wirings is greater than the width of the guiding wirings connected to the pad electrodes that are adjacent to the two or more bump wirings.

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