Data storage method and data reading method of processor chip

Abstract

The present invention relates to a processor chip and a data storage method and a data reading method thereof, wherein the processor chip comprises a SOC chip with data processing capability and a non-volatile memory chip, wherein the non-volatile memory chip is connected to the SOC chip and is used to provide data storage space for the SOC chip, and the SOC chip and the non-volatile memory chip are packaged in the same chip to form a single chip. The present invention can integrate different numbers of non-volatile memory chips and SOC chips with data processing capability into a single chip according to different requirements, and since the price of an external independent non-volatile memory chip is relatively low, the integrated processor chip not only has a large storage capacity, but also has a significantly lower price than a processor chip with a large built-in storage capacity, thereby greatly saving product costs.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a processor chip and a data storage method and a data reading method thereof. Background Art

[0002] At present, processor chips with non-volatile memory have been widely used, such as common single-chip microcomputer products. Compared with other chips that require external memory expansion, the biggest feature of this type of product is that it can run on a single chip. An important consideration in designing this type of product is the design choice of internal non-volatile memory. There are currently several options: Flash unit, OTP (one-time erase and write memory), MTP (multiple erase and write memory), etc. The larger the built-in storage capacity of these processor chips, the higher their price. Some electronic products need to process a large amount of data, so they can only purchase very expensive processor chips with large built-in storage capacity, which is not conducive to reducing the cost of electronic products. Summary of the invention

[0003] The present invention provides a processor chip and a data storage method and a data reading method thereof, which can reduce the product cost of the processor chip. The specific technical solution of the present invention is as follows:

[0004] A processor chip includes a SOC chip with data processing capability and a non-volatile memory chip, wherein the non-volatile memory chip is connected to the SOC chip to provide data storage space for the SOC chip, and the SOC chip and the non-volatile memory chip are packaged in the same chip to form a single chip. This solution can integrate different numbers of non-volatile memory chips and SOC chips with data processing capability into a single chip according to different requirements. Since the price of an external independent non-volatile memory chip is relatively low, the integrated processor chip not only has a large storage capacity, but also has a significantly lower price than a processor chip with a large built-in storage capacity, which greatly saves product costs.

[0005] Furthermore, the SOC chip includes a CPU module, a chip ID module, an encryption generation module, an XOR module, a data reorganization module and an interface module, wherein: the CPU module includes a data input terminal, a data output terminal and an upgrade port, the upgrade port is used to receive external input data; the data output terminal is connected to the encryption generation module, and is used to output data to the encryption generation module; the data input terminal is connected to the XOR module, and is used to input the data stored in the non-volatile storage chip after decryption; the encryption generation module is respectively connected to the chip ID module and the data reorganization module, and is used to receive the ID code output by the chip ID module, and use the ID code to receive the received The data output by the CPU module is encrypted and then output to the data reorganization module; the data reorganization module is connected to the non-volatile storage chip through the interface module, and is used to reorder the encrypted data output by the encryption generation module and output it to the non-volatile storage chip for storage; the data reorganization module is also connected to the XOR module, and is used to restore and sort the data in the non-volatile storage chip and output it to the XOR module; the XOR module is connected to the encryption generation module and the CPU module respectively, and is used to perform XOR operation on the ID code and the restored and sorted data output by the data reorganization module, and then output the decrypted data to the CPU module. This scheme can effectively perform secure storage and reading of data and ensure the performance of the processor chip by adopting a circuit structure having a chip ID module, an encryption generation module, an XOR module and a data reorganization module.

[0006] Furthermore, the non-volatile memory chip adopts a 4-wire SPI flash memory, which can further reduce product costs, and the SPI flash memory has a simple interface and is easier to design and manufacture.

[0007] Furthermore, there are two SPI flash memories, and the interface module includes a first interface module and a second interface module, the first interface module is respectively connected to the data reorganization module and one of the SPI flash memories, and the second interface module is respectively connected to the data reorganization module and another of the SPI flash memories. This solution can improve the program running speed and reduce the problem of low efficiency caused by the serial bus by using two 4-wire SPI flash memories.

[0008] A data storage method based on the above processor chip includes the following steps: the CPU module receives external data through the upgrade port and outputs the data to the encryption generation module; the encryption generation module obtains the ID code output by the chip ID module, and uses the ID code to encrypt the received data output by the CPU module, and then outputs the encrypted data to the data reorganization module; the data reorganization module reorders the encrypted data output by the encryption generation module, and outputs it to the non-volatile storage chip through the interface module; the non-volatile storage chip stores the received data. Through the above data processing steps, the scheme can not only realize the storage of large-capacity data, but also ensure the security of data storage.

[0009] A data reading method based on the above processor chip includes the following steps: the non-volatile memory chip outputs the internally stored data to the data reorganization module through the interface module; the data reorganization module restores and sorts the data output by the non-volatile memory chip and outputs it to the XOR module; the XOR module uses the ID code and the restored and sorted data output by the data reorganization module to perform an XOR operation, and outputs the decrypted data to the CPU module; the CPU module receives and reads the decrypted data. Through the above data processing steps, the scheme can not only realize the reading of large-capacity data, but also ensure the effectiveness of data reading. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a structural block diagram of a processor chip according to an embodiment of the present invention.

[0011] Figure 2 The present invention is a flowchart of a data storage method according to an embodiment of the present invention.

[0012] Figure 3 The figure is a flow chart of a data reading method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0013] The technical scheme in the embodiment of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiment of the present invention. It should be understood that the specific embodiments described below are only used to explain the present invention and are not used to limit the present invention. In the following description, specific details are given to provide a thorough understanding of the embodiments. However, it will be understood by those of ordinary skill in the art that the embodiments can be implemented without these specific details. For example, the circuit can be shown in a block diagram to avoid obscuring the embodiments in unnecessary details. In other cases, in order not to confuse the embodiments, known circuits, structures and techniques may not be shown in detail.

[0014] A processor chip includes a SOC chip with data processing capability and a non-volatile memory chip, wherein the non-volatile memory chip is connected to the SOC chip to provide data storage space for the SOC chip, that is, the SOC chip can write data to the non-volatile memory chip and read data from the non-volatile memory chip. The SOC (System on Chip) chip, called a chip-level system, is also called a system on chip. It is an integrated circuit with a dedicated target, which contains a complete system and embedded software. The non-volatile memory chip can be a NOR flash memory chip, or a NAND flash memory chip, and of course, other memory chips with non-volatile performance can also be used. The interconnected SOC chip and the non-volatile memory chip are packaged in the same chip to form a single chip. Since the chip packaging technology is an existing conventional technology, it will not be described here. In this embodiment, the single chip formed can select the required number of non-volatile memory chips according to different capacity requirements, and then connect all these non-volatile memory chips to the SOC chip, and then integrate all these chips into one chip, so that any configuration of the storage capacity of the processor chip can be achieved. Since the price of external independent non-volatile memory chips is relatively low, the integrated processor chip not only has a large storage capacity, but also has a significantly lower price than the processor chip with a large built-in storage capacity, which greatly saves product costs and is suitable for promotion and application.

[0015] As one of the implementation methods, Figure 1As shown, the SOC chip includes a CPU module, a chip ID module, an encryption generation module, an XOR module, a data reorganization module and an interface module. Among them, the CPU module includes a data input terminal 20, a data output terminal 10 and an upgrade port 30. The upgrade port 30 is used to receive external input data. The data output terminal 10 is connected to the encryption generation module, and is used to output the external input data to the encryption generation module. The data input terminal 20 is connected to the XOR module, and is used to input the data after the XOR (XOR) operation of the XOR module. The encryption generation module is connected to the chip ID module and the data reorganization module respectively, and is used to receive the ID code output by the chip ID module, and use the ID code to encrypt the received data output by the CPU module, and then output it to the data reorganization module. Since each chip has a unique ID code, the data code is encrypted by the unique ID code, which can ensure that the code of each chip will not be the same as that of other chips. The data reorganization module is connected to the non-volatile memory chip through the interface module, and is used to reorder the encrypted data output by the encryption generation module, and then output it to the non-volatile memory chip for storage. The data reorganization module is also connected to the XOR module, and is used to restore and sort the data output from the non-volatile memory chip, and then output it to the XOR module. The XOR module is connected to the encryption generation module and the CPU module respectively, and is used to perform XOR operation on the ID code and the restored and sorted data output by the data reorganization module, and then output the decrypted data to the CPU module. This embodiment adopts a circuit structure having a chip ID module, an encryption generation module, an XOR module and a data reorganization module, so that data can be effectively stored and read securely, thereby ensuring the data processing performance of the processor chip.

[0016] As one implementation method, the non-volatile memory chip uses a 4-wire SPI flash memory. Since this type of memory is relatively cheap, the product cost can be further reduced. In addition, the SPI flash memory has a simple interface and is easier to design and manufacture.

[0017] As one of the implementation methods, Figure 1As shown, the processor chip uses two SPI flash memories and two interface modules. The first interface module is respectively connected to the data reorganization module and one of the SPI flash memories, and the second interface module is respectively connected to the data reorganization module and another of the SPI flash memories. When accessing the two SPI flash memories, the data is read according to a unified address, and then the data is rearranged. Each time an address is sent, the two memories will read the data back and then splice them in bytes. For example, one SPI flash memory reads data0, data1, and the other SPI flash memory reads bytes data2, data3. Then, the spliced ​​32-bit bytes from low to high are data0+data2+data1+data3. This embodiment uses two 4-wire SPI flash memories to increase the speed of program operation and reduce the problem of low efficiency caused by the serial bus.

[0018] Of course, if the bandwidth still does not meet the requirements, the number of SPI flash memories can be increased to increase the data bandwidth and ensure data transmission efficiency.

[0019] A data storage method based on the above processor chip, such as Figure 2 As shown, the following steps are included: the CPU module receives external data through the upgrade port 30, and outputs the data to the encryption generation module. The encryption generation module obtains the ID code output by the chip ID module, and uses the ID code to encrypt the received data output by the CPU module, and then outputs the encrypted data to the data reorganization module. The data reorganization module reorders the encrypted data output by the encryption generation module, for example, splits a 32-bit byte from low to high as data0+data2+data1+data3, sorts data0 and data1 as an array from low to high, and sorts data2 and data3 as an array from low to high. Then, the interface module outputs the relevant data to the non-volatile storage chip. The non-volatile storage chip stores the received data, stores data0 and data1 in one SPI flash memory, and stores data2 and data3 in another SPI flash memory. Through the above data processing steps, this embodiment can not only realize the storage of large-capacity data, but also encrypt the data stored in the non-volatile storage chip to ensure the security of data storage.

[0020] A data reading method based on the above processor chip, such as Figure 3As shown, the following steps are included: the non-volatile memory chip outputs the internally stored data to the data reorganization module through the interface module, for example, one SPI flash memory stores data0 and data1 sorted from low to high, and another SPI flash memory stores data2 and data3 sorted from low to high, and these data are transmitted to the data reorganization module. The data reorganization module restores and sorts the data output by the non-volatile memory chip, for example, restores and sorts data0, data1, data2 and data3 from low to high to become the original 32-bit data data0+data2+data1+data3, and then outputs these restored and sorted data to the XOR module. The XOR module uses the ID code and the restored and sorted data output by the data reorganization module to perform an XOR operation, and outputs the decrypted data to the CPU module. The CPU module receives and reads the decrypted data. Through the above data processing steps, this embodiment can not only realize the reading of large-capacity data, but also ensure the effectiveness of data reading.

[0021] Those skilled in the art will appreciate that all or part of the steps in the above-mentioned method embodiments can be implemented by hardware related to program instructions. When the program is executed, the steps in the above-mentioned method embodiments are executed.

[0022] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data storage method for a processor chip, characterized in that: The steps include: The CPU module receives external data through the upgrade port and outputs the data to the encryption generation module; The encryption generation module obtains the ID code output by the chip ID module, and uses the ID code to encrypt the data output by the CPU module, and then outputs the encrypted data to the data reorganization module; The data reorganization module reorders the encrypted data output by the encryption generation module and outputs the data to the non-volatile storage chip through the interface module; The non-volatile memory chip stores the received data; The processor chip includes a SOC chip with data processing capability and a non-volatile memory chip, the non-volatile memory chip is connected to the SOC chip and is used to provide data storage space for the SOC chip, and the SOC chip and the non-volatile memory chip are packaged in the same chip to form a single chip; The SOC chip includes a CPU module, a chip ID module, an encryption generation module, an XOR module, a data reorganization module and an interface module.

2. The data storage method of a processor chip according to claim 1, characterized in that: The CPU module includes a data input terminal, a data output terminal and an upgrade port, wherein the upgrade port is used to receive external input data; the data output terminal is connected to the encryption generation module, and is used to output data to the encryption generation module; The data input terminal is connected to the XOR module and is used to input the decrypted data stored in the non-volatile storage chip; The encryption generation module is connected to the chip ID module and the data reorganization module respectively, and is used to receive the ID code output by the chip ID module, and use the ID code to encrypt the received data output by the CPU module, and then output it to the data reorganization module; The data reorganization module is connected to the non-volatile storage chip through the interface module, and is used to reorder the encrypted data output by the encryption generation module and output it to the non-volatile storage chip for storage; The data reorganization module is also connected to the XOR module, and is used to restore and sort the data in the non-volatile storage chip and output it to the XOR module; The XOR module is connected to the encryption generation module and the CPU module respectively, and is used to perform an XOR operation on the ID code and the restored and sorted data output by the data reorganization module, and then output the decrypted data to the CPU module.

3. The data storage method of a processor chip according to claim 1 or 2, characterized in that: The non-volatile memory chip adopts a 4-wire SPI flash memory.

4. The data storage method of a processor chip according to claim 3, characterized in that: There are two SPI flash memories, and the interface module includes a first interface module and a second interface module. The first interface module is respectively connected to the data reorganization module and one of the SPI flash memories, and the second interface module is respectively connected to the data reorganization module and another of the SPI flash memories.

5. A method for reading data from a processor chip, characterized in that: The steps include: The non-volatile memory chip outputs the internally stored data to the data reorganization module through the interface module; The data reorganization module restores and sorts the data output by the non-volatile storage chip and outputs the data to the XOR module; The XOR module performs an XOR operation using the ID code and the restored and sorted data output by the data reorganization module, and outputs the decrypted data to the CPU module; The CPU module receives and reads the decrypted data; The processor chip includes a SOC chip with data processing capability and a non-volatile memory chip, the non-volatile memory chip is connected to the SOC chip and is used to provide data storage space for the SOC chip, and the SOC chip and the non-volatile memory chip are packaged in the same chip to form a single chip; The SOC chip includes a CPU module, a chip ID module, an encryption generation module, an XOR module, a data reorganization module and an interface module.

6. The data reading method of a processor chip according to claim 5, characterized in that: The CPU module includes a data input terminal, a data output terminal and an upgrade port, wherein the upgrade port is used to receive external input data; the data output terminal is connected to the encryption generation module, and is used to output data to the encryption generation module; The data input terminal is connected to the XOR module and is used to input the decrypted data stored in the non-volatile storage chip; The encryption generation module is connected to the chip ID module and the data reorganization module respectively, and is used to receive the ID code output by the chip ID module, and use the ID code to encrypt the received data output by the CPU module, and then output it to the data reorganization module; The data reorganization module is connected to the non-volatile storage chip through the interface module, and is used to reorder the encrypted data output by the encryption generation module and output it to the non-volatile storage chip for storage; The data reorganization module is also connected to the XOR module, and is used to restore and sort the data in the non-volatile storage chip and output it to the XOR module; The XOR module is connected to the encryption generation module and the CPU module respectively, and is used to perform an XOR operation on the ID code and the restored and sorted data output by the data reorganization module, and then output the decrypted data to the CPU module.

7. The data reading method of the processor chip according to claim 5 or 6, characterized in that: The non-volatile memory chip adopts a 4-wire SPI flash memory.

8. The data reading method of a processor chip according to claim 7, characterized in that: There are two SPI flash memories, and the interface module includes a first interface module and a second interface module. The first interface module is respectively connected to the data reorganization module and one of the SPI flash memories, and the second interface module is respectively connected to the data reorganization module and another of the SPI flash memories.

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