A clock dynamic switching circuit

Abstract

The present invention relates to the field of circuit design technology, and specifically to a clock dynamic switching circuit, which includes a first AND gate, a second AND gate, a first clock enable signal line, a second clock enable signal line, a first feedback signal line, a second feedback signal line, a first clock signal line, a second clock signal line, a level synchronization circuit, a clock gating circuit and an OR gate circuit. The level synchronization circuit is used to synchronize the first clock enable signal line with the first clock signal, the second clock enable signal line with the second clock signal, and the clock gating circuit is used to control the on and off of the clock signal. In the circuit of the present application, by introducing the clock gating circuit, the triggering of the devices in the circuit all uses the positive edge of the clock, and there is no half-cycle path, which improves the maximum operating frequency of the circuit, avoids the occurrence of clock glitch through the feedback mechanism, and makes the signal output by the circuit free of glitches.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and in particular to a clock dynamic switching circuit. Background Art

[0002] There are usually multiple clocks with different frequencies in the chip. When used in different power consumption modes, the clock will be dynamically switched as needed. For example, when the chip is running at low power consumption, the clock is switched to a low-frequency clock; when the chip is running at full power, the clock is switched to a high-frequency clock. The frequencies of the high-frequency and low-frequency clocks may have no correlation, or they may be multiples. The problem that needs to be paid attention to when dynamically switching the clock is to avoid the occurrence of clock glitches (see Note 1). If an unexpected clock glitch occurs, it may cause a fatal abnormal error in the chip (see Note 2), which is absolutely not allowed in product use.

[0003] Note 1: Clock glitch refers to a high-level pulse or a low-level pulse that is higher than the clock frequency.

[0004] Note 2: Digital circuits have a maximum operating clock frequency limit and can only operate stably at a frequency less than or equal to the maximum clock frequency. If an unexpected clock glitch occurs, it means that the frequency of the current clock glitch is higher than the preset clock frequency in the circuit, and the circuit will become abnormal. Summary of the invention

[0005] In order to solve the problem of clock glitch caused by dynamic clock switching, the present application provides the following technical solutions.

[0006] A clock dynamic switching circuit, comprising: a first AND gate, a second AND gate, a first clock enable signal line, a second clock enable signal line, a first feedback signal line, a second feedback signal line, a first clock signal line, a second clock signal line, a level synchronization circuit, a clock gating circuit and an OR gate circuit;

[0007] Wherein, the level synchronization circuit comprises a first level synchronization unit and a second level synchronization unit;

[0008] The output end of the second feedback signal line and the first clock enable signal line are respectively connected to the input end of the first AND gate, the output end of the first AND gate is connected to the input end of the first level synchronization unit, and the output end of the first level synchronization unit is connected to the input end of the first feedback signal line;

[0009] The output end of the first feedback signal line and the second clock enable signal line are respectively connected to the input end of the second AND gate, the output end of the second AND gate is connected to the input end of the second level synchronization unit, and the output end of the second level synchronization unit is connected to the input end of the second feedback signal line;

[0010] The first clock enable signal line is connected to the signal input end of the first level synchronization unit, the second clock enable signal line is connected to the signal input end of the second level synchronization unit, and the first clock enable signal line and the second clock enable signal line are respectively used to input the required synchronized level signals to the first level synchronization unit and the second level synchronization unit;

[0011] The first clock enable signal line and the second clock enable signal line are used to input the first clock enable signal and the second clock enable signal to the first AND gate and the second AND gate respectively; the first clock enable signal and the second clock enable signal have opposite phases, and the level synchronization circuit is used to synchronize the first clock enable signal and the second clock enable signal, so that the first level synchronization unit and the second level synchronization unit output the first clock enable level synchronization signal and the second clock enable level synchronization signal respectively;

[0012] The clock gating circuit includes a first clock gating unit and a second clock gating unit, the output end of the first level synchronization unit is connected to the gating enable end of the first clock gating unit, and the first clock signal line is also connected to the clock input end of the first clock gating unit; the output end of the second level synchronization unit is connected to the gating enable end of the second clock gating unit, and the second clock enable signal line is also connected to the clock input end of the second clock gating unit; the first clock gating unit and the second clock gating unit respectively use a first clock enable level synchronization signal and a second clock enable level synchronization signal to control the on and off of the first clock signal line and the second clock signal line;

[0013] The output ends of the first clock gating unit and the second clock gating unit are respectively connected to the input ends of the OR gate circuit, and the OR gate circuit is used to obtain a target pulse signal after performing an OR gate operation on the signals output by the first clock gating unit and the second clock gating unit.

[0014] In one embodiment, it further includes a signal feedback circuit, the signal feedback circuit including a first feedback unit and a second feedback unit;

[0015] The output end of the first level synchronization unit is connected to the input end of the first feedback unit, and the input end of the first feedback signal line is connected to the output end of the first feedback unit; the output end of the second level synchronization unit is connected to the input end of the second feedback unit, and the input end of the second feedback signal line is connected to the output end of the second feedback unit; the feedback circuit is used to eliminate the overlap of the first clock enable level synchronization signal and the second clock enable level synchronization signal after synchronization.

[0016] In another embodiment, further comprising an inverter;

[0017] The second clock enable signal line is also connected to the first clock enable signal line through the inverter, and is used to invert the second clock enable signal on the second clock enable signal line to obtain the first clock enable signal.

[0018] In another embodiment, the first level synchronization unit includes a first register and a second register, the input end of the first register is the input end of the first level synchronization unit, the positive phase output end of the first register is connected to the input end of the second register, the positive phase output end of the second register is the output end of the first level synchronization unit, and the first clock signal line is connected to the clock ends of the first register and the second register respectively;

[0019] The second level synchronization unit includes a third register and a fourth register, the input end of the third register is the input end of the second level synchronization unit, the positive phase output end of the third register is connected to the input end of the fourth register, the positive phase output end of the fourth register is the output end of the second level synchronization unit, and the second clock signal line is connected to the clock ends of the third register and the fourth register respectively.

[0020] In another embodiment, the first feedback unit includes a fifth register, a positive phase output terminal of the second register is connected to an input terminal of the fifth register, an input terminal of the first feedback signal line is connected to an inverting phase output terminal of the fifth register, and the first clock signal line is further connected to a clock terminal of the fifth register;

[0021] The second feedback unit includes a sixth register, the positive phase output terminal of the fourth register is connected to the input terminal of the sixth register, the input terminal of the second feedback signal line is connected to the negative phase output terminal of the sixth register, and the second clock signal line is also connected to the clock terminal of the sixth register.

[0022] The clock dynamic switching circuit according to the above embodiment includes: a first AND gate, a second AND gate, a first clock enable signal line, a second clock enable signal line, a first feedback signal line, a second feedback signal line, a first clock signal line, a second clock signal line, a level synchronization circuit, a clock gating circuit and an OR gate circuit; wherein the level synchronization circuit includes a first level synchronization unit and a second level synchronization unit; the output end of the second feedback signal line and the first clock signal line are respectively connected to the input end of the first AND gate, the output end of the first AND gate is connected to the input end of the first level synchronization unit, and the output end of the first level synchronization unit is connected to the input end of the first feedback signal line ; the output end of the first feedback signal line and the second clock signal line are respectively connected to the input end of the second AND gate, the output end of the second AND gate is connected to the input end of the second level synchronization unit, and the output end of the second level synchronization unit is connected to the input end of the second feedback signal line; the first clock enable signal line is connected to the input end of the first level synchronization unit, the second clock enable signal line is connected to the input end of the second level synchronization unit, the first clock enable signal line and the second clock enable signal line are respectively used to input the required synchronized level signals to the first level synchronization unit and the second level synchronization unit; the first clock enable signal line and the second clock enable signal line are respectively used to input the required synchronized level signals to the first level synchronization unit and the second level synchronization unit The AND gate and the second AND gate input the first clock enable signal and the second clock enable signal; the first clock enable signal and the second clock enable signal have opposite phases, and the level synchronization circuit is used to synchronize the first clock enable signal and the second clock enable signal, so that the first level synchronization unit and the second level synchronization unit output the first clock enable level synchronization signal and the second clock enable level synchronization signal respectively; the clock gating circuit includes a first clock gating unit and a second clock gating unit, the output end of the first level synchronization unit is connected to the gating enable end of the first clock gating unit, and the first clock signal line is also connected to the clock input end of the first clock gating unit. The output end of the second level synchronization unit is connected to the gate enable end of the second clock gating unit, and the second clock signal line is also connected to the clock input end of the second clock gating unit; the first clock gating unit and the second clock gating unit respectively use the first clock enable level synchronization signal and the second clock enable level synchronization signal to control the on and off of the first clock signal line and the second clock signal line; the output ends of the first clock gating unit and the second clock gating unit are respectively connected to the input ends of the OR gate circuit, and the OR gate circuit is used to obtain the target pulse signal after performing an OR gate operation on the signals output by the first clock gating unit and the second clock gating unit. In the circuit of the present application, by introducing a clock gating circuit, the triggering of the devices in the circuit all uses the positive edge of the clock, and there is no half-cycle path, which improves the maximum operating frequency of the circuit, avoids the occurrence of clock glitches, and makes the signal output by the circuit free of glitches through the feedback mechanism. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of a clock dynamic switching circuit according to an embodiment of the present application;

[0024] Figure 2 This is a timing diagram of the clock dynamic switching circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] The present invention is further described in detail below by specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments adopt associated similar element numbers. In the following embodiments, many detailed descriptions are for making the present application better understood. However, those skilled in the art can easily recognize that some features can be omitted in different situations, or can be replaced by other elements, materials, methods. In some cases, some operations related to the present application are not shown or described in the specification, this is to avoid the core part of the present application being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations according to the description in the specification and the general technical knowledge in the art.

[0026] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various implementations. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a required sequence, unless otherwise specified that a certain sequence must be followed.

[0027] The serial numbers of the components in this document, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings).

[0028] The clock dynamic switching circuit of the present application introduces a clock gating circuit on the basis of the existing commonly used circuits, so that all registers in the circuit use the positive edge of the clock, and the circuit no longer has a half-cycle path, thereby improving the maximum operating frequency of the circuit and avoiding the occurrence of clock glitches.

[0029] Furthermore, in another embodiment, the clock dynamic switching circuit further adds a signal feedback circuit, which is specifically used for feedback of clock signals to solve the glitch problem that may occur when multiple asynchronous clocks are switched. A synchronous clock refers to a clock whose edges are at the same time, usually a source clock and its divided clock; an asynchronous clock refers to a clock whose edges are not at the same time.

[0030] Embodiment 1:

[0031] Please refer to Figure 1 The present embodiment provides a clock dynamic switching circuit, which includes: a first AND gate 10, a second AND gate 11, a first clock signal line 14, a second clock signal line 15, a first clock enable signal line 17, a second clock enable signal line 16, a first feedback signal line 13, a second feedback signal line 12, a level synchronization circuit 20, a clock gating circuit 21 and an OR gate circuit 23. The level synchronization circuit 20 includes a first level synchronization unit and a second level synchronization unit, such as Figure 1 The upper half of the middle level synchronization circuit 20 is the first level synchronization unit, and the lower half is the second level synchronization unit; the output end of the second feedback signal line 12 and the first clock enable signal line 17 are respectively connected to the input end of the first AND gate 10, the output end of the first AND gate 10 is connected to the input end of the first level synchronization unit, and the output end of the first level synchronization unit is connected to the input end of the first feedback signal line 13. The output end of the first feedback signal line 13 and the second clock enable signal line 16 are respectively connected to the input end of the second AND gate 11, the output end of the second AND gate 11 is connected to the input end of the second level synchronization unit, and the output end of the second level synchronization unit is connected to the input end of the second feedback signal line 12. The first clock signal line 14 is connected to the clock end of the first level synchronization unit, and the second clock signal line 15 is connected to the clock end of the second level synchronization unit. The first clock signal line 14 and the second clock signal line 15 are respectively used to input clock signals to the first level synchronization unit and the second level synchronization unit to control their operations. The first clock enable signal line 17 and the second clock enable signal line 16 are used to input the first clock enable signal and the second clock enable signal to the first AND gate 10 and the second AND gate 11, respectively. Figure 1 The first clock enable signal is sel_clka, the second clock enable signal is sel_clkb, the first clock enable signal and the second clock enable signal have opposite phases, and the level synchronization circuit is used to synchronize the first clock enable signal and the second clock enable signal, so that the first level synchronization unit and the second level synchronization unit output the first clock enable level synchronization signal sel_clka_d2 and the second clock enable level synchronization signal sel_clkb_d2 respectively. The clock gating circuit 22 includes a first clock gating unit and a second clock gating unit, such as Figure 1The upper half of the middle clock gating circuit 22 is the first clock gating unit 221, and the lower half is the second clock gating unit 222. The output end of the first level synchronization unit is connected to the gate enable end EN of the first clock gating unit 221, and the first clock signal line 14 is also connected to the clock end CK of the first clock gating unit 221; the output end of the second level synchronization unit is connected to the gate enable end EN of the second clock gating unit 221, and the second clock signal line 16 is also connected to the clock end CK of the second clock gating unit; the first clock gating unit 221 and the second clock gating unit 222 respectively use the first clock enable level synchronization signal and the second clock enable level synchronization signal to control the on and off of the first clock signal line 14 and the second clock signal line 15. The output ends ECK of the first clock gating unit 221 and the second clock gating unit 222 are respectively connected to the input ends of the OR gate circuit 23, and the OR gate circuit 23 is used to perform an OR gate operation on the signals output by the first clock gating unit 221 and the second clock gating unit 222 to obtain the target pulse signal clk_out. The clock dynamic switching circuit of this embodiment introduces a clock gating circuit on the basis of the existing commonly used circuits, so that all registers in the circuit use the positive edge of the clock, and the circuit no longer has a half-cycle path, thereby improving the maximum operating frequency of the circuit and avoiding the occurrence of clock glitches.

[0032] The clock gating circuit of this embodiment is provided by a digital circuit standard library unit, and usually has four signals: EN, CK, ECK, and TE. CK is the input clock, ECK is the output clock, and EN and CK must be synchronous signals. When EN is high, CK is transmitted to the ECK terminal for glitch-free output after a delay of one CK clock cycle. The TE signal is the test enable of DFT. When TE is high, ECK is equal to CK.

[0033] Furthermore, in another embodiment, the clock dynamic switching circuit also includes a signal feedback circuit 21, which includes a first feedback unit 211 and a second feedback unit 212; the output end Q of the first level synchronization unit is connected to the input end D of the first feedback unit 221, and the input end of the first feedback signal line 13 is connected to the inverting output end of the first feedback unit 211; the output end Q of the second level synchronization unit is connected to the input end D of the second feedback unit 212, and the input end of the second feedback signal line 12 is connected to the inverting output end of the second feedback unit 212; the signal feedback circuit 21 is specifically used for feedback of clock signals, and the feedback circuit 21 is used to eliminate the overlap of the first clock enable level synchronization signal and the second clock enable level synchronization signal after synchronization, so as to solve the glitch problem that may be generated when multiple asynchronous clocks are switched.

[0034] The clock dynamic switching circuit in this embodiment also includes an inverter 18; the second clock enable signal line 16 is also connected to the first clock enable signal line 17 through the inverter 18, which is used to invert the second clock enable signal sel_clkb on the second clock enable signal line to obtain the first clock enable signal sel_clka.

[0035] The first level synchronization unit in this embodiment includes a first register 201 and a second register 202, an input terminal D of the first register 201 is an input terminal of the first level synchronization unit, a positive phase output terminal Q thereof is connected to an input terminal D of the second register 202, a positive phase output terminal Q of the second register 202 is an output terminal of the first level synchronization unit, and a first clock signal line 14 is respectively connected to the clock terminals of the first register 201 and the second register 202. The second level synchronization unit includes a third register 203 and a fourth register 204, an input terminal D of the third register 203 is an input terminal of the second level synchronization unit, a positive phase output terminal thereof is connected to an input terminal of the fourth register 204, a positive phase output terminal Q of the fourth register 204 is an output terminal of the second level synchronization unit, and a second clock signal line 15 is respectively connected to the clock terminals of the third register 203 and the fourth register 204.

[0036] The first feedback unit includes a fifth register, the positive phase output terminal of the second register 202 is connected to the input terminal D of the fifth register, the input terminal of the first feedback signal line 13 is connected to the negative phase output terminal of the fifth register, and the first clock signal line 14 is also connected to the clock terminal of the fifth register. The second feedback unit 212 includes a sixth register, the positive phase output terminal of the fourth register 202 is connected to the input terminal of the sixth register, the input terminal of the second feedback signal line 12 is connected to the negative phase output terminal of the sixth register, and the second clock signal line 15 is also connected to the clock terminal of the sixth register.

[0037] In this embodiment, the level synchronization circuit 20 is used to synchronize the sel_clka and sel_clkb signals to generate the sel_clka_d2 / sel_clkb_d2 signals, so that sel_clka_d2 is synchronized with clka, and sel_clkb_d2 is synchronized with clkb. Then, the clock gating circuit 21 is used to gate clka and clkb, and the EN signal of the clock gating circuit 21 is the synchronized sel_clka_d2 / sel_clkb_d2 signal. The feedback circuit 21 is used to eliminate the delay of one clock cycle introduced by the clock gating circuit 21.

[0038] Figure 2 for Figure 1 The timing diagram of the switching circuit in Figure 2 It can be seen that when sel_clkb changes from low to high, the arrow in curve A represents the signal change from low-frequency clock to high-frequency clock; when sel_clkb changes from high to low, the arrow in curve B represents the signal change from high-frequency clock to low-frequency clock. Figure 2 It can be seen that there is no clock glitch in the whole process, and the registers are all positive-edge triggered.

[0039] In this embodiment, the sel_clka / sel_clkb signal is fed back to the input AND gate after being synchronized by two levels of positive edge registers and tapped by one level of positive edge register under the clka / clkb clock. The feedback turns off the current clock and then turns on the clock to be switched. In this way, only one clock is flipped at the input end of the OR gate at the same time. At the same time, the registers of the entire clock switching circuit are all triggered by the positive edge of the clock, which solves the problem of the clock half-cycle path, improves the maximum frequency of the circuit operation, and can solve the glitch problem that may occur when multiple asynchronous clocks are switched. In addition, the registers of the entire clock switching circuit are all triggered by the positive edge of the clock, which is conducive to the insertion of the Scanchain (scan chain test) by the back-end tool. The Scan chain will determine whether there are defects in chip manufacturing by shifting in and out data under the control of the external clock edge.

[0040] The above specific examples are used to illustrate the present invention, which is only used to help understand the present invention and is not intended to limit the present invention. For those skilled in the art, according to the concept of the present invention, some simple deductions, modifications or substitutions can be made.

Claims

1. A clock dynamic switching circuit, characterized in that: include: A first AND gate, a second AND gate, a first clock enable signal line, a second clock enable signal line, a first feedback signal line, a second feedback signal line, a first clock signal line, a second clock signal line, a level synchronization circuit, a clock gating circuit, and an OR gate circuit; Wherein, the level synchronization circuit comprises a first level synchronization unit and a second level synchronization unit; The output end of the second feedback signal line and the first clock enable signal line are respectively connected to the input end of the first AND gate, the output end of the first AND gate is connected to the input end of the first level synchronization unit, and the output end of the first level synchronization unit is connected to the input end of the first feedback signal line; The output end of the first feedback signal line and the second clock enable signal line are respectively connected to the input end of the second AND gate, the output end of the second AND gate is connected to the input end of the second level synchronization unit, and the output end of the second level synchronization unit is connected to the input end of the second feedback signal line; The first clock enable signal line is connected to the signal input end of the first level synchronization unit, the second clock enable signal line is connected to the signal input end of the second level synchronization unit, and the first clock enable signal line and the second clock enable signal line are respectively used to input the required synchronized level signals to the first level synchronization unit and the second level synchronization unit; The first clock enable signal line and the second clock enable signal line are used to input the first clock enable signal and the second clock enable signal to the first AND gate and the second AND gate respectively; the first clock enable signal and the second clock enable signal have opposite phases, and the level synchronization circuit is used to synchronize the first clock enable signal and the second clock enable signal, so that the first level synchronization unit and the second level synchronization unit output the first clock enable level synchronization signal and the second clock enable level synchronization signal respectively; The clock gating circuit comprises a first clock gating unit and a second clock gating unit, the output end of the first level synchronization unit is connected to the gating enable end of the first clock gating unit, and the first clock signal line is also connected to the clock input end of the first clock gating unit; the output end of the second level synchronization unit is connected to the gating enable end of the second clock gating unit, and the second clock enable signal line is also connected to the clock input end of the second clock gating unit; The first clock gating unit and the second clock gating unit use the output end of the first clock enable level synchronization signal and the output end of the second clock enable level synchronization signal respectively, and are used to control the on and off of the first clock signal line and the second clock signal line; The output ends of the first clock gating unit and the second clock gating unit are respectively connected to the input ends of the OR gate circuit, and the OR gate circuit is used to obtain a target pulse signal after performing an OR gate operation on the signals output by the first clock gating unit and the second clock gating unit; The clock dynamic switching circuit further includes a signal feedback circuit, which includes a first feedback unit and a second feedback unit; The output end of the first level synchronization unit is connected to the input end of the first feedback unit, and the input end of the first feedback signal line is connected to the output end of the first feedback unit; the output end of the second level synchronization unit is connected to the input end of the second feedback unit, and the input end of the second feedback signal line is connected to the output end of the second feedback unit; the signal feedback circuit is used to eliminate the overlap of the first clock enable level synchronization signal and the second clock enable level synchronization signal after synchronization.

2. The clock dynamic switching circuit according to claim 1, characterized in that: Also includes an inverter; The second clock enable signal line is also connected to the first clock enable signal line through the inverter, and is used to invert the second clock enable signal on the second clock enable signal line to obtain the first clock enable signal.

3. The clock dynamic switching circuit according to claim 1, characterized in that: The first level synchronization unit includes a first register and a second register, the input end of the first register is the input end of the first level synchronization unit, the positive phase output end of the first register is connected to the input end of the second register, the positive phase output end of the second register is the output end of the first level synchronization unit, and the first clock signal line is connected to the clock ends of the first register and the second register respectively; The second level synchronization unit includes a third register and a fourth register, the input end of the third register is the input end of the second level synchronization unit, the positive phase output end of the third register is connected to the input end of the fourth register, the positive phase output end of the fourth register is the output end of the second level synchronization unit, and the second clock signal line is connected to the clock ends of the third register and the fourth register respectively.

4. The clock dynamic switching circuit according to claim 3, characterized in that: The first feedback unit includes a fifth register, a positive phase output terminal of the second register is connected to an input terminal of the fifth register, an input terminal of the first feedback signal line is connected to an inverting phase output terminal of the fifth register, and the first clock signal line is also connected to a clock terminal of the fifth register; The second feedback unit includes a sixth register, the positive phase output terminal of the fourth register is connected to the input terminal of the sixth register, the input terminal of the second feedback signal line is connected to the negative phase output terminal of the sixth register, and the second clock signal line is also connected to the clock terminal of the sixth register.

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