A dual-output GIP circuit

Abstract

The present invention relates to the technical field of GIP circuits, and particularly relates to a dual-output GIP circuit, which includes a pre-charge module, a first output module, a second output module, a voltage regulation module, a first pull-down module, a second pull-down module, and a third pull-down module. The first output module is electrically connected to the pre-charge module, the voltage regulation module, and the third pull-down module respectively. The third pull-down module is electrically connected to the pre-charge module, the first pull-down module, and the second pull-down module respectively. The voltage regulation module is electrically connected to the first output module, the second output module, and the first pull-down module respectively. The second pull-down module is electrically connected to the second output module and the first pull-down module respectively. Through the cooperation among the pre-charge module, the first output module, the second output module, the voltage regulation module, the first pull-down module, the second pull-down module, and the third pull-down module, a row of GIP circuits is used to drive two rows of pixels. While ensuring the same charging rate for each row of pixels, the size of the left and right borders of the screen is reduced, and the screen-to-body ratio of the screen is increased.

Description

Technical Field

[0001] The present invention relates to the technical field of GIP circuits, and particularly to a dual-output GIP circuit. Background Art

[0002] The full-screen display not only improves the appearance of the product, making the product look more technological, but also allows the front area of the product to accommodate a larger screen, enhancing the user's visual experience. Therefore, the full-screen technology has become a popular trend in current display devices. The current definition of a full-screen refers to a display device with a super-high screen-to-body ratio design, aiming for a screen-to-body ratio close to 100%. However, due to current technical limitations, the so-called full-screen products in the industry do not have a product with a screen-to-body ratio of 100%, but are ultra-narrow border products with a high screen-to-body ratio. The high screen-to-body ratio design has already formed a trend, especially with a very high penetration rate in mid- to high-end models.

[0003] In order to increase the screen-to-body ratio of the screen, reducing the border of the screen has become an inevitable trend in current technological development. In an active matrix liquid crystal display (fully known as Active Matrix Liquid Crystal Display), each pixel has a TFT (fully known as Thin Film Transistor), whose gate is connected to the horizontal scanning line (also called the scanning signal line), the drain is connected to the vertical data line (also called the source trace), and the source is connected to the pixel electrode. If a sufficient positive voltage is applied to a certain scanning line in the horizontal direction, all the TFTs on this line will be turned on. At this time, the pixel electrode on this line will be connected to the vertical data line, and the video signal voltage on the data line will be written into the pixel, controlling the light transmittance of different liquid crystals to achieve the effect of controlling colors. When designing the scanning drive of the panel, the traditional technology uses COF (fully known as Chip On Film, which is a chip flexible film packaging technology that fixes an integrated circuit on a flexible circuit board) and COG (fully known as Chip On Glass, that is, the chip is directly bonded to the glass) processes. The products obtained by this technology not only have large left and right borders, but also have high costs. Another new GIP (Gate In Panel) technology has the basic concept of integrating the gate driver of the LCD Panel (that is, the liquid crystal display panel, and the full name of LCD is Liquid Crystal Display) on the glass substrate to replace the technology of using an external silicon wafer. It not only saves costs and reduces the border, but also can eliminate the process of gate direction bonding, which is extremely beneficial to improving production capacity and increasing the integration of the TFT-LCD panel.

[0004] The GIP technology reduces the usage of gate driver ICs, lowers power consumption and costs, and at the same time enables the reduction of the border of the display panel to achieve a narrow border design. It is a technology worthy of attention. However, the mainstream driving method of the current GIP circuit technology is the Gate method where one-level GIP drives one row of pixels, and the screen-to-body ratio of its screen is not high. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a dual-output GIP circuit that improves the screen-to-body ratio while ensuring the same charging rate for each row of pixels.

[0006] To solve the above technical problem, the technical solution adopted by the present invention is:

[0007] A dual-output GIP circuit includes a pre-charge module, a first output module, a second output module, a voltage stabilization module, a first pull-down module, a second pull-down module, and a third pull-down module. The first output module is electrically connected to the pre-charge module, the voltage stabilization module, and the third pull-down module respectively. The third pull-down module is electrically connected to the pre-charge module, the first pull-down module, and the second pull-down module respectively. The voltage stabilization module is electrically connected to the first output module, the second output module, and the first pull-down module respectively. The second pull-down module is electrically connected to the second output module and the first pull-down module respectively. The output end of the first output module is connected to the scan signal line G n connection, the output end of the second output module is connected to the scan signal line G n+2 electrical connection, and the parameter n in the scan signal line G n and the scan signal line G n+2 are all positive integers greater than or equal to 2.

[0008] The beneficial effects of the present invention are as follows:

[0009] The pre-charge module is set to play a pre-charge role; the first output module and the second output module are set to play a role in outputting signals; the first pull-down module, the second pull-down module, and the third pull-down module are set to play a role in pulling down the output electrical signal; the voltage stabilization module is set to control the output waveforms of the first output module and the second output module to ensure the consistency of the output waveforms of the first output module and the second output module, thereby ensuring the same charging rate for the corresponding row of pixels; the first pull-down module is the pull-down module of the first output module, and the second pull-down module is the pull-down module of the second output module. Through the cooperation among the pre-charge module, the first output module, the second output module, the voltage stabilization module, the first pull-down module, the second pull-down module, and the third pull-down module, this solution uses one-level GIP circuit to drive two rows of pixels. While ensuring the same charging rate for each row of pixels, it not only reduces the number of GIPs, but also reduces the size of the left and right borders of the screen, improving the screen-to-body ratio. Description of the Drawings

[0010] Figure 1 It is a block connection diagram of a dual-output GIP circuit according to the present invention;

[0011] Figure 2 It is a specific circuit schematic diagram of a dual-output GIP circuit according to the present invention;

[0012] Figure 3 It is a timing diagram of a dual-output GIP circuit according to the present invention;

[0013] Figure 4 It is a circuit diagram during the pre-charge period of a dual-output GIP circuit according to the present invention;

[0014] Figure 5 It is a circuit diagram during the output period of a dual-output GIP circuit according to the present invention;

[0015] Figure 6 It is a circuit diagram during the pull-down period of a dual-output GIP circuit according to the present invention;

[0016] Figure 7 It is a circuit diagram during the pull-down maintenance period of a dual-output GIP circuit according to the present invention;

[0017] Figure 8 It is a simulation result diagram of a dual-output GIP circuit according to the present invention;

[0018] Figure 9 It is a simulation result diagram of a dual-output GIP circuit according to the present invention;

[0019] Label Description:

[0020] 1. Pre-charge module; 2. First output module; 3. Voltage regulation module; 4. Second output module; 5. Third pull-down module; 6. First pull-down module; 7. Second pull-down module. Detailed Embodiments

[0021] To describe in detail the technical content, achieved objectives and effects of the present invention, the following is described in conjunction with the embodiments and with reference to the drawings.

[0022] Please refer to Figure 1 , the technical solution provided by the present invention:

[0023] A dual-output GIP circuit includes a precharge module, a first output module, a second output module, a voltage regulation module, a first pull-down module, a second pull-down module, and a third pull-down module. The first output module is electrically connected to the precharge module, the voltage regulation module, and the third pull-down module respectively. The third pull-down module is electrically connected to the precharge module, the first pull-down module, and the second pull-down module respectively. The voltage regulation module is electrically connected to the first output module, the second output module, and the first pull-down module respectively. The second pull-down module is electrically connected to the second output module and the first pull-down module respectively. The output terminal of the first output module is connected to the scan signal line G n connection, and the output terminal of the second output module is connected to the scan signal line G n+2 electrical connection. The parameter n in the scan signal line G n and the scan signal line G n+2 is a positive integer greater than or equal to 2.

[0024] As can be seen from the above description, the beneficial effects of the present invention are as follows:

[0025] The precharge module is set to play a precharge role; the first output module and the second output module are set to play a role in outputting signals; the first pull-down module, the second pull-down module, and the third pull-down module are set to play a role in pulling down the output electrical signal; the voltage regulation module is set to control the output waveforms of the first output module and the second output module, ensuring the consistency of the output waveforms of the first output module and the second output module, so as to ensure the same charging rate of the corresponding row of pixels; the first pull-down module is the pull-down module of the first output module, and the second pull-down module is the pull-down module of the second output module. Through the cooperation between the precharge module, the first output module, the second output module, the voltage regulation module, the first pull-down module, the second pull-down module, and the third pull-down module, this solution uses a first-level GIP circuit to drive two rows of pixels. While ensuring the same charging rate for each row of pixels, it not only reduces the number of GIPs but also reduces the size of the left and right borders of the screen, improving the screen-to-body ratio.

[0026] Further, the first output module includes a field-effect transistor T4 and a capacitor C2. The gate of the field-effect transistor T4 is electrically connected to one end of the capacitor C2, the precharge module, the third pull-down module, and the voltage regulation module respectively. The source of the field-effect transistor T4 is electrically connected to the other end of the capacitor C2, the first pull-down module, and the scan signal line G n electrical connection, and the drain of the field-effect transistor T4 is connected to the clock signal CK1.

[0027] Further, the second output module includes a field-effect transistor T8 and a capacitor C3. The gate of the field-effect transistor T8 is electrically connected to one end of the capacitor C3 and the voltage regulation module respectively. The source of the field-effect transistor T8 is electrically connected to the other end of the capacitor C3, the second pull-down module, and the scan signal line G n+2Electrically connected, the drain of the field effect transistor T8 is connected to the clock signal CK3.

[0028] Further, the precharging module includes a field effect transistor T1 and a field effect transistor T7. The gate of the field effect transistor T1 is electrically connected to the scanning signal line G n-2 Electrically connected, the drain of the field effect transistor T1 is electrically connected to the source of the field effect transistor T7, the third pull-down module, and the first output module respectively. The gate of the field effect transistor T7 is electrically connected to the scanning signal line G n+6 Electrically connected, the scanning signal line G n-2 and the scanning signal line G n+6 The parameter n in both is a positive integer greater than or equal to 2.

[0029] Further, the voltage stabilizing module includes a field effect transistor T9. The source of the field effect transistor T9 is electrically connected to the second output module, and the drain of the field effect transistor T9 is electrically connected to the first output module.

[0030] As can be seen from the above description, the field effect transistor T9 is changed to a voltage stabilizing module to control the output waveforms of the first output module and the second output module, ensure the consistency of the output waveforms of the first output module and the second output module, and thus ensure the same charging rate of the corresponding row of pixels.

[0031] Further, the first pull-down module includes a field effect transistor T5 and a field effect transistor T6. The gate of the field effect transistor T5 is connected to the clock signal CK5. The drain of the field effect transistor T5 is electrically connected to the drain of the field effect transistor T6 and the first output module respectively. The source of the field effect transistor T5 is electrically connected to the source of the field effect transistor T6, the second pull-down module, and the third pull-down module respectively. The gate of the field effect transistor T6 is connected to the third pull-down module.

[0032] Further, the second pull-down module includes a field effect transistor T10 and a field effect transistor T11. The gate of the field effect transistor T10 is electrically connected to the first pull-down module and the third pull-down module respectively. The source of the field effect transistor T10 is electrically connected to the source of the field effect transistor T11, the first pull-down module, and the third pull-down module respectively. The gate of the field effect transistor T11 is connected to the clock signal CK2. The drain of the field effect transistor T11 is electrically connected to the second output module and the drain of the field effect transistor T10 respectively.

[0033] Further, the third pull-down module includes a field-effect transistor T2, a field-effect transistor T3, and a capacitor C1. The gate of the field-effect transistor T2 is electrically connected to the pre-charge module and the first output module respectively. The drain of the field-effect transistor T2 is electrically connected to the gate of the field-effect transistor T3, one end of the capacitor C1, and the first pull-down module respectively. The other end of the capacitor C1 is connected to the clock signal CK1. The source of the field-effect transistor T2 is electrically connected to the source of the field-effect transistor T3, the first pull-down module, and the second pull-down module respectively.

[0034] Please refer to Figures 1 to 9 , Embodiment 1 of the present invention is as follows:

[0035] Please refer to Figure 1 , A dual-output GIP circuit, characterized in that it includes a pre-charge module 1, a first output module 2, a second output module 4, a voltage stabilization module 3, a first pull-down module 6, a second pull-down module 7, and a third pull-down module 5. The first output module 2 is electrically connected to the pre-charge module 1, the voltage stabilization module 3, and the third pull-down module 5 respectively. The third pull-down module 5 is electrically connected to the pre-charge module 1, the first pull-down module 6, and the second pull-down module 7 respectively. The voltage stabilization module 3 is electrically connected to the first output module 2, the second output module 4, and the first pull-down module 6 respectively. The second pull-down module 7 is electrically connected to the second output module 4 and the first pull-down module 6 respectively. The output end of the first output module 2 is connected to the scan signal line G n connection, the output end of the second output module 4 is connected to the scan signal line G n+2 electrically connected, and the parameters n in the scan signal line G n and the scan signal line G n+2 are all positive integers greater than or equal to 2.

[0036] Please refer to Figure 2 , The first output module 2 includes a field-effect transistor T4 and a capacitor C2. The gate of the field-effect transistor T4 is electrically connected to one end of the capacitor C2, the pre-charge module 1, the third pull-down module 5, and the voltage stabilization module 3 respectively. The source of the field-effect transistor T4 is electrically connected to the other end of the capacitor C2, the first pull-down module 6, and the scan signal line G n electrically connected, and the drain of the field-effect transistor T4 is connected to the clock signal CK1.

[0037] Please refer to Figure 2 , The second output module 4 includes a field-effect transistor T8 and a capacitor C3. The gate of the field-effect transistor T8 is electrically connected to one end of the capacitor C3 and the voltage stabilization module 3 respectively. The source of the field-effect transistor T8 is electrically connected to the other end of the capacitor C3, the second pull-down module 7, and the scan signal line G n+2 electrically connected, and the drain of the field-effect transistor T8 is connected to the clock signal CK3.

[0038] Please refer to Figure 2, the pre-charge module 1 includes a field effect transistor T1 and a field effect transistor T7. The gate of the field effect transistor T1 is electrically connected to the scan signal line G n-2 electrically connected. The drain of the field effect transistor T1 is electrically connected to the source of the field effect transistor T7, the third pull-down module 5, and the first output module 2 respectively. The gate of the field effect transistor T7 is electrically connected to the scan signal line G n+6 electrically connected. The parameter n in the scan signal line G n-2 and the scan signal line G n+6 is a positive integer greater than or equal to 2.

[0039] Please refer to Figure 2 , the voltage stabilization module 3 includes a field effect transistor T9. The source of the field effect transistor T9 is electrically connected to the second output module 4, and the drain of the field effect transistor T9 is electrically connected to the first output module 2.

[0040] Please refer to Figure 2 , the first pull-down module 6 includes a field effect transistor T5 and a field effect transistor T6. The gate of the field effect transistor T5 is connected to the clock signal CK5. The drain of the field effect transistor T5 is electrically connected to the drain of the field effect transistor T6 and the first output module 2 respectively. The source of the field effect transistor T5 is electrically connected to the source of the field effect transistor T6, the second pull-down module 7, and the third pull-down module 5 respectively. The gate of the field effect transistor T6 is electrically connected to the third pull-down module 5.

[0041] Please refer to Figure 2 , the second pull-down module 7 includes a field effect transistor T10 and a field effect transistor T11. The gate of the field effect transistor T10 is electrically connected to the first pull-down module 6 and the third pull-down module 5 respectively. The source of the field effect transistor T10 is electrically connected to the source of the field effect transistor T11, the first pull-down module 6, and the third pull-down module 5 respectively. The gate of the field effect transistor T11 is connected to the clock signal CK2. The drain of the field effect transistor T11 is electrically connected to the second output module 4 and the drain of the field effect transistor T10 respectively.

[0042] Please refer to Figure 2 , the third pull-down module 5 includes a field effect transistor T2, a field effect transistor T3, and a capacitor C1. The gate of the field effect transistor T2 is electrically connected to the pre-charge module 1 and the first output module 2 respectively. The drain of the field effect transistor T2 is electrically connected to the gate of the field effect transistor T3, one end of the capacitor C1, and the first pull-down module 6 respectively. The other end of the capacitor C1 is connected to the clock signal CK1. The source of the field effect transistor T2 is electrically connected to the source of the field effect transistor T3, the first pull-down module 6, and the second pull-down module 7 respectively.

[0043] The above-mentioned field effect transistors T1 to T13 are all N-type TFTs, and the capacitance values of the capacitors C1, C2, and C3 are all 1000 fF.

[0044] The working principle of the above double-output GIP circuit is as follows:

[0045] Please refer to Figure 3 , in this timing diagram, it is divided into four time periods, namely the pre-charge period, the output period, the pull-down period, and the pull-down maintenance period. The working states of the corresponding TFTs (fully known as Thin Film Transistor) are different, as follows:

[0046] Please refer to Figure 4 , which is a schematic diagram of the pre-charge period. This schematic diagram corresponds to Figure 3 the t1 moment. At this time, the scan signal line G n-2 , the potential signal line FW, and the potential signal line VGH are all at high potential. The corresponding field effect transistors T1, T2, T4, T8, and T9 are all turned on; the scan signal line G n+6 , the potential signal line BW, the clock signals CK1, CK3, CK5, and CK7 are at low potential. The corresponding field effect transistors T3, T5, T6, T7, T10, and T11 are all turned off; in this stage, since both the field effect transistors T1 and T9 are turned on and FW is at high potential, the capacitors C2 and C3 are charged, and the potentials of the Q1 node and the Q2 node rise to H. At this time, both the field effect transistors T4 and T8 are turned on. Since the clock signals CK1 and CK3 are both at low potential, the output of the scan signal line G n and the scan signal line G n+2 is at low potential. The P node is pulled to low potential by VGL due to the turn-on of the field effect transistor T2.

[0047] Please refer to Figure 5 , which is a schematic diagram of the output period. This schematic diagram corresponds to Figure 3 the t2 moment. At this time, the clock signals CK1, CK3, the potential signal line FW, the potential signal line VGH, and the Q node are all at high potential. The corresponding field effect transistors T2, T4, T8, and T9 are all turned on; the scan signal line G n-2 , the scan signal line G n+6 , the potential signal line BW, the clock signals CK5, CK7, and the P node are all at low potential. The corresponding field effect transistors T1, T3, T5, T6, T7, T10, and T11 are all turned off; in this stage, since both the field effect transistors T4 and T8 are turned on and the clock signals CK1 and CK3 are both at high potential, the output GIP signal is output at this time, that is, the scan signal line G n and the scan signal line G n+2The outputs are all at high potential. Due to the coupling effect of capacitor C2 and capacitor C3, the Q1 node and the Q2 node are respectively coupled to the potential of 2H, stabilizing the scan signal line G n and the scan signal line G n+2 outputs. At the same time, it also stabilizes the turn-on of the field-effect transistor T2, pulling the P node from VGL to the low potential continuously.

[0048] Please refer to Figure 6 , which is a schematic diagram during the pull-down period. This schematic diagram corresponds to Figure 3 the t3 moment, at this time G n+6 , the clock signal CK5, the clock signal CK7, the potential signal line FW, and the potential signal line VGH are all at high potential, and the corresponding field-effect transistors T5, T7, T9, and T11 are all turned on; the scan signal line G n-2 , the potential signal line BW, the clock signal CK1, and the clock signal CK3 are all at low potential, and the corresponding field-effect transistors T1, T2, T3, T4, T6, T8, and T10 are all turned off; during this stage, since the field-effect transistor T7 is turned on and the potential signal line BW is at low potential, the Q1 node and the Q2 node are pulled down to the low potential; the field-effect transistors T5 and T11 are affected by the high potential of the clock signal CK1 / clock signal CK3, so the field-effect transistor T5 is turned on, pulling the scan signal line G n and the scan signal line G n+2 down to the low potential; the P node is affected by the capacitor C1 and couples the low potential of the clock signal CK1, so the P node is at low potential.

[0049] Please refer to Figure 7 , which is a schematic diagram during the pull-down maintenance period. This schematic diagram corresponds to Figure 3 the t4 moment, at this time the potential signal line FW and the potential signal line VGH are both at high potential, and the corresponding field-effect transistor T9 is turned on; the scan signal line G n-2 , the scan signal line G n+6 and the potential signal line BW are all at low potential, and the corresponding field-effect transistors T1 and T7 are both turned off. The clock signals CK1, CK3, CK5, and CK7 are at high and low potentials in sequence, which stabilizes the low potentials of the Q node, the scan signal line G n and the scan signal line G n+2 , making them stable at low potential within the time of one frame after output.

[0050] Figure 8 and Figure 9 are the simulation result diagrams of the dual-output GIP circuit designed in this scheme: In this simulation result diagram, it can be seen that the output signals G n and Gn+2 The results are normal. The potentials of the Q1 node and the Q2 node are normal, and the coupling values are also similar. The potential of the P node is normal, and the pixel charging rates of the upper and lower levels of the two Gout signals output by the same GIP are also the same (in this patent, a 6.8-inch a-Si HD product is taken as an example for simulation, and the charging rate of the pixels of adjacent output signals is 92%).

[0051] Figure 8 In the waveform diagram in [reference], from top to bottom are the output waveform diagrams of the scanning signal line Gn-2, the clock signal CK1, the clock signal CK3, the clock signal CK5, the clock signal CK7, and the Q node (the output waveforms of the Q1 node and the Q2 node are the same, and the Q node is used to represent them in the figure).

[0052] Figure 9 In the waveform diagram in [reference], from top to bottom are the output waveform diagrams of the Q1 node, CL[1] (the gate output signal of the field effect transistor T4), CL[3] (the gate output signal of the field effect transistor T8), and the P node.

[0053] In summary, a dual-output GIP circuit provided by the present invention has a pre-charge function through the pre-charge module; has an output signal function through the first output module and the second output module; has a function of pulling down the output electrical signal through the first pull-down module, the second pull-down module, and the third pull-down module; and has a voltage stabilization module to control the output waveforms of the first output module and the second output module, ensuring the consistency of the output waveforms of the first output module and the second output module, thereby ensuring the same charging rate of the corresponding row of pixels. The first pull-down module is the pull-down module of the first output module, and the second pull-down module is the pull-down module of the second output module. Through the cooperation among the pre-charge module, the first output module, the second output module, the voltage stabilization module, the first pull-down module, the second pull-down module, and the third pull-down module, this solution uses a single-stage GIP circuit to drive two rows of pixels. While ensuring the same charging rate of each row of pixels, it not only reduces the number of GIPs but also reduces the size of the left and right borders of the screen, improving the screen-to-body ratio of the screen.

[0054] The above are only the embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. A dual-output GIP circuit, characterized in that, It includes a pre-charge module, a first output module, a second output module, a voltage stabilization module, a first pull-down module, a second pull-down module and a third pull-down module. The first output module is electrically connected to the pre-charge module, the voltage stabilization module and the third pull-down module respectively. The third pull-down module is electrically connected to the pre-charge module, the first pull-down module and the second pull-down module respectively. The voltage stabilization module is electrically connected to the first output module, the second output module and the first pull-down module respectively. The second pull-down module is electrically connected to the second output module and the first pull-down module respectively. The output end of the first output module is connected to the scan signal line G n connection, and the output end of the second output module is electrically connected to the scan signal line G n+2 electrical connection. The parameter n in the scan signal line G n and the scan signal line G n+2 is a positive integer greater than or equal to 2; The first output module includes a field effect transistor T4 and a capacitor C2. The gate of the field effect transistor T4 is electrically connected to one end of the capacitor C2, a precharge module, a third pull-down module, and a voltage stabilizing module respectively. The source of the field effect transistor T4 is electrically connected to the other end of the capacitor C2, a first pull-down module, and a scan signal line G n electrically connected, and the drain of the field effect transistor T4 is connected to a clock signal CK1; The pre-charge module includes a field effect transistor T1 and a field effect transistor T7. The gate of the field effect transistor T1 is electrically connected to the scan signal line G n-2 The drain of the field effect transistor T1 is electrically connected to the source of the field effect transistor T7, the third pull-down module, and the first output module respectively. The gate of the field effect transistor T7 is electrically connected to the scan signal line G n+6 The scan signal line G n-2 and the scan signal line G n+6 where the parameter n in both is a positive integer greater than or equal to 2; The first pull-down module includes a field effect transistor T5 and a field effect transistor T6. The gate of the field effect transistor T5 is connected to the clock signal CK5. The drain of the field effect transistor T5 is electrically connected to the drain of the field effect transistor T6 and the first output module respectively. The source of the field effect transistor T5 is electrically connected to the source of the field effect transistor T6, the second pull-down module and the third pull-down module respectively. The gate of the field effect transistor T6 is electrically connected to the third pull-down module; The second pull-down module includes a field effect transistor T10 and a field effect transistor T11. The gate of the field effect transistor T10 is electrically connected to the first pull-down module and the third pull-down module respectively. The source of the field effect transistor T10 is electrically connected to the source of the field effect transistor T11, the first pull-down module and the third pull-down module respectively. The gate of the field effect transistor T11 is connected to the clock signal CK2. The drain of the field effect transistor T11 is electrically connected to the second output module and the drain of the field effect transistor T10 respectively; The third pull-down module includes a field effect transistor T2, a field effect transistor T3 and a capacitor C1. The gate of the field effect transistor T2 is electrically connected to the pre-charge module and the first output module respectively. The drain of the field effect transistor T2 is electrically connected to the gate of the field effect transistor T3, one end of the capacitor C1 and the first pull-down module respectively. The other end of the capacitor C1 is connected to the clock signal CK1. The source of the field effect transistor T2 is electrically connected to the source of the field effect transistor T3, the first pull-down module and the second pull-down module respectively.

2. The dual-output GIP circuit according to claim 1, wherein The second output module includes a field effect transistor T8 and a capacitor C3. One end of the capacitor C3 and the voltage stabilizing module are electrically connected to the gate of the field effect transistor T8 respectively. The other end of the capacitor C3, the second pull-down module and the scan signal line G are electrically connected to the source of the field effect transistor T8 respectively. n+2 The drain of the field effect transistor T8 is connected to the clock signal CK3.

3. The dual-output GIP circuit according to claim 1, wherein The voltage stabilization module includes a field effect transistor T9. The source of the field effect transistor T9 is electrically connected to the second output module. The drain of the field effect transistor T9 is electrically connected to the first output module.

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