Semiconductor Package

Abstract

A semiconductor package is provided. The semiconductor package includes: a first semiconductor chip and a second semiconductor chip arranged on a substrate; a barrier layer arranged on the first semiconductor chip and the second semiconductor chip and including an opening through which at least a portion of the first semiconductor chip is exposed; and a heat transfer portion arranged on the barrier layer, extending along an upper surface of the barrier layer and filling the opening.

Description

[0001] Cross-references to related technologies

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0077851 filed on June 28, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor package. Background Art

[0004] Recently, with the demand for high-performance device realization, the size of semiconductor chips and the accompanying semiconductor package size have increased. On the other hand, the thickness of semiconductor packages has decreased inversely with the trend of thinning of electronic devices.

[0005] On the other hand, semiconductor packages have been developed to meet the requirements of multi-function, large capacity and miniaturization. To this end, by integrating a plurality of semiconductor chips into one semiconductor package, it has been possible to perform high capacity and multi-function while greatly reducing the size of the semiconductor package.

[0006] Therefore, methods of efficiently dissipating heat generated from semiconductor chips are continuously discussed. Summary of the invention

[0007] Aspects of the inventive concept provide a semiconductor package that effectively controls heat generated from a semiconductor chip.

[0008] Aspects of the inventive concept also provide a semiconductor package having improved product reliability.

[0009] According to some embodiments conceived in the present invention, a semiconductor package includes: a first semiconductor chip and a second semiconductor chip arranged on a substrate; a barrier layer, which is arranged on the first semiconductor chip and the second semiconductor chip and includes an opening, and at least a portion of the first semiconductor chip is exposed through the opening; and a heat transfer portion, which is arranged on the barrier layer, extends along an upper surface of the barrier layer and fills the opening.

[0010] According to some embodiments of the present invention, a semiconductor package includes: a first semiconductor chip arranged on a substrate; a second semiconductor chip arranged on the substrate and spaced apart from the first semiconductor chip; and a heat transfer portion arranged on the first semiconductor chip and the second semiconductor chip, in direct contact with the first semiconductor chip, and not in contact with the second semiconductor chip.

[0011] According to some embodiments conceived by the present invention, a semiconductor package includes: a substrate; a molding portion arranged on the substrate and including a first groove and a second groove, through which an upper surface of the substrate is exposed; a first semiconductor chip arranged in the first groove and electrically connected to the substrate; a second semiconductor chip arranged in the second groove and electrically connected to the substrate; a barrier layer arranged on an upper surface of the molding portion, covering the second semiconductor chip and including an opening, through which at least a portion of the first semiconductor chip is exposed; and a heat transfer portion arranged on the barrier layer and in direct contact with the first semiconductor chip exposed through the opening.

[0012] However, aspects of the inventive concept are not limited to those set forth herein. The above and other aspects of the inventive concept will become more apparent to one of ordinary skill in the art to which the inventive concept pertains by referring to the detailed description of the inventive concept given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects and features of the present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0014] Figure 1 are diagrams for explaining semiconductor packages according to some embodiments of the inventive concept;

[0015] Figure 2 are diagrams for explaining semiconductor packages according to some embodiments of the inventive concept;

[0016] Figure 3 are diagrams for explaining semiconductor packages according to some embodiments of the inventive concept;

[0017] Figure 4 are diagrams for explaining semiconductor packages according to some embodiments of the inventive concept;

[0018] Figure 5 are diagrams for explaining semiconductor packages according to some embodiments of the inventive concept;

[0019] Figure 6 are diagrams for explaining semiconductor packages according to some embodiments of the inventive concept;

[0020] Figure 7 are diagrams for explaining semiconductor packages according to some embodiments of the inventive concept;

[0021] Figure 8 is a diagram of an intermediate stage for explaining a method of manufacturing a semiconductor package according to some embodiments of the inventive concept;

[0022] Fig. 9 is a diagram of an intermediate stage for explaining a method of manufacturing a semiconductor package according to some embodiments of the inventive concept;

[0023] Fig.10 is a diagram of an intermediate stage for explaining a method of manufacturing a semiconductor package according to some embodiments of the inventive concept;

[0024] Fig.11 is a diagram of an intermediate stage for explaining a method of manufacturing a semiconductor package according to some embodiments of the inventive concept;

[0025] Fig.12 is a diagram of an intermediate stage for explaining a method of manufacturing a semiconductor package according to some embodiments of the inventive concept;

[0026] Fig.13 is a diagram of an intermediate stage for explaining a method of manufacturing a semiconductor package according to some embodiments of the inventive concept;

[0027] Fig.14 is a diagram of an intermediate stage for explaining a method of manufacturing a semiconductor package according to some embodiments of the inventive concept;

[0028] Fig.15 is an intermediate stage diagram for explaining a method of manufacturing a semiconductor package according to some embodiments of the inventive concept; and

[0029] Fig.16 1 is a diagram of an intermediate stage for explaining a method of manufacturing a semiconductor package according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0030] Figure 1 are views for explaining semiconductor packages according to some embodiments of the inventive concept.

[0031] Reference Figure 1 , a semiconductor package according to some embodiments of the inventive concept may include a substrate 100 , a first connection terminal 110 , a molding portion 200 , a second connection terminal 210 , a first semiconductor chip 300 , a second semiconductor chip 400 , a barrier layer 500 , and a heat transfer portion 600 .

[0032] The substrate 100 may be an interposer substrate, and may include, for example, FR4, polyimide, silicon, or glass.

[0033] The substrate 100 may include an upper surface 100 a and a lower surface 100 b facing each other.

[0034] The first connection terminal 110 may be disposed on the lower surface 100b of the substrate 100. Although the first connection terminal 110 may include, but is not limited to, a conductive bump, the first connection terminal 110 may be a conductive ball or a solder ball.

[0035] The semiconductor package may be electrically connected to an external device or another package substrate through the first connection terminals 110. The number of the first connection terminals 110 shown in the drawings is only for convenience of explanation and is not limited thereto.

[0036] The first semiconductor chip 300 and the second semiconductor chip 400 may be disposed on the upper surface 100 a of the substrate 100 . The second connection terminals 210 may be disposed on one surface of the first semiconductor chip 300 and one surface of the second semiconductor chip 400 .

[0037] For example, the second connection terminals 210 may be solder balls or conductive bumps. The first semiconductor chip 300 and the second semiconductor chip 400 may be electrically connected to the substrate 100 through the second connection terminals 210 .

[0038] The substrate 100 may include a plurality of insulating films and internal wiring layers. The first semiconductor chip 300 and the second semiconductor chip 400 may be electrically connected to each other through the internal wiring layers of the substrate 100.

[0039] The first semiconductor chip 300 and the second semiconductor chip 400 may be memory chips or logic chips. In the following description, the first semiconductor chip 300 may be a logic chip, and the second semiconductor chip 400 may be a memory chip.

[0040] For example, the logic chip may be a central processing unit (CPU), a controller, an application specific integrated circuit (ASIC), etc. For example, the memory chip may be a volatile memory chip such as a dynamic random access memory (DRAM) or a static RAM (SRAM), or a non-volatile memory scale chip such as a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FeRAM), or a resistive RAM (RRAM).

[0041] In addition, the memory chip may be a high bandwidth memory (HBM) memory chip in which a plurality of DRAM memory chips are stacked.

[0042] The molding part 200 may be formed on the upper surface 100 a of the substrate 100 . The molding part 200 may include a first trench 230 and a second trench 250 . The first semiconductor chip 300 may be disposed in the first trench 230 , and the second semiconductor chip 400 may be disposed in the second trench 250 .

[0043] The molding part 200 may be interposed between the first semiconductor chip 300 and the second semiconductor chip 400. The molding part 200 may fill a space between the first semiconductor chip 300 and the substrate 100 and a space between the second semiconductor chip 400 and the substrate 100. The molding part 200 may fill a space between the second connection terminals 210 adjacent to each other.

[0044] That is, the molding portion 200 may wrap the first semiconductor chip 300 , the second semiconductor chip 400 , and the second connection terminals 210 .

[0045] The molding part 200 may expose upper surfaces of the first semiconductor chip 300 and the second semiconductor chip 400. For example, the upper surface of the molding part 200 may be located on the same plane as the upper surfaces of the first semiconductor chip 300 and the second semiconductor chip 400.

[0046] The molding portion 200 may be formed to protect the first semiconductor chip 300 and the second semiconductor chip 400 .

[0047] For example, the molding portion 200 may include two or more of epoxy molding compound (EMC) or silicon hybrid material.

[0048] The barrier layer 500 may be disposed on upper surfaces of the first semiconductor chip 300, the second semiconductor chip 400, and the molding part 220. The barrier layer 500 may include an opening 510 through which at least a portion of the first semiconductor chip 300 is exposed.

[0049] The width W2 of the barrier layer 500 may be greater than the width W1 of the second semiconductor chip 400. The barrier layer 500 may cover the entire upper surface of the second semiconductor chip 400. The barrier layer 500 may cover at least a portion of the upper surface of the first semiconductor chip 300.

[0050] The second semiconductor chip 400 may have a structure in which a plurality of memory chips are stacked. The thickness of each memory chip included in the second semiconductor chip 400 is thinner than that of the first semiconductor chip 300. Therefore, when a metal material layer is formed on each memory chip included in the second semiconductor chip 400, the metal included in the metal material layer can be easily diffused into the element portion of the memory chip included in the second semiconductor chip 400. That is, the metal included in the metal material layer can be easily diffused into the uppermost memory chip of the second semiconductor chip 400.

[0051] Therefore, since the barrier layer 500 is disposed on the upper surface of the second semiconductor chip 400 , the reliability of the second semiconductor chip 400 may be maintained.

[0052] For example, the barrier layer 500 may include, but is not limited to, a photo-imageable dielectric (PID). That is, the barrier layer 500 may include a photosensitive insulating material. The barrier layer 500 may include epoxy resin or polyimide.

[0053] The heat transfer portion 600 may be disposed on the barrier layer 500. The heat transfer portion 600 may extend along an upper surface of the barrier layer 500.

[0054] The heat transfer portion 600 may fill the opening 510 of the barrier layer 500. That is, the heat transfer portion 600 may be continuously formed along the upper surface of the barrier layer 500 and the upper surface of the first semiconductor chip 300.

[0055] The heat transfer portion 600 may be in direct contact with the first semiconductor chip 300 . The heat transfer portion 600 may not be in contact with the second semiconductor chip 400 .

[0056] Since the first semiconductor chip 300 may be a logic chip, the first semiconductor chip 300 may generate more heat than the second semiconductor chip 400. Since the first semiconductor chip 300 is in direct contact with the heat transfer portion 600, the heat generated from the first semiconductor chip 300 may be easily dissipated to the outside through the heat transfer portion 600. Therefore, the reliability and operational performance of the semiconductor package according to some embodiments of the inventive concept may be improved.

[0057] For example, the heat transfer portion 600 may include an adhesive metal layer 610 and a heat transfer material layer 620 .

[0058] The adhesive metal layer 610 may be continuously formed along the upper surface of the barrier layer 500 and the upper surface of the first semiconductor chip 300 .

[0059] The adhesive metal layer 610 may be interposed between the heat transfer material layer 620 and the barrier layer 500. The adhesive metal layer 610 may be interposed between the heat transfer material layer 620 and the first semiconductor chip 300.

[0060] The adhesive metal layer 610 may function as an adhesive layer for attaching the heat transfer material layer 620 to the barrier layer 500 and the first semiconductor chip 300. In addition, the adhesive metal layer 610 may prevent or reduce diffusion of metal included in the heat transfer material layer 620, which will be described later, into the first semiconductor chip 300.

[0061] The adhesion metal layer 610 may include, but is not limited to, at least one of titanium (Ti), titanium-tungsten (Ti—W), chromium (Cr), and aluminum (Al). The adhesion metal layer 610 according to some embodiments of the inventive concept may be titanium (Ti).

[0062] The heat transfer material layer 620 may be continuously formed along the adhesive metal layer 610 .

[0063] The thickness H3 of the heat transfer material layer 620 on the barrier layer 500 may be the same as the thickness H1 of the heat transfer material layer 620 on the first semiconductor chip 300 .

[0064] A thickness H1 of the heat transfer material layer 620 on the first semiconductor chip 300 and a thickness H3 of the heat transfer material layer 620 on the barrier layer 500 may be greater than a thickness H2 of the barrier layer 500 .

[0065] Heat generated from the first semiconductor chip 300 and the second semiconductor chip 400 may be released to the outside through the heat transfer material layer 620. Since the thickness of the heat transfer material layer 620 may be formed thicker, the heat transfer material layer 620 may effectively release heat generated from the first semiconductor chip 300 and the second semiconductor chip 400 to the outside.

[0066] In addition, in the semiconductor package according to some embodiments of the inventive concept, a warpage phenomenon caused by a mismatch in thermal expansion coefficients between different types of materials may be adjusted using the thickness and stiffness of the heat transfer material layer 620 .

[0067] The heat transfer material layer 620 may include a material having high thermal conductivity. For example, the heat transfer material layer 620 may be, but is not limited to, at least one metal material selected from silver (Ag), aluminum (Al), copper (Cu), platinum (Pt), zinc (Zn), nickel (Ni), and iron (Fe), or an alloy of metal materials. In some embodiments of the present inventive concept, the heat transfer material layer 620 may include copper (Cu).

[0068] Figure 2 1 is a diagram for explaining a semiconductor package according to some embodiments of the inventive concept. For the convenience of explanation, the difference from the semiconductor package according to some embodiments of the inventive concept described above will be described with emphasis.

[0069] Reference Figure 2 , a semiconductor package according to some embodiments of the inventive concept may include a substrate 100 , a first connection terminal 110 , a molding portion 200 , a second connection terminal 210 , a first semiconductor chip 300 , a second semiconductor chip 400 , a barrier layer 500 , and a heat transfer portion 600 .

[0070] A thickness H1 of the heat transfer material layer 620 on the first semiconductor chip 300 may be greater than a thickness H3 of the heat transfer material layer 620 on the barrier layer 500 .

[0071] The thickness H1 of the heat transfer material layer 620 on the first semiconductor chip 300 may be substantially equal to the sum of the thickness H2 of the barrier layer 500 and the thickness H3 of the heat transfer material layer 620 on the barrier layer 500 .

[0072] That is, a step may not be formed on the upper surface of the heat transfer material layer 620 .

[0073] Figure 3 1 is a diagram for explaining a semiconductor package according to some embodiments of the inventive concept. For the convenience of explanation, the difference from the semiconductor package according to some embodiments of the inventive concept described above will be described with emphasis.

[0074] Reference Figure 3 , a semiconductor package according to some embodiments of the inventive concept may include a substrate 100 , a first connection terminal 110 , a molding portion 200 , a second connection terminal 210 , a first semiconductor chip 300 , a second semiconductor chip 400 , a barrier layer 500 , and a heat transfer portion 600 .

[0075] The barrier layer 500 may be disposed on the second semiconductor chip 400 . The barrier layer 500 may include an opening 510 exposing the entire upper surface of the first semiconductor chip 300 .

[0076] The barrier layer 500 may cover the entire upper surface of the second semiconductor chip 400. The barrier layer 500 may not cover the entire upper surface of the first semiconductor chip 300.

[0077] Alternatively, for example, the barrier layer 500 may be formed up to a certain point between the upper surfaces of the first semiconductor chip 300 and the second semiconductor chip 400 .

[0078] Figure 4 1 is a diagram for explaining a semiconductor package according to some embodiments of the inventive concept. For the convenience of explanation, the difference from the semiconductor package according to some embodiments of the inventive concept described above will be described with emphasis.

[0079] Reference Figure 4 , a semiconductor package according to some embodiments of the inventive concept may include a substrate 100 , a first connection terminal 110 , a molding portion 200 , a second connection terminal 210 , a first semiconductor chip 300 , a second semiconductor chip 400 , a barrier layer 500 , and a heat transfer portion 600 .

[0080] The adhesion metal layer 610 may be continuously formed along the upper surface of the barrier layer 500 and the upper surface of the first semiconductor chip 300. An undercut may be formed at an end of the adhesion metal layer 610.

[0081] An undercut of the adhesion metal layer 610 may be formed in the process of removing the adhesion metal layer 610 from the mold part 200 .

[0082] A thickness H1 of the heat transfer material layer 620 on the first semiconductor chip 300 may be greater than a thickness H3 of the heat transfer material layer 620 on the barrier layer 500 .

[0083] An upper surface of the heat transfer material layer 620 on the barrier layer 500 may be arranged on the same plane as an upper surface of the heat transfer material layer 620 on the first semiconductor chip 300 .

[0084] No step may be formed on the upper surface of the heat transfer material layer 620 .

[0085] Figure 5 1 is a diagram for explaining a semiconductor package according to some embodiments of the inventive concept. For the convenience of explanation, the difference from the semiconductor package according to some embodiments of the inventive concept described above will be described with emphasis.

[0086] Reference Figure 5 The semiconductor package according to some embodiments of the inventive concept may further include a package substrate 700 .

[0087] The package substrate 700 may be a printed circuit board (PCB), a ceramic substrate, etc. The package substrate 700 may include a plurality of insulating films and internal wiring layers.

[0088] The package substrate 700 may include an upper surface 700 a and a lower surface 700 b facing each other.

[0089] A semiconductor package according to some embodiments of the inventive concept may be arranged on an upper surface 700 a of a package substrate 700 .

[0090] The third connection terminals 710 may be arranged on the lower surface 700b of the package substrate 700. For example, the third connection terminals 710 may be conductive balls or solder balls.

[0091] The semiconductor package may be electrically connected to an external device through the third connection terminals 710. The number of the third connection terminals 710 shown in the drawings is only for convenience of explanation and is not limited thereto.

[0092] The package substrate 700 and the substrate 100 may be electrically connected to each other through the first connection terminals 110. The underfill material 120 may fill a space between the first connection terminals 110 adjacent to each other. The underfill material 120 may protect the first connection terminals 110.

[0093] For example, the bottom filling material 120 may include epoxy resin, benzocyclobutene or polyimide. However, the embodiment is not limited thereto. For example, the bottom filling material 120 may also include a silicon dioxide filler. In another example, the bottom filling material 120 may include an adhesive and a soldering flux. The soldering flux may include an oxide film remover. In another example, the bottom filling material 120 may include a silicon dioxide filler or a soldering flux. In another example, the bottom filling material 120 may include a non-conductive paste.

[0094] Figure 6 1 is a diagram for explaining a semiconductor package according to some embodiments of the inventive concept. For the convenience of explanation, the difference from the semiconductor package according to some embodiments of the inventive concept described above will be described with emphasis.

[0095] Reference Figure 6 The semiconductor package according to some embodiments of the inventive concept may further include a heat slug 800 .

[0096] The heat slug 800 may extend from one side to the other side of the package substrate 700. The heat slug 800 may extend along an upper surface of the heat transfer portion 600.

[0097] The heat slug 800 may be in contact with the heat transfer portion 600 .

[0098] For example, the heat slug 800 may be in contact with the heat transfer material layer 620 .

[0099] Heat generated in the semiconductor package may be transferred to the heat-transfer portion 600. The heat transferred to the heat-transfer portion 600 may be easily dissipated to the outside through the heat slug 800.

[0100] Since the semiconductor package according to some embodiments of the inventive concept includes the heat transfer material layer 620 and the heat slug 800 , the thermal characteristics of the semiconductor package may be effectively improved.

[0101] The heat sink 800 may include a metal, which is a material having a higher thermal conductivity than air. For example, the heat sink 800 may include copper (Cu), iron (Fe), nickel (Ni), cobalt (Co), tungsten (W), chromium (Cr), silver (Ag), gold (Au), platinum (Pt), tin (Sn), aluminum (Al), magnesium (Mg), silicon (Si), zinc (Zn), or a combination thereof.

[0102] Figure 7 1 is a diagram for explaining a semiconductor package according to some embodiments of the inventive concept. For the convenience of explanation, the difference from the semiconductor package according to some embodiments of the inventive concept described above will be described with emphasis.

[0103] The heat sink 800 may be disposed on the heat transfer portion 600 .

[0104] The heat slug 800 may be in contact with the heat transfer portion 600. For example, the heat slug 800 may be in contact with the heat transfer material layer 620.

[0105] Heat generated in the semiconductor package may be transferred to the heat-transfer portion 600. The heat transferred to the heat-transfer portion 600 may be easily dissipated to the outside through the heat slug 800.

[0106] Will refer to Figures 8 to 16 Methods for manufacturing semiconductor packages according to some embodiments of the inventive concepts are described.

[0107] Figures 8 to 16 are intermediate state diagrams for explaining a method of manufacturing a semiconductor package according to some embodiments of the inventive concept.

[0108] Reference Figure 8 , the substrate 100 may include a first semiconductor chip 300 , a second semiconductor chip 400 , and a molding portion 200 . The substrate 100 may be attached to a carrier 160 .

[0109] A first groove 230 and a second groove 250 may be formed in the molding portion 200 .

[0110] The first semiconductor chip 300 may be mounted in the first trench 230. The second semiconductor chip 400 may be mounted in the second trench 250.

[0111] An upper surface of the molding portion 200 may have the same plane as upper surfaces of the first semiconductor chip 300 and the second semiconductor chip 400 .

[0112] The substrate 100 may be attached to the top of the carrier 160. The substrate 100 may be attached to the carrier 160 and may be easily moved. In addition, since the substrate 100 is attached to the carrier 160, damage and warping of the substrate 100 may be prevented or reduced.

[0113] For example, the carrier 160 may include silicon, metal, glass, plastic, ceramic, or the like.

[0114] Next, a barrier layer 500 may be formed on an upper surface of the first semiconductor chip 300 , an upper surface of the second semiconductor chip 400 , and an upper surface of the molding part 200 .

[0115] The barrier layer 500 may be formed by a deposition or coating process. The barrier layer 500 may include a photosensitive polymer having positive photosensitivity. Alternatively, the barrier layer 500 may include a photosensitive polymer having negative photosensitivity.

[0116] Reference Fig. 9 , at least a portion of the barrier layer 500 may be removed.

[0117] The barrier layer 500 may be removed to expose at least a portion of the first semiconductor chip 300 .

[0118] When the barrier layer 500 includes a photosensitive polymer having negative photosensitivity, the light shielding portion of the barrier layer 500 may be removed by a developer. Even after development, the exposed portion of the barrier layer 500 may remain. Therefore, the barrier layer 500 on the first semiconductor chip 300 may be shielded from light.

[0119] When the barrier layer 500 includes a photosensitive polymer having positive photosensitivity, the exposed portion of the barrier layer 500 may be removed by a developer. Even after development, the light shielding portion of the barrier layer 500 may remain. Therefore, the barrier layer 500 on the first semiconductor chip 300 may be exposed.

[0120] Reference Fig.10 , an adhesive metal layer 610 may be formed on the barrier layer 500 and the exposed first semiconductor chip 300 .

[0121] The adhesive metal layer 610 may cover the upper surface and the side surfaces of the barrier layer 500. The adhesive metal layer 610 may cover the upper surface of the exposed first semiconductor chip 300.

[0122] In the following description, the adhesion metal layer 610 may include titanium (Ti).

[0123] The adhesion metal layer 610 may be formed using a method such as, but not limited to, a physical vapor deposition (PVD) method, a sputtering method, and a chemical vapor deposition (CVD) method.

[0124] Next, a mask pattern 650 may be formed on the adhesion metal layer 610 .

[0125] The mask pattern 650 may be formed on an upper surface of the adhesive metal layer 610 between semiconductor packages adjacent to each other.

[0126] The mask pattern 650 may be formed through a photoresist application and patterning process.

[0127] Reference Fig.11 , a seed layer 615 may be formed on the adhesion metal layer 610 .

[0128] The seed layer 615 may be formed on the upper surface of the adhesion metal layer 610 exposed by the mask pattern 650 .

[0129] In the following description, the seed layer 615 may include copper (Cu).

[0130] The seed layer 615 formed on the upper surface of the adhesion metal layer 610 may serve as a seed layer of the heat transfer material layer 620 .

[0131] The seed layer 615 may be formed using, for example, but not limited to, a method such as a physical vapor deposition (PVD) method, a sputtering method, and a chemical vapor deposition (CVD) method.

[0132] Reference Fig.12 , a heat transfer material layer 620 may be formed.

[0133] The heat transfer material layer 620 may be formed on the seed layer exposed by the mask pattern 650. An uppermost surface of the heat transfer material layer 620 may be lower than an uppermost surface of the mask pattern 650.

[0134] The thickness of the heat transfer material layer 620 may be greater than the thickness of the barrier layer 500. The thickness of the heat transfer material layer 620 may be adjusted according to process conditions.

[0135] The heat transfer material layer 620 may be grown by, for example, an electroplating method.

[0136] Reference Fig.13 After forming the heat transfer material layer 620 , the mask pattern 650 may be removed. A portion of the adhesive metal layer 610 may be exposed by the removal of the mask pattern 650 .

[0137] Reference Fig.14 , the exposed adhesion metal layer 610 may be removed.

[0138] The exposed adhesive metal layer 610 may be a portion to be cut later. Therefore, the adhesive metal layer 610 may be removed to facilitate the cutting process.

[0139] For example, the adhesion metal layer 610 may be removed from the substrate 100 using an etching process.

[0140] For example, the adhesion metal layer 610 may be removed using a wet etching process. The wet etching process solution may selectively etch only the adhesion metal layer 610. The wet etching process solution may not damage the heat transfer material layer 620 or the barrier layer 500.

[0141] In the wet etching process, the wet etching process solution may penetrate into the end portion of the adhesion metal layer 610 .

[0142] For example, Figure 4As shown, at the end of the bonding metal layer 610, undercutting may occur.

[0143] Reference Fig.15 , tape 850 may be attached to the heat transfer material layer 620. Next, the top and bottom of the semiconductor package may be turned upside down.

[0144] After the semiconductor package is temporarily fixed by the tape 850, the carrier 160 may be removed from the substrate 100. Next, for each semiconductor package, a plurality of semiconductor packages may be cut by a cutting process. In the cutting process, a cutting wheel or a laser may be used.

[0145] The first connection terminals 110 may be attached to a lower surface of the substrate 100 to which no semiconductor package is attached.

[0146] Reference Fig.16 , the tape 850 on the heat transfer material layer 620 can be removed.

[0147] The semiconductor package from which the tape 850 is removed may be arranged on the upper surface 700 a of the package substrate 700 .

[0148] The package substrate 700 may be a printed circuit board (PCB). The package substrate 700 may be electrically connected to the substrate 100 through the first connection terminal 110. The package substrate 700 may be connected to an external device through the third connection terminal 710.

[0149] Next, refer to Figure 6 , a heat sink 800 may also be formed on the package substrate 700 .

[0150] For example, refer to Figure 7 , the heat sink 800 may also be formed on the heat transfer portion 620 .

[0151] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the preferred embodiments without substantially departing from the principles of the inventive concept. Therefore, the disclosed preferred embodiments of the inventive concept are used only in a general and descriptive sense and not for limiting purposes.

Claims

1. A semiconductor package, comprising: a first semiconductor chip and a second semiconductor chip disposed on a substrate; a barrier layer disposed on the first semiconductor chip and the second semiconductor chip and including an opening through which at least a portion of the first semiconductor chip is exposed; as well as a heat transfer portion disposed on the barrier layer, extending along an upper surface of the barrier layer and filling the opening, wherein the first semiconductor chip and the second semiconductor chip have the same thickness, and top surfaces of the first semiconductor chip and the second semiconductor chip are located at the same height from the substrate, and The width of the opening in a direction parallel to the top surface of the first semiconductor chip is equal to or smaller than the width of the top surface of the first semiconductor chip.

2. The semiconductor package according to claim 1, wherein: The heat transfer portion has a thickness greater than a thickness of the barrier layer.

3. The semiconductor package according to claim 1, wherein: A thickness of the heat transfer portion on the first semiconductor chip is substantially equal to a thickness of the heat transfer portion on the barrier layer.

4. The semiconductor package according to claim 1, wherein: A thickness of the heat transfer portion on the first semiconductor chip is greater than a thickness of the heat transfer portion on the barrier layer.

5. The semiconductor package according to claim 1, wherein: The barrier layer includes a photosensitive polymer.

6. The semiconductor package according to claim 1, wherein: The heat transfer portion includes an adhesive metal layer and a heat transfer material layer disposed on an upper surface of the adhesive metal layer, and an undercut region is formed at an end of the adhesive metal layer.

7. The semiconductor package according to claim 6, wherein: The layer of heat transfer material includes copper.

8. The semiconductor package according to claim 1, wherein: The first semiconductor chip and the second semiconductor chip are electrically connected to each other through the substrate.

9. The semiconductor package according to claim 1, wherein: The first semiconductor chip is a logic chip, and the second semiconductor chip is a memory chip.

10. A semiconductor package, comprising: a first semiconductor chip arranged on a substrate; a second semiconductor chip disposed on the substrate and spaced apart from the first semiconductor chip; as well as a heat transfer portion disposed on the first semiconductor chip and the second semiconductor chip, in direct contact with the first semiconductor chip and not in contact with the second semiconductor chip, The first semiconductor chip and the second semiconductor chip have the same thickness, and top surfaces of the first semiconductor chip and the second semiconductor chip are located at the same height from the substrate.

11. The semiconductor package according to claim 10, wherein: A thickness of the heat-transfer portion on the first semiconductor chip is substantially equal to a thickness of the heat-transfer portion on the second semiconductor chip.

12. The semiconductor package according to claim 10, wherein: A thickness of the heat transfer portion on the first semiconductor chip is greater than a thickness of the heat transfer portion on the second semiconductor chip.

13. The semiconductor package according to claim 10, further comprising: A barrier layer is provided between the second semiconductor chip and the heat transfer portion.

14. The semiconductor package according to claim 13, wherein: The barrier layer includes a photosensitive polymer.

15. The semiconductor package according to claim 13, wherein: The heat transfer portion has a thickness greater than a thickness of the barrier layer.

16. The semiconductor package according to claim 10, wherein: An undercut region is formed at an end of the heat transfer portion.

17. The semiconductor package according to claim 10, wherein: The first semiconductor chip and the second semiconductor chip are electrically connected to each other through the substrate.

18. A semiconductor package, comprising: substrate; a molding portion disposed on the substrate and including a first groove and a second groove, an upper surface of the substrate being exposed through the first groove and the second groove; a first semiconductor chip disposed in the first trench and electrically connected to the substrate; a second semiconductor chip disposed in the second trench and electrically connected to the substrate; a barrier layer disposed on an upper surface of the molding portion, covering the second semiconductor chip and including an opening through which at least a portion of the first semiconductor chip is exposed; as well as a heat transfer portion disposed on the barrier layer and in direct contact with the first semiconductor chip exposed through the opening, wherein the first semiconductor chip and the second semiconductor chip have the same thickness, and top surfaces of the first semiconductor chip and the second semiconductor chip are located at the same height from the substrate, and The first trench and the second trench each continuously extend from the upper surface of the substrate to the barrier layer.

19. The semiconductor package according to claim 18, further comprising: A heat sink surrounds the outer side of the heat transfer portion and the outer side of the molded portion.

20. The semiconductor package according to claim 18, wherein The barrier layer includes a photosensitive polymer.

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