Test structure and method for making the same

Abstract

The present disclosure relates to a test structure and a method for making the same, wherein the test structure comprises: a substrate, a test circuit, a crack stop groove and a sealing layer, wherein the substrate comprises a cutting area; the test circuit is formed in the cutting area; the crack stop groove is formed in the cutting area, and the crack stop groove is arranged on the side of the test circuit; the sealing layer is formed on the surface of the substrate, covering the crack stop groove so that a gas gap is formed in the crack stop groove. The crack stop groove solves the problem that when a wafer is cut along a cutting path, the cutting path cracks due to the influence of the metal layer in the test circuit, and the cutting stress is transferred to the grain area, which may damage the grain area, and is conducive to improving the product yield and stability.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a test structure and a manufacturing method thereof. Background Art

[0002] With the development and progress of technology, the application of integrated circuits is becoming more and more extensive. Wafers are one of the main materials of integrated circuits. During the production process of integrated circuits, wafers need to be cut to form multiple grains.

[0003] In order to facilitate cutting, a cutting area is usually set in the wafer for cutting. A detection circuit is set in the cutting area to test the performance of the components in the grain. There are a large number of metal wires in the test circuit, and the metal wires are attached to the surface of the cutting area. During the wafer cutting process, when the cutter contacts the metal wires, it is easy to pull the wires and cause cracks in the cutting area, which may damage the grain area, resulting in low product yield and reduced product stability.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a test structure and a method for manufacturing the same, thereby overcoming at least to a certain extent the problem of cracking of the cutting path caused by the metal wire of the test circuit during wafer cutting, thereby damaging the grain area due to the limitations and defects of the relevant technology.

[0006] According to a first aspect of the present disclosure, a test structure is provided, the test structure comprising:

[0007] a substrate, the substrate comprising a cutting area;

[0008] A test circuit is formed in the cutting area;

[0009] A crack stopping groove is formed in the cutting area, and the crack stopping groove is arranged on the side of the test circuit;

[0010] A sealing layer is formed on the surface of the substrate and covers the crack stopping groove to form a gas gap in the crack stopping groove.

[0011] According to an embodiment of the present disclosure, the crack stopping groove at least partially surrounds the test circuit. According to an embodiment of the present disclosure, the crack stopping groove is arranged at least on two sides of the test circuit along the cutting direction of the cutting area.

[0012] According to an embodiment of the present disclosure, the depth of the crack stopping groove is greater than that of the test circuit, and the aspect ratio of the crack stopping groove is greater than 3:1.

[0013] According to an embodiment of the present disclosure, the test structure further includes a test pad, and the test pad is located in the cutting area and connected to the test circuit.

[0014] According to one embodiment of the present disclosure, the sealing layer also includes a first opening groove, the first opening groove is located in the projection area of ​​the test circuit on the sealing layer, the test pad is partially covered by the sealing layer, and the test pad is partially exposed to the first opening groove.

[0015] According to one embodiment of the present disclosure, the wafer further includes:

[0016] A passivation layer is formed on a side of the sealing layer away from the substrate, and a second opening groove is provided on the passivation layer, and the second opening groove is located in a projection area of ​​the first opening groove on the passivation layer;

[0017] A protection layer is formed on a side of the passivation layer away from the substrate, and a third opening groove is arranged on the protection layer. The third opening groove is located in a projection area of ​​the first opening groove on the protection layer.

[0018] According to a second aspect of the present disclosure, a method for manufacturing a test structure is provided, the method comprising:

[0019] Providing a substrate, wherein a cutting area for cutting is provided on the substrate, and a test circuit is provided in the cutting area;

[0020] forming a crack stopping groove on a side of the test circuit on the cutting area;

[0021] A sealing layer is formed on the first surface of the substrate, the sealing layer covers the crack stopping groove, and the first surface of the substrate is a surface on which the test circuit is arranged.

[0022] According to one embodiment of the present disclosure, the manufacturing method further includes:

[0023] forming a passivation layer on a side of the sealing layer away from the substrate;

[0024] forming a protective layer on a side of the passivation layer away from the substrate;

[0025] By etching, a third opening groove is formed in the protective layer, a second opening groove is formed in the passivation layer, and a first opening groove is formed in the sealing layer. The third opening groove is located in the projection area of ​​the test circuit on the protective layer, the second opening groove is located in the projection area of ​​the test circuit on the passivation layer, and the first opening groove is located in the projection area of ​​the test circuit on the sealing layer.

[0026] According to an embodiment of the present disclosure, the wafer includes a test pad, the test pad is partially covered by the sealing layer, and the test pad is partially exposed to the first opening groove.

[0027] The test structure provided by the embodiment of the present disclosure includes a substrate, a cutting area is arranged on the substrate, a test circuit is arranged in the cutting area, and an air gap crack stop groove is arranged on the side of the test circuit. The crack stop groove solves the problem that when the wafer is cut along the cutting path, the cutting path is cracked due to the influence of the metal layer in the test circuit, and the cutting stress is transferred to the grain area, which may damage the grain area. This is beneficial to improving product yield and stability.

[0028] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0030] Figure 1 A schematic diagram of a test structure provided for an exemplary embodiment of the present disclosure.

[0031] Figure 2-4 A schematic diagram of a test structure manufacturing process provided by an exemplary embodiment of the present disclosure.

[0032] Figure 5 A schematic top view of a first crack arrest groove distribution provided for an exemplary embodiment of the present disclosure.

[0033] Figure 6 A schematic top view of a second crack arrest groove distribution provided for an exemplary embodiment of the present disclosure.

[0034] Figure 7 A schematic top view of a third crack arrest groove distribution provided for an exemplary embodiment of the present disclosure.

[0035] Figure 8 A schematic top view of a fourth crack arrest groove distribution provided for an exemplary embodiment of the present disclosure.

[0036] Fig. 9 A top view schematically showing a fifth crack arrest groove distribution provided for an exemplary embodiment of the present disclosure.

[0037] Fig.10 A schematic diagram of another test structure provided for an exemplary embodiment of the present disclosure.

[0038] Fig.11 An exemplary embodiment of the present disclosure provides a flowchart of a method for manufacturing a test structure.

[0039] Fig.12 An exemplary embodiment of the present disclosure provides a flowchart of another method for manufacturing a test structure.

[0040] In the figure:

[0041] 100, substrate; 110, base plate; 120, dielectric layer; 200, test circuit; 210, detection pad; 300, crack stop groove; 400, sealing layer; 500, passivation layer; 600, protective layer; 700, photoresist. DETAILED DESCRIPTION

[0042] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0043] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0044] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0045] In this example implementation, a test structure is first provided, such as Figure 1As shown, the test structure includes: a substrate 100, a test circuit 200, a crack stopping groove 300 and a sealing layer 400; a cutting area for cutting is provided on the substrate 100; the test circuit 200 is arranged in the cutting area; the crack stopping groove 300 is formed in the cutting area, and the crack stopping groove 300 is arranged on the side of the test circuit 200; the sealing layer 400 is formed on the first surface of the substrate 100, covering the crack stopping groove 300 so that a gas gap is formed in the crack stopping groove 300, and the first surface of the substrate 100 is the surface of the substrate 100 on which the test circuit 200 is arranged.

[0046] The test structure provided by the embodiment of the present disclosure includes a substrate 100, a cutting area is arranged on the substrate 100, a test circuit 200 is arranged in the cutting area, and an air gap crack stop groove 300 is arranged on the side of the test circuit 200. The crack stop groove 300 solves the problem that when the wafer is cut along the cutting path, the cutting path is cracked due to the influence of the pulling of the wire in the metal layer in the test circuit 200, and the cutting stress is transferred to the grain area, which may damage the grain area. This is beneficial to improving product yield and stability.

[0047] The substrate 100 described in the embodiment of the present disclosure may include a substrate 110 and a dielectric layer 120, the dielectric layer 120 is disposed on the surface of the substrate 110, the test circuit 200 may be located in the dielectric layer 120, the sealing layer 400 is located on the side of the dielectric layer 120 away from the substrate 110, the test circuit 200 may be a wafer acceptance test (WAT) circuit or other circuits, and the embodiment of the present disclosure does not specifically limit this. The substrate 100 may be divided into a cutting area and a grain area, and the cutting blade acts on the cutting area during cutting, and the grain area is retained.

[0048] Among them, the substrate 110 can be a silicon substrate 110 such as a silicon epitaxial wafer, silicon on an insulating layer, or a substrate 110 of other semiconductor materials such as GaN, and the substrate 110 can be an intrinsic semiconductor substrate 110, or an N-type doped or P-type doped semiconductor substrate 110, which is not limited in the embodiments of the present disclosure. The material of the dielectric layer 120 can be one or more of silicon oxide, silicon nitride or silicon oxynitride. In a specific implementation, the dielectric layer 120 can be formed by chemical vapor deposition, atomic layer deposition and other methods. It can be understood that the dielectric layer 120 can be a layer of insulating material, or it can be formed by stacking multiple layers of the same or different insulating materials.

[0049] For example, the test circuit 200 is a WAT ​​circuit, and the WAT circuit may be one or more metal layers. The multiple metal layers may realize electrical connection between two metal layers through conductive vias. The material of the metal layer and the material of the conductive column may be the same, so that they are easy to form in a unified process. The material of the metal layer may be one of metals such as copper, aluminum, tungsten, gold, etc., or an alloy material of the above metal materials.

[0050] The crack stop groove 300 is provided on the side of the metal layer of the test circuit 200. The crack stop groove 300 may at least partially surround the test circuit 200, or the crack stop groove 300 may be arranged at least along the cutting direction of the cutting area on both sides of the test circuit 200. The crack stop groove 300 is covered with a sealing layer 400 to form a gas gap, which may be filled with air or nitrogen, inert gas, etc. Figure 5 As shown, the distance L between the crack stop groove 300 and the metal layer is greater than 5 microns. The distance between the crack stop groove 300 and the metal layer refers to the distance between the side wall of the crack stop groove 300 close to the metal layer and the edge of the metal layer closest to the side wall.

[0051] like Figure 1 As shown, the depth of the crack stop groove 300 is greater than that of the test circuit 200, and the distance S between the bottom of the crack stop groove 300 and the metal layer is greater than 1 micron. The bottom of the crack stop groove 300 refers to the end of the crack stop groove 300 extending into the substrate 100, and the distance between the bottom of the crack stop groove 300 and the metal layer refers to the distance from the bottom of the crack stop groove 300 to the bottom of the metal layer, that is, the crack stop groove 300 is more than 1 micron deeper than the metal layer. Figure 5 As shown, the width of the crack stop groove 300 is 0.5 mm to 5 mm, that is, the distance D between the side wall of the crack stop groove 300 close to the test circuit 200 and the side wall away from the test circuit 200 is 0.5 μm to 5 μm, and the aspect ratio of the crack stop groove is greater than 3: 1. For example, the width of the crack stop groove 300 can be 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm or 5 μm.

[0052] In order to prevent the stress generated by cracking in the cutting area from spreading to the non-cutting area, the crack-stop groove 300 can surround the test circuit 200. By surrounding the crack-stop groove 300, the stress is prevented from spreading. In the first feasible implementation provided by the embodiment of the present disclosure, Figure 5 and Figure 6 As shown, the crack stop groove 300 can be a continuous ring surrounding the test circuit 200, for example, the crack stop groove 300 can be a rectangular ring, a circular ring, an elliptical ring or a special-shaped ring structure; in a second feasible implementation manner provided by the embodiment of the present disclosure, as Figure 7As shown, the crack stop groove 300 can be a discrete annular structure, and a plurality of discrete crack stop grooves 300 surround the test circuit 200; when the plurality of crack stop grooves 300 discretely surround the test circuit 200, the plurality of crack stop grooves can be equidistantly distributed along a circular ring or a rectangular ring; or the relative crack stop grooves 300 can be staggered, for example, Fig. 9 As shown, the relative crack stop grooves 300 in the rectangular ring are staggered, and the discrete staggered crack stop grooves can further disperse the cutting stress and avoid damaging the grain area during cutting. In the third feasible implementation provided by the embodiment of the present disclosure, as Figure 8 As shown, a multi-layer crack stopping groove 300 may be provided on the side of the test circuit 200 .

[0053] Since the test circuit 200 needs to be connected to an external detection device or a detection circuit during testing, the detection circuit may include at least one detection pad 210, which is located on the upper surface of the test circuit 200. A first opening groove is provided on the sealing layer 400, and the first opening groove is located in the projection area of ​​the test circuit 200 on the sealing layer 400. The test pad is partially covered by the sealing layer 400, and the test pad 210 is partially exposed to the first opening groove.

[0054] The sealing layer 400 covers part of the test pad 210, and the rest of the test pad 210 is exposed to the first opening groove. On the one hand, it is convenient for the test pad 210 to connect to the external test circuit, and on the other hand, it prevents the test pad 210 from peeling off during the cutting process and causing damage to the grain area of ​​the wafer.

[0055] For example, three quarters of the area of ​​the test pad 210 is covered by the sealing layer 400, and one quarter of the area of ​​the test pad 210 is exposed to the first opening groove, thereby enhancing the protective buffering effect of the sealing layer 400 on the test pad 210 during the cutting process, preventing damage to the test pad, and protecting the test pad from corrosion damage.

[0056] Furthermore, the test structure may further include a passivation layer 500 and a protective layer 600, wherein the passivation layer 500 is formed on a side of the sealing layer 400 away from the substrate 100, and a second opening groove is provided on the passivation layer 500, the second opening groove is located in a projection area of ​​the test circuit 200 on the passivation layer 500, and the second opening groove is used to expose the test circuit 200. The protective layer 600 is formed on a side of the passivation layer 500 away from the substrate 100, and a third opening groove is provided on the protective layer 600, the third opening groove is located in a projection area of ​​the test circuit 200 on the protective layer 600, and the third opening groove is used to expose the test circuit 200.

[0057] The material of the sealing layer 400 may be the same as that of the dielectric layer 120, such as one or more of silicon oxide, silicon nitride or silicon oxynitride. Of course, the material of the sealing layer 400 may be different from that of the dielectric layer 120, and the embodiments of the present disclosure are not limited thereto. The material of the passivation layer 500 may be silicon nitride or the like. The method of forming the protective layer 600 may be chemical vapor deposition, atomic layer deposition or the like. The material of the protective layer 600 may be one or more combinations of materials such as polyimide and tetraethyl orthosilicate (TEOS).

[0058] In a feasible embodiment of the present disclosure, if Figure 1 As shown, the cross-sections of the first opening groove, the second opening groove and the third opening groove may be rectangular structures, and the projections of the first opening groove, the second opening groove and the third opening groove on the substrate overlap. In another feasible embodiment of the present disclosure, the cross-sections of the first opening groove, the second opening groove and the third opening groove may be trapezoidal structures, and the cross-sectional area of ​​the first opening groove is smaller than the cross-sectional area of ​​the second opening groove, and the cross-sectional area of ​​the second opening groove is smaller than the cross-sectional area of ​​the third opening groove. For example, Fig.10 As shown, the waistlines of the cross-sectional trapezoids of the first opening groove, the second opening groove, and the third opening groove are collinear. Of course, in practical applications, the waistlines of the cross-sectional trapezoids of the first opening groove, the second opening groove, and the third opening groove may not be collinear, and the embodiments of the present disclosure are not limited thereto. The trapezoidal cross-section makes the opening gradually larger on the side away from the substrate, which not only realizes the partial coverage of the detection pad by the sealing layer, but also ensures that the area above the opening is large enough for easy testing.

[0059] It should be noted that the test structure described in the embodiment of the present disclosure may be a wafer test structure, which is used to detect the electrical properties of the grains, etc. After the detection is completed, the wafer is cut along the cutting area to obtain the grains, and the faulty grains can be removed.

[0060] The wafer provided by the embodiment of the present disclosure includes a substrate 100, a cutting area is arranged on the substrate 100, a test circuit 200 is arranged in the cutting area, and an air gap crack stop groove 300 is arranged on the side of the test circuit 200. The crack stop groove 300 solves the problem that when the wafer is cut along the cutting path, the cutting path is cracked due to the influence of the wires in the test circuit 200, and the cutting stress is transferred to the grain area, which may damage the integrated circuit. This is beneficial to improving the product yield and stability.

[0061] This exemplary embodiment also provides a method for manufacturing a test structure, such as Fig.11 As shown, the manufacturing method comprises:

[0062] Step S910, providing a substrate 100, wherein the substrate 100 is provided with a cutting area for cutting, and the cutting area is provided with a test circuit 200;

[0063] Step S920, forming a crack stopping groove 300 on the side of the test circuit 200 on the cutting area;

[0064] Step S930 , forming a sealing layer 400 on the first surface of the substrate 100 , wherein the sealing layer 400 covers the crack stopping groove 300 . The first surface of the substrate 100 is a surface on which the test circuit 200 is disposed.

[0065] The test structure manufacturing method provided in the embodiment of the present disclosure solves the problem that when cutting the wafer along the cutting path, the cutting path is cracked due to the influence of the wires in the test circuit 200, and the cutting stress is transferred to the grain area, which may damage the integrated circuit, by forming a crack-stop groove 300 on the side of the test circuit 200. This is beneficial to improving product yield and stability.

[0066] In step S910 , a substrate 100 may be provided. The substrate 100 is provided with a cutting area for cutting, and the cutting area is provided with a test circuit 200 .

[0067] Among them, the substrate 100 may include a base plate 110 and a dielectric layer 120, the dielectric layer 120 is arranged on the surface of the base plate 110, the test circuit 200 may be located in the dielectric layer 120, and the sealing layer 400 is located on the side of the dielectric layer 120 away from the base plate 110. The test circuit 200 may be a wafer acceptance test (WAT) circuit or other circuits, and the embodiments of the present disclosure do not make specific limitations on this.

[0068] The substrate 110 may be a silicon substrate 110 such as a silicon epitaxial wafer, silicon on an insulating layer, or a substrate 110 of other semiconductor materials such as GaN, and the substrate 110 may be an intrinsic semiconductor substrate 110, or an N-type doped or P-type doped semiconductor substrate 110, which is not limited in the embodiments of the present disclosure. The material of the dielectric layer 120 may be one or more of silicon oxide, silicon nitride, or silicon oxynitride. In a specific implementation, the dielectric layer 120 may be formed by chemical vapor deposition, atomic layer deposition, or the like. It is understandable that the dielectric layer 120 may be a layer of insulating material, or may be a plurality of layers of the same or different insulating materials stacked together.

[0069] For example, the test circuit 200 is a WAT ​​circuit, and the WAT circuit may be one or more metal layers. The multiple metal layers may realize electrical connection between two metal layers through conductive vias. The material of the metal layer and the material of the conductive column may be the same, so that they are easy to form in a unified process. The material of the metal layer may be one of metals such as copper, aluminum, tungsten, gold, etc., or an alloy material of the above metal materials.

[0070] In step S920 , a crack stopping groove 300 may be formed on the side of the test circuit 200 on the cutting area.

[0071] Forming the crack stopping groove 300 on the side of the test circuit 200 on the cutting area may include the following steps:

[0072] like Figure 2 As shown, a photoresist layer 700 is formed on the first surface of the substrate 100;

[0073] Expose through a corresponding mask plate to transfer the pattern of the mask plate to the photoresist layer;

[0074] By developing, the photoresist layer exposes the area where the crack stop groove 300 is to be opened, and the crack stop groove 300 is located at the side of the test circuit 200;

[0075] The crack stop groove 300 is formed by etching, wherein the etching can be dry etching, wet etching or plasma etching;

[0076] like Figure 3 As shown, the photoresist layer is removed to obtain the crack stopping groove 300 .

[0077] In step S930 , a sealing layer 400 may be formed on the first surface of the substrate 100 , where the sealing layer 400 covers the crack stopping groove 300 . The first surface of the substrate 100 is a surface on which the test circuit 200 is disposed.

[0078] The sealing layer 400 may be formed by chemical vapor deposition, atomic layer deposition, etc. The material of the sealing layer 400 may be the same as the material of the dielectric layer 120, such as one or more of silicon oxide, silicon nitride, or silicon oxynitride. Of course, the material of the sealing layer 400 may also be different from the material of the dielectric layer 120, and the embodiments of the present disclosure are not limited thereto.

[0079] Further, such as Fig.12 As shown, before step S920, the method for manufacturing the grain may further include:

[0080] Step S940: forming the test circuit 200 on the cutting area.

[0081] After step S930, Figure 4 As shown, the method for manufacturing the grain may further include:

[0082] In step S950 , a passivation layer 500 is formed on a side of the sealing layer 400 away from the substrate 100 .

[0083] In step S960 , a protection layer 600 is formed on a side of the passivation layer 500 away from the substrate 100 .

[0084] Step S970, forming a third opening groove in the protective layer 600 by etching, forming a second opening groove in the passivation layer 500, and forming a first opening groove in the sealing layer 400, the third opening groove is located in the projection area of ​​the test circuit 200 on the protective layer 600, the second opening groove is located in the projection area of ​​the test circuit 200 on the passivation layer 500, and the first opening groove is located in the projection area of ​​the test circuit 200 on the sealing layer 400.

[0085] The test circuit 200 includes a detection pad 210, wherein the test pad 210 is partially covered by the sealing layer 400, and the test pad 210 is partially exposed to the first opening groove. The sealing layer 400 covers part of the test pad, and the rest of the test pad 210 is exposed to the first opening groove. On the one hand, it is convenient for the test pad 210 to connect to the external test circuit, and on the other hand, it prevents the test pad 210 from peeling off during the cutting process, thereby damaging the grain area of ​​the wafer.

[0086] In step S940, forming the test circuit 200 on the cutting area may include the following steps:

[0087] A photoresist layer is formed on the dielectric layer 120 of the substrate 100 by a spray coating method.

[0088] Exposure and development are performed through a corresponding mask plate to transfer the pattern of the mask plate to the dielectric layer 120 .

[0089] By etching, the opening portion not covered and protected by the photoresist is removed to form a groove. The etching method can be dry etching, wet etching or plasma etching.

[0090] Conductive material is deposited in the grooves. The deposition method can be physical vapor deposition or electroplating.

[0091] The surface is smoothed by a polishing process to form a metal layer. The polishing process may be chemical mechanical polishing.

[0092] A dielectric layer material is coated on the dielectric layer 120 .

[0093] By repeating the above steps, multiple metal layers can be formed.

[0094] In step S950 , the passivation layer 500 may be formed by chemical vapor deposition, atomic layer deposition or the like, and the material of the passivation layer 500 may be silicon nitride or the like.

[0095] In step S960, the protective layer 600 may be formed by chemical vapor deposition, atomic layer deposition, etc. The material of the protective layer 600 may be one or more combinations of materials such as polyimide and tetraethyl orthosilicate (TEOS).

[0096] The test structure manufacturing method provided in the embodiment of the present disclosure solves the problem that when cutting the wafer along the cutting path, the cutting path is cracked due to the influence of the wires in the test circuit 200, and the cutting stress is transferred to the grain area, which may damage the integrated circuit, by forming a crack-stop groove 300 on the side of the test circuit 200. This is beneficial to improving product yield and stability.

[0097] This exemplary embodiment also provides a semiconductor device, which includes the above-mentioned test structure.

[0098] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A test structure, It is characterized in that The test structure includes: A substrate, the substrate comprising a cutting area and a die area; A test circuit is formed in the cutting area; A crack stopping groove is formed in the cutting area, and the crack stopping groove is arranged between the test circuit and the die area; A sealing layer is formed on the surface of the substrate and covers the crack-stopping groove so that a gas gap is formed in the crack-stopping groove. The sealing layer further includes a first opening groove, and the first opening groove is located in a projection area of ​​the test circuit on the sealing layer. The test structure also includes: A passivation layer is formed on a side of the sealing layer away from the substrate, and a second opening groove is provided on the passivation layer, the second opening groove is located in a projection area of ​​the first opening groove on the passivation layer, and the second opening groove exposes the test circuit; A protection layer is formed on a side of the passivation layer away from the substrate, and a third opening groove is arranged on the protection layer. The third opening groove is located in a projection area of ​​the first opening groove on the protection layer.

2. The test structure according to claim 1, It is characterized in that The crack stop groove at least partially surrounds the test circuit.

3. The test structure according to claim 1, It is characterized in that The crack stopping grooves are arranged at least along a cutting direction of the cutting area on two sides of the test circuit.

4. The test structure according to claim 1, It is characterized in that The crack stopping groove has a depth greater than that of the test circuit, and a depth-to-width ratio of the crack stopping groove is greater than 3:

1.

5. The test structure according to claim 1, It is characterized in that The test structure further includes a test pad, which is located in the cutting area and connected to the test circuit.

6. The test structure as claimed in claim 5, It is characterized in that The test pad is partially covered by the sealing layer, and the test pad is partially exposed to the first opening groove.

7. The test structure according to claim 1, It is characterized in that The distance between the crack stopping groove and the test circuit is greater than 5 micrometers.

8. A method for making a test structure, It is characterized in that The production method comprises: Providing a substrate, wherein a crystal grain area and a cutting area for cutting are arranged on the substrate, and a test circuit is arranged in the cutting area; forming a crack stopping groove in the cutting area between the test circuit and the die area; forming a sealing layer on a first surface of the substrate, the sealing layer covering the crack stopping groove so as to form a gas gap in the crack stopping groove, the first surface of the substrate being a surface on which the test circuit is arranged; The production method further comprises: forming a passivation layer on a side of the sealing layer away from the substrate; forming a protective layer on a side of the passivation layer away from the substrate; By etching, a third opening groove is formed in the protective layer, a second opening groove is formed in the passivation layer, the third opening groove and the second opening groove expose the test circuit, and a first opening groove is formed in the sealing layer, the third opening groove is located in the projection area of ​​the test circuit on the protective layer, the second opening groove is located in the projection area of ​​the test circuit on the passivation layer, and the first opening groove is located in the projection area of ​​the test circuit on the sealing layer.

9. The method for manufacturing the test structure according to claim 8, It is characterized in that The test structure includes a test pad, a portion of the test pad is covered by the sealing layer, and a portion of the test pad is exposed to the first opening groove.

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