Vertical Hall sensor structure

Abstract

A vertical Hall sensor structure comprises a substrate layer, a semiconductor region of a first conductivity type, at least one first, second and third semiconductor connection regions of the first conductivity type extending from the upper side of the semiconductor region into the semiconductor region, respectively, and at least one semiconductor connection region of the second conductivity type, wherein the semiconductor connection regions of the first conductivity type are spaced apart from each other, and a metal connection layer is arranged on each semiconductor connection region of the first conductivity type, the first semiconductor connection region of the second conductivity type is adjacent to the first semiconductor connection region of the first conductivity type, or has a spacing of up to 0.2 μm with the first semiconductor connection region of the first conductivity type, and the first semiconductor connection region of the first conductivity type is conductively connected to the first semiconductor connection region of the second conductivity type.

Description

Technical Field

[0001] The invention relates to a vertical Hall sensor structure. Background Art

[0002] DE 10 2011 107 767 A1 discloses a Hall sensor structure which consists of a plurality of Hall sensor elements connected in series. Each Hall sensor element comprises three n-semiconductor contact regions in an n-slot region, wherein a (for example highly doped p-type) semiconductor contact region is arranged between the n-semiconductor contact regions. + Diffusion composed of isolated areas. Summary of the invention

[0003] Against this background, the object of the present invention is to specify a device which expands the prior art.

[0004] This object is achieved by a Hall sensor structure having the features according to the invention. Advantageous embodiments of the invention are preferred embodiments.

[0005] According to the subject matter of the invention, a vertical Hall sensor structure is provided, which has a substrate layer with a semiconductor region formed on or in the substrate layer.

[0006] The semiconductor region has a first conductivity type and is electrically isolated from the substrate layer by means of a dielectric layer or by means of a p / n junction.

[0007] Furthermore, at least one first, second and third semiconductor connection region of the first conductivity type and at least one first semiconductor connection region of the second conductivity type are provided, which each extend from an upper side of the semiconductor region into the semiconductor region.

[0008] The semiconductor contact regions of the first conductivity type are respectively spaced apart from one another.

[0009] A metal connection layer is arranged on each semiconductor connection region of the first conductivity type.

[0010] In addition, at least one first semiconductor connection region (HK2) of the second conductivity type is provided extending into the semiconductor region, wherein the first semiconductor connection region of the second conductivity type is adjacent to the first semiconductor connection region of the first conductivity type or has a spacing of up to 0.2 μm to the first semiconductor connection region (HK1) of the first conductivity type.

[0011] The first semiconductor contact region of the first conductivity type is electrically conductively connected to the first semiconductor contact region of the second conductivity type.

[0012] It can be understood that the first conductivity type is n-type and the second conductivity type is p-type, or the first conductivity type is p-type and the second conductivity type is n-type.

[0013] It should be noted that the term “conductively connected” in this context means an electrical short circuit between a semiconductor contact region of a first conductivity type and a semiconductor contact region of a second conductivity type.

[0014] Studies have shown that, in particular when the sensor is switched on with a low operating current (ie, a current in the range of 10 μA to 100 mA), the generation of minority carriers can be avoided. Temporary exhaustion ( Verarmung).

[0015] Particularly when minority charge carriers have a high effective mass (eg holes in an n-slot) and thus a lower mobility than majority charge carriers, the switch-on time can be significantly reduced by the adjacent arrangement of semiconductor switch regions having different conductivity types.

[0016] Thus, one advantage is that, for example, during the switching on of the sensor, minority charge carriers are provided by at least one semiconductor switching region of the second conductivity type at low currents, thereby improving the transient behavior of the Hall sensor. Immediately after switching on, before the measured value reaches a stable, loadable value after a few seconds, a drift of the measured value is observed in conventional Hall sensors due to the lack of minority charge carriers. This drift is suppressed or avoided by the design according to the invention.

[0017] In other words, the stability of the measured values ​​immediately after switching on is ensured by means of the configuration according to the invention of the semiconductor switching region of the second conductivity type.

[0018] Another advantage is that threshold voltage injection can be avoided in the semiconductor region and that even at a voltage of less than 8·10 15 N / cm 3 Even with low doping of the semiconductor region in the range of , the switching behavior can be improved, thereby achieving a high sensitivity of the Hall sensor structure. That is, a highly sensitive Hall sensor with improved switching behavior is provided.

[0019] According to a first embodiment, the first semiconductor connection region of the first conductivity type has a first region and a second region, wherein the first semiconductor connection region of the second conductivity type is arranged between the first region and the second region, the first semiconductor connection region of the second conductivity type is adjacent to the first region and the second region, or has a spacing of up to 0.2 μm. The semiconductor connection region of the second conductivity type approximately divides the first semiconductor connection region of the first conductivity type into two equal parts and is short-circuited with the first semiconductor connection region of the first conductivity type.

[0020] In another embodiment, the Hall sensor structure comprises a second semiconductor contact region of the second conductivity type, wherein the first semiconductor contact region of the second conductivity type adjoins a first side surface of the first semiconductor contact region of the first conductivity type or has a spacing of up to 0.2 μm to the first side surface, and the second semiconductor contact region of the second conductivity type adjoins a second side surface of the first semiconductor contact region of the first conductivity type that is opposite to the first side surface or has a spacing of up to 0.2 μm to the second side surface. Thus, the two semiconductor contact regions of the second conductivity type approximately surround the first semiconductor contact region of the first conductivity type.

[0021] According to a further embodiment, the semiconductor contact region of the first conductivity type and the semiconductor contact region of the second conductivity type each have a rectangular top side.

[0022] According to one embodiment, semiconductor contact regions of the first conductivity type are arranged along a straight line, wherein the first semiconductor contact region of the first conductivity type is arranged centrally along the straight line between other semiconductor contact regions of the first conductivity type. The central arrangement of the first semiconductor contact region of the first conductivity type and the semiconductor contact region of the second conductivity type adjacent thereto as closely as possible ensure a rapid and simultaneously symmetrical injection of minority charge carriers.

[0023] In one configuration, the Hall sensor structure has at least one additional semiconductor contact region of the second conductivity type, wherein the additional semiconductor contact region of the second conductivity type extends along an edge of the upper side of the semiconductor region from the upper side into the semiconductor region and each has a spacing to the semiconductor contact region of the first conductivity type.

[0024] According to an extension, the additional semiconductor contact region of the second conductivity type extends along at least 50% or at least 75% or at least 90% of the periphery of the semiconductor region or the periphery of the active region of the semiconductor region. For example, the additional semiconductor contact region of the second conductivity type completely surrounds the region including the semiconductor contact region of the first conductivity type.

[0025] In one configuration, the additional semiconductor contact region of the second conductivity type is clamped to the reference potential.

[0026] According to one embodiment, the Hall sensor structure has a dielectric isolation layer, wherein the isolation layer includes an oxide, covers the upper side of the substrate layer and the upper side of the semiconductor region, and has a thickness of at least 1 nm or has a thickness in the range between 3 nm and 30 nm.

[0027] According to a first alternative embodiment, the semiconductor region extends from the upper side of the substrate layer into the substrate layer in a trench-shaped manner, wherein in one embodiment, the Hall sensor structure comprises a polysilicon layer, and the polysilicon layer covers a part of the upper side of the isolation layer, and the polysilicon layer has a thickness of 0.1 μm to 0.8 μm or 0.4 μm to 0.6 μm. In another embodiment, the polysilicon layer has a distance of at least 0.2 μm or at least 0.4 μm to each first semiconductor contact region.

[0028] It can be understood that in this embodiment, the upper side of the trench-shaped semiconductor region and the upper side of the semiconductor contact region coincide with the upper side of the substrate layer and preferably form a flat surface.

[0029] The polysilicon layer forms gate polysilicon (Gate-Poly) and is silicided in one embodiment in order to be able to produce a reliable electrically effective connection. The polysilicon layer is preferably clamped to a reference potential. The reference potential is preferably formed as ground potential.

[0030] In an extended solution, in the boundary region between the substrate layer and the groove-shaped semiconductor region, the additional semiconductor contact region of the second conductivity type extends from the upper side of the substrate layer and the upper side of the semiconductor region into the substrate layer and the semiconductor region. Therefore, the additional semiconductor contact region of the second conductivity type has a first region overlapping with the substrate layer and a second region overlapping with the semiconductor region.

[0031] Advantageously, the second region has a width of at least 0.05 μm or a width of 1 μm to 2 μm, since a relatively small overlap with the semiconductor region is already sufficient to ensure stable, time-independent operation of the Hall sensor structure immediately after switching on.

[0032] In an alternative configuration, the substrate preferably comprises an oxide layer over the entire surface of silicon, wherein the semiconductor region is connected in a materially bonded manner to the top side of the oxide layer.

[0033] The Hall sensor structure has at least one trench which extends from the upper side of the semiconductor region to the full-surface oxide layer.

[0034] The trench surrounds the semiconductor region. A semiconductor box is thus formed. The semiconductor contact region of the first conductivity type and the at least one semiconductor contact region of the second conductivity type are each arranged in a box region of the semiconductor region.

[0035] In a further configuration, the trench is filled with polysilicon and / or the side walls of the trench formed by the semiconductor region are coated with a second dielectric isolation layer, and the second dielectric isolation layer has a thickness of between 3 nm and 30 nm.

[0036] It is understood that the substrate with the semiconductor region forms a so-called SOI structure. Here, the substrate layer and the semiconductor region are respectively formed of silicon and the oxide layer is a silicon dioxide layer.

[0037] It is further understood that the semiconductor region is divided into individual sub-regions by means of a circumferential trench. The individual sub-regions are electrically insulated from one another in that the trench extends from the surface of the semiconductor region to the oxide layer. The individual sub-regions can be designated as box regions.

[0038] It should be noted that the oxide layer is constructed all over the silicon wafer. Thus, the oxide layer is buried and is also referred to as buried-oxide.

[0039] It is also understood that the box region of the semiconductor region surrounded by a trench (also called a trench or deep trench) forms an active region of the component. In other words, the trench isolates the active region (ie, the box region) from the rest of the semiconductor region (eg, adjacent active regions).

[0040] It is understood that, except for the sidewalls, the trench is filled with doped polysilicon. Preferably, the doped polysilicon of the trench is connected to a reference potential (preferably to ground potential). Thus, crosstalk between the cell regions is suppressed, especially when the potential between the cells changes rapidly.

[0041] One advantage is that minority charge carriers are provided in the box region by means of the at least one semiconductor contact region of the second conductivity type.

[0042] In one configuration, the additional semiconductor contact region of the second conductivity type extends along the trench or at least along a part of the trench from an upper side of the box region into the box region.

[0043] According to another embodiment, the semiconductor contact region of the first conductivity type and / or the semiconductor contact region of the second conductivity type each have a 5·10 18 N / cm 3 The dopant concentration of the semiconductor region is 5·10 14 N / cm 3 Until May 1016 N / cm 3 of dopant concentration.

[0044] In a further embodiment, at least a region of the semiconductor region extending between the semiconductor contact regions of the first conductivity type or the entire semiconductor region is threshold voltage implantation-free.

[0045] In one embodiment, the Hall sensor structure is designed monolithically. The semiconductor region is preferably designed from silicon or includes silicon. In a further embodiment, the Hall sensor structure includes at least a portion of a vertical Hall sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The invention is explained in more detail below with reference to the drawings. Components of the same type are marked with the same reference numerals. The embodiments shown are extremely schematic, i.e. the distances, lateral and vertical extensions are not proportional and - unless otherwise specified - do not have any derivable geometrical relationships with one another. The drawings show:

[0047] Figure 1 A top view showing a first embodiment of a Hall sensor structure according to the present invention;

[0048] Figure 2 A cross-sectional view showing an embodiment of a Hall sensor structure according to the present invention;

[0049] Figure 3 A cross-sectional view showing an embodiment of a Hall sensor structure according to the present invention;

[0050] Figure 4 A top view showing another embodiment of a Hall sensor structure according to the present invention;

[0051] Figure 5 A top view showing another embodiment of a Hall sensor structure according to the present invention;

[0052] Figure 6 A cross-sectional view showing another embodiment of a Hall sensor structure according to the present invention;

[0053] Figure 7 A top view showing another embodiment of a Hall sensor structure according to the present invention;

[0054] Figure 8 A cross-sectional view showing another embodiment of a Hall sensor structure according to the present invention;

[0055] Fig. 9 A plan view of another embodiment of a Hall sensor structure according to the present invention is shown. DETAILED DESCRIPTION

[0056] Figure 1 The figure shows a top view of a first embodiment of a Hall sensor structure HAL according to the invention, which has a substrate layer SUB, a semiconductor region HG of a first conductivity type and three semiconductor contact regions HK1 of the first conductivity type formed in the semiconductor region HG. The semiconductor region HG is formed in a rectangular shape. In this context, the semiconductor region is formed as an n-trough in a p-substrate. The substrate consists of silicon or includes silicon.

[0057] Three first conductivity type semiconductor connection regions are arranged side by side at intervals from each other, wherein the centrally arranged first conductivity type first semiconductor connection region HK1 has a first region B1 and a second region B2, and a second conductivity type first semiconductor connection region HK2 is arranged between the first region B1 and the second region B2.

[0058] The second conductivity type first semiconductor contact region HK2 adjoins not only the first region B1 of the first conductivity type first semiconductor contact region HK1 but also the second region B2 of the first conductivity type first semiconductor contact region HK1 .

[0059] A metal connection layer K1 is respectively arranged on each semiconductor connection region HK1 of the first conductivity type, wherein the connection layer K1 arranged on the first semiconductor connection region HK1 of the first conductivity type extends over the first region B1, the first semiconductor connection region HK2 of the second conductivity type and the second region B2, so that the first semiconductor connection region HK2 of the second conductivity type is conductively connected to the first semiconductor connection region HK1 of the first conductivity type.

[0060] exist Figure 2 The accompanying drawings show Figure 1 The following is only a cross-sectional view of the line AA. Figure 1 The difference between the drawings in FIG.

[0061] The semiconductor region HG extends from the upper side of the substrate layer SUB into the substrate layer SUB in a trench-like manner. Furthermore, a semiconductor contact region HK1 of a first conductivity type and a first semiconductor contact region HK2 of a second conductivity type are each formed from the upper side into the semiconductor region HG.

[0062] exist Figure 3 The accompanying drawings show the corresponding Figure 1 The following is a cross-sectional view of the cross section of the line BB. Figure 1 and Figure 2 The difference between the attached drawings.

[0063] The metallic connection layer K1 is formed in each case over a surface area on the semiconductor connection layer HK1 of the first conductivity type and on the first semiconductor connection region HK2 of the second conductivity type.

[0064] The upper side of the substrate layer SUB and the upper side of the semiconductor region HG are each coated with a first dielectric isolation layer ISO1.

[0065] A polysilicon layer POL is arranged on the upper side of the first isolation layer ISO1 , wherein the polysilicon layer has a gap to the first conductivity type semiconductor contact region HK1 and to the second conductivity type first semiconductor contact region HK2 , respectively, and the gap is filled by the second isolation layer ISO2 .

[0066] exist Figure 4 The figure of FIG. 1 shows a top view of another embodiment of the Hall sensor structure HAL. Figure 1 The difference between the attached drawings.

[0067] The Hall sensor structure HAL has five semiconductor contact regions HK1 of the first conductivity type, wherein a first semiconductor contact region HK1 of the first conductivity type and an adjoining first semiconductor contact region HK2 of the second conductivity type are again arranged together centrally.

[0068] exist Figure 5 The figure of FIG. 1 shows a top view of another embodiment of the Hall sensor structure HAL. Figure 1 The difference between the attached drawings.

[0069] The Hall sensor structure HAL has two semiconductor connection regions HK2 of the second conductivity type, wherein the two semiconductor connection regions HK2 of the second conductivity type are arranged adjacently on two mutually opposite sides of a centrally arranged first semiconductor connection region HK1 of the first conductivity type.

[0070] The metallic connection layer arranged on the first semiconductor contact region HK1 of the first conductivity type also extends over two adjacent semiconductor contact regions HK2 of the second conductivity type.

[0071] exist Figure 6 and Figure 7 The figure of is a cross-sectional view and a top view of another specific embodiment of a Hall sensor structure HAL. Only the differences from the previously illustrated figure are explained below.

[0072] The substrate layer SUB comprises an oxide layer ISO3 formed on the upper side of the substrate layer SUB. The semiconductor region HG is materially connected to the upper side of the oxide layer ISO3, wherein a trench T extending from the upper side of the semiconductor region HG to the oxide layer ISO3 surrounds a box region AB of the semiconductor region HG.

[0073] One sidewall of the trench T is coated with a dielectric isolation layer ISO2, and further, the trench T is filled with polysilicon POL1.

[0074] Three semiconductor contact regions HK1 of the first conductivity type and at least one semiconductor contact region of the second conductivity type extend from the upper side of the box region AB into the box region AB of the semiconductor region HG. The upper side of the box region AB is coated with a dielectric insulation layer ISO1.

[0075] exist Figure 8 and Fig. 9 The accompanying drawings show a cross-sectional view and a top view of another embodiment of the Hall sensor structure HAL. Figure 1 and Figure 2 The difference between the attached drawings.

[0076] The Hall sensor structure HAL has another semiconductor contact region HK3 of the second conductivity type, wherein the other semiconductor contact region HK3 surrounds the groove-shaped semiconductor region HG, or the other semiconductor contact region HK3 extends along the boundary between the side wall of the groove-shaped semiconductor region HG and the substrate layer SUB from the upper side of the substrate layer and the upper side of the semiconductor region HG into the substrate layer SUB and the semiconductor region HG, so that in particular an overlapping region with the semiconductor region HG is generated. Furthermore, the other semiconductor contact regions HK3 of the second conductivity type are spaced apart from all the semiconductor contact regions of the first conductivity type.

Claims

1. A vertical Hall sensor structure (HAL), the vertical Hall sensor structure having, Substrate layer (SUB), a semiconductor region (HG) of a first conductivity type, which is formed on or in the substrate layer (SUB), in, The semiconductor region (HG) is electrically isolated from the substrate layer (SUB) by means of a dielectric layer or by means of a p / n junction, at least one first, second and third semiconductor contact region (HK1) of the first conductivity type, each of which extends from an upper side of the semiconductor region (HG) into the semiconductor region (HG), The semiconductor contact regions (HK1) of the first conductivity type are spaced apart from each other, A metal connection layer (K1) is arranged on each semiconductor connection region (HK1) of the first conductivity type, It is characterized in that At least one first semiconductor contact region (HK2) of a second conductivity type is provided, the at least one first semiconductor contact region of a second conductivity type extending into the semiconductor region (HG), wherein: The first semiconductor connection region (HK2) of the second conductivity type is adjacent to the first semiconductor connection region (HK1) of the first conductivity type or has a spacing of at most 0.2 μm to the first semiconductor connection region (HK1) of the first conductivity type, wherein: The first semiconductor connection region (HK1) of the first conductivity type is conductively connected to the first semiconductor connection region (HK2) of the second conductivity type by electrical short circuit, wherein the first conductivity type is n-type and the second conductivity type is p-type, or the first conductivity type is p-type and the second conductivity type is n-type.

2. The vertical Hall sensor structure (HAL) according to claim 1, It is characterized in that The first semiconductor connection region (HK1) of the first conductivity type has a first region and a second region, wherein the first semiconductor connection region (HK2) of the second conductivity type is arranged between the first region and the second region, and the first semiconductor connection region of the second conductivity type is adjacent to the first region and the second region or has a spacing of up to 0.2 μm.

3. The vertical Hall sensor structure (HAL) according to claim 1, It is characterized in that The Hall sensor structure (HAL) includes a second semiconductor connection region (HK2) of the second conductivity type, wherein the first semiconductor connection region (HK2) of the second conductivity type is adjacent to the first side of the first semiconductor connection region (HK1) of the first conductivity type or has a spacing of up to 0.2 μm to the first side, and the second semiconductor connection region (HK2) of the second conductivity type is adjacent to the second side of the first semiconductor connection region (HK1) of the first conductivity type or has a spacing of up to 0.2 μm to the second side, and the second side is opposite to the first side.

4. The vertical Hall sensor structure (HAL) according to claim 1 or 2, It is characterized in that The semiconductor contact region (HK1) of the first conductivity type and the semiconductor contact region (HK2) of the second conductivity type each have a rectangular upper side.

5. A vertical Hall sensor structure (HAL) according to any one of claims 1 to 3, It is characterized in that The semiconductor contact regions (HK1) of the first conductivity type are arranged along a straight line, wherein a first semiconductor contact region (HK1) of the first conductivity type is arranged centrally along the straight line between other semiconductor contact regions (HK1) of the first conductivity type.

6. A vertical Hall sensor structure (HAL) according to any one of claims 1 to 3, It is characterized in that The Hall sensor structure (HAL) has at least one additional semiconductor connection region (HK3) of a second conductivity type, wherein the additional semiconductor connection region (HK3) of the second conductivity type extends from the upper side along the edge of the upper side of the semiconductor region (HG) into the semiconductor region (HG) and has a spacing to each of the plurality of semiconductor connection regions (HK1) of the first conductivity type.

7. The vertical Hall sensor structure (HAL) according to claim 6, It is characterized in that The additional semiconductor contact region (HK3) of the second conductivity type is clamped to a reference potential.

8. A vertical Hall sensor structure (HAL) according to any one of claims 1 to 3, It is characterized in that The Hall sensor structure (HAL) has a dielectric isolation layer (ISO1), wherein the isolation layer (ISO1) comprises an oxide, the isolation layer covers the upper side of the substrate layer (SUB) and the upper side of the semiconductor region (HG), and the isolation layer (ISO1) has a thickness of at least 1 nm or has a thickness in the range between 3 nm and 30 nm.

9. A vertical Hall sensor structure (HAL) according to any one of claims 1 to 3, It is characterized in that The semiconductor region (HG) extends from the upper side of the substrate layer (SUB) into the substrate layer (SUB) in a trench-shaped manner.

10. The vertical Hall sensor structure (HAL) according to claim 8, It is characterized in that The Hall sensor structure (HAL) has a polysilicon layer (POL), wherein the polysilicon layer (POL) covers a portion of the upper side of the isolation layer (ISO1), the polysilicon layer (POL) having a thickness of 0.1 μm to 0.8 μm or a thickness of 0.4 μm to 0.6 μm.

11. The vertical Hall sensor structure (HAL) according to claim 10, It is characterized in that The polysilicon layer (POL) has a spacing of at least 0.2 μm or at least 0.4 μm to each semiconductor contact region ( HK1 ) of the first conductivity type.

12. A vertical Hall sensor structure (HAL) according to any one of claims 1 to 3, It is characterized in that The substrate layer (SUB) has an oxide layer (ISO3), The semiconductor region (HG) is connected to the upper side of the oxide layer (ISO3) in a material-bonded manner, The Hall sensor structure (HAL) has at least one trench (T), which extends from the upper side of the semiconductor region (HG) to the oxide layer (ISO3), The at least one trench (T) surrounds a box region (AB) of the semiconductor region (HG), The semiconductor contact region (HK1) of the first conductivity type and the at least one semiconductor contact region (HK2) of the second conductivity type are respectively arranged in a box region (AB) of the semiconductor region (HG).

13. The vertical Hall sensor structure (HAL) according to claim 12, It is characterized in that The trench (T) is filled with polysilicon (POL1).

14. The vertical Hall sensor structure (HAL) according to claim 12, It is characterized in that The side walls of the trench (T) formed by the semiconductor region (HG) are coated with a second dielectric isolation layer (ISO2), and the second dielectric isolation layer (ISO2) has a thickness between 3 nm and 30 nm.

15. A vertical Hall sensor structure (HAL) according to any one of claims 1 to 3, It is characterized in that The semiconductor contact region (HK1) of the first conductivity type and / or the semiconductor contact region (HK2) of the second conductivity type have a conductivity of 5·10 18 N / cm 3 of dopant concentration.

16. A vertical Hall sensor structure (HAL) according to any one of claims 1 to 3, It is characterized in that The semiconductor region (HG) has a 5·10 14 N / cm 3 Until May 10 16 N / cm 3 of dopant concentration.

17. A vertical Hall sensor structure (HAL) according to any one of claims 1 to 3, It is characterized in that At least a region of the semiconductor region (HG) extending between semiconductor contact regions (HK1) of the first conductivity type or the entire semiconductor region (HG) is free of threshold voltage injection.

18. A vertical Hall sensor structure (HAL) according to any one of claims 1 to 3, It is characterized in that The Hall sensor structure (HAL) is designed monolithically.

19. A vertical Hall sensor structure (HAL) according to any one of claims 1 to 3, It is characterized in that The Hall sensor structure (HAL) includes at least a portion of a vertical Hall sensor.

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