Semiconductor device and inspection method thereof

Abstract

A semiconductor device and an inspection method thereof. In the semiconductor device, a PCMTEG region (100) formed on the surface of a semiconductor substrate is divided into a main PCMTEG region (101) and a sub-PCMTEG region (102), and all TEGs having standard electrical characteristic values ​​are centrally arranged in the sub-PCMTEG region (102).

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a PCMTEG and an inspection method thereof. Background Art

[0002] In a semiconductor integrated circuit device mounted on a semiconductor substrate, in addition to the IC chip as a product, a process control monitor test element group (PCMTEG) for confirming the completion of the semiconductor wafer manufacturing process is also configured. The PCMTEG is sometimes configured in a scribe line area for cutting out a plurality of IC chips (scribe line TEG), and sometimes configured in a specific area without forming an IC chip (external TEG).

[0003] In other words, in a semiconductor integrated circuit device mounted on a semiconductor substrate, a test element group (TEG) as an evaluation IC chip is sometimes configured in addition to the IC chip as a product. Among these TEGs, a TEG composed of a semiconductor element or a plurality of semiconductor elements and used to confirm the completion of a semiconductor wafer manufacturing process is sometimes referred to as a PCMTEG.

[0004] When the semiconductor wafer manufacturing process is nearing completion, the PCMTEG is used for electrical measurement, thereby confirming whether the semiconductor wafer manufacturing process is proceeding normally and whether the characteristics of the product meet the target. The electrical measurement of the PCMTEG is usually performed in the following manner: using a probe card with multiple probes (probes), the pad area set on multiple types of TEGs configured in the PCMTEG area is contacted by needles.

[0005] In order to improve productivity and manufacturing efficiency, PCMTEG measurement needs to be performed in the shortest possible time. In order to make needle contact with a desired plurality of PCMTEGs, the probe card needs to be moved. Due to the moving distance, the time and load of PCMTEG measurement increase. Therefore, PCMTEG measurement needs to be performed in the shortest possible time.

[0006] In addition, if there is a poor contact between the needles of the PCMTEG, the measured value cannot be obtained correctly, and the load increases due to the need for re-measurement. Alternatively, if the poor contact state of the needles is not noticed, there is a high possibility that the quality abnormality of the IC will be overlooked.

[0007] Patent Document 1 mentions a PCMTEG disposed on a scribe line and the width of the scribe line, and discloses a method of increasing the number of IC chips that can be obtained within a semiconductor wafer surface.

[0008] Prior art literature

[0009] Patent Literature

[0010] Patent Document 1: Japanese Patent Application Publication No. 2012-174789 Summary of the invention

[0011] Problem that the invention aims to solve

[0012] According to the semiconductor device described in Patent Document 1, by reducing the width of the scribe groove on the side where the PCMTEG is not configured, the number of ICs that can be manufactured from the entire semiconductor wafer can be increased, which helps to improve productivity. However, there is no mention of shortening the PCMTEG measurement time. In order to improve the productivity of the IC manufacturing process and reduce the workload, the PCMTEG measurement time must be shortened.

[0013] Therefore, an object of the present invention is to provide a semiconductor device capable of shortening the measurement time of PCMTEG.

[0014] Means used to solve problems

[0015] In order to achieve the above-mentioned object, the semiconductor device of the present invention adopts the following means.

[0016] A semiconductor device is provided, characterized in that it has:

[0017] Semiconductor substrate;

[0018] A PCMTEG region, in which a PCMTEG is formed on the surface of the semiconductor substrate, and the PCMTEG includes a plurality of TEGs classified by type;

[0019] a main PCMTEG region and a sub-PCMTEG region, which are arranged in the PCMTEG region; and

[0020] A plurality of TEG category areas divided according to the types of the TEG, which are included in the main PCMTEG area,

[0021] All TEGs having standard electrical characteristic values ​​selected from the various types of TEGs are arranged in the sub-PCMTEG area.

[0022] In addition, a method for inspecting a semiconductor device having a PCMTEG region formed on a surface of a semiconductor substrate is used, and the method for inspecting a semiconductor device is characterized by comprising the following steps:

[0023] Identifying a sub-PCMTEG region within the PCMTEG region;

[0024] Perform detection and inspection on all TEGs in the sub-PCMTEG area in turn; and

[0025] The electrical characteristic values ​​of all the TEGs in the sub-PCMTEG region are determined relative to a standard.

[0026] Effects of the Invention

[0027] According to the present invention, by centrally arranging a plurality of TEGs having standardized electrical characteristic values ​​in a sub-PCMTEG region provided in the PCMTEG region, it is possible to shorten the measurement time of the PCMTEG. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic plan view of a semiconductor device according to a first embodiment of the present invention.

[0029] Figure 2 It is a schematic plan view of a semiconductor device according to a second embodiment of the present invention.

[0030] Figure 3 It is a schematic plan view of a semiconductor device according to a third embodiment of the present invention.

[0031] Figure 4 This is a schematic top view of a conventional semiconductor device.

[0032] Description of symbols

[0033] 100, 500: PCMTEG area

[0034] 101: Main PCMTEG area

[0035] 102: Sub-PCMTEG area

[0036] 201, 501: N-type MOS transistor TEG area (TEG type area)

[0037] 202, 502: P-type MOS transistor TEG region (TEG type region)

[0038] 203, 503: TEG area of ​​the resistor (TEG type area)

[0039] 204, 504: TEG area of ​​capacitor (TEG category area)

[0040] 205: No TEG department

[0041] 301: N-type MOS transistor TEG with standard electrical characteristic values

[0042] 302: P-type MOS transistor TEG with standard electrical characteristic values

[0043] 303: TEG of resistors with standard electrical characteristic values

[0044] 304: TEG with capacitors that have standard electrical characteristic values

[0045] 401: N-type MOS transistor TEG has no standard electrical characteristic values

[0046] 402: P-type MOS transistor TEG has no standard electrical characteristic values

[0047] 403: TEG, a resistor with no standard electrical characteristic values

[0048] 404: TEG capacitors with no standard electrical characteristic values

[0049] 601: TEG for detection and inspection DETAILED DESCRIPTION

[0050] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0051] (First Embodiment)

[0052] Hereinafter, a semiconductor device according to a first embodiment will be described.

[0053] Before describing the embodiments of the present invention, a conventional semiconductor device will be described.

[0054] Figure 4 5 is a schematic top view of a conventional semiconductor device. The PCMTEG region 500 is a region composed of multiple types of TEGs for evaluating the completion of the semiconductor wafer manufacturing process. Figure 4 In the example, an N-type MOS transistor TEG region 501, a P-type MOS transistor TEG region 502, a resistor TEG region 503, and a capacitor TEG region 504 are arranged in the PCMTEG region 500 according to the type of TEG.

[0055] In addition, within the PCMTEG region 500, TEGs without standards for electrical characteristics and TEGs with standards for electrical characteristics are irregularly dispersed, and the TEGs with standards for electrical characteristics are represented as N-type MOS transistor TEG301 with standard electrical characteristic values, P-type MOS transistor TEG302 with standard electrical characteristic values, resistor TEG303 with standard electrical characteristic values, and capacitor TEG304 with standard electrical characteristic values.

[0056] In the case of a "TEG with a standard for electrical characteristics", an upper limit standard or a lower limit standard is set for the measured value of the electrical characteristics obtained when the TEG is measured. When the measured value of the "TEG with a standard for electrical characteristics" is greater than the upper limit standard or less than the lower limit standard, the semiconductor device to be measured is judged to be non-compliant with the standard, and re-inspection and other measures are performed. On the other hand, in a "TEG without a standard for electrical characteristics", no upper limit standard or lower limit standard is set for the measured value of the electrical characteristics obtained when the TEG is measured.

[0057] As mentioned above, in Figure 4 In the conventional semiconductor device shown, the N-type MOS transistor TEG 301 with a standard for electrical characteristic values, the P-type MOS transistor TEG 302 with a standard for electrical characteristic values, the resistor TEG 303 with a standard for electrical characteristic values, and the capacitor TEG 304 with a standard for electrical characteristic values ​​are dispersedly arranged in the arrangement area of ​​the group of TEGs of the same type to which they belong, that is, the N-type MOS transistor TEG area 501, the P-type MOS transistor TEG area 502, the resistor TEG area 503, and the capacitor TEG area 504. Therefore, when measuring the TEG with a standard for electrical characteristic values, it is necessary to move the evaluation probe card or the evaluation probe in the order of the N-type MOS transistor TEG area 501, the P-type MOS transistor TEG area 502, the resistor TEG area 503, and the capacitor TEG area 504, which requires a long measurement time. In addition, the detection state is also easy to change at any time, and it is sometimes difficult to stably obtain the correct characteristic value.

[0058] Next, embodiments of the present invention will be described.

[0059] Figure 1 It is a schematic plan view of a semiconductor device according to a first embodiment of the present invention.

[0060] The PCMTEG region 100 formed on the surface of the semiconductor substrate is a region composed of multiple types of TEGs such as N-type MOS transistors, P-type MOS transistors, resistors, and capacitors for evaluating the completion of the semiconductor wafer manufacturing process. Although not shown, the PCMTEG region 100 is set at one or more locations in the semiconductor substrate.

[0061] exist Figure 1 In the first embodiment of the present invention shown in (a), Figure 4Unlike the conventional semiconductor device shown in FIG. 1 , a main PCMTEG region 101 and a sub-PCMTEG region 102 are provided in the PCMTEG region 100. In the main PCMTEG region 101, a plurality of TEG category regions 201, 202, 203, and 204 are provided, which are divided according to the types of TEGs. For example, the TEG category regions 201, 202, 203, and 204 are respectively allocated to, for example, an N-type MOS transistor TEG region 201, a P-type MOS transistor TEG region 202, a resistor TEG region 203, and a capacitor TEG region 204.

[0062] As shown in the figure, the main PCMTEG region 101 and the sub-PCMTEG region 102 are both rectangular in shape. In the identification of the main PCMTEG region 101 and the sub-PCMTEG region 102, it is best to configure them to be separated from each other by a predetermined distance, such as a distance of 50 μm to 100 μm. In addition, for identification, an identification mark (not shown) is configured in each area of ​​the main PCMTEG region 101 and the sub-PCMTEG region 102.

[0063] In the sub-PCMTEG area 102, only TEGs with standard electrical characteristic values ​​are configured, that is, standard TEGs are configured, and N-type MOS transistor TEG 301 with standard electrical characteristic values, P-type MOS transistor TEG 302 with standard electrical characteristic values, resistor TEG 303 with standard electrical characteristic values, and capacitor TEG 304 with standard electrical characteristic values ​​are concentratedly configured.

[0064] In contrast, an N-type MOS transistor TEG 401 having no standard for electrical characteristic values ​​is configured in the N-type MOS transistor TEG region 201 in the main PCMTEG region 101, a P-type MOS transistor TEG 402 having no standard for electrical characteristic values ​​is configured in the P-type MOS transistor TEG region 202, a resistor TEG 403 having no standard for electrical characteristic values ​​is configured in the resistor TEG region 203, a capacitor TEG 404 having no standard for electrical characteristic values ​​and a non-TEG portion 205 are configured in the capacitor TEG region 204. That is, a TEG having no standard for electrical characteristic values, i.e., a non-standard TEG, is configured in the main PCMTEG region 101. In this case, the TEG configured in the main PCMTEG region 101 and the TEG configured in the sub-PCMTEG region 102 are non-overlapping. Furthermore, the types of TEGs configured in the main PCMTEG region 101 are the same as the types of TEGs configured in the sub-PCMTEG region 102, and the number of TEGs configured in the sub-PCMTEG region 102 is greater than the number of TEG types. That is, in the sub-PCMTEG region 102, one or more TEGs are configured for each type of TEG. The non-TEG portion 205 is a portion where no TEG is configured, and this portion can be compressed to reduce the occupied area of ​​the main PCMTEG region 101. Figure 1 In the example, the main PCMTEG area of ​​4×6 rows and columns can be set to 4×5 rows and columns.

[0065] When there is no extra area for the configuration of the PCMTEG region, such as Figure 1 As shown in (b), the main PCMTEG region 101 and the sub-PCMTEG region 102 may be configured to be connected. In this case, the outer shape of the PCMTEG region 100 in which the TEGs of n rows×m columns are configured is a rectangular shape, and is configured as follows: the sub-PCMTEG region 102 is set to be connected to at least one of the four corners of the rectangular PCMTEG region 100, or to be connected to one of the four sides forming the rectangle, and the remaining area is set as the main PCMTEG region 101.

[0066] By configuring the PCMTEG region 100 in this way, the moving distance of the evaluation probe card or the evaluation probe can be shortened during the electrical evaluation of the semiconductor device, and the time required for the measurement can be shortened, thereby improving the productivity and reducing the workload associated with the evaluation process.

[0067] Next, use Figure 1The inspection method of a semiconductor device according to the first embodiment of the present invention is described. First, a semiconductor substrate is placed on an inspection table of a detection device, and the optical inspection unit of the detection device recognizes identification marks (not shown) respectively set in the main PCMTEG region 101 and the sub-PCMTEG region 102, and the sub-PCMTEG region 102 as the detection inspection region is set as the detection inspection region. Alternatively, the detection inspection region is set using the coordinates of the sub-PCMTEG region 102 on the semiconductor substrate input in advance.

[0068] Next, each TEG with a standard electrical characteristic value, N-type MOS transistor TEG 301 with a standard electrical characteristic value, P-type MOS transistor TEG 302 with a standard electrical characteristic value, TEG 303 of a resistor with a standard electrical characteristic value, and TEG 304 of a capacitor with a standard electrical characteristic value in the sub-PCMTEG area 102 are probed and inspected in sequence. In this way, adjacent TEGs are probed and inspected in sequence starting from the TEG located at one end of the sub-PCMTEG area 102, thereby reducing the moving distance of the probe card, shortening the measurement time, and improving productivity. Next, the electrical characteristic values ​​obtained from the measurement of each TEG are determined based on the predetermined upper limit standard, lower limit standard, and other standards. When the electrical characteristic value of any TEG does not meet the standard, re-inspection and other measures are performed.

[0069] (Second Embodiment)

[0070] Next, a second embodiment of the present invention will be described.

[0071] Figure 2 FIG. 2 is a schematic top view of a semiconductor device according to a second embodiment of the present invention. Figure 1 The same parts as those in the first embodiment described above are denoted by the same reference numerals and the description thereof will be replaced.

[0072] like Figure 2 As shown, in the second embodiment, similar to the first embodiment, a main PCMTEG region 101 and a sub-PCMTEG region 102 are set in the PCMTEG region 100, and an N-type MOS transistor TEG 301 with a standard electrical characteristic value, a P-type MOS transistor TEG 302 with a standard electrical characteristic value, a resistor TEG 303 with a standard electrical characteristic value, and a capacitor TEG 304 with a standard electrical characteristic value are centrally configured in the sub-PCMTEG region 102.

[0073] In contrast, both TEGs without standards for electrical characteristic values ​​and TEGs with standards for electrical characteristic values ​​are configured in the main PCMTEG region 101. For example, both N-type MOS transistor TEG 401 without standards for electrical characteristic values ​​and N-type MOS transistor TEG 301 with standards for electrical characteristic values ​​are configured in the N-type MOS transistor TEG region 201, both P-type MOS transistor TEG 402 without standards for electrical characteristic values ​​and N-type MOS transistor TEG 302 with standards for electrical characteristic values ​​are configured in the P-type MOS transistor TEG region 202, both TEG 403 of resistors without standards for electrical characteristic values ​​and TEG 303 of resistors with standards for electrical characteristic values ​​are configured in the resistor TEG region 203, and both TEG 404 of capacitors without standards for electrical characteristic values ​​and TEG 304 of capacitors with standards for electrical characteristic values ​​are configured in the capacitor TEG region 204.

[0074] In the PCMTEG measurement stage for evaluating the completion of the semiconductor wafer manufacturing process, as in the first embodiment, it is only necessary to measure a specific TEG with a standard for electrical characteristic values, that is, the standardized TEG in the sub-PCMTEG area 102. However, depending on the situation, additional evaluations are sometimes performed on both the TEG without a standard for electrical characteristic values ​​and the TEG with a standard for electrical characteristic values ​​(for example, manual measurement in a laboratory, etc.). In this case, if only the TEG with a standard for electrical characteristic values ​​is away from the main PCMTEG area 101 and is only configured in the sub-PCMTEG area 102, inconvenience will arise.

[0075] When the main PCMTEG region 101 has surplus area, although it becomes an overlapping form, it is convenient to configure the main PCMTEG region 101 to also retain the N-type MOS transistor TEG 301 with standard electrical characteristic values, the P-type MOS transistor TEG 302 with standard electrical characteristic values, the resistor TEG 303 with standard electrical characteristic values, and the capacitor TEG 304 with standard electrical characteristic values ​​that are concentrated in the sub-PCMTEG region 102.

[0076] As described above, by setting TEGs with standardized electrical characteristic values ​​in both the main PCMTEG region 101 and the sub-PCMTEG region 102, in the additional evaluation, only the TEGs in the main PCMTEG region 101 configured with both TEGs without standardized electrical characteristic values ​​and TEGs with standardized electrical characteristic values ​​need to be evaluated.

[0077] (Third Embodiment)

[0078] Next, a third embodiment of the present invention will be described.

[0079] Figure 3 It is a schematic plan view of a semiconductor device according to a third embodiment of the present invention.

[0080] For use with Figure 1 The first embodiment and the Figure 2 The same parts as those in the second embodiment described above are denoted by the same reference numerals and replaced in description.

[0081] exist Figure 3 In the third embodiment of the present invention shown, in addition to the N-type MOS transistor TEG 301 with standard electrical characteristic values, the P-type MOS transistor TEG 302 with standard electrical characteristic values, the resistor TEG 303 with standard electrical characteristic values, and the capacitor TEG 304 with standard electrical characteristic values, which are concentrated in the sub-PCMTEG area 102, a TEG 601 for detection and inspection is also configured.

[0082] In the PCMTEG measurement process of measuring the electrical characteristics of a plurality of TEGs by needle contact (probing), it is very important to perform needle contact accurately. In the third embodiment, by arranging the TEG 601 for probing inspection together, it is possible to simultaneously inspect whether accurate needle contact can be performed.

[0083] Although not shown in the figure, the TEG 601 for detection and inspection can set a needle contact area that is smaller than the conventional TEG for measurement to detect the planar position deviation of the needle, or can confirm the needle contact state in the height direction by having a structure that is different from the conventional TEG in cross-sectional structure (for example, the conventional TEG uses the metal of the second layer to form the needle contact area, while the TEG 601 for detection and inspection uses the metal of the first layer to form the needle contact area, etc.).

[0084] Next, use Figure 3 The inspection method of the semiconductor device according to the third embodiment of the present invention is described. First, a semiconductor substrate is placed on the inspection table of a detection device, and the optical inspection unit of the detection device identifies the identification marks (not shown) respectively set in the main PCMTEG area 101 and the sub-PCMTEG area 102, and sets the sub-PCMTEG area 102 as the detection inspection area as the detection inspection area. Alternatively, the detection inspection area is set using the coordinates on the semiconductor substrate of the sub-PCMTEG area 102 input in advance. Next, a probe provided on a probe card is used to make a needle contact with the TEG 601 for detection inspection provided near the sub-PCMTEG area 102 to confirm that the probe contact state is normal.

[0085] Next, each TEG with a standard electrical characteristic value, TEG 304 with a standard electrical characteristic value, TEG 303 with a resistor with a standard electrical characteristic value, P-type MOS transistor TEG 302 with a standard electrical characteristic value, and N-type MOS transistor TEG 301 with a standard electrical characteristic value in the PCMTEG area 102 are probed and inspected in sequence. Here, after the needle contacts the TEG 601 for probing and inspection, the measurement is performed from the TEG 304 with a standard electrical characteristic value close to the TEG 601 for probing and inspection in the sub-PCMTEG area 102, and then the adjacent TEGs are probed and inspected in sequence, thereby reducing the moving distance of the probe card, shortening the measurement time, and improving productivity. Next, the electrical characteristic value obtained from the measurement of each TEG is determined based on the standards such as the upper limit standard and the lower limit standard determined in advance. In the case where the electrical characteristic value of each TEG does not meet the standard, re-inspection and other measures are taken.

[0086] In this embodiment, the main PCMTEG region 101 may be configured with only a TEG without a standard for electrical characteristic values ​​as in the first embodiment, or may be configured with both a TEG without a standard for electrical characteristic values ​​and a TEG with a standard for electrical characteristic values ​​as in the second embodiment. In addition, by configuring a detection inspection TEG 601 for confirming the needle contact state adjacent to the sub-PCMTEG region 102, a stable and correct electrical characteristic value can be obtained.

Claims

1. A semiconductor device, characterized in that: It has: Semiconductor substrate; A PCMTEG region, wherein a PCMTEG is formed on the surface of the semiconductor substrate, wherein the PCMTEG includes a plurality of TEGs classified by type, wherein the PCMTEG is a process control monitor test element group, and the TEG is a test element group; a main PCMTEG region and a sub-PCMTEG region, which are spaced a prescribed distance apart from each other and are arranged in the PCMTEG region; and A plurality of TEG category areas divided according to the types of the TEG, which are included in the main PCMTEG area, TEGs with standard electrical characteristic values ​​selected from the various types of TEGs are centrally arranged in the sub-PCMTEG area. The main PCMTEG area is configured with TEGs that do not have a standard for electrical characteristic values ​​and the centrally configured TEGs that have a standard for the electrical characteristic values.

2. The semiconductor device according to claim 1, wherein: The types of the TEG are at least N-type MOS transistors, P-type MOS transistors, resistors and capacitors.

3. The semiconductor device according to claim 1, wherein: A probing and testing TEG is arranged adjacent to the sub-PCMTEG region.

Images