Watchdog Timer Hierarchy

Abstract

In one example of the technology herein, a first watchdog timer is caused to be reset periodically via a first independent execution environment in a set of independent execution environments in an integrated circuit. The set of independent execution environments is configured to have a deep defense hierarchy. The set of independent execution environments includes a first independent execution environment and a second independent execution environment. The first independent execution environment is the most trusted execution environment on the integrated circuit. Via the second independent execution environment: a second watchdog timer is caused to be reset periodically. In response to the second watchdog timer timing out, an interrupt is transmitted from the second watchdog timer to the first independent execution environment. In response to the first watchdog timer timing out, at least a portion of the integrated circuit is reset.

Description

Background Art

[0001] The Internet of Things (“IoT”) generally refers to a system of devices that are able to communicate over a network. These devices can include everyday items such as toasters, coffee makers, thermostat systems, washers, dryers, lights, cars, etc. Network communications can be used to automate devices, capture data, provide alerts, personalize settings, and many other applications. Summary of the invention

[0002] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

[0003] Briefly, the disclosed technology generally relates to embedded device security. In one example of the technology herein, a first watchdog timer is caused to be reset periodically via a first independent execution environment in a set of independent execution environments in an integrated circuit. In some examples, the set of independent execution environments is configured to have a defense-in-depth hierarchy. In some examples, the set of independent execution environments includes a first independent execution environment and a second independent execution environment. In some examples, the first independent execution environment is the most trusted execution environment on the integrated circuit. In some examples, via the second independent execution environment: a second watchdog timer is periodically caused to be reset periodically. In some examples, in response to a timeout of the second watchdog timer, an interrupt is transmitted from the second watchdog timer to the first independent execution environment. In some examples, in response to a timeout of the first watchdog timer, at least a portion of the integrated circuit is reset.

[0004] Other aspects and applications of the disclosed technology will be apparent upon reading and understanding the drawings and description. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Non-limiting and non-exhaustive examples of the present disclosure are described with reference to the following drawings. In the drawings, like reference numerals refer to like parts throughout the various figures unless otherwise specified. The drawings are not necessarily drawn to scale.

[0006] For a better understanding of the present disclosure, reference will be made to the following detailed description, which should be read in conjunction with the accompanying drawings, in which:

[0007] Figure 1 is a block diagram illustrating one example of a suitable environment in which various aspects of the techniques herein may be employed;

[0008] Figure 2is a block diagram illustrating one example of a suitable computing device in accordance with various aspects of the disclosed technology;

[0009] Figure 3 is a block diagram illustrating an example of a system;

[0010] Figure 4 It's a picture. Figure 3 A block diagram of an example of an illustrated device controller; and

[0011] FIG. 5A to FIG. 5B is a flow chart illustrating an example process in accordance with various aspects of the present disclosure. DETAILED DESCRIPTION

[0012] The following description provides specific details in order to thoroughly understand the various examples of the technology of this article and to implement the description of the various examples of the technology of this article. It will be understood by those skilled in the art that the technology of this article can be practiced without many of these details. In some instances, well-known structures and functions are not shown or described in detail to avoid unnecessarily obscuring the description of the examples of the technology of this article. It is intended that the terms used in this disclosure are interpreted in their broadest reasonable manner, even if the terms are used in conjunction with the detailed description of certain examples of the technology of this article. Although some terms may be emphasized below, any term intended to be interpreted in any restricted manner will be publicly and clearly defined as in this specific embodiment section. Throughout this specification and claims, the following terms have at least the meanings clearly associated with this article, unless the context otherwise provides. The meanings identified below do not necessarily limit the terms, but only provide illustrative examples of the terms. For example, each of the terms "based on" and "based upon" is not exclusive, but is equivalent to the term "based at least in part on", and includes options based on additional factors, some of which are not described in this article. As another example, the term "via" is not exclusive, but is equivalent to the term "at least partially via", and includes the option of via additional factors, some of which may not be described herein. The meaning of "in" includes "in" and "on". The phrases "in one embodiment" or "in one example" as used herein do not necessarily refer to the same embodiment or example, but they may refer to the same embodiment or example. The use of specific textual numerical designations does not imply the presence of numerical designators with smaller values. For example, the statement "a widget selected from a group consisting of a third foo and a fourth bar" itself will not imply the presence of at least three foos, nor at least four bar elements. Singular references are only for clear reading, and include plural references unless plural references are explicitly excluded. The term "or" is an inclusive "or" operator unless otherwise explicitly indicated. For example, the phrase "A or B" means "A, B, or A and B". As used herein, the terms "component" and "system" are intended to cover various combinations of hardware, software, or hardware and software. Thus, for example, a system or component may be a process, a process executing on a computing device, a computing device, or a portion thereof.

[0013] Briefly, the disclosed technology generally relates to embedded device security. In one example of the technology herein, a first watchdog timer is caused to be reset periodically via a first independent execution environment in a set of independent execution environments in an integrated circuit. In some examples, the set of independent execution environments is configured to have a deep defense hierarchy. In some examples, the set of independent execution environments includes a first independent execution environment and a second independent execution environment. In some examples, the first independent execution environment is the most trusted execution environment on the integrated circuit. In some examples, via the second independent execution environment: a second watchdog timer is periodically caused to be reset periodically. In some examples, in response to a timeout of the second watchdog timer, an interrupt is conducted from the second watchdog timer to the first independent execution environment. In some examples, in response to a timeout of the first watchdog timer, at least a portion of the integrated circuit is reset.

[0014] In some examples, the multi-core integrated circuit has at least two trust levels. In some examples, the trust levels can include a security complex at the highest security level, a class of cores at a second trust level, and another class of cores with I / O functionality at the lowest trust level. In other examples, other suitable trust hierarchies can be used.

[0015] In some examples, a separate watchdog timer is used at each trust level. In some examples, at each trust level, software at that level must reset the watchdog timer periodically to prevent the watchdog timer from elapsing, and if the software does not reset the watchdog timer, the watchdog timer may elapsing within a predetermined period of time (such as 1 ms). In some examples, if the watchdog timer elapsing, it means that a problem has occurred, such as a program error, which prevents the software from running properly. For example, the software may be stuck in a loop.

[0016] In some examples, when the watchdog timer at the highest trust level times out, the watchdog timer at the highest trust level resets the entire integrated circuit. However, in other examples, when the watchdog timer is at the highest trust level, a portion of the integrated circuit may be reset instead. For example, the watchdog timer may be configured to reset a portion of the integrated circuit so that other portions of the integrated circuit can complete one or more operations "elegantly". In some examples, when a watchdog timer at a layer other than the highest level of the hierarchy times out, the watchdog timer sends an interrupt to a higher level in the hierarchy. The watchdog timer may also reset the current trust level. The higher trust level that receives the interrupt may respond accordingly, including: logging and / or tracing events, determining when and how the level that sent the interrupt should be released, and the like.

[0017] Illustrative Equipment / Operating Environment

[0018] Figure 1 1 is a schematic diagram of an environment 100 in which various aspects of the technology herein may be practiced. As shown, the environment 100 includes a computing device 110 and a network node 120 connected via a network 130. Although specific components in the environment 100 are not described in detail, Figure 1 , but in other examples, the environment 100 may also include additional and / or different components. For example, in some examples, the environment 100 may also include a network storage device, a maintenance manager, and / or other suitable components (not shown). Figure 1 The computing device 110 shown in FIG. 1 can be located in various locations, including on-premises, in the cloud, etc. For example, the computing device 110 can be on the client side, on the server side, etc.

[0019] As in Figure 1 As shown in , the network 130 may include one or more network nodes 120, which interconnect multiple computing devices 110 and connect the computing devices 110 to an external network 140, such as the Internet or an intranet. For example, the network node 120 may include a switch, a router, a hub, a network controller or other network elements. In some examples, the computing devices 110 may be organized into racks, action areas, groups, sets or other suitable partitions. For example, in the illustrated example, the computing devices 110 are grouped into three host sets that are individually identified as the first, second and third host sets 112a to 112c. In the illustrated example, each host set in the host set 112a to 112c is operably coupled to the corresponding network nodes 120a to 120c, respectively, and these network nodes 120a to 120c are generally referred to as "rack-type" or "TOR" network nodes. The TOR network nodes 120a to 120c can then be operatively coupled to additional network nodes 120 to form a computer network in a hierarchical, flat, mesh-type topology, or other suitable type of topology that allows communication between the computing device 110 and the external network 140. In other examples, multiple host sets 112a to 112c can share a single network node 120. The computing device 110 can be virtually any type of general-purpose or special-purpose computing device. For example, these computing devices can be user devices, such as desktop computers, laptop computers, tablet computers, display devices, cameras, printers, or smart phones. However, in a data center environment, these computing devices can be server devices, such as application server computers, virtual computing host computers, or file server computers. In addition, the computing devices 110 can be individually configured to provide computing, storage, and / or other suitable computing services.

[0020] In some examples, as discussed in more detail below, one or more computing devices 110 are IoT devices, devices that include part or all of IoT support services, devices that include part or all of an application backend, and the like.

[0021] Illustrative Computing Devices

[0022] Figure 2 is a schematic diagram illustrating one example of a computing device 200 in which various aspects of the techniques of this document may be practiced. The computing device 200 may be virtually any type of general-purpose or special-purpose computing device. For example, the computing device 200 may be a user device, such as a desktop computer, a laptop computer, a tablet computer, a display device, a camera, a printer, or a smart phone. Likewise, the computing device 200 may also be a server device, such as an application server computer, a virtual computing host computer, or a file server computer. For example, the computing device 200 may be Figure 1 The computing device 200 may also be an IoT device connected to a network to receive IoT services. Similarly, as discussed in more detail below, the computing device 200 may be an IoT device connected to a network to receive IoT services. Figure 3 to Figure 4 Examples of any of the devices shown or mentioned in the figure. Figure 2 As illustrated in , computing device 200 includes processing circuit 210, operating memory 220, memory controller 230, data storage memory 250, input interface 260, output interface 270, and network adapter 280. Each of these previously listed components of computing device 200 includes at least one hardware element.

[0023] The computing device 200 includes at least one processing circuit 210 configured to execute instructions, such as instructions for implementing the workload, process or technology described herein. The processing circuit 210 may include a microprocessor, a microcontroller, a graphics processor, a coprocessor, a field programmable gate array, a programmable logic device, a signal processor, or any other circuit suitable for processing data. The processing circuit 210 is an example of a core. The aforementioned instructions and other data (e.g., data sets, metadata, operating system instructions, etc.) can be stored in the operating memory 220 during the runtime of the computing device 200. The operating memory 220 may also include any of a variety of data storage devices / components, such as volatile memory, semi-volatile memory, random access memory, static memory, buffer memory, buffer, or other media used to store runtime information. In one example, when the computing device 200 is powered off, the operating memory 220 does not retain information. Instead, the computing device 200 may be configured to pass instructions from a non-volatile data storage component (e.g., data storage memory 250) to the operating memory 220 as part of a boot or other loading process. In some examples, other forms of execution may be employed, such as executing directly from data storage memory 250 , eg, execute-in-place (XIP).

[0024] The operating memory 220 may include a fourth generation double data rate (DDR4) memory, a third generation double data rate (DDR3) memory, other dynamic random access memory (DRAM), a high bandwidth memory (HBM), a hybrid memory cube memory, a 3D stacked memory, a static random access memory (SRAM), a magnetoresistive random access memory (MRAM), a pseudo random access memory (PSRAM), or other memory, and such memory may include one or more memory circuits integrated into a DIMM, a SIMM, a SODIMM, a known good die (KGD), or other package. Such operating memory modules or devices may be organized according to channels, ranks, and banks. For example, the operating memory device may be coupled to the processing circuit 210 in a channel via the memory controller 230. An example of the computing device 200 may include one or two DIMMs per channel, with one or two ranks per channel. The operating memory within the rank may be operated using a shared clock and a shared address and command bus. Moreover, the operating memory device may be organized into several memory banks, where the bank may be considered as an array addressed in rows and columns. Based on this organization of the operating memory, a physical address within the operating memory can be referenced by a tuple of channel, bank, bank, row, and column.

[0025] Notwithstanding the above discussion, it is expressly intended that the operational memory 220 does not include or encompass multiple communication media, any communication media, or any signal per se.

[0026] The memory controller 230 is configured to interface the processing circuit 210 to the operating memory 220. For example, the memory controller 230 may be configured to interface commands, addresses, and data between the operating memory 220 and the processing circuit 210. The memory controller 230 may also be configured to abstract or otherwise manage certain aspects of memory management from or for the processing circuit 210. Although the memory controller 230 is illustrated as a single memory controller separate from the processing circuit 210, in other examples, multiple memory controllers may be employed, the memory controller(s) may be integrated with the operating memory 220, etc. Further, the memory controller(s) may be integrated into the processing circuit 210. These and other variations are possible.

[0027] In computing device 200, data storage memory 250, input interface 260, output interface 270, and network adapter 280 are interfaced to processing circuitry 210 via bus 240. Figure 2 The bus 240 is illustrated as a single passive bus, but other configurations (such as a collection of buses, a collection of point-to-point links, input / output controllers, bridges, other interface circuit systems, or any collection thereof) may be appropriately used to interface the data storage memory 250, input interface 260, output interface 270, or network adapter 280 to the processing circuit 210.

[0028] In the computing device 200, the data storage memory 250 is adopted for long-term non-volatile data storage. The data storage memory 250 may include any of a variety of non-volatile data storage devices / components, such as non-volatile memory, disk, disk drive, hard disk drive, solid state drive or any other medium that can be used for non-volatile storage of information. However, explicitly, the data storage memory 250 does not include or cover multiple communication media, any communication media or any signal itself. In contrast to the operating memory 220, the computing device 200 adopts the data storage memory 250 for non-volatile long-term data storage rather than runtime data storage. In some examples, the performance counter 475 can also be configured to measure the waiting time from the core to the target (such as from the MCU 462 to the SRAM458).

[0029] Furthermore, the computing device 200 may include or be coupled to any type of processor-readable media, such as processor-readable storage media (e.g., operating memory 220 and data storage memory 250) and communication media (e.g., communication signals and radio waves). Although the term "processor-readable storage medium" includes operating memory 220 and data storage memory 250, throughout this specification and claims, whether used in the singular or plural, the term "processor-readable storage medium" is defined herein such that the term "processor-readable storage medium" explicitly excludes and does not encompass multiple communication media, any communication media, or any signal itself. However, the term "processor-readable storage medium" does encompass processor buffer memory, random access memory (RAM), register memory, etc.

[0030] The computing device 200 also includes an input interface 260, which can be configured to enable the computing device 200 to receive input from a user or from other devices. Additionally, the computing device 200 includes an output interface 270, which can be configured to provide output from the computing device 200. In one example, the output interface 270 includes a frame buffer, a graphics processor, a graphics processor or an accelerator, and is configured to draw a display to be presented on a separate visual display device (such as a monitor, a projector, a virtual computing client computer, etc.). In another example, the output interface 270 includes a visual display device, and is configured to draw and present a display for viewing. In yet another example, the input interface 260 and / or the output interface 270 may include a universal asynchronous receiver / transmitter ("UART"), a serial peripheral interface ("SPI"), an internal integrated circuit ("I2C"), a general purpose input / output (GPIO), etc. In addition, the input interface 260 and / or the output interface 270 may include or be interfaced to any number or type of peripheral devices.

[0031] In the illustrated example, computing device 200 is configured to communicate with other computing devices or entities via network adapter 280. Network adapter 280 may include a wired network adapter, such as an Ethernet adapter, a token ring adapter, or a digital subscriber line (DSL) adapter. Network adapter 280 may also include a wireless network adapter, such as a Wi-Fi adapter, a Bluetooth adapter, a ZigBee adapter, a Long Term Evolution (LTE) adapter, SigFox, LoRa, a powerline, or a 5G adapter.

[0032] Although computing device 200 is illustrated as having certain components configured in a particular arrangement, these components and arrangements are merely one example of a computing device in which the techniques herein may be employed. In other examples, data storage memory 250, input interface 260, output interface 270, or network adapter 280 may be coupled directly to processing circuitry 210, or via an input / output controller, a bridge, or other interface circuitry. Other variations of the techniques herein are possible.

[0033] Some examples of computing device 200 include at least one memory (e.g., operating memory 220) suitable for storing runtime data and at least one processor (e.g., processing circuitry 210) suitable for executing processor-executable code that, in response to execution, enables computing device 200 to perform actions.

[0034] Descriptive System

[0035] Some examples of the present disclosure are used in the context of a multi-core microcontroller included in an IoT device, which operates as a device controller for the IoT device. Examples of the present disclosure may also be used in other suitable contexts. Figure 4 and Figure 5A , Figure 5B Specific examples of the present disclosure used in the context of a multi-core microcontroller included in an IoT device, which operates as a device controller for the IoT device, are discussed.

[0036] Figure 3 300 . The system 300 may include a network 330 , as well as IoT support services 351 , IoT devices 341 and 342 , and an application backend 313 , all connected to the network 330 .

[0037] The term "IoT device" refers to a device designed to utilize IoT services. IoT devices can include virtually any device that is connected to a network to use IoT services, including for telemetry collection or any other purpose. IoT devices include any device that can be connected to a network to utilize IoT services. In various examples, IoT devices can communicate with the cloud, a peer or a local system, or a combination of a peer and a local system and the cloud, or in any other suitable manner. IoT devices can include everyday items such as toasters, coffee makers, thermostat systems, washers, dryers, lights, cars, and the like. IoT devices can also include, for example, various devices in "smart" buildings, including lights, temperature sensors, humidity sensors, occupancy sensors, and the like. IoT services for IoT devices can be used for device automation, data capture, providing warnings, personalizing settings, and many other applications.

[0038] The term "IoT support service" refers to a device, a portion of at least one device, or multiple devices (such as a distributed system), to which, in some examples, IoT devices connect over a network to obtain IoT services. In some examples, the IoT support service is an IoT hub. In some examples, the IoT hub is excluded, and the IoT device communicates with the application backend directly or through one or more intermediaries without including the IoT hub, and the software components in the application backend operate as IoT support services. The IoT device receives IoT services via communication with the IoT support service. In some examples, the IoT support service may be embedded within the device or in the local infrastructure.

[0039] The application backend 313 refers to a device or multiple devices (such as a distributed system) that performs actions to implement data collection, storage, and / or actions to be taken based on IoT data, including user access and control, data analysis, data display, control of data storage, automatic actions taken based on IoT data, etc. The application backend 313 can also be one or more virtual machines deployed in a public cloud or a private cloud. In some examples, at least some of the actions taken by the application backend can be performed by an application running in the application backend 313.

[0040] Each of the IoT devices 341 and 342 and / or the devices including the IoT support service 351 and / or the application backend 313 may include Figure 2An example of a computing device 200 is shown. The term "IoT support service" is not limited to one specific type of IoT service, but refers to a device that an IoT service communicates with to obtain at least one IoT solution or IoT service after the device is provided. That is, the term "IoT support service" as used throughout this specification and claims is generic to any IoT solution. The term "IoT support service" simply refers to the portion of an IoT solution / IoT service that a provided IoT device communicates with. In some examples, communication between an IoT device and one or more application backends occurs with the IoT support service as an intermediary. Figure 3 and in this manual Figure 3 The corresponding description describes an example system for illustration purposes, which does not limit the scope of the present disclosure.

[0041] One or more of the IoT devices 341 and 342 may include a device controller 345 that can operate to control the IoT device. Each device controller 345 may include multiple execution environments configured in a deep defense hierarchy. The device controller 345 may be a multi-core microcontroller. In some examples, the device controller 345 is an integrated circuit with multiple independent execution environments (such as multiple cores, such as at least one central processing unit (CPU) and at least one microcontroller (MCU)).

[0042] The network 330 may include one or more computer networks, including wired and / or wireless networks, each of which may be, for example, a wireless network, a local area network (LAN), a wide area network (WAN), and / or a global network (such as the Internet). On a set of interconnected LANs (including those based on different architectures and protocols), a router acts as a link between LANs, thereby enabling messages to be sent from one LAN to another. Moreover, the communication links within a LAN typically include twisted pairs or coaxial cables, while the communication links between networks may utilize analog telephone lines, fully or partially dedicated digital lines including T1, T2, T3, and T4, integrated services digital networks (ISDN), digital subscriber lines (DSL), wireless links including satellite links, or other communication links known to those skilled in the art. In addition, remote computers and other related electronic devices may be remotely connected to a LAN or WAN via a modem and a temporary telephone link. The network 330 may include various other networks, such as one or more networks using local network protocols (such as 6LoWPAN, ZigBee, etc.). Some IoT devices may be connected to user devices rather than other IoT devices via different networks in the network 330. In essence, network 330 includes any communication method by which information can be transmitted between IoT support services 351, IoT devices 341 and 342, and application backend 313. Although each device or service is shown as being connected to network 330, that does not mean that each device communicates with each other device shown. In some examples, some of the devices / services shown communicate with some of the other devices / services shown only via one or more intermediate devices. Moreover, although network 330 is illustrated as one network, in some examples, network 330 may alternatively include multiple networks that may or may not be connected to each other, wherein some of the devices shown communicate with each other through one of the multiple networks, while other devices in the devices shown communicate with each other using different networks in the multiple networks.

[0043] As one example, IoT devices 341 and 342 are devices intended to utilize IoT services provided by IoT support service 351 .

[0044] System 300 may include Figure 3 More or fewer devices than those shown in the figure, Figure 3 It is shown by way of example only.

[0045] Illustrative equipment

[0046] Figure 4 445 is a block diagram illustrating an example of a device controller 445. The device controller 445 may be used as Figure 3An example of a device controller 345 is shown. The device controller 445 may include a security complex 451, a CPU 453, a direct memory access (DMA) block 454, a trust zone (TZ) DMA block 455, a flash memory 456, a radio block 457, a secure static random access memory (SRAM) 458, an interface 459, an MCU 461, an MCU 462, a primary advanced extensible interface (AXI) bus 463, a secondary AXI bus 464, bridges 465 and 466, an AXI per peripheral to advanced peripheral bus (APB) bridge 467, an interface 471, a GPIO 472, an analog-to-digital converter (ADC) 473, a real-time clock (RTC) 474, DMA blocks 481 and 482, performance counters 475, and watchdog timers 431 to 433.

[0047] In some examples, device controller 445 enables a device in which device controller 445 is included to operate as an IoT device, such as Figure 3 IoT device 341 or 342 shown. In some examples, device controller 445 is a multi-core microcontroller. In some examples, device controller 445 runs a high-level operating system. In some examples, device controller 445 may have at least 4MB of RAM and at least 4MB of flash memory, and may be a single integrated circuit. In some examples, device controller 445 provides not only network connectivity, but also various other functions, including hardware and software security, monitored operating systems, cryptographic functions, peripheral control, telemetry, etc. Additionally, device controller 445 may include technology for allowing device controller 445 to be booted in a secure manner, allowing device controller 445 to be securely updated, ensuring that appropriate software is running on device controller 445, allowing device controller 445 to be properly used as an IoT device, etc.

[0048] In some examples, security complex 451 includes a security complex (SC) as a hardware root of trust in device controller 445. In some examples, the security complex is directly connected to a security MCU in security complex 451. In some examples, the security MCU in security complex 451 has a very high trust, but is less trusted than the security complex in the form of security complex 451. In some examples, security complex 451 causes the entire system to load and start at boot time.

[0049] In some examples, watchdog timer 431 is a watchdog timer for the SC of security complex 451 , watchdog timer 432 is a watchdog timer for CPU 453 , and watchdog timer 433 is a watchdog timer for MCU 461 and MCU 462 .

[0050] In some examples, CPU 453 runs a high-level operating system. In some examples, CPU 453 has two independent execution environments: a secure world execution environment and a normal world execution environment. The term "secure world" is widely used to refer to a trusted environment and is not limited to specific security features. In some examples, the secure world execution environment of CPU 453 is also part of the trusted computing base of the system. For example, in some examples, the secure world execution environment of CPU 453 has free access to reprogrammed hardware protection mechanisms, and in some examples, the hardware protection mechanisms are such as firewalls. However, in some examples, the secure world execution environment of CPU 453 does not have access to the interior of the security complex of security complex 451, and relies on the security MCU of security complex 451 to perform specific security-sensitive operations.

[0051] The radio block 457 can provide Wi-Fi communications. The main AXI bus 463 and the auxiliary AXI bus 464 can be buses that connect the components shown. In some examples, bridges 465, 466, and 467 bridge the components shown. The RTC block 474 can operate as a real-time clock. In some examples, all components in the device controller 345 can be read from the RTC block 474, but not all components have write access to the RTC block 474. The device controller 445 may include various forms of memory, including flash memory and SRAM, such as flash memory 456 and secure SRAM 458.

[0052] In some examples, IO subsystem 1 461 and IO subsystem 2 462 are I / O subsystems for general I / O connectivity. In some examples, IO subsystem 1 461 and IO subsystem 2 462 each include an MCU.

[0053] DMA block 454 may be used to manage data movement for the normal world execution environment of CPU 453. Trust zone (TZ) DMA block 455 may be used to manage data movement for the secure world execution environment of CPU 453. In some examples, each IO subsystem also has its own DMA block. Each of the DMA blocks may be configured to support data movement between cores, peripherals, other components, etc.

[0054] Each core in the core can have a bidirectional mailbox to support inter-processor communication. Performance counters 475 can be configured to count read requests, write requests, and data type requests for performance monitoring. In some examples, performance counters 475 can also be configured to measure the latency from the core to the target (such as from MCU 462 to SRAM 458).

[0055] In some examples, the interface in block 459 includes two inter-IC sound (I2S) interfaces: one for audio input, and one for audio output. In other examples, other configurations of interfaces can be employed, and in various examples, block 459 can include any suitable interface.

[0056] In some examples, the MCU in security complex 451 has a very high level of trust, but is less trusted than the security complex in the form of security complex 451. In these examples, the MCU in security complex 451 controls one or more functions associated with the very high level of trust. In one example, the MCU in security complex 451 controls power to device controller 445 and / or IoT device.

[0057] In some examples, the secure world execution environment of CPU 453 is also part of the trusted computing base of the system. For example, in some examples, the secure world runtime (secure world RT) of CPU 453 has free access to reprogrammed hardware protection mechanisms, such as firewalls in some examples. However, in some examples, the secure world RT does not have access to the internals of the security complex of security complex 451 and relies on the MCU of security complex 451 to perform certain security-sensitive operations.

[0058] The normal world execution environment of CPU 453 can be configured to have limited access to such on-chip resources (such as memory). In some examples, various security and quality standards (e.g., relatively high standards) can be enforced for code running in this environment, but which is less trusted than code running on an MCU in security complex 451 or code running in the secure world of CPU 453.

[0059] In some examples, MCUs 461 and 462 are less trusted than the MCU and CPU 453 in security complex 451. In some examples, radio block 457 can include a core, which in some examples can be an MCU. Radio block 457 can provide Wi-Fi functionality and connectivity to the Internet and cloud services (such as IoT services). In some examples, radio block 457 can provide communication via Bluetooth, near field communication (NFC), ZigBee, long term evolution (LTE), and / or other connectivity technologies. In some examples, the core in radio block 457 does not have any access to unencrypted secrets and cannot compromise the execution of CPU 453.

[0060] In some examples, each independent execution environment is managed by a single software component that executes in a separate execution environment, which is referred to as the "parent" of the execution environment. In such examples, an exception may be that the hardware root of trust (in this example, the security complex of security complex 451) has no parent. In a specific example, each parent executes in an environment that is at least as trusted as the environment it manages. In other examples, other suitable security approaches may be adopted. Management operations may include: booting and continuing the target environment, monitoring and handling resets in the target environment, and configuring access policies for the target environment. In some cases, certain management operations are performed by components other than the parent. For example, in some examples, the normal world of CPU 453 is an environment that manages MCUs 461 and 462, but gets help from the secure world of CPU 453.

[0061] For example, in some examples, the MCU of security complex 451 manages the secure world RT of CPU 453, components in the secure world RT in CPU 453 manage the normal world OS of CPU 453, components in the normal world OS of CPU 453 manage the normal world user mode of CPU 453, and the normal world user mode services of CPU 453 manage MCUs 461 and 462 and the cores in radio block 457.

[0062] In some examples, not only are the independent execution environments managed by software components from a more trusted execution environment, but different independent execution environments are assigned different functions, with more sensitive functions being assigned to more trusted independent execution environments. In a specific example, an independent execution environment that is less trusted than the independent execution environment to which it is assigned is restricted from having access to a function. In this way, in some examples, the independent execution environments implement defense in depth based on a trust hierarchy.

[0063] For example, in some examples, the security complex for security complex 451 is at the top of the hierarchy and is assigned to secrets (e.g., encryption keys), the secure MCU in security complex 451 is next in the hierarchy and is assigned to control power, the secure world RT of CPU 453 is next in the hierarchy and is assigned to storage and write access to the real-time clock (RTC), the normal world OS of CPU 453 is next in the hierarchy and is assigned to Wi-Fi, the normal world user mode applications of CPU 453 is next in the hierarchy and is assigned to applications, and MCUs 461 and 462 are at the bottom of the hierarchy and are assigned to peripherals. In some examples where MCUs 461 and 462 are at the bottom of the hierarchy and are assigned to peripherals, MCUs 461 and 462 may be referred to as input / output (I / O) cores. In other examples, functionality is assigned to independent execution environments in different ways.

[0064] In some examples, each level of the trust hierarchy, except the bottom (i.e., least trusted) level of the hierarchy, controls acceptance or rejection of requests from less trusted levels, such as in terms of implementing support for the software they handle, and has the ability to rate limit or review requests from less trusted levels and verify requests from lower levels, such as to ensure that the requests are correct and authentic. Moreover, as previously discussed, in some examples, each level of the hierarchy, except the top (i.e., most trusted) level, has a parent that is responsible for managing the lower (i.e., less trusted) levels, including monitoring whether the software at the lower levels is running correctly.

[0065] In some examples, each layer of the hierarchy utilizes secure communication channels and firewalls. For example, in some examples, the secure MCU RT of CPU 453 has two message queues that are configured such that: based on hardware, one of the queues can only be used in SW, and one queue can be used by NW. In a specific example, if a message comes from the SW queue, based on hardware, the message must come from SW and, therefore, is more trusted than a message from NW. In other examples, other suitable security approaches may be employed.

[0066] Additionally, in some examples, except for the highest level of the hierarchy, no layer of the hierarchy is started without the higher levels of the hierarchy having verified the layer, but after verifying the layer, the layer is allowed to start. Moreover, in these examples, the layers of the hierarchy have the ability to, for example, stop any lower level of the hierarchy at any time. Therefore, in these examples, the device controller 445 makes the software capabilities of each layer of the hierarchy completely superior to the lower (i.e., less trusted) levels of the hierarchy in terms of stopping and starting the lower levels of the hierarchy and running these lower levels.

[0067] In some examples, the security complex of the security complex in the form of security complex 451 is the highest, most trusted level of the hardware root of trust and defense-in-depth trust hierarchy. In some examples, the security complex contains keys, secrets, cryptographic engines, etc. In some examples, the security complex stores secrets, performs functions such as key generation, encryption, decryption, hashing, other cryptographic functions, other security-related functions, etc. In some examples, the security complex is capable of checking secret values ​​stored in one-way writable memories (such as electrical fuses, one-time programmable elements, etc.).

[0068] In some examples, when the device controller 445 is powered on and its power management unit (PMU) has stable power, it releases the security complex so that it is free from reset. In some examples, the security complex is located at the core of the trusted computing base of the device controller 445. In some examples, the security complex drives the secure boot process. In a particular example, the core is restricted from executing code until the security complex has enabled it to do so. In other examples, other suitable security approaches may be employed.

[0069] Some examples of device controller 445 may be a multi-core microprocessor that includes, for example, at least one CPU and at least one microcontroller in addition to a flash memory having multiple memory banks as previously discussed. In some examples, the multi-core processor may be an integrated circuit having multiple cores. In some examples, the multi-core processor may be used to provide functionality for connected devices. In some examples, device controller 445 may provide network connectivity to connected devices, and may also provide various other functions, such as hardware and software security, monitored operating systems, cryptographic functions, peripheral control, telemetry, and the like. Additionally, device controller 445 may include technology for allowing device controller 445 to be booted in a secure manner, allowing devices to be securely updated, ensuring that “proper” software is running on the device, allowing the device to be properly used as an IoT device, and the like. Security complex 451 may include a hardware root of trust for device controller 445 as the basis for security functions provided by device controller 445.

[0070] In some examples, the flash memory 456 is an external NOR flash memory including a flash controller and a parallel dual quad serial common interface (QSPI) NOR flash device (in this example, two memory banks), where each flash memory bank is a separate integrated circuit accessed via a separate channel. However, the present disclosure is not limited thereto, and any suitable memory configuration and / or suitable memory collection may be employed.

[0071] In some examples, two or more of the independent execution environments in the device controller 445 each have their own watchdog timer. For example, in some examples, the device controller 445 has three watchdog timers—one for the security complex, one for the CPU 453, and one for the I / O core. The I / O core may have a separate timer, or may alternatively have one timer for each core, where each timer for the I / O core is at the same trust level. In this example, there are three trust levels, each with its own watchdog timer—one trust level is the security complex, another trust level is the CPU 453, and another trust level is the I / O core.

[0072] In other examples, more or less than three trust levels may have watchdog timers. For example, in some examples, rather than treating CPU 453 as one trust level for the purpose of a watchdog timer, in some examples the SW world of CPU 453 and the NW world of CPU 453 are each treated as a separate trust layer, such that the SW world of CPU 453 and the NW world of CPU 453 each have their own watchdog timer.

[0073] exist Figure 4 In the specific example illustrated in , there are watchdog timers for three trust levels: watchdog timer 431 is a watchdog timer for the SC of security complex 451 (highest trust level); watchdog timer 432 is a watchdog timer for CPU 453 (second highest trust level); and watchdog timer 433 is a watchdog timer for MCU 461 and MCU 462 (lowest trust level).

[0074] In some examples, each watchdog timer is periodically reset by its corresponding trust level. Resetting the watchdog timer is often referred to as "tapping" the watchdog. During normal functionality, in some examples, the watchdog timer continues to be periodically reset by the corresponding level before the watchdog timer expires. For example, an example watchdog timer may expire within 1 millisecond (ms) since it was last reset.

[0075] In some examples, the watchdog timer is reset by software at a corresponding trust level that writes a predetermined memory map at an address. In some examples, a specific write sequence or a specific data value is required to enable the write to take effect to reset the timer. This can prevent rogue software from resetting the watchdog or an accidental reset of the watchdog.

[0076] In some examples, if one of the watchdog timers (e.g., watchdog timer 431, 432, or 433) has expired, this means that a problem has occurred, such as a program error, which prevents the software from running properly. For example, the software may be stuck in a loop.

[0077] In some examples, when a watchdog timer at the highest trust level (e.g., watchdog timer 431) times out, the watchdog timer at the highest trust level resets the entire integrated circuit 445. However, in other examples, when the watchdog timer is at the highest trust level, a portion of the integrated circuit may be reset instead. For example, the watchdog timer may be configured to reset a portion of the integrated circuit so that other portions of the integrated circuit may complete one or more operations "gracefully."

[0078] In some examples, when a watchdog timer at a layer different from the highest trust level passes time, such as when watchdog timer 432 or watchdog timer 433 passes time, the watchdog timer that passes time sends an interrupt to a higher trust level in the hierarchy. For example, if watchdog timer 432 is reset, watchdog timer 432 can send an interrupt to SC. If watchdog timer 433 is reset, watchdog timer 433 can send an interrupt to CPU 453, SC, or to both CPU 453 and SC. The watchdog timer may also reset the current trust level. For example, if watchdog timer 432 passes time, watchdog timer 432 can reset CPU 453. If watchdog timer 433 passes time, watchdog timer 433 can reset I / O cores 461 and 462.

[0079] In some examples, when a watchdog timer at a trust level different from the highest trust level expires, the trust level associated with the watchdog timer is reset, while other trust levels continue to operate. When a trust level reset by a watchdog timer is restarted, the trust level can evaluate the lower trust levels (multiple) and determine whether to restart those levels.

[0080] Additionally, a watchdog timer at a layer different from the highest trust level may also cause an I / O pin of an associated circuit system to enter a predefined default state during a reset or a period associated with a reset. For example, such a watchdog timer may cause one or more I / O pins of an associated circuit to be set to a high impedance pin during a reset by itself or in combination with software and / or additional hardware.

[0081] The higher trust level of the receiving interrupt can respond accordingly, including: logging and / or tracing the event, determining when and how the level sending the interrupt should be released, etc.

[0082] In some examples, each watchdog timer is a hardware watchdog timer with hardware wiring to cause a corresponding reset and interrupt.

[0083] In various examples, many suitable variations can also be employed. For example, in some examples, each trust level can include a multi-stage watchdog in which, for example, an interrupt and / or reset does not occur until the last stage expires, where other corrective actions and / or warnings occur when an earlier stage expires.

[0084] Moreover, in some examples, multiple watchdog timers may be included at a particular trust level. For example, instead of having one watchdog timer at the level of an I / O core (such as at Figure 4 ), but in some examples, each I / O core can have a separate watchdog timer, where each watchdog timer is reset by its corresponding core, and if the watchdog timer expires, an interrupt is sent to a higher trust level, and if the watchdog timer expires, its corresponding I / O core can be reset.

[0085] Illustrative Process

[0086] For the sake of clarity, the processes described herein are described according to the operations performed in a specific order by a specific device or component of the system. However, it should be noted that other processes are not limited to the stated order, device or component. For example, certain actions can be performed in different orders, performed in parallel, omitted, or supplemented by other actions or features, whether or not such order, parallelism, actions or features are described herein. Similarly, any technology described in this disclosure can be incorporated into the described process or other processes, whether or not the technology is specifically described in conjunction with the process. The disclosed process can also be performed on other devices, components or systems or the disclosed process can be performed by other devices, components or systems, whether or not such devices, components or systems are described herein. These processes can also be implemented in various ways. For example, these processes can be implemented on an article, such as as a processor-readable instruction stored in a processor-readable storage medium, or as a computer-implemented process. As an alternative example, these processes can be encoded as processor-executable instructions and sent via a communication medium.

[0087] FIG. 5A to FIG. 5B An example data flow of process (580) is shown. In some examples, process 580 is performed by a device controller (e.g. Figure 4 In other examples, process 580 may be performed in other suitable devices. For simplicity, Figure 5A and Figure 5B The diagram example in illustrates the steps in a synchronous linear fashion.

[0088] In the illustrated example, step 581 occurs first. In step 581, in some examples, a first watchdog timer is caused to be reset periodically via a first independent execution environment in a set of independent execution environments in the integrated circuit. In some examples, the set of independent execution environments is configured to have a defense-in-depth hierarchy. In some examples, the set of independent execution environments includes a first independent execution environment and a second independent execution environment. In some examples, the first independent execution environment is the most trusted execution environment on the integrated circuit.

[0089] As shown, in some examples, step 582 occurs next. In step 582, in some examples, via the second independent execution environment: the second watchdog timer is caused to reset periodically. As shown, in some examples, decision step 583 occurs next. In decision step 583, in some examples, it is determined whether the second watchdog timer has timed out. If not, in some examples, the process proceeds to step 585. However, if in step 583, it is determined that the second watchdog timer has timed out, the process continues to step 584, in which, in some examples, an interrupt is transmitted from the second watchdog timer to the first independent execution environment.

[0090] As shown, in some examples, a decision step 585 occurs next. In decision step 585, in some examples, it is determined whether the first watchdog timer has expired. If not, the process can then continue to a return frame, in which other processing is continued.

[0091] If, instead, in decision step 585, it is determined that the first watchdog timer has expired, then in some examples, step 586 occurs next. In step 586, in some examples, at least a portion of the integrated circuit is reset. The process can then continue to the return block.

[0092] in conclusion

[0093] Although the above-mentioned specific embodiments describe certain examples of the technology of this article, and describe the expected best mode, no matter how detailed the above content is in the text, the technology of this article can be practiced in many ways. The details may change in the implementation, but are still covered by the technology described in this article. As mentioned above, the specific terms used when describing certain features or aspects of the technology of this article should not be considered to imply that the term is redefined in this article to be limited to any specific characteristics, features or aspects associated with the term. Generally, the terms used in the following claims should not be interpreted as limiting the technology of this article to the specific examples disclosed herein, unless the specific embodiments clearly define such terms. Therefore, the actual scope of the technology of this article not only covers the disclosed examples, but also covers all equivalent ways of practicing or realizing the technology of this article.

Claims

1. A device for managing a program, comprising: A device comprising at least one memory adapted to store runtime data for the device and at least one processor adapted to execute processor executable code, the processor executable code enabling the device to perform actions in response to being executed, the device comprising: Integrated circuits, including: a set of independent execution environments configured to have a defense-in-depth hierarchy, wherein the set of independent execution environments includes a first independent execution environment and a second independent execution environment, and wherein the first independent execution environment is a most trusted execution environment on the integrated circuit; a first watchdog timer, wherein the first independent execution environment is configured to cause the first watchdog timer to be reset periodically, and wherein the first watchdog timer is configured to cause at least a portion of the integrated circuit to be reset in response to the first watchdog timeout; and a second watchdog timer, wherein the second independent execution environment is configured to cause the second watchdog timer to be reset periodically, wherein the second watchdog timer is configured to send an interrupt to the first independent execution environment in response to the second watchdog timer timing out, and wherein the second watchdog timer is further configured to reset the second independent execution environment in response to the second watchdog timer timing out.

2. The apparatus of claim 1 , wherein the set of independent execution environments further comprises a third independent execution environment that is less trusted than the second independent execution environment, the integrated circuit further comprises a third watchdog timer, the third independent execution environment being configured to cause the third watchdog timer to be reset periodically, and wherein the third watchdog timer is configured to send an interrupt to at least one of the first independent execution environment or the second independent execution environment in response to a timeout of the third watchdog timer.

3. The apparatus according to claim 2, wherein at least two independent execution environments in the set of independent execution environments run on general-purpose cores having different capabilities from each other, and wherein the general-purpose cores having different capabilities from each other include at least a first microcontroller and a first central processing unit (CPU).

4. The apparatus of claim 3, wherein the set of independent execution environments further comprises a secure world runtime on the first CPU and a normal world operating system on the first CPU. 5 . The apparatus of claim 1 , wherein the first independent execution environment comprises a security complex configured as a hardware root of trust for the integrated circuit.

6. The apparatus of claim 5 , wherein the set of independent execution environments further comprises a third independent execution environment that is less trusted than the second independent execution environment, the integrated circuit further comprises a third watchdog timer, the third independent execution environment being configured to cause the third watchdog timer to be reset periodically, and wherein the third watchdog timer is configured to send an interrupt to at least one of the first independent execution environment or the second independent execution environment in response to a timeout of the third watchdog timer. 7 . The apparatus of claim 6 , wherein the second independent execution environment comprises a first core, the third independent execution environment comprises a second core, and wherein the second core is configured as an input / output core.

8. The apparatus of claim 6, wherein the second independent execution environment comprises a secure world runtime on a first core, and wherein the third independent execution environment comprises a normal world operating system on the first core.

9. A method for managing a program, comprising: causing, via a first independent execution environment of a set of independent execution environments in an integrated circuit, wherein the set of independent execution environments is configured to have a defense-in-depth hierarchy, the set of independent execution environments including a first independent execution environment and a second independent execution environment, and wherein the first independent execution environment is a most trusted execution environment on the integrated circuit: causing a first watchdog timer to be reset periodically; Via the second independent execution environment: periodically resetting the second watchdog timer; in response to a timeout of the second watchdog timer, transmitting an interrupt from the second watchdog timer to the first independent execution environment; responsive to the first watchdog timer timing out, resetting at least a portion of the integrated circuit; and In response to the second watchdog timer timing out, resetting the second independent execution environment.

10. The method of claim 9, wherein the first independent execution environment comprises a security complex configured as a hardware root of trust for the integrated circuit.

11. The method of claim 10, wherein the set of independent execution environments further comprises a third independent execution environment that is less trusted than the second independent execution environment, and wherein the integrated circuit further comprises a third watchdog timer, the third independent execution environment being configured to cause the third watchdog timer to be reset periodically, the method further comprising sending an interrupt to at least one of the first independent execution environment or the second independent execution environment via the third watchdog timer in response to a timeout of the third watchdog timer.

12. The method of claim 9 , wherein the set of independent execution environments further comprises a third independent execution environment that is less trusted than the second independent execution environment, and wherein the integrated circuit further comprises a third watchdog timer, the third independent execution environment being configured to periodically reset the third watchdog timer, the method further comprising sending an interrupt to at least one of the first independent execution environment or the second independent execution environment via the third watchdog timer in response to a timeout of the third watchdog timer.

13. The method according to claim 12, wherein at least two independent execution environments in the set of independent execution environments run on general cores with different capabilities from each other, and wherein the general cores with different capabilities from each other include at least a first microcontroller and a first central processing unit (CPU).

14. The method of claim 13, wherein the set of independent execution environments further comprises a secure world runtime on the first CPU and a normal world operating system on the first CPU.

15. A method for managing a program, comprising: configuring the watchdog timer to send an interrupt to a first independent execution environment of a set of independent execution environments on the integrated circuit in response to a timeout of the first watchdog timer, wherein the set of independent execution environments also includes a second independent execution environment, and wherein the first independent execution environment is a most trusted execution environment on the integrated circuit; configuring another watchdog timer to reset at least a portion of the integrated circuit in response to a timeout of the another watchdog timer; configuring the watchdog timer to be reset periodically by the second independent execution environment; and The watchdog timer is configured to reset the second independent execution environment in response to the watchdog timer timing out.

16. The method of claim 15, wherein the first independent execution environment comprises a security complex, and wherein the second independent execution environment comprises a first core.

17. The method of claim 15, wherein the second independent execution environment comprises a secure world runtime on the first core.

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