Method for fabricating nonpolar and semipolar devices using epitaxial lateral overgrowth

Abstract

A method for manufacturing a semiconductor device, comprising: forming a growth restriction mask on or above a III-nitride substrate, and growing one or more island-shaped III-nitride semiconductor layers on the III-nitride substrate using the growth restriction mask. The III-nitride substrate has an in-plane distribution of off-axis orientation greater than 0.1 degrees; and the off-axis orientation of the crystal surface plane of the m-plane orientation is about +28 degrees to about ‑47 degrees toward the c-plane. The island-shaped III-nitride semiconductor layer has at least one long side and a short side, wherein the long side is perpendicular to the a-axis of the island-shaped III-nitride semiconductor layer. The island-shaped III-nitride semiconductor layer does not agglomerate with adjacent island-shaped III-nitride semiconductor layers.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit under 35 U.S.C. Section 119(e) of U.S. Provisional Patent Application Serial No. 62 / 650,487, filed on March 30, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, and entitled “METHOD OF FABRICATING NON-POLAR AND SEMI-POLAR DEVICES BY USING LATERAL OVERGROWTH,” co-pending and commonly assigned attorney docket No. G&C30794.0680USP1 (UC 2018-427-1), which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a method for manufacturing non-polar and semi-polar devices using epitaxial lateral overgrowth. Background Art

[0004] Some device manufacturers have used non-polar and semi-polar GaN substrates to produce laser diodes (LDs) and light-emitting diodes (LEDs) for lighting, optical storage, etc. Non-polar and semi-polar GaN substrates are used to avoid large thermal and piezoelectric fields, which can significantly improve emission efficiency. However, epitaxial growth of III-nitrides along non-polar and semi-polar directions is more difficult than growth along the polar c-plane direction.

[0005] According to US20170092810A1, after epitaxial growth, many pyramidal hillocks were observed on the surface of the non-polar m-plane III-nitride film. In addition, a wavy surface appeared, which deteriorated the surface roughness. This is a very serious problem when manufacturing laser structures on the surface, because the surface roughness may cause fluctuations in the uniformity of optical gain and device processes. This may also reduce the yield of the device process. In addition, the reliability of the laser is affected by hillocks and large surface roughness. See, for example, Applied Physics Letters 91, 191906 (2007).

[0006] According to the article, the growth conditions for obtaining a smooth surface are very narrow and have strict restrictions. One problem is that the surface morphology is affected by the off-axis orientation, and it is well known that GaN wafers have a large in-plane distribution with respect to the off-axis orientation. Therefore, the surface morphology within the wafer changes greatly. In this case, the yield is low, which is a big problem. See, for example, Physica Status Solidi (a), Volume 214, Issue 8, 1600829 (2047).

[0007] Furthermore, according to the article, the dependence of the hillock facets on the leakage current under reverse bias conditions was observed. They showed that the leakage current distribution is caused by the dependence of the hillock facets on the carrier concentration and the oxygen concentration. The leakage current distribution is a problem when manufacturing devices such as LEDs, LDs, power devices such as Schottky barrier diodes (SBDs), or metal oxide semiconductor field effect transistors (MOSFETs).

[0008] Another problem is that the use of non-polar and semi-polar III-nitride substrates to grow an epi layer on a growth limit mask results in the epi layer agglomerating in the center of the opening area in the mask. In this case, the island III-nitride layer has a concave area or depression near the center of the epi layer. Under different growth conditions, there are cases where the island III-nitride layer has a convex area or protrusion near the center of the epi layer. Both of these situations are problematic when trying to obtain a flat surface for the epi layer.

[0009] Therefore, there is a need in the art for improved methods of planarizing epitaxial layers on non-polar and semi-polar substrates using epitaxial lateral overgrowth (ELO). The present invention satisfies this need. Summary of the invention

[0010] In order to overcome the limitations in the prior art described above and to overcome other limitations that will become apparent upon reading and understanding this specification, the present invention discloses a method for manufacturing a semiconductor device, comprising: forming a growth restriction mask on or above a III-nitride substrate, wherein: the III-nitride substrate has an in-plane distribution of off-axis orientation greater than 0.1 degrees; the off-axis orientation of the crystal surface plane of the m-plane orientation is about +28 degrees to about -47 degrees toward the c-plane; and growing one or more island-shaped III-nitride semiconductor layers on the III-nitride substrate using the growth restriction mask. The island-shaped III-nitride semiconductor layers are then removed from the III-nitride substrate.

[0011] The obtained island-shaped III-nitride semiconductor layer has an on-axis orientation and an off-axis orientation of a crystal surface plane oriented in an m-plane, wherein: the off-axis orientation of the crystal surface plane oriented in the m-plane is about +28 degrees to about -47 degrees toward the c-plane; the island-shaped III-nitride semiconductor layer has at least one long side and a short side, wherein the long side is perpendicular to the a-axis of the island-shaped III-nitride semiconductor layer; and the island-shaped III-nitride semiconductor layer does not aggregate with adjacent island-shaped III-nitride semiconductor layers.

[0012] The island III-nitride semiconductor layer has an emission region, wherein the emission region is at least 1 μm away from the edge of the layer bending region of the island III-nitride semiconductor layer. The emission region is greater than 5 μm away from the edge of the top surface of the island III-nitride semiconductor layer.

[0013] The island-shaped Group III nitride semiconductor layer has an edge growth region with a height less than 0.2 μm, wherein a width of the edge growth region is less than 5 μm.

[0014] The island-shaped Group III nitride semiconductor layer also has a separate region where an n-electrode is formed.

[0015] The present invention also discloses a method for growing a flat III-nitride epi layer on a semi-polar and non-polar III-nitride substrate using ELO, thereby reducing or eliminating pyramidal hillocks, wavy surfaces, and concave-convex areas.

[0016] On the one hand, it has been recognized that the edge of the substrate causes the surface roughness to deteriorate. Therefore, it is necessary to isolate the growth region (such as the opening region in the growth restriction mask) from the edge of the substrate. In the present invention, the growth region is isolated by the growth restriction mask.

[0017] Furthermore, the substrate may have pits and defects on its surface, which lead to a rough surface after epitaxial growth using metal organic chemical vapor deposition (MOCVD). This has been known for some time. One pit may affect the surface roughness of a large area. However, separating each growth area prevents the surface roughness from becoming worse in adjacent areas. In semi-polar and non-polar epitaxial growth, it is important to isolate the growth area from the edge of the substrate and not affect a large area.

[0018] In other words, the growth region is surrounded by a growth restriction mask, which isolates the growth region. For example, the growth restriction mask can be a dielectric film or a metal, such as SiO 2 、SiN、HfO 2 、Al 2 O 3 , MgF, W, Mo, etc. In addition, the growth limit mask may use a multilayer selected from these materials.

[0019] The group III nitride layer grown using the ELO method is referred to as an ELO group III nitride layer. When the ELO group III nitride layer is grown using MOCVD or HVPE, the carrier gas flow contains hydrogen.

[0020] If the ELO III-nitride layers coalesce with each other, it causes fluctuations in surface roughness. In addition, the coalesced areas cause many stacking failures and misfit dislocations.

[0021] Therefore, in the present invention, the growth of the ELO III-nitride layer is stopped before the adjacent island layers coalesce with each other. Then, the flat area of ​​the ELO III-nitride layer is substantially free of hillocks. Thereafter, a III-nitride semiconductor device layer is grown on the ELO III-nitride layer, and the III-nitride semiconductor device layer is removed from the III-nitride substrate. They are separated from each other because the MOCVD growth is stopped before they coalesce. The method obtains a flat surface layer and a device layer with a high yield.

[0022] The present invention can use a III-nitride substrate or a foreign substrate. More preferably, the present invention uses a III-nitride substrate to obtain a high-quality III-nitride-based semiconductor layer and avoid bending or curvature of the substrate during epitaxial growth. The present invention also obtains a low defect density device.

[0023] As long as the III-nitride-based semiconductor layer can be grown through a growth confinement mask, any III-nitride-based substrate or foreign substrate, such as sapphire, SiC, LiAlO 2 , Si, etc.

[0024] In addition, the III-nitride-based semiconductor layer and the III-nitride-based substrate may further include Al, In, and B, as well as other impurities such as Mg, Si, O, C, H, and the like.

[0025] The ELO III-nitride layer is epitaxially grown on the III-nitride substrate at the opening region and / or through an intermediate layer at the opening region. The quality of the ELO III-nitride layer and the III-nitride semiconductor device layer is very high, and the device composed of the island-shaped III-nitride-based semiconductor layer has a very high quality. In addition, the island-shaped III-nitride semiconductor layer has a flat surface morphology without hillocks, which usually appear on the surface of the epitaxial layer after growing the epitaxial layer on non-polar and semi-polar substrates.

[0026] In MOCVD or HVPE, it is best to use a carrier gas containing hydrogen. Hydrogen plays a key role in the early stages of growth. According to the prior art, it has been shown that hydrogen carrier gas deteriorates the surface morphology during the growth of GaN layers using MOCVD. However, the situation changes when the growth area is surrounded by a growth restriction mask.

[0027] The carrier gas containing hydrogen effectively etches the edge side of the epi layer in the opening area. This effect prevents the epi layer from starting to grow on both sides of the opening area.

[0028] If the carrier gas does not contain hydrogen, there will be many cores of the epi layer on both sides of the open area. With further growth, the cores of the epi layer will coalesce in the center or near the open area. Therefore, the ELO III-nitride layer has a depressed area. This growth has occurred on various non-polar and semi-polar planes.

[0029] On the other hand, a carrier gas including hydrogen can be used, where the core of the epitaxial layer is formed at or near the center of the opening region in the early stage of growth. In this case, the ELO III-nitride layer does not have any depressed areas or pyramidal hillocks, and a very flat and smooth surface roughness can be obtained.

[0030] For the reasons stated above, when growing an ELO Group III nitride layer, it is preferred to use a carrier gas containing hydrogen at least at the beginning of the growth. In addition, the carrier gas may be hydrogen alone or a mixture of hydrogen and nitrogen.

[0031] In the present invention, the island layer can also be removed from the substrate. Homoepitaxial layers are difficult to remove from the substrate because there is no heterogeneous interface between the homoepitaxial layer and the substrate surface. However, using the present invention, homoepitaxial island layers can be removed from the substrate in a fast and easy manner.

[0032] For example, the method of removing the substrate may use a growth limiting mask, which may be a dielectric film or a metal such as SiO 2 、SiN、HfO 2 、Al 2 O 3 , MgF, etc. The interface between the growth restriction mask and any subsequent III-nitride layer grown by ELO on the mask has a weaker bonding strength. The bonding area (opening area width) is controlled to be larger or smaller than the chip size. In addition, the ELO method provides a split point and a split interface. Therefore, it is easy to peel off the homoepitaxial layer from the substrate.

[0033] In addition, these methods use cleavage with the m-plane. The m-plane is the easiest plane to cleave among the GaN planes. The method can also easily determine the cleavage point. For example, the cleavage point can be the edge of the growth limit mask. An improvement is to dissolve the mask using hydrofluoric acid (HF), buffered HF (BHF) or another etchant before removing the substrate.

[0034] Afterwards, the wafer is bonded to a support substrate using a low temperature molten metal and / or solder, where the metal is dissolved by the etchant. The bonding portion is the III-nitride layer on the III-nitride substrate. A support substrate having a different thermal expansion than the III-nitride substrate can be used. The two substrates are heated or cooled after bonding. Due to the difference in thermal expansion, stress is applied to the III-nitride layer bonded to the support substrate. The stress is applied to the portion of the III-nitride layer between the III-nitride layer and the substrate. The splitting starts from the splitting point which is the edge of the growth limiting mask. Finally, the splitting reaches the opposite side of the splitting point. However, a trigger is required to start the splitting.

[0035] As in the above case, stress from thermal expansion differences can be used to trigger the splitting. However, it may not be necessary to use such stress. For example, ultrasound or the like can be used to trigger the splitting. If mechanical removal (e.g., ultrasonic splitting) can be used, the substrate can be removed quickly and the stress is very weak due to the splitting of the m-plane. In addition, the splitting point is wedge-shaped, which makes it easy to determine the splitting point. Moreover, the shape of the splitting point is important for achieving high yields.

[0036] Using these methods, device layers can be easily removed from Group III-nitride based substrates and wafers, including large size wafers, eg, over 2 inches.

[0037] In addition, the island-shaped Group III nitride-based semiconductor layers do not coalesce with each other, and the internal strain is released, which prevents the occurrence of any cracks.

[0038] As a main object of the present invention, even if a III-nitride based substrate or a foreign substrate has a large in-plane distribution of off-axis orientations, a smooth surface with a large area without hillocks or wavy roughness can be obtained.

[0039] In the present invention, it is not necessary to remove the island-shaped group III nitride layer from the substrate. If the island-shaped group III nitride layer is removed from the substrate, the above method can be used. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Referring now to the drawings, wherein like reference numerals designate corresponding parts throughout:

[0041] Figure 1 is a schematic diagram of a structure according to an embodiment of the present invention, the structure including a substrate with various layers deposited thereon.

[0042] Figure 2 (a), 2(b), 2(c), 2(d), 2(e), and 2(f) are schematic diagrams illustrating the fabrication of a structure according to an embodiment of the present invention.

[0043] Figure 3(a) and 3(b)is a schematic diagram illustrating growth of a semiconductor layer on a growth limit mask according to an embodiment of the present invention.

[0044] Figure 4(a) and 4(b) is a schematic diagram illustrating a growth restriction mask according to an embodiment of the present invention.

[0045] Figure 5 are photographs showing experimental results according to an embodiment of the present invention.

[0046] Figure 6(a) , 6(b) , 6(c), 6(d), 6(e), 6(f), 6(g), 6(h) and 6(i) are photographs showing experimental results according to an embodiment of the present invention.

[0047] Figure 7(a) , 7(b) 7( c ) are schematic diagrams illustrating a growth limit mask according to an embodiment of the present invention.

[0048] Figure 8(a) and 8(b) is a schematic diagram showing a device structure and its manufacturing according to an embodiment of the present invention.

[0049] Fig. 9 9(a) and 9(b) are schematic diagrams showing a structure removal process according to an embodiment of the present invention. Fig. 9 (c) is a photograph of the removed structure.

[0050] Figure 10(a) , 10(b) , 10(c) and 10(d) are photographs showing experimental results according to an embodiment of the present invention.

[0051] Figure 11(a) and 11(b) is a schematic diagram showing crystal orientation according to an embodiment of the present invention.

[0052] Fig.12 is a schematic diagram showing a device structure according to an embodiment of the present invention.

[0053] Fig.13 is a series of photographs showing experimental results according to the present invention.

[0054] Figure 14(a) and 14(b) are schematic diagrams and photographs showing experimental results according to the present invention.

[0055] Fig.15 (a) and 15(b) are schematic diagrams showing semiconductor growth structures according to embodiments of the present invention, Fig.15 (c) Yes Fig.15 (b) Photograph of the structure.

[0056] Fig.16 are schematic diagrams and photographs showing experimental results according to an embodiment of the present invention.

[0057] Fig.17 (a), 17(b) and 17(c) are schematic diagrams showing the growth of a semiconductor layer on a growth limit mask according to an embodiment of the present invention. DETAILED DESCRIPTION

[0058] In the following description of the preferred embodiments, reference is made to specific embodiments in which the invention may be practiced. It should be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.

[0059] Overview

[0060] The present invention describes a method of manufacturing a semiconductor device, comprising: obtaining a smooth and flat surface for an epitaxial III-nitride layer grown on a non-polar or semi-polar III-nitride substrate, and then manufacturing a semiconductor device on the surface.

[0061] In one embodiment, the method comprises the following steps:

[0062] A growth restriction mask having a plurality of stripe-shaped opening regions is formed directly or indirectly on a substrate, which may be a III-nitride substrate or a foreign substrate, wherein:

[0063] o the substrate has an in-plane distribution of off-axis orientations greater than 0.1 degrees; the off-axis orientations of the m-plane oriented crystallographic surface planes are from about +28 degrees to about -47 degrees toward the c-plane; and

[0064] ο the opening area has a long side and a short side, and the long side is perpendicular to the a-axis direction;

[0065] Growing one or more island-shaped III-nitride semiconductor layers on a substrate using a growth restriction mask, wherein:

[0066] o growing an island-shaped Group III nitride-based semiconductor layer in a hydrogen atmosphere; and

[0067] o growth extends in a direction parallel to the stripe-shaped opening region of the growth limit mask, wherein the island-shaped Group III nitride-based semiconductor layer is not aggregated; and

[0068] Removing the island-shaped Group III nitride semiconductor layer from the Group III nitride substrate.

[0069] The resulting island-like III-nitride semiconductor layer has an on-axis orientation and an off-axis orientation of a crystal surface plane oriented in an m-plane, wherein: the off-axis orientation of the crystal surface plane oriented in the m-plane is from about +28 degrees to about -47 degrees toward the c-plane; the island-like III-nitride semiconductor layer has at least one long side and a short side, wherein the long side is perpendicular to the a-axis of the island-like III-nitride semiconductor layer; and the island-like III-nitride semiconductor layer does not aggregate with adjacent island-like III-nitride semiconductor layers.

[0070] The island III-nitride semiconductor layer has an emission region at least 1 μm away from an edge of a layer bending region of the island III-nitride semiconductor layer and greater than 5 μm away from an edge of a top surface of the island III-nitride semiconductor layer.

[0071] The island-shaped Group III nitride semiconductor layer has an edge growth region having a height of less than 0.2 μm and a width of less than 5 μm.

[0072] The island-shaped Group III nitride semiconductor layer also has a separate region where an n-electrode is formed.

[0073] Finally, devices fabricated using the island-shaped III-nitride semiconductor layer may include a light emitting diode (LED), a laser diode (LD), a Schottky barrier diode (SBD), or a metal oxide semiconductor field effect transistor (MOSFET), which are processed on a flat surface area and / or an opening area.

[0074] Semiconductor structure and manufacturing method

[0075] Figure 1 1 is a schematic diagram showing a semiconductor structure according to an embodiment of the present invention, wherein the structure includes a substrate 101, a growth limiting mask 102, an opening region 103, a non-growth region 104, an ELO III-nitride layer 105, a III-nitride semiconductor device layer 106, a flat surface region 107, a layer bending region 108, and an island-shaped III-nitride semiconductor layer 109 (which is formed on the flat surface region 107 and the layer bending region 108) that may include a light emitting region 110.

[0076] The method for manufacturing a semiconductor structure comprises the following steps:

[0077] 1. ELO + Group III nitride semiconductor layer.

[0078] like Figure 2 As shown in (a), the III-nitride layer 105 (e.g., GaN layer) is formed by ELO on a SiO 2 The growth restriction mask 102 is patterned on the substrate 101 .

[0079] Substrate 101 may include, for example, a GaN substrate, an AlN substrate, an m-plane sapphire substrate, etc. In one embodiment, a GaN substrate 101 is used, whose growth surface is an m-plane with an off-axis orientation of -47 to +47 degrees toward the c-plane (0001).

[0080] The growth restriction mask 102 is patterned with SiO 2 The width is 20 μm and the spacing is 150 μm, where the SiO growth restriction mask 102 2 Along the <0001> The ELO III-nitride layer 105 does not aggregate on the SiO2 of the growth restriction mask 102. 2 Then, an epi layer including a III-nitride semiconductor device layer 106 is grown, which has a flat surface region 107 and a layer bending region 108, thereby obtaining an island-shaped III-nitride semiconductor layer 109, which may include a GaN layer, an AlGaN layer, an AlInGaN layer, etc.

[0081] A ridge process may then be performed on the island-shaped Group III nitride semiconductor layer 109 on the flat surface region 107 to form an LD device. Alternatively, an LED device or other devices may be manufactured.

[0082] 2. Dissolve the growth limiting mask by wet etching.

[0083] like Figure 2 As shown in (b), the SiO of the growth restriction mask 102 2 The epi layer is dissolved using a chemical solution such as hydrogen fluoride (HF), buffered HF (BHF), etc., or is otherwise removed. This makes it easier to split the device from the GaN substrate 101. It is best to perform this process before removing the epi layer from the substrate 101.

[0084] 3. TCO p-pad deposition + ridge process.

[0085] like Figure 2 As shown in (c), for ZrO 2 Layer 201 is patterned and a top side p-contact 202 such as a TCO (transparent conductive oxide) is deposited on the device, followed by a p-pad 203. Additionally, p-AlGaN capping layers and electrodes may be used, but the invention is not limited to these structures.

[0086] 4. Combine with supporting substrate.

[0087] like Figure 2 As shown in (d), the device is flip-chip bonded to a carrier wafer (Si, Cu, Cu-W, etc.) as a supporting substrate 204 using metal-metal bonding or soldering technology.

[0088] 5. Heat the supporting substrate.

[0089] like Figure 2 As shown in (e), the support substrate 204 is heated to remove the device from the substrate 101 at the cleavage point 205 and across the cleavage surface 206. Alternatively, the support substrate 204 may be cooled to achieve this function.

[0090] 6. N-electrode deposition.

[0091] like Figure 2 As shown in (f), a back side n-contact 207 such as TCO, Ti / Al, Ti / Au, Hf / Al / Mo / Au, etc. is deposited on the device. However, the n-contact 207 is not limited to these materials.

[0092] 6. Chip scribing.

[0093] like Figure 3(a)-3(b) As shown, chip scribing can be performed to separate devices, wherein FIG3(a) shows a top view of a flat surface region 107, a layer bending region 108, and an island-shaped III-nitride-based semiconductor layer 109 separated by a no-growth region 104, and FIG3(b) is an enlarged portion of FIG3(a), showing additional features of the LD device, including a ridge structure 301, an etched mirror region 302, and a chip scribing line 303.

[0094] Definition of terms

[0095] III-nitride based substrates

[0096] Any III-nitride-based substrate 101 sliced ​​on a {1-100}, {20-21}, {20-2-1}, {10-11}, {10-1-1} plane, etc., or other planes such as from bulk GaN or AlN crystals may be used as long as the III-nitride-based substrate 101 is capable of growing a III-nitride-based semiconductor layer through a growth confinement mask 102. The off-axis orientation of the bulk GaN substrate is from 0 to +47 degrees from the m-plane toward the c-plane.

[0097] The III-nitride based substrate 101 and bulk GaN may include Al, In, B, and the like.

[0098] III-nitride based semiconductor layers

[0099] The III-nitride-based semiconductor layers include an ELO III-nitride layer 105, a III-nitride semiconductor device layer 106, and an island III-nitride-based semiconductor layer 109. These III-nitride-based semiconductor layers may include In, Al, and / or B as well as other impurities, such as Mg, Si, Zn, O, C, H, and the like.

[0100] The ELO Group III-nitride layer 105 typically comprises a GaN layer, although other Group III-nitride layers may be used.

[0101] The III-nitride semiconductor device layer 106 generally includes two or more layers, including at least one of an n-type layer, an undoped layer, and a p-type layer. The III-nitride semiconductor device layer 106 may include one or more GaN layers, AlGaN layers, InGaN layers, AlGaInN layers, etc.

[0102] The island-shaped III-nitride-based semiconductor layer 109 is typically formed with sides along the (1-10a) plane (where a is an arbitrary integer), the (11-2b) plane (where b is an arbitrary integer), or planes crystallographically equivalent to these, or the sides of the island-shaped III-nitride semiconductor layer 109 include the (1-10a) plane (where a is an arbitrary integer).

[0103] The distance between adjacent island-shaped group III nitride semiconductor layers 109 is generally 30 μm or less, preferably 10 μm or less, but is not limited to these values. The distance between the island-shaped group III nitride semiconductor layers 109 is preferably equal to the width of the no-growth region 104 .

[0104] like Figure 4(a) and 4(b) As shown, the island-shaped group III nitride semiconductor layer 109 has a short side 401 and a long side 402 , wherein the long side 402 is perpendicular to the a-axis.

[0105] In various embodiments, the island-shaped III-nitride semiconductor layer 109 can be used to manufacture light-emitting diodes, laser diodes, Schottky diodes, photodiodes, transistors, etc., but is not limited to these devices. The present invention is particularly useful for micro-LEDs and LDs, such as edge-emitting lasers (EELs) and vertical-cavity surface-emitting lasers (VCSELs).

[0106] The number and arrangement of electrodes depend on the type of semiconductor device, and are generally provided at predetermined portions.

[0107] Growth restriction mask

[0108] The growth restriction mask 102 includes a dielectric layer such as SiO 2 、SiN、SiON、Al 2 O 3 , AlN, AlON, MgF, or refractory metals or noble metals, such as W, Mo, Ta, Nb, Rh, Ir, Ru, Os, Pt, etc. The growth restriction mask 102 may be a laminated structure selected from the above materials. It may also be a multi-layer stacked structure selected from the above materials.

[0109] In one embodiment, the thickness of the growth limiting mask 102 is about 0.05-3 μm. The width of the mask is preferably greater than 20 μm, and more preferably, greater than 40 μm.

[0110] Effects of Hydrogen Etching

[0111] In the present invention, the carrier gas may include hydrogen. Hydrogen has the effect of corroding the GaN layer or reducing its growth rate. The width of the growth restriction mask 102 affects these effects. No GaN layer is grown on the growth restriction mask 102, so the area consumption of hydrogen used to etch the GaN layer is very low.

[0112] Therefore, the number of hydrogen atoms reaching the edge of the opening region 103 increases, so that the edge of the opening region 103 is strongly affected by hydrogen etching. On the other hand, the number of hydrogen atoms reaching the center of the opening region 103 decreases compared to the edge.

[0113] exist Figure 5 This effect can be seen in FIG. For simplicity, the patterned substrate 101 has a wide opening area of ​​about 100 μm. Figure 5 As shown, the edge region 501 of the opening region 103 is thinner than the central region thereof, which shows the effect of hydrogen etching.

[0114] like Figure 6(a)-6(i) As shown, this effect also affects the initial layer growth. For example, as shown in FIG6( b ), the effect of hydrogen etching causes the core 601 to be formed at the center of the opening region 103 , which avoids the formation of a recessed region at the center of the ELO III-nitride layer 105 .

[0115] For the above reasons, the wider the growth limit mask 102 is, the stronger the effect of hydrogen etching at the edge of the opening region 103 is. Therefore, the width of the mask 102 is preferably greater than 20 μm, and more preferably, the width is greater than 40 μm. However, in the case where debris exists on the growth limit mask 102, the width of the growth limit mask 102 is preferably below 180 μm.

[0116] In addition, the width of the opening region 103 is preferably greater than 2 μm. If the width of the opening region 103 is less than 2 μm, it is difficult to grow a GaN layer at the opening region 103 under hydrogen carrier gas conditions due to the effect of hydrogen etching.

[0117] Direction of the growth restriction mask

[0118] In one example, the growth restriction mask 102 includes a plurality of stripe-shaped opening regions 103. Figure 7(a)-7(c)The stripe-shaped opening regions 103 are periodically arranged at first and second intervals along a first direction parallel to the 11-20 direction of the III-nitride based semiconductor layer and a second direction parallel to the 0001 direction of the III-nitride based semiconductor layer, respectively, and extend along the second direction.

[0119] The width of the strip-shaped opening area 103 is usually constant in the second direction, but may be changed in the second direction as required.

[0120] The growth limiting mask 102 includes: a plurality of stripe-shaped opening regions 103 periodically arranged in a first direction parallel to the 11-20 direction of the ELO III-nitride layer 105 and extending in a second direction parallel to the 1-100 direction of the ELO III-nitride layer 105; and a plurality of stripe-shaped opening regions 103 periodically arranged in the first direction at the same intervals as the stripe-shaped opening regions 103 and offset by half an interval relative to the stripe-shaped opening regions 103, and extending in a second direction, so that the plurality of stripe-shaped opening regions 103 overlap the ends of the stripe-shaped opening regions 103 in the second direction by a predetermined distance. The widths of these stripe-shaped opening regions 103 are generally constant in the second direction, but may be changed in the second direction as required.

[0121] As shown in Fig. 7(c), in this case, the substrate 101 has no overlapping area. The spacing c is the distance between the islands in the direction parallel to the 1-100 direction. In this case, a smooth surface without hillocks is easily obtained.

[0122] Flat surface area

[0123] The flat surface region 107 is located between the layer bending regions 108. Furthermore, the flat surface region 107 is on the growth limiting mask 102.

[0124] The semiconductor device is mainly manufactured on the flat surface region 107. The width of the flat surface region 107 is preferably at least 5 μm, more preferably 10 μm or more. The flat surface region 107 has high uniformity in thickness for each semiconductor layer.

[0125] Layer bending area

[0126] Figure 8(a)-8(b) The layer bending region 108 is shown along with the bent active region 801 that may remain in the device. The layer bending region 108 is defined as the region outside of the bent active region 801 including the bent active region 801 .

[0127] Device fabrication may be performed partially on the layer bending region 108. More preferably, the layer at the bent layer region 108 is removed by etching. For example, at least a portion of the active layer in the layer bending region 108 is preferably removed by using an etching process such as dry etching or wet etching.

[0128] If a nonpolar or semipolar substrate 101 is used, the island-shaped III-nitride semiconductor layer 109 has two or three facets 802, 803, 804 on one side. In the case of three facets, the first facet 802 is the main area for forming the ridge structure, while the second facet 803 and the third facet 804 are included in the layer bending area 108.

[0129] If the layer bending region 108 including the active layer remains in the LED device, a portion of the light emitted from the active layer is reabsorbed. As a result, at least a portion of the active layer in the layer bending region 108 is preferably removed by etching.

[0130] If the layer bending region 108 including the active layer remains in the LD device, the laser mode may be affected by the layer bending region 108 due to the low refractive index (e.g., InGaN layer). As a result, at least a portion of the active layer in the layer bending region 108 is preferably removed by etching. More preferably, two etchings may be performed, wherein the first etching removes the active layer in the region of the second facet 803 before removing the epi layer from the substrate 101, and the second etching removes the active layer in the region of the third facet 804 after removing the epi layer from the substrate 101. If the layer bending region 108 remains in the LD device, the edge of the ridge stripe structure should be at least 1 μm away from the edge of the layer bending region 108.

[0131] The emission region is a current injection region. In the case of LD, the emission region is a ridge structure. In the case of LED, the emission region is a region where a p-contact electrode is formed. In the case of LD and LED, the edge of the emission region should be at least 1 μm away from the edge of the layer bending region 108, more preferably 5 μm.

[0132] From another perspective, the defect density of the epitaxial layer of the flat surface region 107 except the opening region 103 is lower than that of the epitaxial layer of the opening region 103. Therefore, it is more preferable that the ridge stripe structure is formed on the flat surface region 107 including the wing portion thereof.

[0133] First and second supporting substrates

[0134] If necessary, the method for manufacturing a semiconductor device may further include the following steps: before peeling off the island-shaped III-nitride semiconductor layer 109 from the III-nitride substrate 101, bonding a first support substrate to the exposed surface side of the island-shaped III-nitride semiconductor layer 109 and bonding the first support substrate to the exposed surface side of the III-nitride substrate 101. The first and second support substrates may be composed of elemental semiconductors, compound semiconductors, metals, alloys, nitride-based ceramics, oxide-based ceramics, diamond, carbon, plastics, etc., and may include a single-layer structure or a multilayer structure made of these materials. Metals such as solder or organic adhesives may be used for bonding the first and second support substrates, and are selected as needed.

[0135] Support film

[0136] Fig. 9 (a)-9(b) show the use of a support film 901 when removing a device from a substrate 101. The support film 901 may be an adhesive tape, a UV tape, a polyimide tape, etc., but is not limited to these materials.

[0137] In one embodiment, support film 901 comprises a layer of polyimide tape (20-50 μm) which is roll-applied to the surface of the metal layer of p-pad 203. When tape 901 is gently pulled away from the surface of substrate 101 and along cleavage surface 206, cleavage occurs at cleavage point 205. An image of a device bar removed in this manner is shown in FIG. Fig. 9 As shown in (c).

[0138] Furthermore, to prevent excessive bending of the film after peeling, the outer portion of the tape 901 can be used to secure the sample to the frame.

[0139] Manufacturing method

[0140] The method of manufacturing a semiconductor device may further include the step of forming a growth limiting mask 102 on the group III nitride substrate 101 .

[0141] For example, the m-plane (1-100) free-standing GaN substrate 101 can be bonded to a SiO 2 The growth restriction mask 102 is used together with the Figure 7(a)-7(c) As shown, the opening region 103 is in a direction parallel to <1-100>. If a semi-polar (20-21), (20-2-1) substrate 101 is used, the opening region 103 is in a direction parallel to [-1014], [10-14], respectively. The opening region 103 has a width b of 2 μm to 180 μm, more preferably 4 μm to 50 μm, which makes it easy to obtain a smooth surface.

[0142] Metal organic chemical vapor deposition (MOCVD) was used for epitaxial growth. Trimethyl gallium (TMGa), trimethyl indium (TMIn), and triethyl aluminum (TMAl) were used as group III element sources. Ammonia (NH 3 ) is used as the raw material gas for supplying nitrogen. Hydrogen (H 2 ) and nitrogen (N 2 ) is used as a carrier gas for the Group III element source. It is important to include hydrogen in the carrier gas to obtain a smooth surface for the epi layer.

[0143] Salt and bis(cyclopentadienyl)magnesium (Cp 2 Mg) is used as n-type and p-type dopants. The pressure is set at 50 to 760 Torr. The GaN growth temperature ranges from 1050 to 1250°C.

[0144] After about 2-8 hours of growth time, the island-shaped III-nitride semiconductor layer 109 has the following dimensions:

[0145] Thickness: 20-60 μm; and

[0146] Rod width: 40-150 μm (wherein the rod width is the width of the island-shaped Group III nitride semiconductor layer 109).

[0147] The method may include bonding a first support substrate to an upper surface side of the III-nitride-based semiconductor layer after growing the III-nitride-based semiconductor layer on the substrate 101 , and then peeling the first support substrate and the III-nitride-based semiconductor layer from the III-nitride-based substrate 101 .

[0148] In addition, the method may further include the following steps: after peeling the first support substrate and the island-shaped III-nitride semiconductor layer 109 from the substrate 101 , forming one or more electrodes on the surface of the exposed island-shaped III-nitride semiconductor layer 109 .

[0149] If necessary, the method for manufacturing a semiconductor device may further include the following steps: after growing an island-shaped III-nitride semiconductor layer 109 on the substrate 101, forming one or more electrodes on the upper surface of the island-shaped III-nitride semiconductor layer 109. The n-electrode may be formed after removing the III-nitride-based semiconductor layer using a splitting technique.

[0150] The method may further include a step of removing at least a portion, preferably almost all, or most preferably all of the growth limit mask 102 by a wet etchant. However, the process does not always have to remove the substrate 101. Also, as needed, a conductor film or conductor wire may be formed on the main surface of the first support substrate on the side bonded to the Group III nitride-based semiconductor layer.

[0151] According to the present invention, the crystallinity of island-shaped III-nitride semiconductor layer 109 laterally grown on growth restriction mask 102 from stripe-shaped opening regions 103 of growth restriction mask 102 is very high, and a III-nitride-based semiconductor layer made of high-quality semiconductor crystals can be obtained.

[0152] In addition, two advantages can be obtained by using a III-nitride-based substrate 101. One advantage is that a high-quality island-shaped III-nitride semiconductor layer 109, for example, with a very low defect density, can be obtained compared to using a sapphire substrate 101. Another advantage is that by using similar or identical materials for the epitaxial layer and the substrate 101, it can reduce the strain in the epitaxial layer. Moreover, due to similar or identical thermal expansion, this method can reduce the amount of bending of the substrate 101 during epitaxial growth. As described above, the effect is that productivity can be improved to improve temperature uniformity. However, a heterogeneous substrate 101, such as sapphire (m-plane), LiAlO 2 , SiC, Si, etc. More preferably, an independent III-nitride substrate 101 can be used for the above reasons. If a foreign substrate 101 is used, it is easy to remove because the bonding strength at the cleavage point is weak.

[0153] Therefore, the present invention discloses: a substrate 101 composed of a semiconductor based on a group III nitride; a growth restriction mask 102 having one or more stripe-shaped opening regions 103 directly or indirectly arranged on the substrate 101; and one or more island-shaped group III nitride semiconductor layers 109 grown on the substrate 101 using the growth restriction mask 102 along a (1-100) plane orientation, wherein the stripe-shaped opening regions 103 of the growth restriction mask 102 have long sides and short sides, wherein the long sides are in a direction perpendicular to the a-axis direction of the island-shaped group III nitride semiconductor layer 109, such as Figure 7(a) , 7(b) and 7(c).

[0154] In one embodiment, the growth limit mask 102 is deposited by sputtering or electron beam evaporation or PECVD (Plasma Enhanced Chemical Vapor Deposition); but is not limited to these methods.

[0155] Moreover, when growing a plurality of island-shaped III-nitride semiconductor layers 109, these layers 109 are separated from each other, i.e., formed in isolation, so that the tensile stress or compressive stress generated in each island-shaped III-nitride semiconductor layer 109 is confined within the island-shaped III-nitride-based semiconductor layer 109, and the effect of the tensile stress or compressive stress does not fall on other III-nitride-based semiconductor layers.

[0156] Furthermore, since the growth limiting mask 102 and the ELO group III nitride layer 105 are not chemically bonded, stress in the ELO group III nitride layer 105 may be relaxed by sliding caused at the interface between the growth limiting mask 102 and the ELO group III nitride layer 105 .

[0157] Moreover, if Figure 1 and Figure 4(a)-4(b) As shown in the no-growth region 104, the presence of gaps between each island-shaped III-nitride semiconductor layer 109 causes the substrate 101 to have a plurality of island-shaped III-nitride semiconductor layers 109 in rows, which are flexible and thus easily deformed and able to bend when an external force is applied.

[0158] Therefore, even if slight warping, bending or deformation occurs in the substrate 101, it can be easily corrected by a small external force, thereby preventing cracks from occurring. As a result, the substrate 101 can be handled by a vacuum chuck, which makes the manufacturing process of the semiconductor device easier.

[0159] As described, an island-shaped III-nitride semiconductor layer 109 made of high-quality semiconductor crystals can be grown by suppressing the bending of the substrate 101. In addition, even when the III-nitride-based semiconductor layer is very thick, the occurrence of cracks, etc. can be suppressed, thereby easily realizing a large-area semiconductor device.

[0160] First embodiment

[0161] A Group III nitride based semiconductor device and a method for manufacturing the same according to a first embodiment are described.

[0162] In the first embodiment, a substrate 101 is first provided, and a growth restriction mask 102 having a plurality of stripe-shaped opening regions 103 is formed on the substrate 101. In this embodiment, the substrate 101 is made of a group III nitride semiconductor such as GaN.

[0163] Some substrates 101 may be prepared to have different off-axis orientations. FIG6( d ) has four SEM (scanning electron microscope) images of the surface of the island-shaped III-nitride semiconductor layer 109 on the substrate 101 with different off-axis orientations (labeled as misalignment "(toward the c-axis, a-axis)"), where the carrier gas is H 2 The off-axis orientation ranges from -1 degree toward the c-axis (ie, c-plane) from the m-plane and 0 degree (ie, less than 0.02 degree) toward the a-axis (ie, a-plane). In this embodiment, the substrate 101 has an on-axis orientation of less than 0.2 degrees.

[0164] Making a patterned substrate

[0165] For example, the thickness of the III-nitride based semiconductor layer to be grown on the GaN substrate is about 5 to 80 μm, but is not limited to these values. As described herein, the thickness of the III-nitride based semiconductor layer is measured from the surface of the growth limit mask 102 to the upper surface of the III-nitride based semiconductor layer.

[0166] The growth restriction mask 102 may be formed of an insulator film, such as SiO2, which is deposited on the substrate 101 by plasma chemical vapor deposition (CVD), sputtering, ion beam deposition (IBD), etc. 2 Film, in which SiO 2 The film is then patterned by photolithography and etching using a predetermined photomask. 2 The thickness of the film is 0.3 μm, but is not limited to this value.

[0167] The ELO III-nitride layer 105 is grown in an island shape in the (1-100) plane orientation by a vapor deposition method such as a metal organic chemical vapor deposition (MOCVD) method using the growth limiting mask 102. In this case, the surface of the substrate 101 is exposed in the opening region 103, and the ELO III-nitride layer 105 is selectively grown thereon, and is continuously grown laterally on the growth limiting mask 102. The growth is stopped before the ELO III-nitride layer 105 is coalesced with the adjacent ELO III-nitride layer 105.

[0168] The thickness of the ELO III-nitride layer 105 is important because it determines the width of the flat surface region 107. Preferably, the width of the flat surface region 107 is 20 μm or more.

[0169] The thickness of the ELO III-nitride layer 105 is preferably as thin as possible in order to reduce the processing time and to easily etch the opening region 103 .

[0170] The growth rate of ELO is the ratio of the growth rate in the lateral direction parallel to the 11-20 axis of the GaN substrate 101 to the growth rate in the vertical direction parallel to the 1-100 axis of the GaN substrate 101. The ratio of ELO is preferably high, where the ratio of ELO = lateral growth rate / vertical growth rate. By optimizing the growth conditions, the ratio of ELO can be controlled between 0.4 and 4.

[0171] Next, a III-nitride device layer 106 is grown on the ELO III-nitride layer 105. The III-nitride device layer 106 is composed of a plurality of III-nitride based layers.

[0172] Growth restriction mask

[0173] The growth restriction mask 102 is directly disposed on the substrate 101 including the group III nitride based semiconductor. Specifically, the growth restriction mask 102 is disposed in direct contact, or is indirectly disposed through an intermediate layer made of the group III nitride based semiconductor grown by MOCVD or sputtering. Two examples of the growth restriction mask 102 are shown in FIG. Figure 7(a) and 7(b) Shown in.

[0174] The growth restriction mask 102 shown in FIG. 7( a) includes a plurality of opening regions 103, which are periodically arranged at intervals p1 and p2 in a first direction parallel to the 11-20 direction of the III-nitride semiconductor substrate 101 oriented in the (1-100) plane and in a second direction parallel to the 0001 direction of the III-nitride semiconductor substrate 101, respectively, and extend in a second direction. Each of a pair of opening regions 103 is adjacent to each other in the second direction by a length q. The length a of the opening region 103 is, for example, 200 to 3500 μm; the width b is, for example, 2 to 180 μm; the interval p1 of the opening region 103 is, for example, 20 to 180 μm; and the interval p2 is, for example, 200 to 2000 μm.

[0175] The island-shaped III-nitride semiconductor layer 109 has a long side and a short side. Preferably, the long side is perpendicular to the a-axis direction. In this case, as shown in the rightmost image of FIG. 6( b), the core 601 of the epi layer is aligned perpendicularly to the a-axis direction in the center of the opening region 103. By doing so, the start of growth can be controlled, making it easy to obtain a smooth surface in the flat surface region 107 of the ELO III-nitride layer 105.

[0176] Typical dimensions of a growth limit mask

[0177] Generally, the growth restriction mask 102 used in the present invention has the following dimensions. In one embodiment, an m-plane GaN substrate 101 is used. As shown in FIG. 7( c ), the growth restriction mask 102 is formed with a 0.3 μm thick SiO 2 The membrane comprises a length a of an opening area 103 of 1200 μm, a width b of 20 μm, an interval p1 of the opening area 103 of 80 μm, an interval p2 of 1300 μm, a width of the mask 102 strips between the opening areas 103 of 60 μm, and a distance between the opening areas 103 and the opening areas 103 in the 1-100 direction of 100 μm.

[0178] Limiting the opening area of ​​the growth mask

[0179] The growth limiting mask 102 shown in Fig. 7(b) includes a plurality of opening regions 103 which are periodically arranged at intervals p1 in a first direction parallel to the 11-20 direction of the III-nitride semiconductor substrate 101 oriented in the (1-100) plane, and extend in a second direction parallel to the 0001 direction of the III-nitride semiconductor substrate 101. In order to prevent embossing of both ends in the 0001 direction of the III-nitride semiconductor substrate 101 as described later, the growth limiting mask 102 further includes a plurality of opening regions 103 which are periodically arranged in the first direction at the same intervals p1 as the opening windows 103, are offset by half the intervals p1 relative to the opening regions 103, and extend in the second direction so that the plurality of opening regions 103 overlap with the ends of the opening regions 103 in the second direction by a length q.

[0180] The length a of the opening area 103 is, for example, 200 to 3500 μm; the width b is, for example, 4 to 60 μm; the interval p1 of the opening area 103 is, for example, 20 to 120 μm; the width L of the mask 102 strip is, for example, p1-b, so when p1=55 μm, b=5 μm, L is 50 μm and the overlapping length r of the ends of the opening area 103 is 35 to 40 μm.

[0181] Advantages of open area

[0182] use Figure 1 The growth restriction mask 102 shown for growing the ELO III-nitride layer 105 and the island III-nitride semiconductor layer 109 has many advantages.

[0183] In the growth limit mask 102 shown in FIGS. 4 and 7 , since the longitudinal direction of the opening region 103 is along the 0001 direction, the growth rate of the semiconductor based on the group III nitride is low at both ends of the opening region 103, the island-shaped group III nitride semiconductor layers 109 facing each other in the 0001 direction are not agglomerated, and the island-shaped group III nitride semiconductor layers 109 can be separated from each other. At this time, the size of the island-shaped group III nitride semiconductor layer 109 in the 0001 direction becomes almost equal to the length a of the opening region 103.

[0184] In the island-shaped III-nitride semiconductor layer 109 surrounded by a plane including a plane with a low growth rate, when the distance between the adjacent III-nitride semiconductor layers 109 in the relative plane with a low growth rate is large, the following disadvantages occur. That is, in the stripe of the growth limit mask 102 between the adjacent island-shaped III-nitride semiconductor layers 109, since the raw material gas is not consumed there, the gas concentration rises, and a concentration gradient is generated in the direction connecting the adjacent III-nitride semiconductor layers 109, and a large amount of raw material gas is supplied at the edge portion of the island-shaped III-nitride semiconductor layer 109 by diffusion according to the concentration gradient. As a result, the thickness of the edge portion of the island-shaped III-nitride-based semiconductor layer 109 becomes larger than that of other portions, and becomes a convex shape. More specifically, at the stripes of the growth limit mask 102 between the island-shaped III-nitride-based semiconductor layers 109 adjacent in the 0001 direction where the growth rate is smaller, the raw material gas is not consumed there, so the gas concentration rises, and a concentration gradient in the 0001 direction is generated, and a large amount of raw material gas is supplied at the edge portion in the 0001 direction of the island-shaped III-nitride semiconductor layer 109 by diffusion according to the concentration gradient. As a result, the thickness of the edge portion in the 0001 direction of the island-shaped III-nitride semiconductor layer 109 becomes larger than other portions, and becomes a convex shape. The specific convex shape of the edge portion of the island-shaped III-nitride semiconductor layer 109 not only causes structural inconvenience of the III-nitride-based semiconductor device, but also causes problems in subsequent manufacturing processes such as photolithography.

[0185] In order to prevent the thickness of the island-shaped III-nitride semiconductor layer 109 from being uniform due to the specific convex shape of the edge portion, the adjacent island-shaped III-nitride semiconductor layers 109 are as close as possible, and it is not necessary to generate the in-plane uniformity of the raw material gas from the beginning of growth. For this reason, in the growth limit mask 102 shown in FIG. 7( b), the bisector of the area between a pair of opening areas 103 adjacent to each other in the 11-20 direction is formed so that the opening area 103 overlaps with the opposite ends of the opening areas 103 adjacent to each other in the 0001 direction by a length q.

[0186] As a result, in-plane uniformity of gas concentration can be obtained by consumption of raw material gas caused by growing island-shaped group III nitride semiconductor layer 109. Finally, uniformity of thickness of island-shaped group III nitride semiconductor layer 109 can be obtained.

[0187] Growth Conditions of ELO III-Nitride Layer

[0188] The growth conditions of the island III-nitride semiconductor layer 109 can be the same MOCVD growth conditions as the ELO III-nitride layer 105. For example, the growth of the GaN layer is performed at a temperature of 950-1200° C. and a pressure of 15 kPa. In order to grow the GaN layer, trimethylgallium (TMG) and ammonia (NH 3 ) is used as the raw gas, and the carrier gas is only hydrogen (H 2 ), wherein silane (SiH4) is used as the dopant gas. The growth time is 4 hours.

[0189] The growth gas flow rates are as follows: TMG is 12 sccm, NH 3 The V / III ratio is about 7700. Then, a 20 μm thick ELO III-group nitride layer 105 can be obtained.

[0190] Isolation and growth impact

[0191] In addition, if Figure 4(a)-4(b) As shown, the III-nitride based semiconductor layer is isolated from the edge of the substrate 101 .

[0192] 10(a) is a photograph of a GaN layer on a semipolar (20-21) substrate without a pattern, in which the shape of the edge of the substrate 101 surrounded by a dotted line is uneven. Therefore, the growth rate and shape of the core are unstable, so that the edge region of the substrate 101 has a rough surface.

[0193] A non-polar III-nitride substrate 101 such as an m-plane III-nitride substrate 101 has similar results. As shown in the two images on the left side of FIG. 10( b ), there are many randomly shaped cores 1001 without a pattern on the substrate 101, which results in a large amount of surface roughness. On the other hand, as shown in the two images on the right side of FIG. 10( b ), due to the isolation region, the cores 1001 formed by using SiO 2 The growth restriction mask 102 is patterned on the substrate 101 with a smooth surface.

[0194] At least the opening region 103 should be isolated from the facets of the substrate 101, which are enclosed by dashed lines in Figure 10(a). These facets are perpendicular to the a-axis. Preferably, the opening region 103 is isolated from the facets perpendicular to the projected c-axis.

[0195] Therefore, in order to obtain a smooth surface in the planar surface region 107 , the Group III nitride based semiconductor layer should be isolated from the edge of the substrate 101 .

[0196] exist Figure 10(c)-10(d)Other examples are shown in the images of , where the substrate of FIG. 10( c ) is (10-1-1) and the substrate of FIG. 10( d ) is (1-100) without off-axis orientation. Figure 10(c) and 10(d) Both include images of substrate 101 without patterning 1002 and patterning 1003, which are grown simultaneously by MOCVD. The surface morphology of substrate 101 without patterning 1002 is rough, with uneven edges and pits on the surface. On the other hand, substrate 101 with patterning 1003 has a very smooth surface. An enlarged portion of substrate 101 with patterning 1003 shows some debris on the growth limit mask 102, but the surface of ELO III-nitride layer 105 is very smooth. Moreover, when the growth conditions are optimized, the debris disappears. Normally, the (10-1-1) plane may obtain a rough surface, but using substrate 101 with patterning 1003 can produce a smooth surface.

[0197] Different carrier gas conditions

[0198] In order to compare the effect depending on the carrier gas, two samples have been grown under hydrogen carrier gas conditions and nitrogen carrier gas conditions.

[0199] As shown in the three images of FIG. 6( a ), which reflect growth on the (1-100), (20-21), and (20-2-1) planes, the nitrogen carrier gas condition results in a recessed region formed on the surface at the center of the ELO III-nitride layer 105. As described above, the reason is the lack of hydrogen etching at the edge of the opening region 103.

[0200] As shown in the two images of Figure 6(c), the hydrogen carrier gas condition does not present the same problem.

[0201] 6( b ), the core 601 produced at the beginning of the growth is formed in the center of the open region 103. This growth avoids the core 601 from coalescing in the center, so that the recessed region has disappeared from the ELO III-nitride layer 105.

[0202] Figure 6(a) , 6(b) and 6(c) result in a situation where the width of the opening region 103 is 8-9 μm.

[0203] 6(h) show the results in the case where the width of the opening region 103 is 25 μm. In these cases, the use of a hydrogen carrier gas alone or in combination with a nitrogen carrier gas can also result in a smooth surface, but the case of using a nitrogen carrier gas alone results in a surface having a large amount of surface roughness without a flat area.

[0204] Furthermore, the growth region has been isolated from the edge of the substrate 101, which prevents hillocks from appearing on the surface.

[0205] Different off-axis orientations

[0206] Different off-axis orientations as well as on-axis orientations of the substrates 101 have been prepared. The off-axis orientation is the crystal surface plane of the m-plane orientation, where the off-axis orientation is about +47 degrees to about -47 degrees toward the c-plane. ELO III-nitride layers 105 are grown simultaneously on these substrates 101 under hydrogen carrier gas conditions.

[0207] 6( d ) includes four images of the surface of the ELO III-nitride layer 105, where from left to right the angle of the substrate 101 from the m-plane toward the (0001) c-plane is 0, -0.45, -0.6, and -1 degrees. It is expected that these off-axis orientations will affect the surface morphology, which is the case when using a substrate 101 without a pattern. Some substrates 101 will have pyramidal hillocks, wavy surfaces, etc.

[0208] However, as shown in Figure 6(d), even with different off-axis orientations, each sample still has good surface morphology at the same time. This result has not been reported before in m-plane growth.

[0209] In addition, as shown in the eight images of Figure 6(f), it is possible to use only H 2 The same technique is used to achieve a smooth surface on a substrate 101 having different planes (e.g., (10-10), (20-2-1), (10-1-1), (10-1-2), (20-21), (10-11), and (10-12)) that are coaxial (0 degree off-axis orientation) or offset (-15, -28, -47, +15, +28, +47 degree off-axis orientation).

[0210] The surfaces of these samples are very smooth. The surfaces of the (10-1-2) and (10-11) planes are somewhat rough, but a portion of the surface shows a flat area. Optimizing the growth conditions, such as the hydrogen-nitrogen ratio of the carrier gas, the V / III ratio, and the growth temperature, will improve the surface roughness. Therefore, the present invention can also use these planes. On the other hand, the (10-12) plane is triangular and has no flat area.

[0211] As shown in the image of Figure 6(i), the present invention can employ substrates 101 having an off-axis orientation in the range of -47 to +28 degrees from the m-plane toward the c-plane. More preferably, the off-axis orientation is in the range of -28 to +15 degrees from the m-plane toward the c-plane.

[0212] Alternatively, growth can be performed using a hydrogen and nitrogen carrier gas under mixed gas conditions, with both gases flowing at 1.5 slm and a total carrier gas flow of 3.0 slm.

[0213] Use H 2 and N 2 The results for the mixed carrier gas are shown in the images of Figure 6(g) and Figure 6(e). In these cases, essentially the same results were obtained for the (10-10), (20-2-1), (10-1-1), (10-10), and (20-21) surfaces at 0, -15, -28, 0, and +15 degrees, respectively. Therefore, including hydrogen in the carrier gas is important for obtaining a smooth surface.

[0214] Therefore, even with different off-axis orientations and planes, a very smooth surface can be obtained. This is especially true for off-angles below 0.6 degrees where it is difficult to obtain a smooth surface. However, even for off-angles below 0.6 degrees, a smooth surface can be obtained using the present invention.

[0215] Generally, the GaN substrate 101 has a large off-axis orientation in-plane distribution. However, previously, the large off-axis orientation in-plane distribution caused a decrease in yield due to a rough surface, which was a major problem.

[0216] like Figure 11(a)-11(b) As shown, the off-axis orientation of each point A, B, and C is different. Consider an example where point A is an m-plane with no off-axis orientation, i.e., on-axis, point B is 0.1 degrees off-axis from the m-plane, and point C is 0.2 degrees off-axis from the m-plane. In this example, the surface morphology at each point A, B, and C is different.

[0217] On the other hand, the present invention can avoid this problem and obtain a smooth surface at each point A, B and C, thereby making mass production more efficient and less costly.

[0218] Therefore, the present invention is very useful in cases where the in-plane distribution fluctuation of the off-axis orientation of the substrate 101 is greater than 0.1 degrees and more preferably greater than 0.2 degrees.

[0219] III-nitride semiconductor device layer

[0220] Next, a III-nitride semiconductor device layer 106 was grown on the ELO III-nitride layer 105. To grow the AlGaN layer, triethylaluminum (TMA) was used as a raw material gas; to grow the InGaN layer, trimethylindium (TMI) was used as a raw material gas. Under these conditions, the following layers were grown on the ELO III-nitride layer 105.

[0221] Fig.12 is a cross-sectional view of a nitride semiconductor laser bar along a direction perpendicular to an optical resonator, wherein the optical resonator is composed of a ridge stripe structure.

[0222] The nitride semiconductor laser has the following layers (which are stacked one on top of another in the order mentioned): ELO III-group nitride layer 105 (which is a GaN layer), InGaN / GaN 5MQW active layer 1201 (8nm×8nm: 5MQW), AlGaN-EBL (electron blocking layer) layer 1202, p-GaN guide layer 1203, ZrO 2 The current confinement layer 1204 and the p-electrode 1205. Note that these Group III nitride semiconductor layers can be formed of any nitride-based Group III-V compound semiconductor grown in the above order.

[0223] The ridge structure consists of p-GaN cap layer 1203, ZrO 2 The current confinement layer 1204 and the p-electrode 1205 provide optical confinement in the horizontal direction. The width of the ridge stripe structure is on the order of 1.0 to 20 μm, and is typically 10 μm.

[0224] In one embodiment, the p-electrode 1205 may include one or more of the following materials: Pd, Ni, Ti, Pt, Mo, W, Ag, Au, etc. For example, the p-electrode 1205 may include Pd-Ni-Au (thickness is 3-30-300 nm). These materials may be deposited by electron beam evaporation, sputtering, thermal evaporation, etc.

[0225] In addition, if Figure 2 As shown in (c), an ITO cap layer may be added between the p-GaN cap layer 1203 and the p-electrode 1205 .

[0226] Initial growth

[0227] In order to obtain a smooth surface with a non-polar or semi-polar substrate 101, it is necessary to consider the mechanism of initial growth, which is different from that of a polar c-plane substrate. Fig.13 As shown in the image of , the initial growth on the polar c-plane substrate 101 with a (0001) surface shows isotropic growth, such as hexagons 1301. On the other hand, Fig.13 As shown, the initial growth on the non-polar substrate 101 having an off-axis orientation tilted from the m-plane (10-10) to the c-plane shows anisotropic growth.

[0228] Some researchers have explained this phenomenon. For example, Lymperakis and Neugebauer calculated that the highly anisotropic diffusion barriers of Ga atoms on the m-plane GaN surface along the c-direction and the a-direction are 0.93 eV and 0.21 eV, respectively. See Phys. Rev. B 79, 241308 (R). It can be considered that the anisotropic diffusion barrier of Ga atoms causes anisotropic initial growth. In addition, without limiting the growth area, this anisotropic initial growth will lead to a large amount of surface roughness, as shown in the initial growth of the m-plane without the mask shown in Figure 14 (a) and with the mask 102 shown in Figure 14 (b).

[0229] Due to the above reasons, the non-polar substrate 101 having an off-axis orientation tilted from the m-plane to the c-plane grows rapidly at the start of growth along the long dimension of the a-axis rather than the c-axis. In this case, the growth limiting mask 102 can be formed with an opening 103 having a long side in the a-direction rather than protruding from the c-axis, which makes the surface smooth due to the ability to control the initial growth position and avoid coalescence of the initial growth from an unintentional direction, such as Fig.16 and 17 As shown. The off-axis oriented non-polar substrate 101 with the crystal surface plane oriented in the m-plane is about +28 degrees to about -47 degrees toward the c-plane. For the above reasons, these substrates can use the growth limit mask 102 to obtain a smooth surface.

[0230] Fig.13 Similar results for the non-polar (10-10) substrate 101 for the semi-polar (20-21) and (20-2-1) substrates 101 are also shown.

[0231] Edge Growth

[0232] The ELO III-nitride layer 105 has an on-axis orientation and an off-axis orientation of a crystal surface plane oriented from the m-plane, wherein the off-axis orientation ranges from about +28 degrees to about -47 degrees toward the c-plane. A III-nitride semiconductor device layer 106 is grown on the ELO III-nitride layer 105. In this case, edge growth is restricted.

[0233] like Fig.15 As shown in (a)-15(c), in the case of a c-plane substrate 101, an edge growth region 1501 is provided at the edge of the island-shaped III-nitride semiconductor layer 109. Typically, the width of the edge growth region 1501 is about 10-15 μm, and the height T of the edge growth region 1501 is 0.3-0.4 μm. The edge growth region 1501 has a high growth rate, so that each layer thickness is different from the center of the island-shaped III-nitride semiconductor layer 109.

[0234] In this case, it is best to avoid forming a ridge structure from the edge growth region 1501 because the productivity will be reduced due to the fluctuation of the thickness of the layer. In the case of the c-plane substrate 101, the edge growth region 1501 is wide and high. However, in the present invention, the height T is less than 0.2 μm and the width W is about 5 μm.

[0235] Limiting the edge growth region 1501 is very important in the manufacture of the device. By optimizing the growth conditions, the edge growth region 1501 can be substantially eliminated.

[0236] Making the ridge structure

[0237] like Figure 3(a)-3(b) As shown, after MOCVD growth, a ridge stripe structure 301 is fabricated using conventional methods such as photolithography and dry etching. The ridge depth (from the surface to the bottom of the ridge) is in the p-GaN guide layer. The ridge depth is predetermined before performing the dry etching based on simulations or previous experimental data.

[0238] How to make noodles

[0239] like Figure 3(a)-3(b) As shown, the etched mirror region 302 is positioned based on the optical resonance length. The etching process of GaN etching uses Ar ion beam and Cl 2 Ambient gas. The etching depth is about 1 μm to about 4 μm. The etched mirror facets may be coated with a dielectric film selected from the group consisting of: SiO 2 、Al 2 O 3 , AlN, AlON, SiN, SiON, TiO 2 、 2 O 5 , Nb 2 O 5 、Zr 2 O etc.

[0240] III-nitride based device layers bonded to a supporting substrate

[0241] Figure 2 (d) shows the first support substrate 204, which is bonded to the island-shaped group III nitride semiconductor layer 109. Conventional bonding techniques can be used for bonding.

[0242] In general, the most common types of flip chip bonding are thermocompression bonding and wafer fusion / bonding. Wafer fusion has been widely used in InP-based devices. However, thermocompression bonding is generally much simpler than wafer fusion because it uses a metal-to-metal bond and has the benefit of also greatly improving thermal conductivity.

[0243] Au-Au compression bonding is by far the simplest bonding and results in a fairly strong bond. Au-Sn eutectic bonding provides greater bonding strength.

[0244] In one embodiment, a Cu substrate is used as the support substrate 204. A patterned Ti / Au electrode is fabricated on the Cu substrate by electron beam evaporation or sputtering. The thickness of the electrode is Ti (10 nm) and Au (500 nm).

[0245] Preferably, activation of the surface for wafer bonding is performed before press bonding. The activation of the surface is performed by using Ar and / or O 2 The island-shaped III-nitride semiconductor layer 109 is then bonded to the support substrate 204 at 150-300° C. under pressure.

[0246] Removal of substrate by thermal expansion

[0247] The bonded wafers are immersed in a solvent for wet etching to remove the substrate 101. In one embodiment, the growth restriction mask 102 used is SiO 2 , which is dissolved by the HF or BHF solvent. The advantage of this technique is that there is no mechanical damage when the substrate 101 is removed (very gently), and wide areas of SiO 2 Dissolved by HF.

[0248] After that, the wafer bonded to the III-nitride substrate 101 and the support substrate 204 is heated. The Cu support substrate 204 has a larger CTE (Coefficient of Thermal Expansion) than the GaN substrate 101. Figure 2 As shown in (e), the expansion of the supporting substrate 204 due to heating applies strong stress to the cleavage point 205. Thereafter, cleavage starts at the cleavage point 205 toward the opposite side of the cleavage surface 206.

[0249] N electrode

[0250] like Figure 2 As shown in (f), the n-electrode 207 is placed on the back side of the island-shaped group III nitride semiconductor layer 109. Generally, the n-electrode 207 is made of the following materials: Ti, Hf, Cr, Al, Mo, W, Pt, Au.

[0251] For example, the n-electrode 207 may be made of Ti-Al-Pt-Au (thickness of 30-100-30-500 nm), but is not limited to these materials. The deposition of these materials may be performed by electron beam evaporation, sputtering, thermal evaporation, etc. Preferably, the p-electrode 207 is deposited on ITO.

[0252] like Fig.16As shown, after the island-shaped III-nitride semiconductor layer 109 is removed from the substrate 101, an n-electrode (not shown) is preferably formed in a separation region 1601 on the back side of the island-shaped III-nitride semiconductor layer 109. The separation region 1601 has a good surface condition for the n-electrode to obtain a low contact resistivity. Specifically, the present invention keeps the separation region 1601 clean until the island-shaped III-nitride semiconductor layer 109 is removed.

[0253] Chip partitioning method

[0254] The chip dividing method has two steps. The first step is to scribing the island-shaped group III nitride semiconductor layer 109. The second step is to divide the supporting substrate 204 using a laser scribing method or the like.

[0255] like Figure 3(a)-3(b) As shown, the chip scribe line 303 is made by a diamond scriber or a laser scriber. The chip scribe line 303 is made on the back side of the island-shaped group III nitride semiconductor layer 109. The chip scribe line 303 may be a solid line or a dotted line.

[0256] Next, the support substrate 204 is also divided by laser scribing to obtain LD devices. When making chip scribe lines 303, it is best to avoid ridge stripe structures.

[0257] Second embodiment

[0258] The second embodiment is almost the same as the first embodiment except that the island-shaped III-nitride semiconductor layer 109 is not removed. The steps of the manufacturing method are the same as the first embodiment until step 3 (TCO p-pad deposition + ridge process). In the second embodiment, the island-shaped III-nitride semiconductor layer 109 is not bonded to the supporting substrate 204. The following processing is the same as the conventional device processing.

[0259] 4. Polish the substrate 101 until its thickness is 80-100 μm.

[0260] 5. An n-electrode is formed on the back side of the substrate 101 .

[0261] 6. Separate the substrate 101 into rods, such as Fig.17 (a)-17(b), where Fig.17 (a) shows a flat surface region 107, a layer bending region 108, and an island-shaped III-nitride-based semiconductor layer 109 separated by a no-growth region 104, and a scribe line 1701; Fig.17 (b) shows the device divided into rods 1702 along scribe line 1701.

[0262] 7. Facet coating (using the same method as mentioned in the first example).

[0263] 8. Separate the rod 1702 into individual devices or chips 1703, such as Fig.17 (b)-17(c) as shown.

[0264] By doing so, the device 1703 can be obtained without removing the island-shaped group III nitride semiconductor layer 109 from the substrate 101. By using the method of this second embodiment, the same effect as that of the first embodiment is obtained.

[0265] Modifications and Replacements

[0266] Numerous modifications and substitutions may be made without departing from the scope of the invention.

[0267] For example, the present invention can be used with other oriented III-nitride substrates. Specifically, the substrate can be a base non-polar m-plane {1 0 -1 0} family; and a semi-polar plane family having at least two non-zero h, i or k Miller indices and a non-zero l Miller index, such as a {2 0 -2 -1} plane. (20-2-1) semi-polar substrates are particularly useful because of wide area planarized ELO growth.

[0268] In another example, the present invention is described as being used to manufacture different optoelectronic device structures, such as light emitting diodes (LEDs), laser diodes (LDs), Schottky barrier diodes (SBDs), or metal oxide semiconductor field effect transistors (MOSFETs). The present invention can also be used to manufacture other optoelectronic devices, such as micro-LEDs, vertical cavity surface emitting lasers (VCSELs), edge emitting laser diodes (EELDs), and solar cells.

[0269] in conclusion

[0270] Thus, the description of the preferred embodiments of the present invention is concluded. For the purpose of illustration and description, the foregoing description of one or more embodiments of the present invention has been given. It is not intended to be exhaustive or to limit the present invention to the precise form disclosed. In accordance with the above teachings, many modifications and variations are possible. It is intended that the scope of the present invention is not limited by this detailed description, but by the appended claims.

Claims

1. A device comprising: One or more island-shaped Group III nitride semiconductor layers having an off-axis orientation of the crystallographic surface plane in an m-plane orientation, wherein: The island-shaped III-nitride semiconductor layer is grown in an opening region of a growth restriction mask deposited on the III-nitride substrate; The off-axis orientation of the m-plane-oriented crystal surface plane of the island-shaped Group III nitride semiconductor layer is +28 degrees to -47 degrees toward the c-plane of the island-shaped Group III nitride semiconductor layer; and The island-shaped group III nitride semiconductor layer has at least one long side and at least one short side, wherein the long side is perpendicular to the a-axis of the island-shaped group III nitride semiconductor layer, The island-shaped III-nitride semiconductor layer has an edge growth region with a height of less than 0.2 micrometers at a short side of the island-shaped III-nitride semiconductor layer, in which the growth of the island-shaped III-nitride semiconductor layer is restricted, and the edge growth region is located at an edge of the island-shaped III-nitride semiconductor layer and has a width of less than 5 micrometers; and The island-shaped Group III nitride semiconductor layer has a flat surface region without hillocks.

2. The device according to claim 1, wherein The island-shaped Group III nitride semiconductor layer is not aggregated with adjacent island-shaped Group III nitride semiconductor layers.

3. The device according to claim 1, wherein The growth limiting mask (102) is isolated from the edge of the III-nitride substrate.

4. The device according to claim 3, wherein The island-shaped Group III nitride semiconductor layer is removed from the Group III nitride substrate.

5. The device according to claim 1, wherein The island-shaped Group III nitride semiconductor layer has an emission region, and the emission region is a current injection region.

6. The device according to claim 5, wherein The emission region is greater than 5 μm from an edge of a top surface of the island-shaped Group III nitride semiconductor layer.

7. The device according to claim 1, wherein The island-shaped Group III nitride semiconductor layer has a single region forming an n-electrode.

8. A method for manufacturing a semiconductor device, comprising: A growth limit mask is formed on or over a III-nitride substrate, wherein: The Group III nitride substrate has an in-plane distribution of off-axis orientation greater than 0.1 degrees; and and One or more island-shaped group III nitride semiconductor layers are grown on a group III nitride substrate using the growth restriction mask, wherein: The island-shaped group III nitride semiconductor layer has an off-axis orientation of a crystal surface plane of an m-plane orientation, and the off-axis orientation of the crystal surface plane of the m-plane orientation is +28 degrees to -47 degrees toward the c-plane; The island-shaped group III nitride semiconductor layer has at least one long side and at least one short side, wherein the long side is perpendicular to the a-axis of the island-shaped group III nitride semiconductor layer, The island-shaped III-nitride semiconductor layer has an edge growth region with a height of less than 0.2 micrometers at a short side of the island-shaped III-nitride semiconductor layer, the edge growth region is located at an edge of the island-shaped III-nitride semiconductor layer and has a width of less than 5 micrometers; and The island-shaped Group III nitride semiconductor layer has a flat surface region without hillocks.

9. The method according to claim 8, wherein: The growth limiting mask (102) is isolated from an edge of the III-nitride substrate.

10. The method according to claim 8, wherein: The island-shaped Group III nitride semiconductor layer is not aggregated with adjacent island-shaped Group III nitride semiconductor layers.

11. The method according to claim 9, wherein: The island-shaped Group III nitride semiconductor layer is removed from the Group III nitride substrate.

12. The method according to claim 8, wherein: The island-shaped Group III nitride semiconductor layer has an emission region, and the emission region is a current injection region.

13. The method according to claim 12, wherein: The emission region is greater than 5 μm from an edge of a top surface of the island-shaped Group III nitride semiconductor layer.

14. The method according to claim 8, wherein: The island-shaped Group III nitride semiconductor layer has a single region forming an n-electrode.

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