Floating point processor

Abstract

The present invention provides a floating point processor, including a codec component and a floating point operation logic, wherein the codec component is used to receive a standard format floating point number, and compress the bit width of the standard format floating point number to generate a low bit width floating point number, and the floating point operation logic is used to operate the low bit width floating point number to obtain an operation result. The present invention can obtain low bit width floating point numbers with different exponent bit widths according to different standard format floating point numbers, and the low bit width floating point numbers can meet the data accuracy requirements of algorithms such as neural network algorithms and image processing, while avoiding the waste of floating point operation power.

Description

Technical Field

[0001] The invention belongs to the field of computers, and in particular relates to a low-power free exponent domain floating-point processor. Background Art

[0002] In recent years, the requirement for high dynamic range has gradually become an important part in applications in various fields. Compared with fixed-point numbers, floating-point numbers with the same data bit width have a higher dynamic range, so floating-point numbers are becoming more and more important. Therefore, powerful computing systems usually use floating-point processors as part of the main processor or as a coprocessor.

[0003] Floating point numbers are used to approximate a real number. Their format usually includes a sign bit S, an exponent bit E, and a mantissa bit M, which can be expressed as {S, E, M}. In order to facilitate storage in computers, the base of the power of floating point numbers is 2, that is, the floating point number {S, E, M} = (-1) s ×(1+M)×2 E .

[0004] The precision of a floating point number is defined by the data bit width used to represent the mantissa. The larger the mantissa data bit width, the higher the precision of the floating point number. Most existing general-purpose processors use IEEE 754 standard floating point numbers for addition, subtraction, multiplication, and division operations. In the 32-bit floating point format of the IEEE 754 standard, it has 1 sign bit, 8 exponent bits, and 23 mantissa bits, of which the integer bits to the left of the mantissa binary point are implicit. IEEE 754 also has a 64-bit format with higher precision and higher dynamic range.

[0005] However, no matter which floating-point format is used, the characteristics of floating-point numbers themselves determine that floating-point operations are more complicated. Therefore, how to improve the floating-point operation speed and reduce the operation power consumption has become one of the core issues in today's hardware design.

[0006] General-purpose processors are usually limited to a single floating-point format. Although this format can meet the accuracy and dynamic range requirements of some applications, other applications may not need it. For example, in neural network algorithms, floating-point numbers with larger exponents (local induced domains) require lower precision, while floating-point numbers with smaller exponents (weights or weight changes and gradients in the directional propagation algorithm) require higher precision. Because the activation functions in neural network algorithms are nonlinear, such as sigmoid and tanh functions, the accuracy of the results of local induced domains with different precisions after the activation function is not much different, and high-precision local induced domain floating-point representation will cause unnecessary power consumption. Similarly, weights, weight changes and gradients in the directional propagation algorithm require higher precision, but the data of this type is relatively small, and the required dynamic range is smaller, that is, the exponent is smaller.

[0007] In the floating point number format and its operation method provided by CN200810216631, the precision of the floating point number is variable, but its exponent part is fixed. Moreover, the data structure of this floating point number format is relatively complex, which is not conducive to improving the floating point operation rate.

[0008] The optional sub-precision floating-point arithmetic unit described in CN200780006490, wherein the format of the floating-point number is fixed, provides an excess bit to remove the power of the high-precision mantissa part, thereby reducing the floating-point operation power. However, in this method, the floating-point number is still represented by the above-mentioned single floating-point number format, which will cause a certain degree of waste of storage space and power consumption. Summary of the invention

[0009] 1. Technical issues to be resolved

[0010] The object of the present invention is to provide a floating point number processing device, which can compress the bit width of a floating point number in a standard format to generate a floating point number with a low bit width, thereby saving storage space and reducing the power consumption of floating point number operations.

[0011] (II) Technical solution

[0012] The present invention provides a floating point number processing device, comprising:

[0013] A conversion unit, configured to receive at least one first floating-point number, and convert the at least one first floating-point number into a corresponding number of second floating-point numbers, wherein each second floating-point number includes a 1-bit sign bit, N-bit exponent bits, and CN-1-bit mantissa bits, C and N are integers greater than or equal to 1, C is a total number of bits of the second floating-point number, and the value of N is determined by the at least one first floating-point number;

[0014] The operation unit is used to operate the second floating-point number to obtain an operation result.

[0015] (III) Beneficial effects

[0016] The present invention compresses the bit width of a standard format floating-point number to generate a low bit width floating-point number, wherein for different standard format floating-point numbers, the exponent bit width and mantissa bit width in the corresponding low bit width floating-point number are variable, so that the precision and dynamic range of the low bit width floating-point number are variable, and the low bit width floating-point number can meet the data precision requirements of algorithms such as neural network algorithms and image processing, while avoiding the waste of floating point operation power. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of a floating point number processing device provided by an embodiment of the present invention.

[0018] Figure 2Schematic diagram of a standard format floating point number and a low bit width floating point number in an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The present invention provides a floating point number processing device, comprising a conversion unit and an operation unit, wherein the conversion unit receives a standard format floating point number, and compresses the bit width of the standard format floating point number to generate a low bit width floating point number, and the operation unit operates the low bit width floating point number to obtain an operation result. The present invention can obtain low bit width floating point numbers with different exponent bit widths according to different standard format floating point numbers, and the low bit width floating point numbers can meet the data accuracy requirements of algorithms such as neural network algorithms and image processing, while avoiding the waste of floating point number operation power.

[0020] According to one embodiment of the present invention, a floating point number processing device comprises:

[0021] The conversion unit is used to receive a group of first floating-point numbers and convert the group of first floating-point numbers into a corresponding number of second floating-point numbers, wherein the group of first floating-point numbers may include one or more first floating-point numbers, and the same number of second floating-point numbers are obtained after conversion, each first floating-point number corresponds to each second floating-point number one by one, each of the second floating-point numbers includes a 1-bit sign bit, N-bit exponent bits and CN-1-bit mantissa bits, C and N are integers greater than or equal to 1, C is the total number of bits of the second floating-point number, and the value of N is determined by the group of first floating-point numbers; the first floating-point number is a standard format floating-point number, and the second floating-point number is a low-bit-width floating-point number obtained by bit-width compression of the standard format floating-point number.

[0022] The operation unit is used to operate the second floating-point number to obtain an operation result.

[0023] The standard format floating point number includes 1 sign bit, K1 exponent bits and K2 mantissa bits. For example, the 32-bit standard format floating point number defined by IEEE 754 includes 1 sign bit, 8 exponent bits and 23 mantissa bits. The value V1 of the standard format floating point number is expressed as:

[0024] V1=(-1) S ×(1+M)×2 E ,

[0025] Wherein, S is the value of the sign bit of the standard format floating point number, E is the value of the K1 exponent bit of the standard format floating point number, and M is the value of the K2 mantissa bit of the standard format floating point number;

[0026] The value of N in low-width floating-point numbers is:

[0027] N = log2(E max -E min ) / 2,

[0028] Among them, Emax is the maximum value of E in a set of standard format floating point numbers, E min is the minimum value of E in a group of standard format floating-point numbers; the principle of the floating-point number conversion of the present invention is that, for a group of standard format floating-point numbers, the bit width of the exponent bit is fixed, but the values ​​corresponding to the exponent bit are not the same, and a relatively average exponent bit value is obtained by analyzing the values ​​corresponding to the exponent bits in a group of standard format floating-point numbers, and the number of exponent bits N in the low-bit-width floating-point number is determined according to the minimum number of bits required for the value, and according to the total number of bits C of the set low-bit-width floating-point number and 1 sign bit, it can be known that the mantissa of the low-bit-width floating-point number is CN-1.

[0029] The above is the division of the number of exponent bits and mantissa bits in low-width floating-point numbers, and then it is necessary to determine the values ​​of the exponent bits and mantissa bits in the low-width floating-point numbers.

[0030] According to an embodiment of the present invention, the sign bit of the low-width floating-point number is equal to the sign bit of the standard-format floating-point number; the CN-1-bit mantissa of the low-width floating-point number is equal to the first CN-1 bit of the K2-bit mantissa of the standard-format floating-point number; and the value E′ of the N-bit exponent bit is:

[0031] E′=E-B+A,

[0032] Among them, B is the offset of the exponent bit of the standard format floating point number, for example, the offset of the 32-bit floating point number in the IEEE 754 standard is 127. A is the exponent base of the low-bit width floating point number, and its expression is:

[0033] A=(E max +E min ) / 2.

[0034] According to one embodiment of the present invention, the conversion unit is further used to receive a low-width floating-point number and convert the low-width floating-point number into a standard format floating-point number, wherein: the sign bit of the standard format floating-point number is equal to the sign bit of the low-width floating-point number; the first CN-1 bit of the K2-bit mantissa of the standard format floating-point number is equal to the CN-1-bit mantissa of the low-width floating-point number, and the last K2+1+NC bit is 0; the value E′ of the N-bit exponent bit is:

[0035] E′=E-B+A.

[0036] According to an embodiment of the present invention, the conversion unit includes a first register and a second register, the first register is used to store the value of N, and the second register is used to store the value of the exponent base A of the low-bit width floating point number.

[0037] According to one embodiment of the present invention, the floating point number processing device further includes: a storage unit for storing standard format floating point numbers and low bit width floating point numbers. The storage unit, the conversion unit, and the operation unit are connected in pairs, and the floating point numbers in each component can flow in both directions. It should be noted that the operation unit can only operate on low bit width floating point numbers, so its input and output data are all low bit width floating point numbers.

[0038] According to an embodiment of the present invention, the floating point number processing device can be used as a main processor or a coprocessor, and can perform data exchange with other external processors using a bus.

[0039] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0040] Figure 1 is a schematic diagram of a floating point processor provided by an embodiment of the present invention, such as Figure 1 As shown, the floating-point processor 1 includes a codec component 2, a floating-point operation logic 3 and a memory (RAM) 4. In this embodiment, the codec component 2 is used as a conversion unit to perform floating-point conversion, the floating-point operation logic 3 is used as an operation unit to perform floating-point operations, and the memory 4 is used as a storage unit to store floating-point numbers. The floating-point processor is externally connected to an external input device 5 (mouse / keyboard) and a bus 6. The input device 5 can directly input standard format floating-point numbers to the codec component 2. The floating-point processor can be used as a main processor or a coprocessor through the bus 6. It can use a bus to exchange data with other external processors.

[0041] The codec component 2 includes a set of configuration registers (cfg) and a set of exponent base registers (base). The configuration register (cfg) stores the number of bits N of the exponent bits of the low-bit-width floating-point number, which is used to define the exponent and mantissa of the low-bit-width floating-point number. The exponent base register (base) stores the value of the exponent base A of the low-bit-width floating-point number. The codec component 2 uses the values ​​in the two registers to implement encoding (conversion of standard-format floating-point numbers to low-bit-width floating-point numbers) and decoding (conversion of low-bit-width floating-point numbers to standard-format floating-point numbers) of standard-format floating-point numbers and low-bit-width floating-point numbers.

[0042] The floating point operation logic 3 is coupled to the data memory 4 and the codec component 2 to process the requested low-bit width floating point number. The floating point operation logic 3 outputs the operation result to the codec component 2, and the codec component outputs the result to the storage unit 4 according to the executed floating point operation request.

[0043] This embodiment converts the standard 32-bit floating point number into a 16-bit low-bit width floating point number in the neural network algorithm. Figure 2As shown in the figure, the comparison between the IEEE 754 floating point standard floating point format and the 16-bit wide free exponent field floating point format is shown. If the configuration register value corresponding to the low-width floating point number is N, then the exponent field width in the floating point number is N, and the mantissa width is 15-N.

[0044] In the neural network algorithm, data calculation is performed according to different layers. In one layer of the neural network, the dynamic range of the same type of data is not much different. At the same time, data with higher dynamic range requirements have relatively lower requirements for data accuracy, while data with higher accuracy requirements have lower dynamic range requirements. Therefore, two sets of registers are used to control the accuracy and dynamic range of low-bit width floating-point numbers. For example, the exponent value of a set of standard format floating-point numbers in [E min , E max ] interval, using the formula: N = log2 (E max -E min ) / 2, A=(E max +E min ) / 2, the value of the configuration register (cfg) is set to N (that is, the split bit is at the 15-Nth bit), and the corresponding exponent base register (base) is set to A. During encoding, the exponent of the IEEE 754 floating point number (minus the offset 127) plus A is assigned to the [14:15-N] bits of the free exponent domain floating point number, and the first 15-N bits of the mantissa of the IEEE 754 floating point number are intercepted and assigned to the lower 15-N bits of the low-width floating point number, thereby realizing the encoding of the IEEE 754 floating point number exponent and mantissa to the low-width floating point number. During decoding, [14:15-N] of the IEEE 754 floating-point number is subtracted from A and then added with 127 as the exponent of the IEEE 754 floating-point number, and N+7 zeros are added after the lower 15-N bits of the low-width floating-point number and assigned to the mantissa of the IEEE 754 floating-point number to achieve decoding of the low-width floating-point number to the IEEE 754 floating-point number.

[0045] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A floating point processor, characterized in that: The floating point processor comprises: A codec component, configured to receive at least one first floating-point number and convert the at least one first floating-point number into a corresponding number of second floating-point numbers; wherein the codec component is configured to analyze the value corresponding to the exponent bit in the received at least one first floating-point number to obtain an average exponent bit value, and determine the number of bits N of the exponent bit in the second floating-point number according to the number of bits required for the average exponent bit value, so as to convert the at least one first floating-point number into a corresponding number of second floating-point numbers; and Floating-point operation logic, used for operating the second floating-point number to obtain an operation result; The first floating-point number and the second floating-point number both include a sign bit, an exponent bit, and a mantissa bit; and the bit width of the second floating-point number is smaller than the bit width of the first floating-point number.

2. The floating point number processor according to claim 1, wherein: Each of the first floating-point numbers includes a 1-bit sign bit, K1-bit exponent bits, and K2-bit mantissa bits. The value V1 of the first floating-point number is expressed as: V1=(-1) S ×(1+M)×2 E Among them, S is the value of the sign bit of the first floating point number, E is the value of the K1-bit exponent bit of the first floating point number, and M is the value of the K2-bit mantissa bit of the first floating point number.

3. The floating point processor according to claim 1, wherein: When the encoding and decoding component is used to convert the at least one first floating-point number into a corresponding number of second floating-point numbers, it is specifically used to: According to the at least one first floating-point number, the values ​​of the exponent bits and the mantissa bits corresponding to the second floating-point number are determined to convert the at least one first floating-point number into a corresponding number of second floating-point numbers.

4. The floating point number processor according to claim 1, wherein: The encoding and decoding component is also used for: Determine the mantissa of the second floating-point number according to the total number of digits C of the set second floating-point number and the sign bit of the second floating-point number, thereby converting the first floating-point number into the second floating-point number; Each of the second floating-point numbers includes a 1-bit sign bit, N-bit exponent bits and CN-1-bit mantissa bits, C and N are integers greater than or equal to 1, and C is the total number of bits of the second floating-point number.

5. The floating point number processor according to claim 1 or 4, characterized in that: The number of exponent bits N in the second floating point number is: N=log2(E max -AND min ) / 2, Among them, E max is the maximum value of E among at least one first floating-point number, E min is the minimum value of E in at least one first floating-point number; E is the value of the K1-bit exponent bit of the first floating-point number.

6. The floating point processor according to claim 3, characterized in that: The encoding and decoding component is used to determine the value of the exponent bit and the value of the mantissa bit in the second floating point number according to the at least one first floating point number, including: The codec component is used to determine the value E′ of the N-bit exponent bit as follows, E′=E-B+A, Wherein, E is the value of the K1-bit exponent bit of the first floating-point number, B is the offset of the exponent bit of the first floating-point number, and A is the exponent base of the second floating-point number, and the expression is: A=(E max +E min ) / 2, E max is the maximum value of E among at least one first floating-point number, E min is the minimum value of E in at least one first floating-point number; The value of the CN-1-bit mantissa of the second floating-point number is equal to the first CN-1 bit of the K2-bit mantissa of the first floating-point number; the sign bit of each of the second floating-point numbers is equal to the sign bit of the first floating-point number.

7. The floating point processor according to claim 1, characterized in that: The encoding and decoding component is further used to receive a second floating point number and convert the second floating point number into a first floating point number.

8. The floating point number processor according to claim 7, characterized in that: When the encoding and decoding component is used to convert the second floating-point number into a first floating-point number, it is specifically used to: Setting the sign bit of the first floating point number to be equal to the sign bit of the second floating point number; The value of the first CN-1 bit of the K2-bit mantissa of the first floating point number is set to be equal to the CN-1-bit mantissa of the second floating point number, and the last K2+1+NC bit of the K2-bit mantissa of the first floating point number is set to 0; Determine the value E of the K1-bit exponent bit of the first floating point number according to the relationship E′=E−B+A between the value E′ of the N-bit exponent bit of the second floating point number and the value E of the K1-bit exponent bit of the first floating point number; Among them, B is the offset of the exponent bit of the first floating-point number, A is the exponent base of the second floating-point number, N bits are the exponent bits of the second floating-point number, C is the total number of bits of the second floating-point number, and C and N are integers greater than or equal to 1.

9. The floating point number processor according to claim 7 or 8, characterized in that: The encoding and decoding component also includes: at least one first register, the first register being used to store a value of the number of bits N of the exponent bits of each of the second floating-point numbers; and At least one second register, wherein the second register is used to store the value of the exponent base A of each of the second floating-point numbers.

10. The floating point processor according to claim 1, characterized in that: The floating point number processor further includes a memory for storing the first floating point number and the second floating point number.

11. The floating point number processor according to claim 2 or 3, characterized in that: The floating point processor uses a bus to perform data exchange with an external processing device.

12. The floating point number processor according to claim 1, characterized in that: For the at least one first floating-point number in different standard formats, the exponent bit width and mantissa bit width of the corresponding number of second floating-point numbers may be variable.

13. A floating point number processing method, characterized in that: The method comprises: receiving at least one first floating point number and converting the at least one first floating point number into a corresponding number of second floating point numbers; and Performing an operation on the second floating-point number to obtain an operation result; Wherein, both the first floating-point number and the second floating-point number include a sign bit, an exponent bit, and a mantissa bit; and the bit width of the second floating-point number is smaller than the bit width of the first floating-point number; The receiving of at least one first floating-point number and converting the at least one first floating-point number into a corresponding number of second floating-point numbers further includes: receiving at least one first floating-point number, and analyzing a value corresponding to an exponent bit in the at least one first floating-point number to obtain an average exponent bit value; The number of exponent bits N in the second floating point number is determined according to the number of bits required for the average exponent bit value, so as to convert the at least one first floating point number into a corresponding number of second floating point numbers.

14. The method according to claim 13, characterized in that Each of the first floating-point numbers includes a 1-bit sign bit, K1-bit exponent bits, and K2-bit mantissa bits. The value V1 of the first floating-point number is expressed as: V1=(-1) S ×(1+M)×2 E Among them, S is the value of the sign bit of the first floating point number, E is the value of the K1-bit exponent bit of the first floating point number, and M is the value of the K2-bit mantissa bit of the first floating point number.

15. The method according to claim 13, characterized in that The converting of the at least one first floating point number into a corresponding number of second floating point numbers comprises: According to the at least one first floating-point number, the values ​​of the exponent bits and the mantissa bits corresponding to the second floating-point number are determined to convert the at least one first floating-point number into a corresponding number of second floating-point numbers.

16. The method according to claim 15, characterized in that The receiving at least one first floating point number and converting the at least one first floating point number into a corresponding number of second floating point numbers also includes: Determine the mantissa of the second floating-point number according to the total number of digits C of the set second floating-point number and the sign bit of the second floating-point number; Each of the second floating-point numbers includes a 1-bit sign bit, N-bit exponent bits and CN-1-bit mantissa bits, C and N are integers greater than or equal to 1, and C is the total number of bits of the second floating-point number.

17. The method according to claim 13 or 16, characterized in that The number of exponent bits N in the second floating point number is: N=log2(E max -AND min ) / 2, Among them, E max is the maximum value of E among at least one first floating-point number, E min is the minimum value of E in at least one first floating-point number; E is the value of the K1-bit exponent bit of the first floating-point number.

18. The method according to claim 15, characterized in that Determining the value of the exponent bit and the value of the mantissa bit in the second floating point number according to the at least one first floating point number includes: The value E' of the N-bit exponent is determined as follows, E′=E-B+A, Wherein, E is the value of the K1-bit exponent bit of the first floating-point number, B is the offset of the exponent bit of the first floating-point number, and A is the exponent base of the second floating-point number, and the expression is: A=(E max +E min ) / 2, E max is the maximum value of E among at least one first floating-point number, E min is the minimum value of E in at least one first floating-point number; The value of the CN-1-bit mantissa of the second floating-point number is equal to the first CN-1 bit of the K2-bit mantissa of the first floating-point number; the sign bit of each of the second floating-point numbers is equal to the sign bit of the first floating-point number.

19. The method according to claim 13, characterized in that The method further comprises: A second floating point number is received and the second floating point number is converted into a first floating point number.

20. The method according to claim 19, characterized in that The converting the second floating point number into a first floating point number comprises: Setting the sign bit of the first floating point number to be equal to the sign bit of the second floating point number; The value of the first CN-1 bit of the K2-bit mantissa of the first floating point number is set to be equal to the CN-1-bit mantissa of the second floating point number, and the last K2+1+NC bit of the K2-bit mantissa of the first floating point number is set to 0; Determine the value E of the K1-bit exponent bit of the first floating point number according to the relationship E′=E−B+A between the value E′ of the N-bit exponent bit of the second floating point number and the value E of the K1-bit exponent bit of the first floating point number; Among them, B is the offset of the exponent bit of the first floating-point number, A is the exponent base of the second floating-point number, N bits are the exponent bits of the second floating-point number, C is the total number of bits of the second floating-point number, and C and N are integers greater than or equal to 1.

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