A circuit and a chip

Abstract

The embodiment of the present invention relates to an electrostatic protection circuit design, and discloses a circuit, including: an internal circuit, a CDM protection unit, and a clamping circuit; the CDM protection unit includes a first diode, a second diode, a first capacitor, a first resistor module, and a first NMOS transistor; the cathode and anode of the first diode are respectively coupled to the power supply end and the cathode of the second diode, and the anode and anode of the second diode are respectively coupled to the ground end and the first connection point; the two ends of the first capacitor are respectively coupled to the power supply end and the first resistor module, the other end of the first resistor module is coupled to the ground end, the gate of the first NMOS transistor is coupled to the first resistor module and the connection end of the first capacitor, and the drain and source of the first NMOS transistor are respectively coupled to the power supply end and the ground end; the first connection point is electrically connected to the input end, and the CDM protection unit is arranged adjacent to the internal circuit. The circuit and chip provided by the present invention can effectively realize the CDM electrostatic protection of the internal circuit.

Description

Technical Field

[0001] The embodiments of the present invention relate to the design of an electrostatic protection circuit for an integrated circuit, and more particularly to a circuit and a chip. Background Art

[0002] Integrated circuits are easily subjected to destructive electrostatic discharge (ESD) during manufacturing or use, or in final applications, which can damage the integrated circuits. ESD is usually generated by high voltage potential (e.g., several kilovolts) discharge, and results in short-duration high current pulses. ESD test models are usually divided into three categories. The first category is caused by human contact with ICs. Usually, HBM (human body model) type ESD protection circuits can be made for this type of ESD, and the rise time of HBM type ESD pulses is about 10ns; the second category is caused by mechanical equipment contact with ICs. Usually, MM (machine model) type ESD protection circuits can be made for this type of ESD; the third category is caused by the charge of the IC itself, and its discharge can occur through a single pin of the IC. This type of ESD can be made into CDM (charged-device-model) type ESD protection circuits for discharge protection, and the rise time of CDM type ESD pulses is even less than 1ns.

[0003] The inventors have found that there are at least the following problems in the prior art: the manufacturing process of modern semiconductors is becoming more and more advanced, the channel length is becoming shorter and shorter, the junction depth is becoming shallower and shallower, and the application of silicide and LDD (lightly doped drain) structure has led to the oxide layer becoming thinner and thinner, and the ESD design window is becoming smaller and smaller. The breakdown voltage of the oxide layer of the NMOS transistor or PMOS transistor of the input buffer will be lower than the breakdown voltage of the NMOS transistor or PMOS transistor used for CDM electrostatic protection. When ESD occurs, the oxide layer of the NMOS transistor or PMOS transistor of the input buffer will be broken down before the NMOS transistor or PMOS transistor used for CDM electrostatic protection. The original ESD design window no longer exists, and thus the CDM electrostatic protection effect cannot be well achieved. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a circuit and a chip, which can reduce the trigger voltage of the electrostatic protection circuit, thereby effectively realizing CDM electrostatic protection of the internal circuit.

[0005] To solve the above technical problems, an embodiment of the present invention provides a circuit, including: an input terminal, a power supply terminal, a ground terminal, an internal circuit, a CDM protection unit for electrostatic protection of the internal circuit, and a clamping circuit coupled to the power supply terminal and the ground terminal; the CDM protection unit includes a first diode, a second diode, a first capacitor, a first resistor module and a first NMOS transistor; the cathode of the first diode is coupled to the power supply terminal, the anode of the first diode is coupled to the cathode of the second diode, the anode of the second diode is coupled to the ground terminal, and the cathode of the second diode is coupled to a first connection point; the first end of the first capacitor is coupled to the power supply terminal, the second end of the first capacitor is coupled to the first end of the first resistor module, the second end of the first resistor module is coupled to the ground terminal, the gate of the first NMOS transistor is coupled to the first end of the first resistor module, and the drain and source of the first NMOS transistor are coupled to the power supply terminal and the ground terminal respectively; wherein the first connection point is electrically connected to the input terminal, and the CDM protection unit is arranged adjacent to the internal circuit.

[0006] An embodiment of the present invention further provides a chip, comprising: an input terminal, a power supply terminal, a ground terminal, an internal circuit, and a CDM protection unit for providing electrostatic protection to the internal circuit; the CDM protection unit comprises a first diode, a second diode, a first capacitor, a first resistance module and a first NMOS transistor; the cathode of the first diode is coupled to the power supply terminal, the anode of the first diode is coupled to the cathode of the second diode, the anode of the second diode is coupled to the ground terminal, and the cathode of the second diode is coupled to a first connection point; the first end of the first capacitor is coupled to the power supply terminal, the second end of the first capacitor is coupled to the first end of the first resistance module, the second end of the first resistance module is coupled to the ground terminal, the gate of the first NMOS transistor is coupled to the first end of the first resistance module, and the drain and source of the first NMOS transistor are coupled to the power supply terminal and the ground terminal, respectively; wherein the first connection point is electrically connected to the input terminal, and the CDM protection unit is arranged adjacent to the internal circuit.

[0007] Compared with the prior art, the clamping circuit of the embodiment of the present invention is used to discharge the electrostatic current between the power supply terminal and the ground terminal of the entire chip, and the CDM protection unit is used to provide electrostatic protection for the internal circuit. Specifically, regarding the working state of the CDM protection unit, there can be two states: normal operation and ESD. In normal operation, the gate of the first NMOS transistor is coupled to the ground terminal through the first resistor module, and the first NMOS transistor is turned off. At this time, the CDM protection unit does not affect the operation of the internal circuit, ensuring the normal operation of the internal circuit. When ESD occurs, the electrostatic discharge path either discharges the electrostatic current through a simple first diode or a second diode, or discharges the electrostatic current through a combination circuit composed of the first diode and the first NMOS transistor or a combination circuit composed of the first NMOS transistor and the second diode. If the electrostatic current is discharged through a simple first diode or a second diode, since the turn-on voltage of the first diode and the second diode is lower than the breakdown voltage of the oxide layer of the internal circuit, the CDM electrostatic protection of the internal circuit is effectively realized. If the electrostatic current is discharged through the combination circuit composed of the first diode and the first NMOS transistor or the combination circuit composed of the second diode and the first NMOS transistor, since the first NMOS transistor adopts the gate coupling effect, the trigger voltage is relatively low, so that the trigger voltage of the combination circuit composed of the first diode and the first NMOS transistor or the combination circuit composed of the second diode and the first NMOS transistor is lower than the breakdown voltage of the oxide layer of the internal circuit, and the original ESD design window is restored, thereby effectively realizing the CDM electrostatic protection of the internal circuit. At the same time, since the CDM protection unit is specifically for electrostatic protection of the internal circuit, the CDM protection unit can be set near the internal circuit, so that the electrostatic current can be discharged through the first NMOS transistor. Since the first NMOS transistor is directly close to the internal circuit, the CDM static electricity is more easily discharged quickly through the first NMOS transistor. The short distance and small parasitic resistance can ensure that the voltage difference on both sides of the oxide layer of the internal circuit is small, further ensuring the CDM electrostatic protection effect of the internal circuit.

[0008] In addition, the first resistance module includes a second NMOS transistor and a first resistor, the gate of the second NMOS transistor is coupled to the power supply terminal via the first resistor, the drain of the second NMOS transistor is the first terminal of the first resistance module, and the source of the second NMOS transistor is the second terminal of the first resistance module. Compared with the method of directly using a resistor to couple the gate and the ground terminal of the first NMOS transistor, using the second NMOS transistor and the first resistor as the first resistance module to couple the gate and the ground terminal of the first NMOS transistor can reduce the volume of the first resistance module, thereby better adapting to a smaller ESD design window.

[0009] In addition, the clamping circuit includes a second capacitor, a second resistor module and a third NMOS transistor, the first end of the second capacitor is coupled to the power supply end, the second end of the second capacitor is coupled to the first end of the second resistor module, the second end of the second resistor module is coupled to the ground end, the gate of the third NMOS transistor is coupled to the first end of the second resistor module, the drain and source of the third NMOS transistor are coupled to the power supply end and the ground end respectively, and the second capacitor, the second resistor module and the third NMOS transistor are arranged adjacent to the power supply end and the ground end.

[0010] In addition, the first connection point is electrically connected to the input terminal through a protection resistor.

[0011] In addition, a third diode and a fourth diode are also included, wherein the cathode of the third diode is coupled to the power supply terminal, the anode of the third diode is coupled to the cathode of the fourth diode, the anode of the fourth diode is coupled to the ground terminal, the cathode of the fourth diode is coupled to the input terminal, and the third diode and the fourth diode are arranged adjacent to the input terminal.

[0012] In addition, the internal circuit includes a PMOS transistor and a fourth NMOS transistor, the source of the PMOS transistor is coupled to the power supply terminal, the drain of the PMOS transistor is coupled to the drain of the fourth NMOS transistor, the source of the fourth NMOS transistor is coupled to the ground terminal, and the gate of the PMOS transistor and the gate of the fourth NMOS transistor are both coupled to the first connection point. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0014] Figure 1 is a circuit diagram of a circuit provided by a first embodiment of the present invention;

[0015] Figure 2 is a circuit diagram of a CDM protection unit provided in a first embodiment of the present invention;

[0016] Figure 3 yes Figure 1 Schematic diagram of the relative position of the circuit shown in the chip. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the following will be described in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present invention, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented.

[0018] A first embodiment of the present invention relates to a circuit, such as Figure 1 , Figure 2 As shown, it includes: an input terminal input, a power supply terminal VDD, a ground terminal VSS, an internal circuit 11, a CDM protection unit 12 for electrostatic protection of the internal circuit 11, and a clamp circuit 13 coupled to the power supply terminal VDD and the ground terminal VSS; the CDM protection unit 12 includes a first diode Dp1, a second diode Dn1, a first capacitor Cr, a first resistor module 14 and a first NMOS transistor Mnr; the cathode of the first diode Dp1 is coupled to the power supply terminal VDD, the anode of the first diode Dp1 is coupled to the cathode of the second diode Dn1, the anode of the second diode Dn1 is coupled to the ground terminal VSS is coupled, the cathode of the second diode Dn1 is coupled to the first connection point 15; the first end of the first capacitor Cr is coupled to the power supply terminal VDD, the second end of the first capacitor Cr is coupled to the first end of the first resistor module 14, the second end of the first resistor module 14 is coupled to the ground terminal VSS, the gate of the first NMOS transistor Mnr is coupled to the first end of the first resistor module 14, the drain and source of the first NMOS transistor Mnr are coupled to the power supply terminal VDD and the ground terminal VSS respectively; wherein the first connection point 15 is electrically connected to the input terminal input, and the CDM protection unit 12 is arranged adjacent to the internal circuit 11.

[0019] In practical applications, the above circuit structure can be applied to CDM electrostatic protection of input circuits of advanced processes with relatively thin oxide layers of semiconductor integrated circuits, and can be applied to CDM electrostatic protection of various semiconductor integrated circuits such as logic, analog and various memory chips.

[0020] In this embodiment, the first resistance module 14 includes a second NMOS transistor Mr and a first resistor R1, the gate of the second NMOS transistor Mr is coupled to the power supply terminal VDD via the first resistor R1, the drain of the second NMOS transistor Mr is the first end of the first resistance module 14, and the source of the second NMOS transistor Mr is the second end of the first resistance module 14, that is, the first resistance module 14 is a normally open MOS tube. Specifically, in normal operation, the gate of the second NMOS transistor Mr is connected to the power supply terminal VDD via the first resistor R1, so the second NMOS transistor Mr is grounded, so that the gate of the first NMOS transistor Mnr is grounded, so that the first NMOS The OS transistor Mnr is in the off state, at which time the first NMOS transistor Mnr does not affect the normal operation of the circuit; when an electrostatic pulse is generated, causing the potential of the input terminal input to increase, the first diode Dp1 is turned on, causing the voltage value of the power supply terminal VDD to increase. Due to the existence of the first capacitor Cr, the gate voltage of the first NMOS transistor Mnr is correspondingly increased, triggering the first NMOS transistor Mnr to turn on, so that the electrostatic current is discharged through the first NMOS transistor Mnr; when an electrostatic pulse is generated, causing the potential of the input terminal input to decrease, the second diode Dn1 is triggered to turn on, correspondingly reducing the source voltage of the first NMOS transistor Mnr. However, due to the existence of the first capacitor Cr, the gate of the first NMOS transistor will not decrease instantly, that is, the gate voltage of the first NMOS transistor Mnr is higher than the source voltage, and the first NMOS transistor Mnr is turned on, so that the electrostatic current can be discharged. Of course, the first resistance module 14 can also be a pure resistor. The specific process of discharging the electrostatic current is similar to the above and will not be repeated here. It is worth mentioning that compared with the method of directly using a resistor to couple the gate and the ground terminal VSS of the first NMOS transistor Mnr, in this embodiment, the second NMOS transistor Mr and the first resistor R1 are used as the first resistance module 14 to couple the gate and the ground terminal VSS of the first NMOS transistor Mnr, which can reduce the volume of the first resistance module 14 (if a resistor is used as the first resistance module 14, the required resistance value is larger, so the volume is larger), so as to better adapt to the smaller ESD design window.

[0021] In practical applications, the clamping circuit 13 includes a second capacitor C, a second resistor module R and a third NMOS transistor Mn. The first end of the second capacitor C is coupled to the power supply terminal VDD, the second end of the second capacitor C is coupled to the first end of the second resistor module R, the second end of the second resistor module R is coupled to the ground terminal VSS, the gate of the third NMOS transistor Mn is coupled to the first end of the second resistor module R, the drain and source of the third NMOS transistor Mn are respectively coupled to the power supply terminal VDD and the ground terminal VSS, and the clamping circuit 13 can be arranged near the power supply terminal VDD and the ground terminal VSS to discharge the power supply terminal VDD and the ground terminal VSS of the entire chip. Specifically, in normal operation, the gate of the third NMOS transistor Mn is coupled to the ground terminal VSS via the second resistor module R, so that the third NMOS transistor Mn is in a disconnected state. At this time, the third NMOS transistor Mn does not affect the operation of the circuit; when an electrostatic pulse is generated, causing the potential of the power supply terminal VDD to increase, the gate voltage of the third NMOS transistor Mn is increased accordingly, triggering the third NMOS transistor Mn to turn on, so that the electrostatic current is discharged through the third NMOS transistor Mn, thereby realizing the discharge of the electrostatic current between the power supply terminal VDD and the ground terminal VSS of the entire chip.

[0022] Optionally, the circuit may further include an IO protection circuit 16, wherein the IO protection circuit 16 includes a third diode Dp and a fourth diode Dn, wherein the cathode of the third diode Dp is coupled to the power supply terminal VDD, the anode of the third diode Dp is coupled to the cathode of the fourth diode Dn, the anode of the fourth diode Dn is coupled to the ground terminal VSS, the cathode of the fourth diode Dn is coupled to the input terminal input, and the third diode Dp and the fourth diode Dn may be arranged near the input terminal input, thereby forming an electrostatic protection of the entire chip in combination with the clamping circuit 13. Specifically, during normal operation, due to the electric The potential of the source terminal VDD is higher than the potential of the ground terminal VSS, so that the voltage of the positive electrode of the third diode Dp and the fourth diode Dn is not higher than the voltage of the negative electrode, so that the third diode Dp and the fourth diode Dn are both in a disconnected state. At this time, the third diode Dp and the fourth diode Dn do not affect the operation of the circuit; when an electrostatic pulse is generated, causing the potential of the ground terminal VSS to increase, the electrostatic current causes the third diode Dp and the fourth diode Dn to be turned on, so that the electrostatic current is discharged through the third diode Dp and the fourth diode Dn, thereby realizing the discharge of the electrostatic current between the power supply terminal VDD and the ground terminal VSS of the entire chip.

[0023] Specifically, the internal circuit 11 includes a PMOS transistor Mp2 and a fourth NMOS transistor Mn2, the source of the PMOS transistor Mp2 is coupled to the power supply terminal VDD, the drain of the PMOS transistor Mp2 is coupled to the drain of the fourth NMOS transistor Mn2, the source of the fourth NMOS transistor Mn2 is coupled to the ground terminal VSS, the gate of the PMOS transistor and the gate of the fourth NMOS transistor Mn2 are both coupled to the first connection point 15, and the internal circuit 11 is an element to be protected, which is an input buffer. Ordinary technicians in this field can understand that the internal circuit 11 may also be other internal circuits that receive input signals.

[0024] Optionally, the first connection point 15 is electrically connected to the input terminal input through a protection resistor Rin, and the protection resistor Rin is used for voltage division (or current blocking) to prevent excessive transmission of ESD in HBM or other modes to the internal circuit and damage it.

[0025] Compared with the prior art, the clamping circuit 13 of the embodiment of the present invention is used to discharge the electrostatic current between the power supply terminal VDD and the ground terminal VSS of the entire chip, and the CDM protection unit 12 is used to provide electrostatic protection for the internal circuit 11. Specifically, regarding the working state of the CDM protection unit 12, there can be two states: normal operation and ESD occurrence. In normal operation, the gate of the first NMOS transistor Mnr is coupled to the ground terminal VSS through the first resistor module 14, so that the first NMOS transistor Mnr is in a disconnected state. At this time, the CDM protection unit 12 does not affect the operation of the internal circuit 11, ensuring the normal operation of the internal circuit 11. When an electrostatic pulse is generated, the electrostatic discharge path either discharges the electrostatic current through the simple first diode Dp1 or the second diode Dn1, or discharges the electrostatic current through a combination circuit composed of the first diode Dp1 and the first NMOS transistor Mnr or a combination circuit composed of the first NMOS transistor Mnr and the second diode Dn1. If the electrostatic current is discharged through the simple first diode Dp1 or the second diode Dn1, since the conduction voltage of the first diode Dp1 and the second diode Dn1 is lower than the breakdown voltage of the oxide layer of the internal circuit 11, the CDM electrostatic protection of the internal circuit 11 is effectively achieved. If the electrostatic current is discharged through the combination circuit composed of the first diode Dp1 and the first NMOS transistor Mnr or the combination circuit composed of the second diode Dn1 and the first NMOS transistor Mnr, since the first NMOS transistor Mnr adopts the gate coupling effect, the trigger voltage is relatively low, so that the trigger voltage of the combination circuit composed of the first diode Dp1 and the first NMOS transistor Mnr or the combination circuit composed of the second diode Dn1 and the first NMOS transistor Mnr is lower than the breakdown voltage of the oxide layer of the internal circuit 11, the original ESD design window is restored, and the CDM electrostatic protection of the internal circuit 11 is effectively achieved. At the same time, since the CDM protection unit 12 is specifically used to perform electrostatic protection on the internal circuit 11, the CDM protection unit 12 can be set near the internal circuit 11, so that the electrostatic current can be discharged through the first NMOS transistor Mnr. Since the first NMOS transistor Mnr is directly close to the internal circuit 11, the CDM static electricity is more easily discharged quickly through the first NMOS transistor Mnr. The short distance and small parasitic resistance can ensure that the voltage difference on both sides of the oxide layer of the internal circuit 11 is small, thereby further ensuring the CDM electrostatic protection effect of the internal circuit 11.

[0026] A second embodiment of the present invention relates to a chip 100, such as Figure 3As shown, it includes: an input terminal input, a power supply terminal VDD, a ground terminal VSS, an internal circuit 11, and a CDM protection unit 12 for electrostatic protection of the internal circuit 11; the CDM protection unit 12 includes a first diode Dp1, a second diode Dn1, a first capacitor Cr, a first resistor module 14 and a first NMOS transistor Mnr; the cathode of the first diode Dp1 is coupled to the power supply terminal VDD, the anode of the first diode Dp1 is coupled to the cathode of the second diode Dn1, the anode of the second diode Dn1 is coupled to the ground terminal VSS, and the second diode Dn 1 is coupled to the first connection point 15; the first end of the first capacitor Cr is coupled to the power supply terminal VDD, the second end of the first capacitor Cr is coupled to the first end of the first resistor module 14, the second end of the first resistor module 14 is coupled to the ground terminal VSS, the gate of the first NMOS transistor Mnr is coupled to the first end of the first resistor module 14, the drain and source of the first NMOS transistor Mnr are coupled to the power supply terminal VDD and the ground terminal VSS respectively; wherein the first connection point 15 is electrically connected to the input terminal input, and the CDM protection unit 12 is arranged adjacent to the internal circuit 11.

[0027] Optionally, the chip 100 further includes a clamping circuit 13 coupled to the input terminal input, the power supply terminal VDD and the ground terminal VSS. The clamping circuit 13 is arranged adjacent to the power supply terminal VDD and the ground terminal VSS. Further, the clamping circuit 13 includes a second capacitor C, a second resistor module R and a third NMOS transistor Mn. The first end of the second capacitor C is coupled to the power supply terminal VDD, the second end of the second capacitor C is coupled to the first end of the second resistor module R, the second end of the second resistor module R is coupled to the ground terminal VSS, the gate of the third NMOS transistor Mn is coupled to the first end of the second resistor module R, the drain and source of the third NMOS transistor Mn are coupled to the power supply terminal VDD and the ground terminal VSS respectively, and the second capacitor C, the second resistor module R and the third NMOS transistor Mn are coupled to the power supply terminal VDD and the ground terminal VSS respectively. The power supply terminal VDD and the ground terminal VSS are arranged adjacent to each other, and the clamping circuit 13 is used to discharge the electrostatic current between the power supply terminal VDD and the ground terminal VSS of the entire chip 100. Specifically, in normal operation, the gate of the third NMOS transistor Mn is coupled to the ground terminal VSS via the second resistor module R, so that the third NMOS transistor Mn is in a disconnected state. At this time, the third NMOS transistor Mn does not affect the operation of the circuit; when an electrostatic pulse is generated, causing the potential of the power supply terminal VDD to increase, the gate voltage of the third NMOS transistor Mn is increased, triggering the third NMOS transistor Mn to turn on, so that the electrostatic current is discharged through the third NMOS transistor Mn, thereby achieving the discharge of the electrostatic current between the power supply terminal VDD and the ground terminal VSS of the entire chip 100.

[0028] Optionally, the first connection point 15 is electrically connected to the input terminal input through a protection resistor Rin, and the protection resistor Rin is used for voltage division (or current blocking) to prevent excessive transmission of ESD in HBM or other modes to the internal circuit and damage it.

[0029] Optionally, the chip 100 further includes a third diode Dp and a fourth diode Dn, the cathode of the third diode Dp is coupled to the power supply terminal VDD, the anode of the third diode Dp is coupled to the cathode of the fourth diode Dn, the anode of the fourth diode Dn is coupled to the ground terminal VSS, the cathode of the fourth diode Dn is coupled to the input terminal input, the third diode Dp and the fourth diode Dn are arranged adjacent to the input terminal input, the third diode Dp and the fourth diode Dn are combined with the clamping circuit 13 to form the electrostatic protection of the entire chip 100, specifically, in normal operation, due to the power supply terminal VDD The potential of the third diode Dp and the fourth diode Dn is higher than the potential of the ground terminal VSS, so that the voltage of the positive electrode of the third diode Dp and the fourth diode Dn is not higher than the voltage of the negative electrode, so that the third diode Dp and the fourth diode Dn are both in a disconnected state. At this time, the third diode Dp and the fourth diode Dn do not affect the operation of the circuit; when an electrostatic pulse is generated, causing the potential of the ground terminal VSS to increase, the electrostatic current causes the third diode Dp and the fourth diode Dn to be turned on, so that the electrostatic current is discharged through the third diode Dp and the fourth diode Dn, thereby realizing the discharge of the electrostatic current between the power supply terminal VDD and the ground terminal VSS of the entire chip 100.

[0030] It is not difficult to find that this embodiment is an embodiment of the chip 100 corresponding to the first embodiment, and this embodiment can be implemented in conjunction with the first embodiment. The relevant technical details mentioned in the first embodiment are still valid in this embodiment, and in order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the first embodiment.

[0031] Compared with the prior art, the clamping circuit 13 of the embodiment of the present invention is used to discharge the electrostatic current between the power supply terminal VDD and the ground terminal VSS of the entire chip 100, and the CDM protection unit 12 is used to provide electrostatic protection for the internal circuit 11. Specifically, regarding the working state of the CDM protection unit 12, there can be two states: normal operation and ESD occurrence. In normal operation, the gate of the first NMOS transistor Mnr is coupled to the ground terminal VSS through the first resistor module 14, and the first NMOS transistor Mnr is turned off. At this time, the CDM protection unit 12 does not affect the operation of the internal circuit 11, ensuring the normal operation of the internal circuit 11. When ESD occurs, the electrostatic discharge path either discharges the electrostatic current through the simple first diode Dp1 or the second diode Dn1, or discharges the electrostatic current through a combination circuit composed of the first diode Dp1 and the first NMOS transistor Mnr or a combination circuit composed of the first NMOS transistor Mnr and the second diode Dn1. If the electrostatic current is discharged through the simple first diode Dp1 or the second diode Dn1, since the conduction voltage of the first diode Dp1 and the second diode Dn1 is lower than the breakdown voltage of the oxide layer of the internal circuit 11, the CDM electrostatic protection of the internal circuit 11 is effectively achieved. If the electrostatic current is discharged through the combination circuit composed of the first diode Dp1 and the first NMOS transistor Mnr or the combination circuit composed of the second diode Dn1 and the first NMOS transistor Mnr, since the first NMOS transistor Mnr adopts the gate coupling effect, the trigger voltage is relatively low, so that the trigger voltage of the combination circuit composed of the first diode Dp1 and the first NMOS transistor Mnr or the combination circuit composed of the second diode Dn1 and the first NMOS transistor Mnr is also lower than the breakdown voltage of the oxide layer of the internal circuit 11, and the original ESD design window is restored, thereby effectively achieving the CDM electrostatic protection of the internal circuit 11. At the same time, since the CDM protection unit 12 is specifically used to perform electrostatic protection on the internal circuit 11, the CDM protection unit 12 can be set near the internal circuit 11, so that the electrostatic current can be discharged through the first NMOS transistor Mnr. Since the first NMOS transistor Mnr is directly close to the internal circuit 11, the CDM static electricity is more easily discharged quickly through the first NMOS transistor Mnr, and the short distance and small parasitic resistance can ensure that the voltage difference on both sides of the oxide layer of the internal circuit 11 is small, further ensuring the CDM electrostatic protection effect of the internal circuit 11.

[0032] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present invention, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present invention.

Claims

1. A circuit, characterized in that: include: An input terminal, a power terminal, a ground terminal, an internal circuit, a CDM protection unit for providing electrostatic protection to the internal circuit, and a clamping circuit coupled to the power terminal and the ground terminal; The CDM protection unit includes a first diode, a second diode, a first capacitor, a first resistor module and a first NMOS transistor; The cathode of the first diode is coupled to the power supply terminal, the anode of the first diode is coupled to the cathode of the second diode, the anode of the second diode is coupled to the ground terminal, and the cathode of the second diode is coupled to the first connection point; The first end of the first capacitor is coupled to the power supply end, the second end of the first capacitor is coupled to the first end of the first resistor module, the second end of the first resistor module is coupled to the ground end, the gate of the first NMOS transistor is coupled to the first end of the first resistor module, and the drain and source of the first NMOS transistor are coupled to the power supply end and the ground end respectively; Wherein, the first connection point is electrically connected to the input terminal, and the CDM protection unit is arranged adjacent to the internal circuit; The first resistance module includes a second NMOS transistor and a first resistor, the gate of the second NMOS transistor is coupled to the power supply end via the first resistor, the drain of the second NMOS transistor is the first end of the first resistance module, and the source of the second NMOS transistor is the second end of the first resistance module.

2. The circuit according to claim 1, characterized in that The clamping circuit includes a second capacitor, a second resistance module and a third NMOS transistor, the first end of the second capacitor is coupled to the power supply end, the second end of the second capacitor is coupled to the first end of the second resistance module, the second end of the second resistance module is coupled to the ground end, the gate of the third NMOS transistor is coupled to the first end of the second resistance module, and the drain and source of the third NMOS transistor are coupled to the power supply end and the ground end, respectively.

3. The circuit according to claim 1, characterized in that The first connection point is electrically connected to the input terminal through a protection resistor.

4. The circuit according to claim 3, characterized in that It also includes a third diode and a fourth diode, wherein the cathode of the third diode is coupled to the power supply end, the anode of the third diode is coupled to the cathode of the fourth diode, the anode of the fourth diode is coupled to the ground end, and the cathode of the fourth diode is coupled to the input end.

5. The circuit according to claim 1, characterized in that The internal circuit includes a PMOS transistor and a fourth NMOS transistor, the source of the PMOS transistor is coupled to the power supply terminal, the drain of the PMOS transistor is coupled to the drain of the fourth NMOS transistor, the source of the fourth NMOS transistor is coupled to the ground terminal, and the gate of the PMOS transistor and the gate of the fourth NMOS transistor are both coupled to the first connection point.

6. A chip, characterized in that: include: An input terminal, a power supply terminal, a ground terminal, an internal circuit, and a CDM protection unit for providing electrostatic protection to the internal circuit; The CDM protection unit includes a first diode, a second diode, a first capacitor, a first resistor module and a first NMOS transistor; The cathode of the first diode is coupled to the power supply terminal, the anode of the first diode is coupled to the cathode of the second diode, the anode of the second diode is coupled to the ground terminal, and the cathode of the second diode is coupled to the first connection point; The first end of the first capacitor is coupled to the power supply end, the second end of the first capacitor is coupled to the first end of the first resistor module, the second end of the first resistor module is coupled to the ground end, the gate of the first NMOS transistor is coupled to the first end of the first resistor module, and the drain and source of the first NMOS transistor are coupled to the power supply end and the ground end respectively; Wherein, the first connection point is electrically connected to the input terminal, and the CDM protection unit is arranged adjacent to the internal circuit; The first resistance module includes a second NMOS transistor and a first resistor, the gate of the second NMOS transistor is coupled to the power supply end via the first resistor, the drain of the second NMOS transistor is the first end of the first resistance module, and the source of the second NMOS transistor is the second end of the first resistance module.

7. The chip according to claim 6, characterized in that: It also includes a clamping circuit coupled to the input terminal, the power terminal and the ground terminal, and the clamping circuit is arranged adjacent to the power terminal and the ground terminal.

8. The chip according to claim 7, characterized in that: The clamping circuit includes a second capacitor, a second resistor module and a third NMOS transistor, wherein the first end of the second capacitor is coupled to the power supply end, the second end of the second capacitor is coupled to the first end of the second resistor module, the second end of the second resistor module is coupled to the ground end, the gate of the third NMOS transistor is coupled to the first end of the second resistor module, the drain and source of the third NMOS transistor are respectively coupled to the power supply end and the ground end, and the second capacitor, the second resistor module and the third NMOS transistor are arranged adjacent to the power supply end and the ground end.

9. The chip according to claim 6, characterized in that: The first connection point is electrically connected to the input terminal through a protection resistor.

10. The chip according to claim 9, characterized in that: It also includes a third diode and a fourth diode, wherein the cathode of the third diode is coupled to the power supply terminal, the anode of the third diode is coupled to the cathode of the fourth diode, the anode of the fourth diode is coupled to the ground terminal, the cathode of the fourth diode is coupled to the input terminal, and the third diode and the fourth diode are arranged adjacent to the input terminal.

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