Managing Power in Integrated Circuits for High-Speed ​​Activation

Abstract

A vehicle and a method of controlling the vehicle. Controlling the vehicle includes: providing an activation signal from an activation port for activating control of at least one of the one or more electronically controllable devices during a high-speed activation time interval; and managing power consumed by an integrated circuit including two or more processor cores during the high-speed activation time interval. The management includes: receiving the activation signal from the activation port; in response to the activation signal, executing at least a portion of stored code by a first subset of processor cores less than all of the processor cores in the processor cores at a first power level; and after the high-speed activation time interval, executing at least a portion of the stored code by a second subset of one or more processor cores in the processor cores at a second power level lower than the first power level.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application Serial No. 62 / 875,439, filed on July 17, 2019, entitled “FREQUENCY SCALING TO REDUCE BOOTTIME,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to managing power in an integrated circuit for high-speed activation. Background Art

[0004] In some processors, the clock frequency is dynamically increased relative to the default clock frequency in order to provide higher performance under certain conditions. For example, such a clock frequency increase may occur after the computing system has booted an operating system and is executing tasks that require additional processing power. The clock frequency increase is typically subject to various power or temperature operating ranges of the digital circuitry and other circuitry (e.g., circuitry of a system on a chip (SoC), CPU, GPU, or other integrated circuit) that includes one or more cores of the processor.

[0005] The above description is presented as general background related to the technical field and should not be construed as an admission that any of the information contained therein constitutes prior art with respect to the present patent application. Summary of the invention

[0006] In one aspect, in general, a vehicle includes: one or more electronically controllable devices; a controller configured to manage power consumed by an integrated circuit in the controller during a high-speed activation time interval, the controller configured to control at least one of the electronically controllable devices in the vehicle in response to receiving an activation signal, the controller including: two or more processor cores arranged on the integrated circuit, a storage module for storing code executable by two or more of the processor cores, and an overdrive manager configured to cause at least a portion of the stored code to be executed at a first power level by a first subset of processor cores less than all of the processor cores in the processor cores during the high-speed activation time interval, and at least a portion of the stored code to be executed at a second power level lower than the first power level by a second subset of one or more of the processor cores in the processor cores after the high-speed activation time interval; and an activation port configured to provide an activation signal for activating the controller's control of at least one of the electronically controllable devices.

[0007] Aspects may include one or more of the following features.

[0008] The controller is further configured to execute at least a portion of the stored code at a second power level by the processor cores in the first subset after the high-speed activation time interval.

[0009] The first subset includes a single processor core and the second subset includes one or more additional processor cores.

[0010] The controller is further configured to prevent execution of any of the stored code by any processor core in the second subset during the high-speed activation time interval.

[0011] The first subset and the second subset include different processor cores.

[0012] The storage module includes a solid state drive.

[0013] The overdrive manager is configured to cause execution at the first power level by increasing a frequency of a first clock signal generated by a clock in a processor core in the first subset to be higher than a second frequency of a second clock signal generated by a clock in a processor core in the second subset.

[0014] The overdrive manager is further configured to cause execution at the first power level by increasing the amplitude of the voltage of the first clock signal above a default voltage amplitude.

[0015] In another aspect, in general, a method for controlling a vehicle includes: providing an activation signal from an activation port for activating control of at least one of one or more electronically controllable devices during a high-speed activation time interval; and managing power consumed by an integrated circuit including two or more processor cores during the high-speed activation time interval. The management includes: receiving the activation signal from the activation port; in response to the activation signal, executing at least a portion of stored code by a first subset of processor cores less than all of the processor cores in the processor cores at a first power level; and after the high-speed activation time interval, executing at least a portion of the stored code by a second subset of one or more processor cores in the processor cores at a second power level lower than the first power level.

[0016] Aspects may include one or more of the following features.

[0017] Managing also includes executing at least a portion of the stored code at a second power level by the processor cores in the first subset after the high-speed activation time interval.

[0018] The first subset includes a single processor core and the second subset includes one or more additional processor cores.

[0019] Managing also includes preventing execution of any of the stored code by any processor core in the second subset during the high-speed activation time interval.

[0020] Executing a portion of the stored code by the first subset includes executing code for booting at least a portion of an operating system.

[0021] Executing a portion of the stored code by a processor core in the first subset after the high-speed activation time interval includes executing code within an operating system to control an electronically controllable device in a first subsystem of a vehicle, the first subsystem of the vehicle being associated with at least one of: a powertrain, steering, acceleration, or deceleration.

[0022] Executing a portion of the stored code by the processor cores in the second subset after the high-speed activation time interval includes executing code to control an electronically controllable device in a second subsystem of the vehicle different from the first subsystem of the vehicle.

[0023] The method also includes terminating the high-speed activation time interval in response to the indication that the directing has been completed.

[0024] Execution at the first power level includes increasing a first frequency of a first clock signal generated by a clock in a processor core in the first subset to be higher than a second frequency of a second clock signal generated by a clock in a processor core in the second subset.

[0025] Execution at the first power level includes increasing a magnitude of a voltage of the first clock signal above a default voltage magnitude.

[0026] The first frequency is increased to be at least 50% higher than the second clock frequency.

[0027] The first frequency is increased to at least twice the second clock frequency.

[0028] Aspects may have one or more of the following advantages.

[0029] When a computing system operates in some environments such as a vehicle, there may be more operational requirements than in other environments. For example, vehicles such as automobiles have various standards that require certain subsystems to be ready to operate (e.g., start driving) within a predetermined time period. For some cars, this time period is associated with the time it takes for an internal combustion engine (ICE) to start (e.g., less than 2 seconds), in some cases even if the car uses an alternative form of power other than an ICE (e.g., a battery). Many of the subsystems of the car need to be able to operate within the predetermined time period. Some of these subsystems are controlled by a controller. In order to meet the subsystem startup requirements, there are usually more stringent startup requirements for the controller, which usually includes a SoC with a processor core that needs to boot at least a portion of the operating system software. The startup (or "boot time") requirement for some SoCs is less than 100ms or less than 200ms. The boot time is measured from the time an activation signal is received. For example, the activation signal can be generated in response to a user's interaction with the car (such as turning a key or pressing a button). For some complex SoCs, it is a challenge to meet this requirement in a cost-effective manner. The technology described herein contributes to short boot time with minimal or no additional cost and minimal or no effect on the aging of the processor core of the SoC. For example, some processor cores are designed so that the internal circuit system and components can operate for at least a predetermined service life under certain assumptions of operating conditions. In some cases, one of these operating conditions is the amount of power dissipated over time and the associated stress on the components that accompanies such power consumption. One of the operating characteristics that affects power consumption is the clock frequency. In some cases, other characteristics also affect power consumption, such as voltage and associated current flow and resistive heating. Since the processor overdrive used to reduce the boot time does not require a long increase in the clock frequency, there is minimal stress increase on the processor components.

[0030] Other features and advantages will be apparent from the following description and from the drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, according to common practice, the various features of the drawings are not drawn to scale. Instead, the sizes of the various features are arbitrarily expanded or reduced for clarity.

[0032] Figure 1 is a schematic diagram of an example vehicle according to an embodiment of the present disclosure.

[0033] Figure 2 It is used for Figure 1A diagram of an example timing pattern for powering multiple processor cores in a control circuit system of a vehicle.

[0034] Figure 3 Is used for Figure 1 Flowchart of an example process for controlling high-speed activation of a processor core in a vehicle.

[0035] Figure 4 Included in deployment Figure 1 Schematic diagram of an example system-on-chip of a processor core in a vehicle. DETAILED DESCRIPTION

[0036] Figure 1 is a schematic diagram showing an example of a vehicle 100 in which various aspects, features, and elements described herein may be implemented according to an embodiment of the present disclosure. The vehicle 100 includes a communication network (or simply "network") that enables communication between different subsystems in the vehicle 100 and electronic control of electronically controllable devices within these subsystems. The network can have any of a variety of network topologies. In some implementations, the communication medium of the network includes a shared medium such as a bus, to which different nodes are connected. In some implementations, certain nodes are connected to other nodes (e.g., switching nodes) via point-to-point links. Figure 1 In the example of , the network includes multiple network segments that are configured to provide communication and control of multiple areas 102A-102C within the vehicle 100. The front area network segment 102A includes a switch 104A that serves as a gateway for the network segment 102A, the middle area network segment 102B includes a switch 104B that serves as a gateway for the network segment 102B, and the rear area network segment 102C includes a switch 104C that serves as a gateway for the network segment 102C. In this example, the front area network segment 102A and the rear area network segment 102C include respective device controllers 106A and 106B that provide control functions for various subsystems in the vehicle 100. In this example, the middle area network segment 102B is configured to enable communication with various sensor modules, but does not include communication with dedicated controllers. The controller 106A is connected to a network controller 108, which couples the controller 106A to the network via the switch 104A. The network controller 108 is configured to link the controller 106A to various subsystems and modules in the vehicle 100. One control function provided by the controller 106A is to temporarily overdrive the processor core at startup and selectively execute a portion of the software code while the processor core is overdriven. As described in more detail below, this overdrive function helps to start certain electronically controllable devices within the vehicle 100 more quickly.

[0037] In an embodiment of the present disclosure, for example, the controller and the switch are implemented using a system on chip (SoC) or other electronic circuit system including one or more processor cores. A given processor core can be configured as a general-purpose unit such as a central processing unit (CPU), a dedicated unit such as a graphics processing unit (GPU), and / or other forms of processing circuit systems. For example, some controllers are implemented using one or more dedicated processors, one or more digital signal processors, one or more microprocessors, one or more controllers, one or more microcontrollers, one or more integrated circuits, one or more application-specific integrated circuits (ASICs), one or more field programmable gate arrays, one or more programmable logic arrays, one or more programmable logic controllers, one or more state machines, or any combination thereof. The controller is capable of executing a program based on stored code, the stored code including code stored in a storage module, the storage module including any tangible non-transient computer-usable or computer-readable medium, which, for example, is capable of containing, storing, communicating or transmitting machine-readable instructions or any information associated therewith for use by the controller or in combination with the controller. For example, the storage module may include any suitable form of volatile or non-volatile memory, including one or more solid-state drives, one or more memory cards, one or more removable media, one or more read-only memories, one or more random access memories (one or more disks, including hard disks, floppy disks, optical disks, magnetic or optical cards, or any type of non-volatile medium suitable for storing electronic information), or any suitable combination thereof.

[0038] Examples of sensor module types suitable for inclusion in any of the areas of the vehicle include imaging / navigation sensors 110A (e.g., cameras, radars, LiDAR, rangefinders or other proximity sensors, speed sensors, accelerometers, infrared sensing, sound sensing (including ultrasonic sensors), GPS, etc.), and environmental / user interface sensors 110B (e.g., air flow, engine speed, acceleration, braking, traction, oxygen, fuel temperature, pressure, voltage, steering wheel position, seat position, eye tracking, etc.). The imaging / navigation sensors 110A provide data to the network via a communication bridge 112A, and the environmental / user interface sensors 110B provide data to the network via a communication bridge 112B. These communication bridges are configured according to a communication protocol to facilitate the transmission of messages, data, signals, or other information for operating and controlling the electronically controllable sensor modules.

[0039] Usually, there are many subsystems of the vehicle including electronic controllable devices, and the electronic controllable devices are also configured to be controlled by one or more controllers. For example, some of these subsystems are associated with the chassis, wheels or power transmission system (for example, including power source, suspension, drive shaft, axle and exhaust system) of the vehicle. The power source such as the combination of internal combustion engine, electric motor or internal combustion engine and electric motor can be operated to provide kinetic energy as motive force to one or more wheels. There can also be many driver controls (for example, for powering up / ignition, steering, acceleration and braking) and displays or other user interface input and output elements that communicate with the network. Moreover, the vehicle of the alternative type outside the automobile sometimes includes a subsystem for other types of propulsion, such as a propeller for an aircraft. Any one of the various modules of these subsystems can be an electronic controllable device, which is controlled at least in part based on a signal sent to or sent from one or more controllers. Communication nodes associated with these subsystems in different network segments communicate with other subsystems (such as, for example, the powertrain, wheels, or both) to control the vehicle 100 , such as to accelerate, decelerate, steer, or otherwise control the vehicle 100 .

[0040] There are various types of communication media that connect different nodes of the network. Switches and communication bridges can be interconnected by cables for transmitting encoded signals (e.g., signals encoded using the amplitude and / or phase of the transmission wave according to a suitable protocol). In some cases, different types of cables exist between different types of nodes, some of which may have different physical properties, such as length, bandwidth capacity, and / or shielding materials. For example, one type of cable 114 may be used between a sensor bridge and a switch, while another type of cable 116 may be used between different switches. In some embodiments, the cable includes one or more communication media, such as wires and / or optical fibers. Switches and communication bridges are configured to include circuit systems for providing appropriate functions according to a specific communication protocol in a layered protocol stack. For example, a PHY layer protocol may be used by a transceiver that includes a circuit system for transmitting a signal to a communication medium and a circuit system for receiving a signal from a communication medium. In some implementations, there are separate transmitter circuit systems and receiver circuit systems, as well as circuit systems for controlling whether a transmitter or receiver is actively accessing a communication medium. The MAC layer may be used by a media access controller that controls transceiver access to the communication medium. Other types of cables, such as cables for transmitting electrical power, are also typically included in the vehicle 100. For example, the control switches, controllers, and sensors may be configured to receive electrical power from the powertrain via the electrical transmission network.

[0041] Figure 2A set of timing diagrams are shown, where power as a function of time is shown for each of the four processor cores CORE1, CORE2, CORE3, and CORE4 within the integrated circuit of the controller 106A. As described in more detail below (refer to Figure 4 ), the clock frequency of the processor core is managed by the overdrive manager 418A, and the clock frequency is used to determine the rate at which the processor core performs calculations and the amount of power consumed to do so. In this example, in response to detecting a user interaction indicating an intention to activate (or "start" or "turn on") the vehicle 100, the user interface module 120 provides an activation signal 122 from an activation port on the user interface module 120. The user interaction can include any of a variety of actions, such as turning a key (e.g., in an ignition assembly or virtual ignition interface), pressing a button in the car or on a key fob or other form of remote control, speaking a command (into a microphone), making a gesture (in front of a camera), or completing a series of actions (e.g., a series of actions including opening and / or closing a driver's door).

[0042] The overdrive manager within the controller 106A is configured to manage the power consumed by a processor core on an integrated circuit (eg, SoC) during high-speed activation time intervals. Figure 2 In the example shown, the initial state of each of the four processor cores is an idle or off state in which a significant amount of power is not consumed. For example, the vehicle 100 may be parked and inactive. At time T1, an activation signal 122 is received by the controller 106A. In response, the controller 106A performs a high-speed activation process that temporarily overdrives CORE1 to selectively execute a portion of software code that performs a startup function. For example, in some implementations, CORE1 executes startup code that boots an operating system so that a control program can run within the operating system to control any number of electronically controllable devices of various subsystems in the vehicle 100 that need to be able to respond quickly when a user wishes to operate the vehicle 100. The controller 106A overdrives CORE1 by setting the clock frequency of CORE1 to an increased value so that CORE1 uses an increased amount of power (at a default power level) than the default power level. Figure 2 Marked as P 过驱动), CORE1 is limited to a default power level during normal operation. CORE1's clock is set to this higher power (in this example, approximately 4 times higher than the default power level) until, at time T2, CORE1 has completed booting its operating system or has completed booting (or is assumed to have completed booting) sufficient portions of the operating system to enable certain critical control functions for critical electronic controllable devices within the vehicle 100 to operate. Other levels of overdrive are used in other embodiments, including higher multiples or lower multiples (e.g., 50% or 100% higher than the default power level). In some embodiments, critical control functions include functions that are time-critical for interacting with a user (e.g., instrument panel display, backup camera display) that are booted in overdrive mode, while other control functions that do not need to be used immediately (e.g., entertainment system display or navigation display) are booted at the default power and clock frequency.

[0043] In some embodiments, more than one processor core may be subjected to power overdrive during startup, but in other embodiments, it may be sufficient to overdrive only a single processor core without subjecting more processor cores to the potential stress of being overdriven. In some embodiments, the particular processor core that is subjected to power overdrive is rotated between multiple processor cores. Alternatively, in some embodiments, the power budget is predetermined, and simultaneous startup of one or more processor cores is performed at the overdrive power level without exceeding the power budget. In some embodiments, other operating parameters are changed in addition to the clock frequency. For example, in some embodiments, the overdrive manager is also configured to temporarily increase the amplitude of the clock voltage and / or the voltage used by other processor components when the clock frequency is temporarily increased.

[0044] The operating system (OS) is any of a variety of suitable types of OS, such as Linux or RTLinux, a real-time operating system (RTOS) microkernel that runs the Linux OS in a fully preemptive manner. In some implementations, the OS software loaded during high-speed activation is a simplified version of the OS (e.g., including only selected software modules) that has a reduced size (e.g., 20MB) and boots faster.

[0045] In some integrated circuits, the amount of power consumed by a processor core is approximately proportional to the clock frequency. Typically, there is a limit on the amount of power that a processor core is designed to consume, and consuming more power than that limit for a significant amount of its useful life may have an adverse effect on the length of that useful life and / or performance during that useful life. Therefore, while extended operation at power levels exceeding a default power is not feasible, infrequent short pulse periods of operation at "overdrive" exceeding the default power have a negligible, acceptable adverse effect. In some implementations, operating at overdrive includes an increase in the voltage level of the clock signal (i.e., the voltage at a logic high level) along with an increase in the frequency of the clock signal. In some implementations, while CORE1 is booting its OS, other processor cores are maintained in an idle or off state (e.g., a state in which no software modules or OS software are executing) to further control the total amount of power consumed in the integrated circuit during high-speed activation.

[0046] In this example, after CORE1 has been booted, the controller 106A sets the other processor cores CORE2, CORE3, and CORE4 to use a default clock frequency so that the default power amount is used while booting their operating systems. When these processor cores are booting, between time T2 and T3, CORE1 can use the default clock frequency and the corresponding default power level to perform control functions. After the other processor cores have finished booting their operating systems, one or more of the processor cores (such as CORE4 in this example) can continue to perform functions at the default clock frequency and default power level, while the other processor cores can also be placed in low power mode if they are not needed at this time. During low power mode, the clock frequency is reduced or the clock is completely turned off to save power consumption, but since the operating system has been loaded, the low power mode can be quickly exited. In this example, CORE1, CORE2, and CORE3 are placed in low power mode at T3, and CORE4 is placed in low power mode at T4. Then, at T5, CORE1 and CORE2 are restored to the default clock frequency and default power.

[0047] Figure 3An example high-speed activation process 300 is shown that can be used by various nodes in a network, such as a controller including controller 106A and / or a switch including gateway switch 104B. Process 300 is used to selectively overdrive one processor core (referred to as a "boot core") at high power (exceeding a nominal "power limit") for a limited high-speed activation (HSA) time interval. However, there is an HSA mode that determines whether high-speed activation will be used. For example, a stored variable can be set to turn the HSA mode on or off. A mode check step determines (302) whether high-speed activation will be used. If not, process 300 directs (304) the boot core at the power limit and keeps other processor cores in an idle state. After the boot core has been started, process 300 directs (306) other processor cores at the power limit. If the mode check step determines that high-speed activation will be used, the process directs (308) the boot core at a high power above the power limit and keeps other processor cores in an idle state. The process 300 then waits for a predetermined HSA time interval (e.g., 500 ms) that is sufficient for the boot core to boot with overdrive. The process 300 then reduces the boot core to the power limit. The process then boots (306) the other processor cores at the power limit. Alternative implementations of the high speed activation process may use other steps or conditions, such as, for example, overdriving a selected set of multiple boot cores that are composed of a subset of processor cores that are less than all of the processor cores in the processor core. Alternatively, in some implementations, instead of waiting for a predetermined amount of time, the boot core sends a notification after booting has completed indicating that power will be reduced and the other processor cores will be booted.

[0048] The amount by which the processor core(s) are overdriven above the nominal power limit depends on the normal operating range of a given integrated circuit. For example, the processor cores in some SoCs are designed to use a nominal power that corresponds to a clock running at a nominal frequency (e.g., 500 MHz). However, within a limited amount of time, the clock frequency can be increased by a predetermined multiple (e.g., 3 times faster, 4 times faster, or 5 times faster).

[0049] Figure 44 is a schematic diagram showing an example of a SoC 400 suitable for use in a controller, switch, or other electronic system as described herein. The SoC 400 has a multi-core architecture including multiple processor cores (or simply "cores") 402, wherein each processor core 402 generally includes a clock 403, a pipeline 404, one or more register files 406, and a processor memory system 408. The clock 403 has an input that determines the frequency of a clock signal (e.g., a square wave) used to synchronize digital circuitry within the processor core 402. Each processor core 402 is connected to a communication and memory system 410, which includes a SoC interconnect 412 (e.g., a bus, a crossbar switch, a mesh network, etc.) and an external memory system 413. The SoC interconnect 412 enables communication with the external memory system 413, an input / output (I / O) bridge 414, and a network controller 430. I / O bridge 414 enables communication over I / O bus 416 with various I / O devices including overdrive manager 418A and storage devices 418B.

[0050] As described herein, the overdrive manager 418A manages the clock frequency of each processor core in the processor core during the high-speed activation process 300. In some implementations, the overdrive manager 418A includes dedicated hardware and / or firmware, or alternatively includes another core or a separate processor. The storage device 418B typically includes a hard disk drive, a solid-state drive (SSD), or other (usually non-volatile) storage medium that stores various program codes and other information, including the code of the operating system that is loaded into the main memory during the boot process of the high-speed activation process 300. To facilitate fast booting of the operating system, in one embodiment, the storage device 418B includes a fast non-volatile storage medium such as an NVMe SSD, and the I / O bus 416 is configured to use a fast communication medium such as PCIe. The storage device 418B can also reserve some space for use as secondary storage (or "backing storage") in a virtual memory scheme for the (usually volatile) main memory. The network controller 430 couples the SoC 400 to a network 440, such as a communication network of the vehicle 100. In other examples, network controller 430 is connected to I / O bus 416 rather than directly to SoC interconnect 412 .

[0051] The processor memory system 408 and the external memory system 413 together form a hierarchical memory system that includes at least a first level (L1) cache within the processor memory system 408, and any number of higher level (L2, L3, ...) caches within the external memory system 413 (i.e., the portion of the hierarchical memory system that is external to the processor core). At each cache level, the cache may include a module that provides an instruction cache for caching instructions, and a separate module that provides a data cache for caching data. The memory system loads blocks of instructions or data into entries and evicts blocks of instructions or data from entries in a unit cache block (also referred to as a cache line). A memory page includes a plurality of cache blocks, each of which includes a plurality of words, each word consisting of a predetermined number of bytes. In addition to the L1 instruction cache and data cache, the processor memory system 408 also includes a translation lookaside buffer (TLB) for caching recent translations, and various other circuit systems for handling misses in the L1 instruction or data cache or TLB. For example, in some embodiments, circuitry in the processor memory system 408 of the processor core 402 includes a write buffer for temporarily holding values ​​to be written from a store instruction being executed within the pipeline 404 .

[0052] The highest level of cache within the external memory system 413 (in some embodiments, an L2 cache if there are only two levels in the hierarchy) is the last level cache (LLC) 420, which is accessed just before the main memory. Of course, this is just one example. In other examples, the exact division between the level caches within the processor memory system 408 and the level caches within the external memory system 413 may be different. For example, both the L1 cache and the L2 cache may be internal to the processor core 402, while the L3 (and higher level) cache may be external to the processor core 402. Each processor core 402 may have its own internal L1 cache, and the processor cores may share an L2 cache. The external memory system 413 also includes a main memory controller 422, which is connected to any number of memory modules 424 (e.g., dynamic random access memory modules) used as main memory. At a particular cache level of the hierarchy, each cache entry includes space for storing a data word from a particular memory block and a bit that is used to determine whether the particular word from the memory block is present (i.e., a "hit") or not present (i.e., a "miss") in that cache level. After a level 1 miss, the cache system attempts to access (read or write) the memory block from a higher level cache or from main memory (in the case of a miss in the LLC).

[0053] The pipeline 404 includes multiple stages through which instructions advance, one cycle at a time. Some stages occur in the front-end portion of the pipeline. An instruction is fetched (e.g., in one or more instruction fetch (IF) stages). The instruction is fetched based on a program counter (PC), which is a pointer used to identify an instruction in a memory (e.g., in a portion of main memory or in an instruction cache of a processor). The PC is able to advance through the address of a compiled instruction block (called a "basic block"), incrementing a certain number of bytes (depending on the length of each instruction and how many instructions are fetched at a time). The instruction is then decoded (e.g., in one or more instruction decode (ID) stages) to determine the operation and one or more operands. Alternatively, in some pipelines, the instruction fetch and instruction decode stages may overlap. The instruction has its operands fetched (e.g., in one or more operand fetch (OF) stages). The instruction is then ready to be issued. Issuing the instruction begins execution of the instruction through the stages in the back-end portion of the pipeline to execute the instruction. Execution may involve applying the operation of the instruction to its operands to produce a result for an arithmetic logic unit (ALU) instruction, storing or loading to or from a memory address for a memory instruction, or may involve evaluating the condition of a conditional branch instruction to determine whether the branch will be taken. After the instruction has completed execution, the instruction may be committed so that any effect of the instruction is globally visible to the software. Committing the instruction may involve, for example, storing the result in register file 406 (e.g., in one or more write-back (WB) stages). In most implementations, all instructions are typically committed in order, even if any instruction is issued out of order.

[0054] While the present disclosure has been described in conjunction with certain embodiments, it should be noted that the present disclosure is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements within the scope of the appended claims, the scope of which should be given the broadest interpretation so as to encompass all such modifications and equivalent structures permitted by law.

Claims

1. A system on chip SoC, comprising: a first set of two or more processor cores configured to execute code using an amount of power below a nominal power limit during operation of the SoC after activation; a second set of one or more processor cores, the second set of one or more processor cores constituting a subset of the processor cores within the first set of two or more processor cores, configured to execute code using an amount of power above the nominal power limit during an activation time interval to direct functionality of the SoC; An interconnect configured to communicate with two or more electronically controllable devices; as well as A circuit system is configured such that: After the activation time interval, the second set of one or more processor cores execute code during subsequent operation using an amount of power below the nominal power limit, After booting the functionality of the SoC, at least one processor core in the first set or the second set executes code to activate control of a first electronically controllable device of the two or more electronically controllable devices, and After activating control of the first electronically controllable device, at least one processor core in the first set or the second set executes code to activate control of a second electronically controllable device among the two or more electronically controllable devices, the second electronically controllable device being different from the first electronically controllable device. 2 . The SoC of claim 1 , wherein the second set includes a single processor core and the first set includes one or more additional processor cores other than the single processor core in the second set. 3 . The SoC of claim 1 , wherein the SoC is further configured to prevent execution of any of the codes by any processor core in the first set that is not in the second set during the activation time interval. 4 . The SoC of claim 1 , wherein the SoC is configured to retrieve the code from a storage module comprising a solid-state drive.

5. The SoC of claim 1 , wherein the SoC is configured to cause execution at a first power level above the nominal power limit by increasing a first frequency of a first clock signal generated by a clock in a processor core in the second set to be higher than a second frequency of a second clock signal generated by a clock in a processor core not in the second set. 6 . The SoC of claim 5 , wherein the SoC is further configured to cause execution at the first power level by increasing a magnitude of a voltage of the first clock signal above a default voltage magnitude.

7. The SoC according to claim 1, wherein: the at least one processor core in the first set or the second set that causes activation of control of the first electronically controllable device is in the second set, and The at least one processor core in the first set or the second set that causes activation of control of the second electronically controllable device is not in the second set.

8. A method comprising: receiving an activation signal, wherein the activation signal initiates an activation time interval; as well as managing power consumed by a system on a chip (SoC), the SoC comprising a first set of two or more processor cores, the first set of two or more processor cores configured to execute code using an amount of power below a nominal power limit during operation of the SoC after the activation time interval, The management includes: In response to the activation signal, executing code during the activation time interval using an amount of power above the nominal power limit by a second set of one or more processor cores to direct functionality of the SoC, the second set of one or more processor cores constituting a subset of the processor cores of the first set of two or more processor cores, and After the activation time interval, executing code by a second set of the one or more processor cores using an amount of power below the nominal power limit; and Activate control of two or more electronically controllable devices, including: After booting the functionality of the SoC, executing code by at least one processor core in the first set or the second set to activate control of a first electronically controllable device among the two or more electronically controllable devices, and After activating control of the first electronically controllable device, code is executed by at least one processor core in the first set or the second set to activate control of a second electronically controllable device among the two or more electronically controllable devices, the second electronically controllable device being different from the first electronically controllable device.

9. The method of claim 8, wherein the second set includes a single processor core and the first set includes one or more additional processor cores other than the single processor core in the second set.

10. The method according to claim 8, wherein the managing further comprises: During the activation time interval, execution of any of the code by any processor core in the first set that is not in the second set is prevented.

11. The method of claim 8, wherein executing the code by the second set to boot the function of the SoC comprises: Code for booting at least a portion of an operating system is executed.

12. The method according to claim 8, wherein: Executing code by at least one processor core in the first set or the second set to activate control of the first electronically controllable device includes: executing the code by at least one processor core in the second set to activate control of the first electronically controllable device; and Executing code by at least one processor core in the first set or the second set to activate control of the second electronically controllable device includes: executing the code by at least one processor core not in the second set to activate control of the second electronically controllable device.

13. The method of claim 12, wherein executing the code by the at least one processor core in the second set comprises: Code is executed within the operating system to control the first electronically controllable device in a first subsystem of a vehicle, the first subsystem being associated with at least one of: a powertrain, steering, acceleration, or deceleration.

14. The method of claim 13, wherein executing the code by the at least one processor core that is not in the second set comprises: Code is executed to control the second electronically controllable device in a second subsystem of the vehicle different from the first subsystem of the vehicle.

15. The method according to claim 11, further comprising: A high-speed activation time interval is terminated in response to an indication that the booting of at least a portion of the operating system has completed.

16. The method of claim 8, wherein performing at a first power level above the nominal power limit comprises: A first frequency of a first clock signal generated by a clock in a processor core in the second set is increased to be higher than a second frequency of a second clock signal generated by a clock in a processor core not in the second set. 17 . The method of claim 16 , wherein performing at the first power level comprises increasing a magnitude of a voltage of the first clock signal above a default voltage magnitude.

18. The method of claim 16, wherein the first frequency is increased to be at least 50% higher than the second frequency.

19. The method of claim 18, wherein the first frequency is increased to at least twice the second frequency.

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