Self-aligned layer patterning

Abstract

A method comprising the steps of: a. forming a first pattern of regularly spaced apart templates (4) on a layer (3) to be patterned by self-aligned multiple patterning, b. subsequently forming hard mask spacers (5) on the sidewalls of said templates (4), thereby forming a second pattern formed by assemblies (4, 5) comprising a template (4) and a hard mask spacer (5) on its sidewall, and c. subsequently etching said second pattern in the layer (3) to be patterned.

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of patterning of layers and more specifically to the patterning of parallel lines in a semiconductor material, especially for the formation of a gate for a FinFET. BACKGROUND

[0002] When parallel lines in a semiconductor material are needed, a typical procedure is to cover the semiconductor with a hard mask to form parallel lines of photoresist material by lithography on the hard mask, followed by transferring these lines in the hard mask and finally into the semiconductor material.

[0003] For example, this process allows to form lines of 42 nm wide, spaced apart by spaces of 42 nm. However, forming lines of a narrower width is beyond the capabilities of current lithography processes. To increase the density of lines, a line multiplication process can be used, such as SAMP (self-aligned multiple patterning). The simplest SAMP process is SADP (self-aligned double patterning). In a typical SADP process, each line of the lithographically printed pattern will act as a hard mask spacer that will be deposited on a nucleus or core mold. The hard mask spacer is present on the sidewalls and the top of the core mold. The hard mask spacer is then etched back until the top of the core mold is exposed. The core mold can then be removed by etching, leaving a pattern formed by the hard mask spacer. This pattern can then be transferred in the lower layer. This pattern will have a pitch that is half the pitch of the lithographically printed pattern. The density of lines is thus doubled. In our example, the lines and the spaces between them are now each 21 nm wide. While SAMP is routinely performed today, standard SAMP procedures form lines having the same width as the spaces between the lines. However, this feature is not always desirable. Therefore, there is a need in the art for a method that allows to form lines wider than the spaces between the lines at a pitch that is not achievable by direct lithography. SUMMARY

[0004] It is an object of the present invention to provide a good method for patterning a layer.

[0005] In a first aspect, the invention relates to a method comprising the steps of:

[0006] a. forming a first pattern of regularly spaced apart core molds (4) on a layer (3) to be patterned by self-aligned multiple patterning,

[0007] b. subsequently forming a hard mask spacer (5) on the sidewalls of the core molds (4), thereby forming a second pattern, the second pattern being formed by an assembly (4, 5) comprising the core molds (4) and the hard mask spacers (5) on their sidewalls, and

[0008] c. Subsequently, the second pattern is etched in the layer (3) to be patterned.

[0009] This first aspect of the invention provides a procedure that allows to form lines wider than the space between them at a pitch that is not achievable with direct lithography. In the example introduced in the background section, this can be interpreted as a pitch that is kept at 42 nm, but where the lines are wider than 21 nm (e.g. 28 nm), and the space between them is narrower than 21 nm (e.g. 14 nm).

[0010] The formation of a FinFET requires the formation of a semiconductor fin and a gate covering the sides of a part of this fin. The part of the fin that is covered by the gate will act as a channel, and the gate will be used to control the current flow through this channel. The formation of the gate is usually done through a replacement metal gate (RMG) process, involving the formation of a dummy gate at an early stage of the process and replacing it at the end of the process by an actual gate stack. The dummy gate is a sacrificial structure that is intended to occupy the place that will eventually be occupied by the actual gate stack. The dummy gate is usually formed of polysilicon. As depicted in Figure 12 , the dummy gate (3) is usually protected by a hard mask on top of this dummy gate, and a gate spacer (6) covers the sides of the dummy gate and the hard mask. During the etch step used during the early stage of the RMG process, the hard mask protects the dummy gate from the top, and during said early stage, the gate spacer protects the dummy gate from the sides, while defining the lateral span of the future actual gate. Today, to form these dummy gates, a SAMP line multiplication process is used to achieve a gate width that is smaller than what is achievable by pure lithography.

[0011] At the end of the dummy gate patterning, the required gate width can be smaller than what is achieved by the SAMP process used. For example, a SAMP process can form 21 nm dummy gate lines at a pitch of 42 nm, while for this same 42 nm pitch, 16 nm dummy gate lines would be desirable. Thus, a trimming of the dummy gate lines is usually performed. Once this trimming is performed, as depicted in Figure 12 , the trimmed dummy gate lines (3) and the sidewalls of the hard mask on top of them are coated with a gate spacer (6). For example, a 6 nm gate spacer can be present on each side of each line. In this case, the width of the trimmed line-spacer assembly will be 28 nm.

[0012] At the early stage of the RMG process, the part of the fin (on both sides of the gate) that is not covered by the dummy gate will be used to form the source and drain of the FinFET. The source and drain are usually formed by epitaxially growing a semiconductor on the part of the fin that is not covered by the dummy gate.

[0013] Prior to this epitaxial growth, it can be advantageous to lower the height of these uncovered portions of the fin. This is especially true when the fin is very high, for example in the case of Complementary Field Effect (CFET) technology. In CFET, the state of the art is to have fins of about 80 nm high. It is problematic to epitaxially grow the source and drain on such high fin portions. It is advantageous to lower the height of the uncovered fin portions to a large extent to epitaxially grow the source and drain therefrom. As a result, in the case of an 80 nm fin, the uncovered fin portions will be recessed less than 80 nm. After recessing the uncovered fin portions, it is desirable that the dummy gate remains covered on all sides. If this is not the case, the subsequent step of epitaxially growing the source and drain will cause parasitic epitaxial growth on the exposed dummy gate. In order to achieve proper protection of the dummy gate, the height of the hard mask is usually chosen to be high enough so that it is not completely consumed before the uncovered fin portions are recessed. As depicted in Figure 13 The problem with the current approach is that the gate spacers (6) are exposed to the etchant and thus are consumed during the recessing of the uncovered fin portions. This can easily lead to the sidewalls (7) of the dummy gate (3) becoming exposed during the recessing of the uncovered fin portions.

[0014] The inventors found that one possible solution to this problem would be to protect the gate spacers from the top with a hard mask, i.e. to make the hard mask lines wider than the dummy gate lines, so that the hard mask lines would be wide enough to cover at least part of the gate spacer lining the dummy gate line. However, in order to keep both the pitch (e.g. 42 nm) and the dummy gate line (e.g. 16 nm) unchanged, this requires the hard mask lines to be wider than the space between them. This is the case for example where the first aspect of the invention can be used.

[0015] The inventors realized that by skipping the core removal step in the SAMP process, thicker lines than the interline space can be obtained. In other words, instead of removing the core before transferring the hard mask pattern into the semiconductor material, the core is left in place and instead the entire assembly hard mask spacer-core is transferred. As a result, thicker lines than the interline space can be formed in the semiconductor material, which are smaller in size than what is achievable by lithography alone.

[0016] An advantage of embodiments of the first aspect of the invention is that more uniform thick dummy gate lines can be obtained compared to the state of the art. This also means that less unwanted etching of the dummy gate occurs. In embodiments, less than 50% of the dummy gate is etched away compared to the state of the art.

[0017] Without being bound by theory, it is believed that this more uniform thickness of the dummy gate lines is due to the smaller space between the hard mask lines.

[0018] Another advantage of embodiments of the first aspect of the invention is that it permits to form a higher gate than the prior art. In the prior art, the irregular profile of the dummy gate line limits the dummy gate height that can be reached. In embodiments of the invention, this is less the case. In addition, the risk of collapse of the dummy gate line is reduced compared to the prior art.

[0019] Yet another advantage of embodiments of the first aspect is that they adapt to the existing SAMP recipe that is well established in the field of semiconductor processing.

[0020] In a second aspect, the invention relates to an intermediate structure in the formation of a fin-based field effect transistor, comprising:

[0021] - a semiconductor fin,

[0022] - a dummy gate,

[0023] - an assembly comprising a core mold having a hard mask spacer on its sidewalls, the assembly covering the top of the dummy gate,

[0024] wherein the width of said assembly is within 5% of the width of said dummy gate.

[0025] The intermediate structure of embodiments of the second aspect can be obtained by the method according to embodiments of the first aspect, and can be used as a signature that the method according to embodiments of the first aspect has been used.

[0026] The above objects are achieved by the method and apparatus according to the invention.

[0027] Particular and preferred aspects of the invention are set out in the appended independent and dependent claims. Features from the dependent claims can be combined with features of the independent claims and other dependent claims as appropriate and not just in the combinations explicitly set out in the claims.

[0028] While the apparatus in the field is continually improving, changing and evolving, it is believed that the present inventive concept represents sufficiently novel and inventive improvements over prior practice to provide more efficient, stable and reliable apparatus of this nature.

[0029] The above and other features, aspects and advantages of the present invention will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, the principles of the invention. This description is given for purposes of exemplification only, not limitation, and the present invention should in no way be limited to the description and drawings, which are included merely as examples. Reference will now be made to the drawings in which reference numerals refer to similar structures throughout. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 、 35, 6, 9, 10 and 11 are schematic representations of the vertical cross-sections of intermediate structures obtained after each step of the embodiments of the first aspect of the invention.

[0031] Figure 2 , 4 7 were obtained through top-down critical size scanning electron microscopy, empirically, and respectively with Figure 1 , 3 Images of the intermediate structures corresponding to the stages explained in section 6.

[0032] Figure 8 It was obtained through cross-sectional scanning electron microscopy, experimentally, and is consistent with... Figure 6 The image shows the vertical cross-sectional view of the intermediate structure corresponding to the stage of the explanation.

[0033] Figure 12 and 13 It is a schematic representation of the vertical cross-sections of intermediate structures obtained after each step of the process in the prior art.

[0034] In different accompanying drawings, the same reference numerals refer to the same or similar elements. Detailed Implementation

[0035] The invention will be described with reference to specific embodiments and particular drawings, but the invention is not limited thereto but is defined only by the claims. The described drawings are merely illustrative and not restrictive. In the drawings, for illustrative purposes, the dimensions of some elements may be enlarged and are not drawn to scale. Dimensions and relative dimensions do not correspond to an actual reduction of the invention.

[0036] Furthermore, the terms first, second, and third, etc., used in the specification and claims are used to distinguish similar elements and are not necessarily used to describe a temporal, spatial, arrangement, or any other chronological order. It should be understood that the terms thus used are interchangeable where appropriate, and the embodiments of the invention described herein can be operated in a different order than those described or illustrated herein.

[0037] Furthermore, the terms top, bottom, above, below, etc., used in the specification and claims are for descriptive purposes and not necessarily for describing relative positions. It should be understood that such terms are interchangeable where appropriate, and embodiments of the invention described herein can operate in orientations different from those described or illustrated herein.

[0038] It is to be noticed that the term "comprising", used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted that the term "comprising" means "consisting at least of the stated features". The embodiments are thus to be construed in accordance with the principle of "any of". Therefore, the term "comprising" encompasses the case where only the stated features are present and the case where additional features are also present. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B. It means that with respect to the device, the only relevant components of the device are A and B.

[0039] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but can refer to different embodiments. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0040] Similarly, it is to be appreciated that, wherever used, the description of an embodiment of the application applying to one element is intended to be read either as applying to one or more of them or to all of them but not necessarily to each of them individually. Similarly, wherever used, the description of an embodiment of the application applying to "one", "an" or "the" element is intended to be read either as applying to one or more of them or to all of them but not necessarily to each of them individually. Likewise, the terms "comprising", "including", "containing", "having" and "encompassing" when used in this disclosure specify the presence of stated features, integers, steps or components but do not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof. Therefore, the term "comprising" encompasses the case where only the stated features are present and the case where additional features are also present. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B. It means that with respect to the device, the only relevant components of the device are A and B.

[0041] Furthermore, although some embodiments described herein include some features of other embodiments that are described herein, unless the content clearly indicates otherwise, it is contemplated that features of one embodiment can be combined with features of any other embodiment or other embodiments. For example, in the claims, any of the claimed embodiments can be used in any combination.

[0042] Further, some of the embodiments herein are described in terms of a method or combination of elements of a method that can be implemented by a processor of a computing system or other device for performing this process. Thus, a processor that has the necessary instructions for performing such a method or element of a method forms a means for implementing the process or element of a process. Further, elements of a device embodiment are presented that are implemented in a computing system where the elements are either hardware- or software- based and / or stored in one or more computer-readable storage media.

[0043] In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the application can be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

[0044] Reference will be made to transistors. These are three-terminal devices having a first main electrode (such as a drain), a second main electrode (such as a source) and a control electrode (such as a gate for controlling the flow of charge between the first and second main electrodes).

[0045] A first aspect of the application relates to a method comprising the steps of:

[0046] a. forming a first pattern of regularly spaced apart cores (4) on a layer (3) to be patterned by self-aligned multiple patterning (see Figure 1 and 2 ),

[0047] b. subsequently forming a hard mask spacer (5) on the sidewalls of the cores, thereby forming a second pattern from an assembly comprising the cores and the hard mask spacers on their sidewalls (see Figures 3 to 5 ), and

[0048] c. subsequently etching the second pattern in the layer to be patterned (see Figures 6 to 8 ).

[0049] In step a, SAMP is used to form a first pattern of regularly spaced apart cores on a layer to be patterned.

[0050] SAMP (not shown) typically comprises forming a pattern of first elements regularly spaced apart on a layer to be patterned, forming a hard mask spacer on the sidewalls of these first elements, removing the first elements, thereby leaving a pattern of spacers, and transferring the pattern of spacers into the layer to be patterned, thereby forming a pattern of second elements regularly spaced apart (corresponding to the cores formed in step a). In SADP, the first elements are formed directly by lithography, i.e. by transferring a photoresist pattern into a hard mask. In SAQP, the first elements are the second elements formed by SADP.

[0051] Generally, if the SADP is considered to be a first order SAMP, the SAQP is considered to be a second order SAMP, and so on, for an n+1 order SAMP, the first element is a second element formed by an n order SAMP.

[0052] The shape of each element is preferably the same.

[0053] In embodiments, the shape of each element is preferably the same.

[0054] The elements are typically lines. As a result, in embodiments, the mandrels are typically lines.

[0055] The first pattern is typically formed by parallel lines.

[0056] In embodiments, each mandrel forming the pattern can have a width of at most 40 nm. For example, they can have a width from 1 to 40 nm.

[0057] Preferably, they can have a width from 1 to 30 nm. More preferably, from 1 to 25 nm. Typically, from 12 to 25 nm.

[0058] The width of the mandrels is preferably within 10% of each other, more preferably within 5%. More preferably, they are the same.

[0059] In embodiments, the height of the mandrels can be 1.5 to 10 times, preferably 3 to 6 times, more preferably 4 to 5 times, the width of the mandrels.

[0060] The height of the mandrels is preferably within 10% of each other, more preferably within 5%. More preferably, they are the same.

[0061] The mandrels are spaced apart by spaces. The width of the spaces is preferably within 10% of each other, more preferably within 5%. More preferably, they are the same.

[0062] The average width of the spaces is preferably within 10% of the average width of the mandrels, more preferably within 5%. Preferably, the average width of the spaces is the same as the average width of the mandrels.

[0063] In embodiments, the width of the mandrels can be within 10% of each other, wherein the width of the spaces between the mandrels is within 10% of each other, and wherein the average mandrel width is within 10% of the average space width

[0064] In embodiments, the mandrels can comprise a bottom layer made of a first material and a top layer made of a second material.

[0065] In embodiments, the bottom layer can be made of silicon nitride or silicon carbide, and the top layer can be made of silicon oxide.

[0066] In embodiments, the height of the bottom layer can be 0.7 to 4.5 times, preferably 1.5 to 2.5 times, the width of the core.

[0067] In embodiments, the height of the top layer can be 0.8 to 5.5 times, preferably 2 to 3 times, the width of the core.

[0068] In embodiments, the layer to be patterned in step a can be a layer of semiconductor material. For example, it can be polysilicon or amorphous silicon.

[0069] Typically, the material of the layer to be patterned is chosen in such a way that it can be etched selectively with respect to the material forming the core and the spacers.

[0070] In embodiments, the thickness of the layer to be patterned can be 5 to 15 times, preferably 7 to 13 times, the width of the core.

[0071] In embodiments, the thickness of the layer to be patterned can be 100 to 350 nm, preferably 150 to 300 nm.

[0072] In step b, forming a hard mask spacer on the sidewalls of the core can comprise the step bl of forming a layer of conformal spacer material on the core thereby lining the top and sidewalls of the core, followed by the step b2 of etching parts of the spacer material to expose the core top while keeping the sidewalls of the core covered.

[0073] The material of the hard mask spacer can for example be an oxide, nitride, carbide, carbonitride, oxycarbonitride, oxynitride, or oxycarbide of silicon. It is typically an oxide of silicon because polysilicon, which is typically used as the layer to be patterned, shows a higher etch selectivity with respect to an oxide of silicon than with respect to a nitride or a carbide.

[0074] The result of step b is that a second pattern is formed, the second pattern being formed by the assemblages comprising the core and the hard mask spacer.

[0075] The assemblages are wider than the space between them.

[0076] In embodiments, the assemblages can be spaced apart by a space, and the assemblages can have an average width that is at least 5% larger than the width of the space between them.

[0077] In step c, the second pattern is etched in the layer to be patterned.

[0078] While the method of the first aspect can find various applications, it is particularly useful for forming a pattern of dummy gates during the manufacture of a semiconductor device, wherein the layer to be patterned is a layer of dummy gate material. In this case, step c results in forming a pattern of dummy gates etched in the layer of dummy gate material.

[0079] In such a case, the intermediate structure from step c can comprise:

[0080] - a semiconductor fin,

[0081] - a dummy gate,

[0082] - an assembly comprising a core mold having a hard mask spacer on its sidewalls, the assembly covering the top of the dummy gate,

[0083] wherein the width of the assembly is within 5% of the width of the dummy gate. Preferably, the width of the assembly is within 2% of the width of the dummy gate. Preferably, the widths are the same.

[0084] When the method aims at forming a pattern of dummy gates, the method can further comprise a step d of reducing the width of the dummy gate after step c. The width of the dummy gate can for example be reduced by 25% to 40%, for example 30% to 35%. After trimming, the assemblies are wider than the dummy gate lines. The method can further comprise a step e of forming gate spacers on the sidewalls of the dummy gate after step d.

[0085] In embodiments, the assemblies are wide enough to cover at least a portion of the gate spacers lining the dummy gate lines.

[0086] In embodiments, step e can comprise a step el of forming gate spacers on the sidewalls of the dummy gate and on the sidewalls of the hard mask spacer, and a step e2 of selectively etching the gate spacers present on the sidewalls of the hard mask spacer with respect to the gate spacers present on the sidewalls of the dummy gate. Step el can for example be performed by ALD. Step e2 operates while the gate spacers present on the dummy gate sidewalls are protected by the assembly.

[0087] In embodiments, the material of the gate spacers can be different from the material of the hard mask spacer. Examples of suitable materials for the gate spacers are silicon nitride and silicon oxycarbide, among others.

[0088] In embodiments, the dummy gate material layer can be on the semiconductor fin, and the method can further comprise:

[0089] - after step e, a step f of etching the portions of the semiconductor fin that are not covered by the dummy gate, thereby reducing the height of the semiconductor fin, and

[0090] - after step f, a step g of epitaxially growing a source or drain on the etched portions of the semiconductor fin.

[0091] In embodiments, the height of the semiconductor fin can be at least 70 nm.

[0092] Any feature of the first aspect can correspondingly be described in any embodiment of the second aspect.

[0093] In a second aspect, the application relates to an intermediate structure in the formation of a fin-based field effect transistor, comprising:

[0094] - a semiconductor fin,

[0095] - a dummy gate,

[0096] - an assembly comprising a mandrel having a hard mask spacer on its sidewalls, the assembly covering the top of the dummy gate,

[0097] wherein the width of the assembly is within 5% of the width of the dummy gate.

[0098] In embodiments, the dummy gate has a first width measured at 10% of its height and a second width measured at 90% of its height, and wherein the first width and the second width are within 10% of each other.

[0099] Any feature of the second aspect can correspondingly be described in any embodiment of the first aspect.

[0100] The application will now be described by a detailed description of several embodiments of the application. It is clear that other embodiments of the application can be configured according to the knowledge of the skilled person in the art without departing from the technical teaching of the application, the application being limited only by the terms of the appended claims.

[0101] We now refer to Figure 1 and 2 .

[0102] Figure 1 A simplified schematic vertical cross-section of a semiconductor structure is shown. A silicon substrate comprising a plurality of 80 nm high, 6 nm wide fins with a pitch of 25 nm is present in this cross-section but not shown. A shallow trench isolation made of silicon oxide (1), 2 nm silicon oxide deposited on the shallow trench isolation by plasma enhanced atomic layer deposition (PEALD) (2), a layer to be patterned (3) on the PEALD silicon oxide, and a first pattern of regularly spaced mandrels (4) formed by SADP on the layer (3) are depicted. In this example, this layer (3) is made of polysilicon and is 200 nm thick. The mandrels are made of a bottom 40 nm Si3N4 layer and a top 50 nm SiO2 layer. The mandrels are spaced with a pitch of 42 nm and have a width of 21 nm. Figure 2 is an overview of this structure obtained by top-down critical dimension scanning electron microscopy.

[0103] In Figure 3 , a SiO2 layer (5) has been applied on the mandrels and is thus present on the top and sidewalls of the mandrels.Figure 4 is a top view of this structure obtained by top-down critical dimension scanning electron microscopy.

[0104] In Figure 5 , the SiO2layer (5) has been etched until the top of the mandrel is exposed. The assembly consisting of the mandrel and the hard mask is wider than the space between them.

[0105] In Figure 6 , the assembly consisting of the mandrel and the hard mask spacer has been used as a mask to etch the layer to be patterned, thereby forming a dummy gate wider than the space between them. The pitch remains the same as in Figure 1 and 2 . Figure 7 is a top view of this structure obtained by top-down critical dimension scanning electron microscopy. Figure 8 shows a vertical cross-section micrograph of this structure obtained by cross-section scanning electron microscopy.

[0106] In Figure 9 , the dummy gates have been trimmed to reduce their width from more than 24 nm to about 16 nm.

[0107] In Figure 10 , silicon nitride gate spacers (6) are conformally deposited by ALD on the dummy gates and the assembly. Next, in Figure 11 , the gate spacers present on the sidewalls of the hard mask spacers are selectively etched away with respect to the gate spacers present on the sidewalls of the dummy gates. This etch operates while the gate spacers present on the dummy gate sidewalls are protected by the hard mask spacers.

[0108] It is understood that while the preferred embodiments, specific structures and configurations, and materials according to the present application have been discussed herein, various changes or modifications in form and detail can be made without departing from the scope of the application. Steps can be added or deleted to methods of the application.

Claims

1. A method for forming a pattern of dummy gates during the manufacturing of a semiconductor device, comprising the steps of: a. forming a first pattern of regularly spaced apart cores (4) on a layer (3) to be patterned by self-aligned multiple patterning, b. subsequently forming hard mask spacers (5) on the sidewalls of the cores (4), thereby forming a second pattern, the second pattern being formed of assemblies (4, 5) comprising a core (4) and a hard mask spacer (5) on its sidewall, and c. subsequently etching the second pattern in the layer (3) to be patterned, characterized in that the hard mask lines are wider than the dummy gate lines, such that the hard mask lines will be wide enough to cover at least part of the gate spacers of the dummy gate lines.

2. The method of claim 1, wherein, The layer (3) to be patterned is a layer (3) of dummy gate material.

3. The method of claim 2, wherein, Further comprising a step d. of reducing the width of the dummy gate after step c.

4. The method of claim 3, wherein, Further comprising a step e. of forming the gate spacers (6) on the sidewalls of the dummy gate after step d.

5. The method of claim 4, wherein, Step e. comprises a step el. of forming gate spacers (6) on the sidewalls of the dummy gate and on the sidewalls of the hard mask spacers (5), and a step e2. of selectively etching the gate spacers (6) present on the sidewalls of the hard mask spacers (5) with respect to the gate spacers (6) present on the sidewalls of the dummy gate.

6. The method of claim 4 or claim 5, wherein, The layer (3) of dummy gate material is on a semiconductor fin, and wherein the method further comprises: - a step f. of etching the part of the semiconductor fin not covered by the dummy gate after step e., thereby reducing the height of the semiconductor fin, and - a step g. of epitaxially growing a source or drain on the etched part of the semiconductor fin after step f.

7. The method of claim 6, wherein, The semiconductor fin is at least 70 nm high.

8. The method of any of claims 1-5, wherein, Each core (4) forming the pattern has a width of at most 40 nm.

9. The method of any of claims 1-5, wherein, The widths of the cores (4) are within 10% of each other, wherein the widths of the spaces between the cores (4) are within 10% of each other, and wherein the average core (4) width is within 10% of the average space width.

10. The method of any of claims 1-5, wherein, The layer (3) to be patterned is a layer (3) of semiconductor material.

11. The method of any one of claims 1-5, wherein, The cores (4) comprise a bottom layer and a top layer, wherein the bottom layer is made of silicon nitride or silicon carbide, and wherein the top layer is made of silicon oxide.

12. The method of any one of claims 1-5, wherein, The assemblies (4, 5) are spaced apart by a space, and wherein the assemblies (4, 5) have an average width that is at least 50% larger than the width of the space between them.

13. The method of any of claims 4-5, wherein, The material of the gate spacers (6) is different from the material of the hard mask spacers (5).

14. An intermediate structure in the formation of a fin-based field effect transistor using the method of any one of claims 1-13, comprising: - a semiconductor fin, - a dummy gate, - assemblies (4, 5) comprising a core (4) with a hard mask spacer (5) on its sidewall, the assemblies (4, 5) covering the top of the dummy gate, wherein the width of the assemblies is within 5% of the width of the dummy gate.

15. The intermediate structure of claim 14, wherein, The dummy gate has a first width measured at 10% of its height and a second width measured at 90% of its height, and wherein the first width and the second width are within 10% of each other.

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