Event-based vision sensor made with 3D-IC technology

Abstract

Event-based vision sensors are manufactured using an advanced stacking technique known as 3D integrated circuits, which stacks more wafers (or dies) and interconnects them vertically. The sensor's electronic integrated circuits are then distributed between two or more electrically connected dies.

Description

[0001] Related applications

[0002] This application claims the benefit under 35 USC 119(e) of U.S. Provisional Application No. 62 / 642,838, filed on Mar. 14, 2018, the entire contents of which are incorporated herein by reference. Background Art

[0003] An important parameter in the design of event-based pixel arrays, also known as dynamic vision sensors (DVS), is the quantum efficiency (QE), which is the ratio of the number of electrons generated in response to a light signal to the number of photons in that light signal. This parameter is directly dependent on the fill factor (FF), which is the ratio of the area of ​​the photosensitive device exposed to light to the total area of ​​the integrated circuit exposed to light.

[0004] Because today's event-based vision sensors are implemented using planar silicon processes, the area exposed to light must be shared between the photosensitive device and other semiconductor devices that form the pixel circuitry. This approach has two main drawbacks: the area of ​​the photosensitive device is limited, and circuitry not intended to be exposed to light may experience performance degradation due to this radiation exposure. Summary of the Invention

[0005] The main purpose of this invention is to alleviate these two problems by using an advanced stacking technology called three-dimensional integrated circuits in the fabrication of event-based vision sensors, which stacks more wafers (or dies) and interconnects them vertically.

[0006] There are many motivations, including:

[0007] Increase FF;

[0008] Shielded circuits that do not need / must not receive light; and

[0009] Different components of the pixel have different requirements that are best met by implementing them in different IC processes (the photosensitive device could even theoretically be manufactured in non-silicon-based technologies, such as GaAs).

[0010] In general, according to one aspect, the invention features an event-based vision sensor (EBVS) comprising vertically connected stacked dies. Thus, the light-sensitive device of each pixel of the pixel array can be located in the die exposed to illumination, while other devices not useful for light capture can be located in other wafers or dies.

[0011] Preferably, there is at least one connection per pixel of the pixel array between the dies.

[0012] Typically, the photodiode for each pixel of the pixel array is in a first die and the corresponding event detector for each pixel of the pixel array is in a second die, and interconnects between the first die and the second die connect the photodiode to the corresponding event detector.

[0013] This approach can be used in either front-side or back-side lighting architectures.

[0014] In addition, the light sensing circuit of each pixel in the pixel array can be implemented in a variety of different ways. For example, it can be located on the second die, or in the first die, or distributed between the first die and the second die.

[0015] Additional amplification stages can be added in the first die.

[0016] Typically n-FET transistors are used in a first wafer or die, and both n-FET transistors and p-FET transistors are used in a second die.

[0017] Additionally, transistor characteristics may be different between transistors on the first die and the second die, including different gate oxide thicknesses or different implants.

[0018] In general, according to one aspect, the invention features a method of making an event-based vision sensor. Generally, the method includes making different devices for each pixel of a pixel array in different wafers or dies, and then stacking the wafers or dies.

[0019] As used herein, a "die" is a piece or portion of a semiconductor wafer, typically rectangular in shape, such as a chip. In this context, this semiconductor wafer includes a portion of an integrated circuit device example, such as an event-based vision sensor. References to wafers or die are based on the possibility of different manufacturing methods. Stacking can be performed at the wafer level before being cut into die. Alternatively, stacking can be performed on individual die after they have been cut or diced from the wafer. Thus, the final device produced by the manufacturing process is a stack of die.

[0020] The method would then include connecting each pixel, for example using Cu-Cu connections.

[0021] In one embodiment, the method further includes fabricating a photodiode for each pixel of the pixel array in a first wafer or die and fabricating a corresponding event detector for each pixel of the pixel array in a second wafer or die.

[0022] The above and other features of the present invention, including various novel construction details and combinations of parts and other advantages, will now be described in more detail with reference to the accompanying drawings and pointed out in the claims. It should be understood that the specific methods and devices embodying the present invention are shown by way of illustration and not limitation. The principles and features of the present invention may be employed in a variety of embodiments without departing from the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In the accompanying drawings, reference characters refer to the same parts throughout the different views. The drawings are not necessarily drawn to scale; emphasis is instead placed upon illustrating the principles of the invention. In the drawings:

[0024] Figure 1 : Circuit diagram showing a pixel implementation of a prior art event-based image sensor (SOA), such as according to PCT / IB2017 / 058526 and U.S. Publication No. 2018 / 0191972;

[0025] Figures 2A to 2C :Image sensor based on SOA event: Single chip to realize the sensor Figure 2A and Figure 2B Part of the vertical section, Figure 2C Partial top view in ); Figure 2A Refers to front-side illumination (FSI) applications; Figure 2B Refers to backside illumination (BSI) applications;

[0026] Figures 3A to 3D : A partial vertical cross section of two (2) stacked wafers showing the preferred embodiment before dicing the wafers ( Figure 3A ); Partial vertical cross section focused on one pixel, showing the top wafer of the backside illumination (BSI), with only the photodiode (PD) and a single connection per pixel to the bottom wafer ( Figure 3B );block diagram( Figure 3C ) and circuit diagram ( Figure 3D ), showing details of the pixel front-end circuitry and how it is arranged between wafers / dies;

[0027] Figures 4A to 4B : A partial vertical cross section of two (2) stacked wafers showing an alternative embodiment in which the top wafer also contains two transistors of the front-end circuitry ( Figure 4A ); Circuit diagram showing details of the pixel front-end circuit and how it is arranged between wafers / die ( Figure 4B );

[0028] 5A to 5D : Partial vertical cross section of two (2) stacked wafers showing the entire front end in the top wafer, ultimately including the source follower stage ( Figure 5A ); Partial vertical cross section focused on one pixel, showing how the output from the first wafer is directly connected to one plate of the MIM (metal-insulator-metal) capacitor of the event detector on the bottom wafer (which is located between the two uppermost metals), shown in a simplified vertical cross section including details of the silicon process layers of the two stacked wafers ( Figure 5B ); also depicts two circuit diagrams ( Figure 5C and Figure 5D ), showing the pixel front-end circuit details;

[0029] Figures 6A to 6B : Circuit diagram showing an alternative pixel front-end circuit with an additional p-FET transistor for improved performance ( Figure 6A ); Circuit diagram( Figure 6B ), showing separation between wafers / dies;

[0030] 7A to 7C : Three circuit diagrams showing variations of the pixel front-end circuit, where multiple Cu-Cu connections are required in each pixel; Figure 7A is preferred; Figure 7B and Figure 7C , shows how circuit elements can be placed between wafers / dies so that the top wafer contains no p-FET devices, showing how in this case more than two cross-wafer (or die) connections are required per pixel. DETAILED DESCRIPTION

[0031] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which illustrative embodiments of the invention are shown. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0032] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, the singular forms and the articles "a", "an" and "the" are also intended to include the plural forms, unless otherwise expressly stated. It will be further understood that when used in this specification, the terms include, including and / or comprise, comprising specify the presence of the features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. In addition, it should be understood that when an element comprising a component or subsystem is referred to as and / or shown as being connected or coupled to another element, it can be directly connected or coupled to the other element, or there can be intervening elements.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It should also be understood that those terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted as idealized or overly formal unless expressly defined herein.

[0034] definition

[0035] An event-based pixel array (EBPA) is an array of pixels containing light-sensitive devices; these pixels are independent of each other in space and / or time and generate discretized data based on the light radiation they receive.

[0036] An event-based vision sensor (EBVS) is a sensor that outputs data extracted and / or interpreted from an EBPA.

[0037] Fill Factor (FF) is defined as the ratio of the pixel area to the area of ​​the photosensitive device present in that pixel. It is a measure of how much of the total light radiation impinging on the sensor surface can be effectively captured by the sensor.

[0038] Quantum efficiency (QE) is defined as the ratio between the number of photons striking the surface of a photosensor and the number of electrons generated in response and converted into an electrical signal.

[0039] 3D IC: Short for three-dimensional integrated circuit; this is a technology for making integrated circuits by stacking silicon wafers or dies and interconnecting them vertically.

[0040] Front Side Illumination (FSI): A type of image sensor implemented as an integrated circuit (IC) so that it is illuminated from the top of the die, which is the side of the layers implementing the planar process; all devices and metal wiring, along with the photosensitive devices, receive direct light radiation.

[0041] Backside Illumination (BSI): A type of image sensor implemented as an IC so that illumination is from the bottom of the die (ie, one side of the substrate); the device and metal wiring do not receive direct light radiation, but only through the substrate.

[0042] Existing technology

[0043] Examples of event-based vision sensors are described in, for example, PCT / IB2017 / 058526 or US7728269B2 or US Publication No. 2018 / 0191972.

[0044] Figure 1An example of a pixel architecture for an EBPA of an EBVS is shown in

[15] , which will be used as a reference in this document. It is taken from PCT / IB2017 / 058526 and U.S. Publication No. 2018 / 0191972, both of which are incorporated herein by reference in their entireties. However, the core concepts of the proposed invention can be applied to virtually any event-based vision sensor implemented as an IC, independent of any specific pixel architecture used.

[0045] The main components of the pixel circuit are listed below.

[0046] 1. Photosensitive Module. As shown in the figure, pixel circuit 100 includes: a photodiode PD or other photosensor to measure incident light and convert the light intensity into a current Iphoto; a photosensitive circuit PRC to generate a photosensitive signal Vpr based on the light intensity; and a storage capacitor C1 to store past photosensitive signals. The photosensor PD and photosensitive circuit PRC constitute the photosensitive module PR.

[0047] 2. Storage capacitor C1: Receives the light-sensing signal Vpr, causing the first plate of the capacitor to carry a charge responsive to the light-sensing signal Vpr and, therefore, to the light received by the photosensor PD, which is part of the event detector ED. The second plate of storage capacitor C1 is connected to the comparator node (inverting input) of A1. Therefore, the voltage Vdiff at the comparator node varies with changes in the light-sensing signal Vpr.

[0048] 3. Comparator A1: This is a method that compares the difference between the current light-sensing signal Vpr and the past light-sensing signal to a threshold value and is part of the event detector ED. This comparator A1 can be in each pixel or shared between a subset of pixels (e.g., a column). In a preferred embodiment, the comparator will be integrated into the pixel, with each pixel having a dedicated comparator A1.

[0049] 4. Memory: The memory 50 stores the comparator output based on the sampling signal from the controller 60 and is part of the event detector ED. The memory can be a sampling circuit (e.g., a switch and parasitic or explicit capacitors) or a digital storage circuit (latch or flip-flop). In one embodiment, the memory will be a sampling circuit, and each pixel will have two memories.

[0050] 5. Conditional reset circuit R1: The reset condition is a combination of the state of the stored comparator output and the reset signal applied by the controller 60, and is part of the event detector ED.

[0051] 6. Peripheral circuit components: The comparator A1 and the memory 50 can be located in the pixel or in the peripheral circuit (outside the pixel circuit).

[0052] The peripheral circuitry includes a controller 60 that applies a threshold signal to the comparator A1, sends a control signal to the memory 50, and selects when the conditional reset circuit R1 becomes active.

[0053] The peripheral circuitry may also include readout circuitry that reads the contents of memory 50, determines whether the light intensity at a given pixel has increased, decreased, or remained unchanged, and sends an output (calculated based on the current memory value) to the processor.

[0054] More specifically, the comparator determines whether the light is increasing and / or decreasing. For an "off" event: If Vdiff is below the threshold Voff (on Vb), the comparator output is high, and this level is stored in memory. This means a dip was detected. If Vdiff is not below the threshold, the comparator output is low: no dip was detected.

[0055] The only difficulty is that for an "on" event, a low comparator output means an increase, while a high means no change; but for an "off" event, a high comparator output means a decrease, while a low means no change.

[0056] Therefore, the readout must know the memory contents and which threshold is applied.

[0057] The pixel circuit 100 and the controller 60 operate as follows.

[0058] Changes in the light intensity received by photosensor PD are converted into changes in the light-sensing signal Vpr. When reset circuit R1 is non-conductive, changes in Vpr are also reflected in the voltage Vdiff at the comparator node at the inverting input (-) of comparator A1. This is because the voltage across storage capacitor C1 remains constant.

[0059] At times selected by controller 60 , comparator A1 compares the voltage (Vdiff) at the comparator node at the second terminal of storage capacitor C1 with a threshold voltage Vb (from the controller) applied to the non-inverting input (+) of comparator A1 .

[0060] The controller 60 operates the memory 50 to store the comparator output Vcomp. As shown, the memory 50 is typically implemented as part of the pixel circuit 100. However, in other embodiments, the memory 50 is implemented as part of the column logic circuit (a peripheral circuit, one peripheral circuit for each column of the pixel array).

[0061] If the state of the stored comparator output stored in memory 50 indicates a change in light intensity AND, the global reset signal GlobalReset from controller 60 is asserted, turning on conditional reset circuit R1. Here, AND represents a logical AND operator. When conditional reset circuit R1 is in the on state, the voltage (Vdiff) at the comparator node at the inverting input of comparator A1 is reset to a known level. Consequently, the current light-sensing signal Vpr is stored on storage capacitor C1.

[0062] So far, as Figure 1 These EBVSs with pixel EBPAs shown have been fabricated as integrated circuits on a single wafer using a silicon planar process. With this technology, semiconductor devices (e.g., MOS transistors, diodes and photodiodes, polysilicon resistors, etc.) can only be arranged on a single layer; they cannot be stacked vertically.

[0063] In this way, the area of ​​the pixel 100 must be shared between the photosensitive device (e.g., PD) and the rest of the circuitry, as shown in the front-side illumination configuration. Figure 2A and showing the back lighting structure Figure 2B As seen in the diagram, especially in the Figure 2C This means that the photodetector PD cannot use all the light that strikes the surface. Even if this problem can be mitigated by using a layer of microlenses, some part of the sensor surface will always absorb the optical radiation and not convert it into a useful electrical signal.

[0064] Furthermore, light shining on non-photosensitive devices can have undesirable effects because some of the properties of these devices may be altered by the light shining on them. For example, MOS transistors typically contain semiconductor pn junctions that can trap photogenerated carriers and generate unwanted signals in response.

[0065] A more advanced process technology, called backside illumination (BSI), allows for improved use of the available area by exposing the backside (the side of the silicon substrate) of the wafer or die to light. In this way, there is more freedom in routing metal connections and they can be placed over the light-sensitive devices in the pixels, whereas in frontside illumination (FSI) technology, the light-sensitive devices must be exposed to light towards the top of the wafer, so no metal can be placed on top of the light-sensitive devices to maximize the light captured. The proposed invention offers advantages over both BSI and FSI approaches implemented on a single wafer or die.

[0066] As is well known, event-based vision sensors are based on arrays of pixels that generate data in response to the light that strikes them, with each pixel being spatially and / or temporally independent of the others.

[0067] Each of these pixels contains circuitry divided between a light-sensitive portion (e.g., photodiode PD) and a non-light-sensitive portion (e.g., light-sensing circuit PRC, capacitor C1, comparator A1, memory 50, and reset circuit R1). This second portion is responsible for biasing the light-sensitive circuit, collecting the signal generated in response to light, and often performing a first signal conditioning or refinement. Examples of these types of pixels are mentioned in the previous section (Prior Art).

[0068] Typically, these sensors are manufactured as silicon integrated circuits (ICs) based on planar processes. This means that the light-sensitive portion of the pixel and the rest of the circuitry must be implemented using a single-layer semiconductor device. A direct consequence of this is that part of the pixel area must be occupied by non-light-sensitive circuitry, effectively reducing the pixel's fill factor ( Figure 2A 、 Figure 2B and Figure 2C ). As a result, quantum efficiency is reduced. This is also true for backside illuminated (BSI) ICs manufactured on a single wafer or die.

[0069] Using the proposed invention, the fill factor of pixels in event-based vision sensors can be maximized by stacking multiple wafers or dies, utilizing a technology known as three-dimensional integrated circuits (3D ICs).

[0070] Using this technology, the circuitry for a pixel can be divided between different wafers or dies, potentially maximizing the area of ​​the light-sensitive devices since they can overlap with the non-light-sensitive portions of the circuitry. Furthermore, the circuitry on the wafer below the top wafer does not receive any (or nearly any) light radiation, which is captured by the top wafer, thereby significantly reducing undesirable behavior in the non-light-sensitive circuitry due to incident light.

[0071] Another advantage of this approach is that two different processes can be used to manufacture the two wafers or dies, allowing the best available process to be selected for the photosensitive device and the rest of the circuit. Typically, the technical requirements of these two circuits do not completely overlap.

[0072] Examples of Implementation

[0073] exist Figures 3A to 3C In , a first (and preferred) embodiment of the proposed invention is presented. Figure 3A and Figure 3B In , a vertical cross section of the IC of the EBVS is depicted. Figure 3AIn FIG, two stacked wafers (or dies) are shown. Connection to the bottom wafer (Wafer 2) is provided by wire bond pads 210 deposited on the top surface of the top wafer (Wafer 1). Electrical connections are provided through the body of the top wafer 1 using TSVs (Through Silicon Vias). These TSVs terminate in Cu-Cu connectors, such as copper ball bumps. In this way, electrical connections extend from the bottom of the top wafer to the circuitry on the top of the bottom wafer, Wafer 2.

[0074] Note that in this specification, die and wafer are used interchangeably. Typically, a "die" is a piece or portion of a semiconductor wafer, typically rectangular in shape, such as a chip. Here, this semiconductor wafer includes a portion of an integrated circuit device instance, such as an event-based vision sensor. Reference to wafers or die is based on the possibility of different manufacturing methods. Stacking can be performed at the wafer level before cutting into die. Alternatively, stacking can be performed on individual dies after they have been cut or diced from the wafer. However, the final separated device (i.e., EBVS) resulting from the manufacturing process will be a stack of dies.

[0075] Figure 3B A detail of a vertical cross-section of an EBVS pixel is shown. It can be seen how light impinges only on the surface of the top wafer (Wafer 1) on the substrate side (BSI) and how only the photosensitive device, the photodiode PD, is present in this wafer. A single Cu-Cu connector CC per pixel can then be used to connect to the bottom wafer (or die). In the bottom wafer (Wafer 2), the non-photosensitive part of the pixel circuitry, for example, the comparator A1, is implemented.

[0076] Figure 3C This example is referenced in PCT / IB2017 / 058526 and U.S. Publication No. 2018 / 0191972 and Figure 1 The pixel circuitry presented in FIG2 is similar to that presented in FIG2 , but other architectures for event detection pixels can be used. FIG2 shows how the circuitry is distributed between two wafers (or dies): on the top wafer / die, wafer 1, only the photodiode PD is implemented, while the rest of the pixel circuitry is implemented in the bottom wafer / die; in each pixel, a Cu-Cu CC connection exists between the photodiode and the light receiving circuitry. The event detector on wafer 2 is also shown. The readout circuitry can be provided on wafer 2 or on another wafer or die.

[0077] exist Figure 3D , this circuit is shown in more detail by a circuit schematic of a photoreceptor circuit PRC implemented on wafer 2 .

[0078] exist Figure 4A and Figure 4B Another embodiment is shown in FIG. 1 . The circuit for selecting a pixel is the same as Figure 3C and Figure 3D The circuits shown are the same, but the arrangement of the circuit elements differs between wafers / dies.

[0079] In addition, similar to Figure 4B The wafer / die partitioning shown in will also allow the circuitry in the bottom wafer to be implemented entirely with p-type MOSFET devices, since the event detector can be implemented with only p-type devices. This approach is interesting because it allows for a further reduction in pixel area, since the entire field of pixels can be placed in the same n-well. Typically, a minimum gap must be considered between the n-type MOSFET devices and the n-well (where the p-type MOSFET devices are located). If there are no n-type devices and all pixels are contained in a single n-well, the area required for the pixel can be smaller than if both devices were used in each pixel.

[0080] like Figure 4B As shown, in the top wafer, wafer 1, two n-FET transistors (M1 and MA1) from the light receiving circuit PRC are added along with the photodiode PD. Thus, the cross-wafer / die Cu-Cu connection CC is located between the node connected to the gate of the feedback transistor M1 and the drain of MA1 and the node connected to the drain of the bias p-FET transistor MA2 and the input of the event detector, which corresponds to Figure 1 One plate of capacitor C1 in the middle. With this setup, the performance of light detection can be improved without reducing the fill factor too much and keeping the complexity of the top wafer low (effectively limiting the number of process masks required for manufacturing). Performance is improved especially with respect to noise: Cu-Cu connections typically introduce a certain resistance due to the need for metal layers and vias to reach the surface of one wafer and then to the device in the other wafer, and this resistance introduces thermal noise. In addition, such stacking of metal layers and vias is usually done with different metals, introducing noise associated with such metal junctions. For this reason, similar Figure 4A and Figure 4B The solution shown can be beneficial without sacrificing too much of the area benefits first introduced by wafer / die stacking technology. In addition, this solution allows for smaller pixel sizes because less area is required on the lower wafer, Wafer 2, because fewer transistors are needed. Another advantage of this solution (and other solutions that include transistors on both wafers) is that the characteristics of the two transistors on the upper wafer can be optimized independently of the characteristics of the transistors on the lower wafer, Wafer 2.

[0081] exist 5A to 5D , a third embodiment is shown. This again refers to the circuit of the previous embodiment, with the addition of bias transistors for the front-end circuitry in the top wafer, wafer 1. Finally, a buffer stage can also be added, preferably implemented as a source follower amplifier stage.

[0082] This embodiment has the advantage of increasing the circuit's drive capability before cross-wafer (cross-die) connections. In particular, if a buffer stage is added, the resistance of the Cu-Cu CC connection has less impact on the performance of the front-end because the load on the output node is reduced. In this case, the Cu-Cu connection would be located between the output nodes of the front-end, which in one example currently includes the gate of M1, the drain of MA1 and the drain of MA2, and the input of the event detector circuit, which corresponds to one plate of capacitor C1.

[0083] However, the biggest advantage of this approach is related to the fact that capacitor C1 is typically manufactured as a MIM (metal-insulator-metal) capacitor. This type of device is manufactured using two metal layers, which can be the topmost layer of a silicon planar process or, ultimately, one metal layer below the topmost layer. The output of the circuit implemented in the top wafer can then be directly connected to the top plate of the MIM capacitor, allowing the capacitor size to be maximized because it can be implemented by occupying the entire area of ​​the pixel, as the circuit in the top wafer does not need to be connected to any other nodes besides the top plate of the MIM capacitor C1.

[0084] This approach then greatly simplifies pixel layout by judiciously distributing the devices between the two wafers / dies, ultimately allowing for smaller pixels.

[0085] This can be Figure 5B This figure is a simplified representation of two stacked wafers Wafer 1 and Wafer 2 implemented in silicon planar process technology, depicting the various layers that form the wafers. It can be seen how the last metal layer in the top wafer is directly connected to one plate of the MIM capacitor C1. In this specific representation, the top wafer / die is set up as BSI (back side illumination) and therefore receives light on the substrate side, and is connected to the other wafer using Cu-Cu connectors CC, so that the two corresponding top metal layers of the two wafers / dies are bonded together. To simplify the drawing, the photodiode junction described here is implemented as an n-well in a p-substrate, but more advanced structures are actually preferred.

[0086] Figure 5C and Figure 5D Two different circuit layouts are shown. Figure 5D In the embodiment, the front end includes a buffer amplifier B (preferably a source follower amplifier).

[0087] An FSI (front side illumination) approach of the top wafer can be implemented, connecting it to the bottom wafer using TSVs (through silicon vias).

[0088] Using this same approach and the same transistor setup between the two wafers (or dies), the MIMI capacitor C1 can alternatively be placed in the top wafer (or die) Wafer 1 instead of the bottom wafer (or die) Wafer 2. This approach can be justified, for example, by specifically considering the metal layers so as to be distributed between the wafers (or dies) according to the most cost-effective solution: the two wafers may be implemented in two different technologies, and in one of the technology processes adding metal layers or MIM-specific metal layers may be cheaper than the other.

[0089] In all wafer representations shown along the document, on the side exposed to light, a stack of layers implementing microlenses and / or optical waveguides may be added to improve the QE of the optical receiver, but for simplicity this is not shown in the figures.

[0090] exist Figure 6A In FIG, an alternative embodiment of the pixel front end is depicted. In this case, only one cross-wafer (or chip) connection is required per pixel. The top wafer 1 contains the transistors forming the pixel front end including the photosensitive circuit PRC together with the photodiode PD.

[0091] exist Figure 6B In Figure 1, it is shown how an amplifier stage B can eventually be added, preferably implemented as a source follower amplifier, and how it can be included in the top wafer, Die 1. This will have the advantage of increasing the driving capability of the front end, effectively limiting the load on the front end output nodes (gate of M1, drain of MA1 and drain of MA2). In fact, without any amplifier stage, the Cu-Cu CC connection can have a non-negligible resistance that will directly load the output of the front end.

[0092] exist Figure 7A In the Figure 5B The pixel front-end circuit is shown, with the amplification stage explicitly shown as a source-follower amplifier implemented using n-FET MOS devices. The solution proposed here does not have p-FET devices in the top wafer, so more than one cross-wafer (or die) connection is required, specifically two per pixel.

[0093] The choice of no p-FET MOS devices in the top wafer has the advantage of improving the QE effect, since if an n-well is present in the illuminated wafer, it attracts carriers generated by the incident light, acting as a parasitic photodiode connected between the supply voltage and ground.

[0094] exist Figure 7C In , an alternative pixel front-end implementation is shown, with Figure 6B In the proposed embodiment, as Figure 7AAs shown, the top illumination wafer does not contain p-FET MOS devices, so each pixel requires multiple cross-wafer (or die) connections, in this particular case four per pixel. The buffer stage is implemented as a source follower amplifier and consists of n-FET devices.

[0095] exist Figure 7C In the figure, it is shown that Figure 7B The same pixel structure is used in , but the source follower amplifier used as a buffer is implemented using a p-FET MOS device. This way, one connection can be spared per pixel, only three are needed.

[0096] In general, the pixel circuit can be partitioned in many different ways, all with potential advantages and disadvantages. For example, if the focus is on finding the best technology for each part of the circuit, you might consider separating the digital and analog portions of the circuit. In addition, stacking technology does not impose a theoretical limit on the number of wafers / dies that can be stacked together and connected vertically, for example, by using Cu-Cu connectors and TSVs. Connectors can be placed in each pixel or on the edge of the pixel array, for example, once per column and / or once per row.

[0097] While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention as encompassed by the appended claims.

Claims

1. An event-based visual sensor, comprising a first die and a second die stacked, wherein: The photodiode of each pixel of the pixel array is located on the first die, An event detector for each pixel of the pixel array and a photosensitive circuit for generating a photosensitive signal according to light intensity and inputting the photosensitive signal into the event detector are located on the second die, The photosensitive circuit includes a plurality of transistors. The event detector includes a storage capacitor, a comparator and a memory, The storage capacitor includes a metal-insulator-metal structure capacitor, a first plate of the metal-insulator-metal structure capacitor is connected to the light sensing signal generated by the light sensing circuit, a second plate of the metal-insulator-metal structure capacitor is connected to one input terminal of the comparator, and another input terminal of the comparator is connected to a threshold signal applied by a controller, and The output of the comparator is stored in the memory.

2. The event-based visual sensor of claim 1, wherein: A conditional reset circuit is connected between the second plate of the metal-insulator-metal structure capacitor and one input terminal of the comparator, and the conditional reset circuit is configured to switch the conduction state according to a combination of the output of the comparator stored in the memory and a reset signal applied by the controller.

3. The event-based vision sensor of claim 1, wherein: The first die uses a backside illumination architecture in which the wiring layers are behind the light radiating surface.

4. The event-based vision sensor of claim 1, wherein: The first die and the second die are connected to each other with Cu-Cu connectors.

5. The event-based vision sensor of claim 1, wherein: The first die and / or the second die include stacked dies, and the stacked dies have through silicon via connections.

6. The event-based vision sensor of claim 1, wherein: The photosensitive circuit includes an n-FET transistor and a p-FET transistor.

7. The event-based vision sensor of claim 1, wherein: The photosensitive circuit includes two n-FET transistors and a p-FET transistor.

8. A method for manufacturing the event-based vision sensor according to claim 1.

9. The method according to claim 8, wherein: A conditional reset circuit is connected between the second plate of the metal-insulator-metal structure capacitor and one input terminal of the comparator, and the conditional reset circuit is configured to switch the conduction state according to a combination of the output of the comparator stored in the memory and a reset signal applied by the controller.

10. The method according to claim 8, wherein: The first die uses a backside illumination architecture in which the wiring layers are behind the light radiating surface.

11. The method according to claim 8, wherein: The first die and the second die are connected to each other with Cu-Cu connectors.

12. The method according to claim 8, wherein: The first die and / or the second die include stacked dies, and the stacked dies have through silicon via connections.

13. The method according to claim 8, wherein: The photosensitive circuit includes an n-FET transistor and a p-FET transistor.

14. The method according to claim 8, wherein: The photosensitive circuit includes two n-FET transistors and a p-FET transistor.

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