A Micro-LED chip structure and preparation method for reducing sidewall defect recombination

Abstract

The present invention discloses a composite Micro-LED chip structure with reduced sidewall defects and a preparation method thereof. Based on the traditional Micro-LED chip structure, the structures among the P-type semiconductor material layer, the P-type heavily doped semiconductor material layer and the N-type material transport layer of the chip structure are changed; the P-type heavily doped semiconductor material layer is only located in the middle area above the P-type semiconductor material layer, and the N-type material transport layer completely covers the P-type semiconductor material layer and the P-type heavily doped semiconductor material layer, wherein the N-type material transport layer is in direct contact with part of the P-type semiconductor material layer; the device structure proposed in the present invention utilizes the reverse bias junction formed at the contact interface between the N-type material transport layer and the P-type semiconductor material layer to deplete the holes in the P-type semiconductor material layer, thereby reducing the non-radiative recombination effect in the chip sidewall area, and at the same time can also improve the lateral limitation effect of the injected current, thereby reducing the optical crosstalk effect between display pixels.

Description

Technical Field

[0001] The present invention relates to a novel Micro-LED chip structure and a preparation method for reducing sidewall defect recombination, and in particular to a preparation method for a high-power micro semiconductor light emitting diode, belonging to the technical field of semiconductor optoelectronic devices. Background Art

[0002] With the continuous innovation and development of display technology, the size of each pixel display unit is constantly decreasing, and Micro-LED display technology has emerged. It inherits the high efficiency, high brightness, high reliability and fast response time of inorganic LEDs, and has the characteristics of self-luminescence without backlight. It also has the advantages of energy saving and environmental protection, simple structure, compact size, and thin devices. It is expected to be applied to augmented reality micro-projection devices and automotive head-up display projections with high brightness requirements, and expand to many fields such as wearable devices, virtual reality, optical communications, and space imaging, and is expected to shine in the fields of display and visible light communication.

[0003] However, as the device size continues to decrease, the uneven damage around the device caused by cutting damage will lead to current leakage and external quantum efficiency attenuation, affecting the overall luminescence characteristics, especially when the device size is reduced to below 100μm, this sidewall damage effect becomes more serious. Therefore, the development of Micro-LED display technology is severely restricted by the device size effect. Based on this, researchers have conducted a series of studies and proposed to use insulating materials such as AlN, SiO2 or Al2O3 as passivation layers to suppress the sidewall damage effect and improve the external quantum efficiency of Micro-LED. For example, by using atomic layer deposition technology combined with wet etching process, the study found that it can reduce the damage caused by etching to the ITO layer or p-GaN layer to a certain extent, alleviate the sidewall damage effect, and improve the optoelectronic performance of Micro-LED. Not only is the luminous intensity more uniform, but the current leakage is significantly reduced, but this does not completely solve the problem of Micro-LED luminous efficiency and uniformity (Wong MS, et al. High efficiency of III-nitride micro-light-emitting diodes by sidewall passivation using atomiclayer deposition [J]. Optics Express, 2018, 26); Chinese patent number CN202010401581.5 discloses a preparation method, structure and display terminal of a Micro-LED chip. The structure bombards the middle position of the ITO layer with oxygen ions to increase the conductivity of the middle position of the ITO layer, while the conductivity of the surrounding area is relatively low, effectively avoiding the leakage phenomenon, current congestion effect and thermal effect caused by the large conductivity of the upper and lower edge areas, and improving the luminous efficiency. However, this method is complicated, and ITO is originally a good N-type semiconductor. Even if the local conductivity is improved by oxygen ion bombardment, it cannot produce a significant potential difference between the middle and edge positions of ITO, and cannot effectively confine the current to the middle area of ​​the device. Therefore, a new chip structure design is urgently needed to modulate the lateral distribution law of current inside the device. Summary of the invention

[0004] The purpose of the present invention is to provide a Micro-LED chip structure and a preparation method thereof for reducing sidewall defect recombination in view of the shortcomings of the current technology, and to use the reverse bias junction formed at the interface between the N-type material transmission layer and the P-type semiconductor material layer to deplete the holes in the P-type semiconductor material layer, thereby reducing the non-radiative recombination effect of the chip sidewall area, and at the same time, it can also improve the lateral restriction effect of the injected current, so that the light-emitting area of ​​the chip is concentrated in the middle position of the chip, thereby reducing the optical crosstalk effect between display pixels. The preparation method of the present invention is simple, highly operable, and low in cost.

[0005] The technical solution adopted by the present invention to solve the technical problem is:

[0006] A Micro-LED chip structure that reduces sidewall defect recombination, wherein a P-type heavily doped semiconductor material layer is only located in the middle area above the P-type semiconductor material layer; an N-type material transmission layer completely covers the P-type semiconductor material layer and the P-type heavily doped semiconductor material exposed layer; and the N-type material transmission layer is in direct contact with a portion of the P-type semiconductor material layer.

[0007] The area of ​​the exposed portion of the edge of the P-type semiconductor material layer of the chip structure accounts for 1% to 80% of its total area.

[0008] The material of the N-type material transmission layer of the chip structure is GaN, GaP, ZnO, ITO, graphene, AZO, Ni / Au or Al.

[0009] The chip structure Micro-LED chip is any one of the standard Micro-LED chips, and includes, from bottom to top, a substrate, a buffer layer, an undoped semiconductor material layer, an N-type semiconductor material layer, a multi-quantum well layer, a P-type confinement layer, a P-type semiconductor material layer, a P-type heavily doped semiconductor material layer and an N-type material transmission layer; and corresponding P-type ohmic electrodes and N-type ohmic electrodes.

[0010] A method for preparing a Micro-LED chip structure with reduced sidewall defect compounding of the present invention comprises the following steps:

[0011] 1) etching the edge region of the P-type heavily doped semiconductor material layer to expose the P-type semiconductor material layer through photolithography and wet etching processes, wherein the P-type heavily doped semiconductor material layer is located in the middle region above the P-type semiconductor material layer and occupies 20% to 99% of the area of ​​the P-type semiconductor material layer;

[0012] 2) Surface deposition or secondary epitaxial growth is performed on the obtained P-type heavily doped semiconductor material layer and the upper surface of the P-type semiconductor material layer; and an N-type material transport layer.

[0013] The specific instructions are as follows:

[0014] A Micro-LED chip structure for reducing sidewall defect recombination, based on a conventional Micro-LED chip structure, the difference of the novel chip structure lies in the structural design between a P-type semiconductor material layer (107), a P-type heavily doped semiconductor material layer (108) and an N-type material transport layer (109); the P-type heavily doped semiconductor material layer (108) is only located in the middle region above the P-type semiconductor material layer (107); the N-type material transport layer (109) is completely located above the P-type semiconductor material layer (107) and the P-type heavily doped semiconductor material layer (108); wherein the N-type material transport layer (109) is in direct contact with a portion of the P-type semiconductor material layer (107); and this innovative technology is applicable to a full-band Micro-LED chip structure.

[0015] The present invention discloses a novel Micro-LED chip structure for reducing sidewall defect recombination, characterized in that the P-type heavily doped semiconductor material layer (108) is located above the P-type semiconductor material layer (107), and the lateral size of the P-type heavily doped semiconductor material layer (108) is definitely smaller than the lateral size of the P-type semiconductor material layer (107), and the area of ​​the edge exposed portion of the P-type semiconductor material layer (107) accounts for 1% to 80% of its total area; the N-type material transmission layer (109) is located above the P-type semiconductor material layer (107) and the P-type heavily doped semiconductor material layer (108), and is in direct contact with the entire P-type heavily doped semiconductor material layer (108), and is in direct contact with the edge exposed portion of the P-type semiconductor material layer (107); wherein the lateral size of the N-type material transmission layer (109) is the same as the lateral size of the P-type semiconductor material layer (107).

[0016] The present invention discloses a novel Micro-LED chip structure for reducing sidewall defect recombination, characterized in that the material of the N-type material transmission layer (109) is GaN, GaP, ZnO, ITO, graphene, AZO, Ni / Au or Al.

[0017] The present invention discloses a novel Micro-LED chip structure for reducing sidewall defect recombination, wherein the Micro-LED chip is any one of standard Micro-LED chips, wherein the standard Micro-LED chip mainly comprises a substrate (101), a buffer layer (102), a non-doped semiconductor material layer (103), an N-type semiconductor material layer (104), a multi-quantum well layer (105), a P-type confinement layer (106), a P-type semiconductor material layer (107), a P-type heavily doped semiconductor material layer (108), an N-type material transmission layer (109), a P-type ohmic electrode (110), and an N-type ohmic electrode (111).

[0018] The present invention provides a novel Micro-LED chip structure for reducing sidewall defect recombination, comprising the following steps:

[0019] 1) Based on the existing epitaxial deposition technology level, a buffer layer (102), a non-doped semiconductor material layer (103), an N-type semiconductor material layer (104), a multi-quantum well layer (105), a P-type confinement layer (106), a P-type semiconductor material layer (107), a P-type heavily doped semiconductor material layer (108) and an N-type material transmission layer (109) are sequentially epitaxially grown on the surface of a substrate (101) to obtain a standard Micro-LED chip epitaxial structure;

[0020] 2) etching the edge region of the P-type heavily doped semiconductor material layer (108) through photolithography and wet etching processes until the P-type semiconductor material layer (107) is exposed, wherein the P-type heavily doped semiconductor material layer (108) is located in the middle region above the P-type semiconductor material layer (107) and occupies 20% to 99% of the area of ​​the P-type semiconductor material layer (107);

[0021] 3) An N-type material transport layer (109) is evaporated or epitaxially grown on the upper surface of the P-type heavily doped semiconductor material layer (108) and the P-type semiconductor material layer (107) obtained in step 2.

[0022] Thus, a novel Micro-LED chip structure with reduced sidewall defect recombination is obtained.

[0023] The essential features of the present invention are:

[0024] The etching process of Micro-LED chips will cause serious damage to the side walls of the chip, resulting in a large number of defects on the side walls of the chip, thus becoming a channel for non-radiative recombination. For Micro-LED chips with traditional structures, a large number of carriers in the edge area will be consumed by these defects, resulting in low chip luminous efficiency and poor luminous uniformity. However, the Micro-LED chip structure of the present invention uses the reverse-biased junction formed at the interface between the N-type material transmission layer and the P-type semiconductor material layer in the edge area to deplete the holes in the edge area of ​​the P-type semiconductor material layer, so that the carriers are concentrated and distributed in the middle area of ​​the chip, thereby reducing the non-radiative recombination effect of the chip side wall area, greatly improving the chip's luminous efficiency, and also helping to improve the lateral limitation of the injected current, so that the chip's luminous area is concentrated in the middle of the chip, thereby reducing the optical crosstalk effect between display pixels, and the chip's luminous uniformity is effectively improved.

[0025] The beneficial effects of the present invention are as follows: compared with the prior art, the present invention has the following outstanding substantive features and significant improvements:

[0026] (1) The Micro-LED chip structure of the present invention is to etch away the P-type heavily doped semiconductor material layer above the edge portion of the P-type semiconductor material layer, and then grow an N-type material transport layer. In the edge region of the chip, the reverse bias junction formed at the interface between the N-type material transport layer and the P-type semiconductor material layer is utilized to deplete the holes in the edge region of the P-type semiconductor material layer, thereby improving the lateral distribution of carriers inside the chip and reducing the sidewall effect of the Micro-LED.

[0027] (2) The present invention utilizes the reverse bias junction formed at the interface between the N-type material transport layer and the P-type semiconductor material layer to modulate the traditional distribution trend of carriers inside the chip, so that the carriers are concentrated and distributed in the middle area of ​​the chip. This can not only weaken the non-radiative recombination intensity in the edge area of ​​the chip and improve the luminous efficiency of the chip, but also concentrate the luminous area in the middle position of the chip, which can effectively improve the luminous uniformity of the chip and reduce the optical crosstalk effect between display pixels to a certain extent.

[0028] (3) The method of the present invention has strong operability, low cost, simple and reliable process, and is suitable for industrial promotion and use.

[0029] The present invention discloses a novel Micro-LED chip structure for reducing sidewall defect recombination, which is specially suitable for optoelectronic semiconductor devices, and in particular for micro semiconductor light emitting diodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Schematic diagram of the structure of a new Micro-LED chip for reducing sidewall defect recombination in Example 1.

[0031] Figure 2 Schematic diagram of the epitaxial wafer structure of the standard Micro-LED chip of Example 1 and Example 2.

[0032] Figure 3 For Example 1 Figure 2 The product shown is a schematic structural diagram in which a step is made by photolithography and dry etching to expose the N-type semiconductor material layer, and then the edge area of ​​the P-type heavily doped semiconductor material layer is etched on its surface by photolithography and wet etching processes until the P-type semiconductor material layer is exposed.

[0033] Figure 4 For Example 1 Figure 3 The product shown is a schematic structural diagram after an N-type material transport layer is grown on its P-type heavily doped semiconductor material layer and a portion of the P-type semiconductor material layer.

[0034] Figure 5 : is a performance comparison chart of the traditional Micro-LED chip structure in Example 1 and the novel Micro-LED chip structure of the present invention; wherein Figure 5a is a graph showing the internal quantum efficiency and luminous intensity of the conventional Micro-LED chip structure and the novel Micro-LED chip structure of the present invention in Example 1; Figure 5 b is a lateral distribution diagram of hole concentration in the P-type semiconductor material layer of the traditional Micro-LED chip structure in Example 1 and the novel Micro-LED chip structure of the present invention.

[0035] Figure 6 For Example 2 Figure 2 The product shown is a schematic structural diagram of a surface of which the edge area of ​​the P-type heavily doped semiconductor material layer is etched through photolithography and wet etching processes to expose the P-type semiconductor material layer.

[0036] Figure 7 For Example 2 Figure 6 The product shown is a schematic structural diagram after an N-type material transmission layer is evaporated on its P-type heavily doped semiconductor material layer and a portion of the P-type semiconductor material layer.

[0037] Figure 8 Schematic diagram of the structure of a new type of Micro-LED chip that reduces sidewall defect recombination in Example 2.

[0038] Among them, 101. substrate, 102. buffer layer, 103. non-doped semiconductor material layer, 104. N-type semiconductor material layer, 105. multi-quantum well layer, 106. P-type confinement layer, 107. P-type semiconductor material layer, 108. P-type heavily doped semiconductor material layer, 109. N-type material transport layer, 110. P-type ohmic electrode, 111. N-type ohmic electrode. DETAILED DESCRIPTION

[0039] The present invention is further described below in conjunction with embodiments and drawings, but this is not intended to limit the scope of protection of the claims of this application.

[0040] The present invention provides a novel Micro-LED chip structure (abbreviated as epitaxial structure, see Figure 1 ), the structure includes, along the epitaxial growth direction, a substrate 101, a buffer layer 102, a non-doped semiconductor material layer 103, an N-type semiconductor material layer 104, a multi-quantum well layer 105, a P-type confinement layer 106, a P-type semiconductor material layer 107, a P-type heavily doped semiconductor material layer 108, an N-type material transport layer 109, a P-type ohmic electrode 110, and an N-type ohmic electrode 111. The N-type material transport layer 109 is located on a portion of the P-type semiconductor material layer 107 and a portion of the P-type heavily doped semiconductor material layer 108, and the P-type ohmic electrode 110 is located on the N-type material transport layer 109.

[0041] Among them, the P-type heavily doped semiconductor material layer 108 is only located in the middle area above the P-type semiconductor material layer 107, accounting for 20% to 99% of the area of ​​the P-type semiconductor material layer 107, so that the N-type material transmission layer 109 is directly in contact with the P-type semiconductor material layer 107, and its contact area accounts for 1% to 80% of the area of ​​the P-type semiconductor material layer 107.

[0042] The material of the P-type semiconductor material layer 107 includes but is not limited to AlGaInP or AlInGaN;

[0043] The material of the P-type heavily doped semiconductor material layer 108 includes but is not limited to AlGaInP or AlInGaN;

[0044] The material of the N-type material transmission layer 109 includes but is not limited to AlGaInP, AlInGaN, indium tin oxide, nickel, graphene or zinc oxide.

[0045] The present invention provides a method for preparing a novel Micro-LED chip structure with reduced sidewall defect recombination, the method comprising the following steps:

[0046] In the first step, the substrate 101 is cleaned in ultrasound using acetone, anhydrous ethanol, and deionized water in sequence, each ultrasonic cleaning lasting 5 to 10 minutes to remove foreign matter attached to the surface of the substrate 101;

[0047] The second step is to epitaxially grow a buffer layer 102 with a thickness of 0.01 μm to 0.05 μm on the surface of the substrate 101 processed in the first step at a low temperature in a MOCVD or MBE reactor to realize a nucleation layer and release stress caused by lattice mismatch;

[0048] The third step is to epitaxially grow a non-doped N-type semiconductor material layer 103 with a thickness of 2 μm to 6 μm on the buffer layer 102 obtained in the second step in a MOCVD or MBE reactor at a high temperature to achieve the function of filtering dislocations;

[0049] In the fourth step, in a MOCVD or MBE reactor, a 0.1 μm to 3 μm thick N-type semiconductor material layer 103 obtained in the third step is deposited with a doping concentration of 1×10 16 cm -3 ~1×10 19 cm -3 N-type semiconductor material layer 104;

[0050] Step 5: In a MOCVD or MBE reactor, epitaxially grow a multi-quantum well layer 105 on the N-type semiconductor material layer 104 obtained in step 4; the thickness is 0.01 μm to 0.5 μm, and the doping concentration is 1×10 17 cm -3~1×10 19 cm -3 The P-type confinement layer 106 has a thickness of 0.05 μm to 2 μm and a doping concentration of 1×10 17 cm -3 ~1×10 19 cm -3 The P-type semiconductor material layer 107 has a thickness of 0.05 μm to 1 μm and a doping concentration of 1×10 17 cm -3 ~1×10 20 cm -3 A P-type heavily doped semiconductor material layer 108. The thickness of the quantum barrier AlGaInP or AlInGaN is 1nm to 30nm, the thickness of the quantum well AlGaInP or AlInGaN is 1nm to 15nm, the bandgap width of the quantum barrier is greater than the bandgap width of the quantum well, the number of quantum barriers is always one more than the number of quantum wells, and there is at least one quantum well;

[0051] Step 6: On the P-type heavily doped semiconductor material layer 108 obtained in step 5, a mesa is formed by photolithography and dry etching to expose a portion of the N-type semiconductor material layer 104;

[0052] Step 7: On the mesa obtained in step 6, the edge region of the P-type heavily doped semiconductor material layer 108 is etched away by photolithography and wet etching processes until the P-type semiconductor material layer 107 is exposed, and the P-type heavily doped semiconductor material layer 108 is located in the middle region above the P-type semiconductor material layer 107, and occupies 20% to 99% of the area of ​​the P-type semiconductor material layer 107;

[0053] Step 8: Vapor-deposit or secondary epitaxially grow an N-type material transport layer 109 on the P-type heavily doped semiconductor material layer 108 and the P-type semiconductor material layer 107 obtained in the seventh step;

[0054] In the ninth step, a P-type ohmic electrode 110 is prepared by evaporation on the N-type material transport layer 109 obtained in the eighth step, and an N-type ohmic electrode 111 is prepared by evaporation on the table of the N-type semiconductor material layer 104;

[0055] Thus, a novel Micro-LED chip structure with reduced sidewall defect recombination is obtained.

[0056] Example 1

[0057] This embodiment is a novel Micro-LED chip structure for reducing sidewall defect recombination, and the epitaxial structure thereof includes, in order along the epitaxial growth direction: a substrate 101, a buffer layer 102, an undoped semiconductor material layer 103, an N-type semiconductor material layer 104, a multi-quantum well layer 105, a P-type confinement layer 106, a P-type semiconductor material layer 107, a P-type heavily doped semiconductor material layer 108, an N-type material transport layer 109, a P-type ohmic electrode 110, and an N-type ohmic electrode 111. The lateral size of the chip is 10 μm, the material of the N-type material transport layer 109 is indium tin oxide, the P-type heavily doped semiconductor material layer 108 is located in the middle area above the P-type semiconductor material layer 107, and occupies 80% of the area of ​​the P-type semiconductor material layer 107, and the N-type material transport layer 109 is in direct contact with the P-type semiconductor material layer 107, and its contact area occupies 20% of the area of ​​the P-type semiconductor material layer 107.

[0058] In the above, the substrate 101 is sapphire, epitaxially grown along the

[0001] direction; the material of the buffer layer 102 is GaN, with a thickness of 10 nm; the material of the non-doped semiconductor material layer 103 is GaN, with a thickness of 4 μm; the material of the N-type semiconductor material layer 104 is GaN, with a thickness of 2 μm and a doping concentration of 5×10 18 cm -3 ; The structure of the multi-quantum well layer 105 is 4 periods of In 0.25 Ga 0.75 N / GaN layer, in which the thickness of quantum barrier GaN is 6nm, and the quantum well In 0.15 Ga 0.85 The thickness of N is 3nm; the material of P-type confinement layer 106 is Al 0.15 Ga 0.85 N, thickness is 26nm, doping concentration is 4×10 17 cm -3 The material of the P-type semiconductor material layer 107 is GaN, the thickness is 120nm, and the doping concentration is 5×10 17 cm -3 The material of the P-type heavily doped semiconductor material layer 108 is GaN, with a thickness of 20 nm and a doping concentration of 5×10 19 cm -3 ; The material of the N-type material transmission layer 109 is indium tin oxide with a thickness of 20 nm; the material of the P-type ohmic electrode 110 is Cr / Au; the material of the N-type ohmic electrode 111 is Ti / Au.

[0059] The above-mentioned novel Micro-LED chip structure has a reduced sidewall defect recombination, and its preparation method is as follows:

[0060] In the first step, the substrate is cleaned in ultrasound using acetone, anhydrous ethanol, and deionized water in sequence, with the growth surface facing upward, and each ultrasonic cleaning lasts for 10 minutes to remove foreign matter attached to the surface of the substrate 101;

[0061] In the second step, in an MOCVD reactor, a buffer layer GaN with a thickness of 10 nm is epitaxially grown on the surface of the substrate 101 processed in the first step at a growth temperature of 550° C. and a gas pressure of 200 mbar to realize a nucleation layer and release stress caused by lattice mismatch;

[0062] Step 3: epitaxially grow a non-doped GaN layer 103 with a thickness of 4 μm on the buffer layer 102 obtained in the second step in a MOCVD reactor at a growth temperature of 1050° C. and a gas pressure of 200 mbar to achieve the function of filtering dislocations;

[0063] In the fourth step, in the MOCVD reactor, an epitaxial growth with a thickness of 2 μm and a doping concentration of 5×10 18 cm -3 The N-type semiconductor material layer 104 is grown at a temperature of 1050° C. and a gas pressure of 300 mbar;

[0064] Step 5: epitaxially grow 4 cycles of In on the N-type semiconductor material layer 104 obtained in the fourth step in a MOCVD reactor. 0.15 Ga 0.85 N / GaN multi-quantum well layer 105, wherein the thickness of the quantum barrier GaN is 6nm, and the quantum well In 0.15 Ga 0.85 The thickness of N is 3nm, the regrown thickness is 26nm, and the doping concentration is 4×10 17 cm -3 The P-type confinement layer 106 has a thickness of 120 nm and a doping concentration of 5×10 17 cm -3 The P-type semiconductor material layer 107 has a thickness of 20 nm and a doping concentration of 5×10 19 cm -3 The P-type heavily doped semiconductor material layer 108 is grown at a temperature of 970° C. and a gas pressure of 150 mbar;

[0065] Step 6: On the P-type heavily doped semiconductor material layer 108 obtained in step 5, a mesa is formed by photolithography and dry etching process, the step height is 1.5 μm, the width of the high mesa, i.e. the P-type heavily doped semiconductor material layer 108, is 7 μm, and the width of the low mesa, i.e. the N-type semiconductor material layer 104, is 3 μm, exposing a portion of the N-type semiconductor material layer 104;

[0066] Step 7: On the mesa obtained in step 6, a 0.7 μm width region at the edge of the P-type heavily doped semiconductor material layer 108 is etched away by photolithography and wet etching processes until the P-type semiconductor material layer 107 is exposed. The P-type heavily doped semiconductor material layer 108 has a width of 5.6 μm and is located in the middle region above the P-type semiconductor material layer 107, which accounts for 80% of the area of ​​the P-type semiconductor material layer 107.

[0067] Step 8: Vapor-deposit an N-type material transmission layer 109 with a width of 7 μm and a thickness of 20 nm on the P-type heavily doped semiconductor material layer 108 and a portion of the P-type semiconductor material layer 107 obtained in step 7;

[0068] In the ninth step, a P-type ohmic electrode 110 is prepared by evaporation on the N-type material transport layer 109 obtained in the eighth step, and an N-type ohmic electrode 111 is prepared by evaporation on the table of the N-type semiconductor material layer 104;

[0069] Thus, a novel Micro-LED chip structure with reduced sidewall defect recombination is obtained in this embodiment.

[0070] Figure 1 This is a structural schematic diagram of an embodiment of a novel Micro-LED chip structure for reducing sidewall defect recombination according to the present invention.

[0071] Figure 2 This is a schematic diagram of the epitaxial wafer structure of the standard Micro-LED chip of Example 1 and Example 2, which includes in sequence along the epitaxial growth direction: a substrate 101, a buffer layer 102, an undoped semiconductor material layer 103, an N-type semiconductor material layer 104, a multi-quantum well layer 105, a P-type confinement layer 106, a P-type semiconductor material layer 107 and a P-type heavily doped semiconductor material layer 108.

[0072] Figure 3 For Example 1 Figure 2 The product shown is a schematic diagram of a structure in which, after making steps by photolithography and dry etching to expose the N-type semiconductor material layer, the edge area of ​​the P-type heavily doped semiconductor material layer is etched on its surface by photolithography and wet etching processes until the P-type semiconductor material layer is exposed. The product includes, along the epitaxial growth direction, a substrate 101, a buffer layer 102, an undoped semiconductor material layer 103, an N-type semiconductor material layer 104, a multi-quantum well layer 105, a P-type confinement layer 106, a P-type semiconductor material layer 107 and a P-type heavily doped semiconductor material layer 108.

[0073] Figure 4 For Example 1 Figure 3The product shown is a schematic structural diagram after an N-type material transport layer 109 is evaporated on its P-type heavily doped semiconductor material layer 108 and a portion of the P-type semiconductor material layer 107, which includes, along the epitaxial growth direction, a substrate 101, a buffer layer 102, an undoped semiconductor material layer 103, an N-type semiconductor material layer 104, a multi-quantum well layer 105, a P-type confinement layer 106, a P-type semiconductor material layer 107, a P-type heavily doped semiconductor material layer 108 and an N-type material transport layer 109.

[0074] Figure 5 : is a performance comparison chart of the traditional Micro-LED chip structure in Example 1 and the novel Micro-LED chip structure of the present invention; wherein Figure 5 a is a graph showing the internal quantum efficiency and luminous intensity of the conventional Micro-LED chip structure and the novel Micro-LED chip structure of the present invention in Example 1; Figure 5 b is a lateral distribution diagram of hole concentration in the P-type semiconductor material layer 107 of the conventional Micro-LED chip structure in Example 1 and the novel Micro-LED chip structure of the present invention. Figure 5 (a) and Figure 5 The curve shown in (b) indicates that, in this embodiment, due to the reverse-biased junction formed at the interface between the N-type material transport layer and the P-type semiconductor material layer, the holes in the edge region of the P-type semiconductor material layer are depleted, causing the carriers to aggregate and distribute in the middle region of the chip, thereby reducing the non-radiative recombination effect in the side wall region of the chip, greatly improving the luminous efficiency of the chip. Compared with traditional Micro-LEDs, the hole concentrations at the edges of both sides of the Micro-LED are reduced by 7 orders of magnitude, thereby suppressing the non-radiative recombination in the edge regions on both sides of the Micro-LED, thereby increasing the luminous efficiency of the device by 80%.

[0075] Example 2

[0076] This embodiment is a novel Micro-LED chip structure for reducing sidewall defect recombination, and the epitaxial structure thereof includes, in order along the epitaxial growth direction: substrate 101, buffer layer 102, non-doped semiconductor material layer 103, N-type semiconductor material layer 104, multi-quantum well layer 105, P-type confinement layer 106, P-type semiconductor material layer 107, P-type heavily doped semiconductor material layer 108, N-type material transport layer 109, P-type ohmic electrode 110 and N-type ohmic electrode 111. The lateral size of the chip is 30 μm, the material of the N-type material transport layer 109 is indium tin oxide, the P-type heavily doped semiconductor material layer 108 is located in the middle area above the P-type semiconductor material layer 107, and occupies 90% of the area of ​​the P-type semiconductor material layer 107, and the N-type material transport layer 109 is in direct contact with the P-type semiconductor material layer 107, and its contact area occupies 10% of the area of ​​the P-type semiconductor material layer 107.

[0077] In the above, the substrate 101 is GaAs, epitaxially grown along the (100) crystal plane; the material of the buffer layer 102 is GaAs, with a thickness of 200 nm; the material of the non-doped semiconductor material 103 is Al 0.49 Ga 0.51 As / AlAs, thickness is 44.81nm / 50.46nm; the material of the N-type semiconductor material layer 104 is Al 0.5 In 0.5 P, thickness is 0.5 μm, doping concentration is 5×10 17 cm -3 The structure of the multi-quantum well layer 105 is 10 periods of Al 0.60 InGa 0.40 P / InGaP layer, where the quantum barrier Al 0.60 InGa 0.40 The thickness of P is 12nm, the thickness of quantum well InGaP is 3nm; the material of P-type confinement layer 106 is Al 0.5 In 0.5 P, thickness is 0.5 μm, doping concentration is 1×10 18 cm -3 The material of the P-type semiconductor material layer 107 is GaP, the thickness is 1 μm, and the doping concentration is 5×10 18 cm -3 The material of the P-type heavily doped semiconductor material layer 108 is GaP, the thickness is 2 μm, and the doping concentration is 1×10 19 cm -3 ; The material of the N-type material transmission layer 109 is indium tin oxide with a thickness of 20 nm; the material of the P-type ohmic electrode 110 is Cr / Al / Ti; the material of the N-type ohmic electrode 111 is Ti / Au.

[0078] The above-mentioned novel Micro-LED chip structure has a reduced sidewall defect recombination, and its preparation method is as follows:

[0079] The first step is to bake the substrate 101 at a high temperature in a MOCVD (metal organic chemical vapor deposition) reactor to remove foreign matter attached to the surface of the substrate;

[0080] In the second step, a buffer layer 102 with a thickness of 200 nm is epitaxially grown on the surface of the substrate 101 processed in the first step in an MOCVD reactor at a growth temperature of 650° C. and a gas pressure of 100 mbar to filter dislocations and release stress caused by lattice mismatch;

[0081] Step 3: epitaxially grow 8 pairs of non-doped semiconductor materials 103 with a thickness of 44.81 nm / 50.46 nm on the buffer layer 102 obtained in the second step in a MOCVD reactor at a growth temperature of 680° C. and a gas pressure of 70 mbar;

[0082] In the fourth step, in the MOCVD reactor, epitaxial growth with a thickness of 0.5 μm and a doping concentration of 5×10 17 cm -3 The N-type semiconductor material layer 104 is grown at a temperature of 700° C. and a pressure of 100 mbar;

[0083] Step 5: In the MOCVD reactor, 10 periods of Al are epitaxially grown on the N-type semiconductor material layer 104 obtained in the fourth step. 0.60 InGa 0.40 A P / InGaP multi-quantum well layer 105, a P-type confinement layer 106, a P-type semiconductor material layer 107 and a P-type heavily doped semiconductor material layer 108 are grown at a growth temperature of 750°C and a gas pressure of 120 mbar;

[0084] Step 6: On the P-type heavily doped semiconductor material layer 108 obtained in the fifth step, a 1.5 μm width region at the edge of the P-type heavily doped semiconductor material layer 108 is etched away by photolithography and wet etching processes until the P-type semiconductor material layer 107 is exposed. The P-type heavily doped semiconductor material layer 108 has a width of 27 μm and is located in the middle region above the P-type semiconductor material layer 107, which accounts for 90% of the area of ​​the P-type semiconductor material layer 107.

[0085] Step 7: Vapor-deposit an N-type material transmission layer 109 with a width of 30 μm and a thickness of 20 nm on the P-type heavily doped semiconductor material layer 108 and a portion of the P-type semiconductor material layer 107 obtained in Step 6;

[0086] In the eighth step, a P-type ohmic electrode 110 is prepared by evaporation above the N-type material transport layer 109 obtained in the seventh step, and an N-type ohmic electrode 111 is prepared by evaporation below the substrate 101;

[0087] Thus, a novel Micro-LED chip structure with reduced sidewall defect recombination is obtained in this embodiment.

[0088] Figure 6 For Example 2 Figure 2The product shown is a schematic diagram of the structure after the edge area of ​​the P-type heavily doped semiconductor material layer is etched on its surface through photolithography and wet etching processes to expose the P-type semiconductor material layer, which includes: a substrate 101, a buffer layer 102, an undoped semiconductor material layer 103, an N-type semiconductor material layer 104, a multi-quantum well layer 105, a P-type confinement layer 106, a P-type semiconductor material layer 107 and a P-type heavily doped semiconductor material layer 108 in sequence along the epitaxial growth direction.

[0089] Figure 7 For Example 2 Figure 6 The product shown is a schematic structural diagram after an N-type material transport layer is evaporated on its P-type heavily doped semiconductor material layer and part of the P-type semiconductor material layer, which includes, along the epitaxial growth direction, a substrate 101, a buffer layer 102, an undoped semiconductor material layer 103, an N-type semiconductor material layer 104, a multi-quantum well layer 105, a P-type confinement layer 106, a P-type semiconductor material layer 107, a P-type heavily doped semiconductor material layer 108 and an N-type material transport layer 109.

[0090] Figure 8 Schematic diagram of the structure of a new Micro-LED chip for reducing sidewall defect recombination in Example 2.

[0091] Example 3

[0092] The components and connections of the present embodiment are the same as those of the embodiment 1, except that the lateral size of the chip in the present embodiment is 100 μm, the material of the N-type material transmission layer 109 is ZnO, the thickness is 300 nm, and the doping concentration is 5×10 19 cm -3 The P-type heavily doped semiconductor material layer 108 is located in the middle area above the P-type semiconductor material layer 107, and it occupies 99% of the area of ​​the P-type semiconductor material layer 107. The N-type material transmission layer 109 directly contacts the P-type semiconductor material layer 107, and its contact area occupies 1% of the area of ​​the P-type semiconductor material layer 107.

[0093] The present invention discloses a composite Micro-LED chip structure with reduced sidewall defects and a preparation method thereof. Based on the traditional Micro-LED chip structure, the structures among the P-type semiconductor material layer, the P-type heavily doped semiconductor material layer and the N-type material transmission layer of the chip structure are changed; the P-type heavily doped semiconductor material layer is only located in the middle area above the P-type semiconductor material layer, and the N-type material transmission layer completely covers the P-type semiconductor material layer and the P-type heavily doped semiconductor material layer, wherein the N-type material transmission layer is in direct contact with part of the P-type semiconductor material layer; the device structure proposed in the present invention utilizes the reverse bias junction formed at the contact interface between the N-type material transmission layer and the P-type semiconductor material layer to deplete the holes in the P-type semiconductor material layer, thereby reducing the non-radiative recombination effect in the chip sidewall area, and at the same time can also improve the lateral limitation effect of the injected current, thereby reducing the optical crosstalk effect between display pixels.

[0094] The above embodiments can improve the lateral distribution of carriers inside the chip, reduce the sidewall effect of Micro-LED, weaken the non-radiative recombination intensity in the edge area of ​​the chip, improve the luminous efficiency of the chip, and effectively improve the luminous uniformity of the chip and reduce the light source crosstalk effect between display pixels. The method of the present invention is simple to operate and easy to implement.

[0095] The raw materials involved in the present invention can be obtained through known routes, and the operation process in the preparation method thereof can be mastered by those skilled in the art.

[0096] Any matters not described in the present invention are applicable to the prior art.

Claims

1. A Micro-LED chip structure for reducing sidewall defect recombination, characterized in that: The P-type heavily doped semiconductor material layer is only located in the middle area above the P-type semiconductor material layer; the N-type material transmission layer completely covers the P-type semiconductor material layer and the P-type heavily doped semiconductor material exposed layer; the N-type material transmission layer is in direct contact with part of the P-type semiconductor material layer; The area of ​​the exposed portion of the edge of the P-type semiconductor material layer accounts for 1% to 80% of its total area; the material of the N-type material transmission layer is GaN, GaP, ZnO, ITO, graphene, AZO, Ni / Au or Al; The preparation method comprises the following steps: 1) etching the edge region of the P-type heavily doped semiconductor material layer to expose the P-type semiconductor material layer through photolithography and wet etching processes, wherein the P-type heavily doped semiconductor material layer is located in the middle region above the P-type semiconductor material layer and occupies 20% to 99% of the area of ​​the P-type semiconductor material layer; 2) Vapor deposition or secondary epitaxial growth of an N-type material transport layer is performed on the obtained P-type heavily doped semiconductor material layer and the upper surface of the P-type semiconductor material layer.

2. The chip structure according to claim 1, characterized in that: The Micro-LED chip is any one of the standard Micro-LED chips, and includes, from bottom to top, a substrate, a buffer layer, an undoped semiconductor material layer, an N-type semiconductor material layer, a multi-quantum well layer, a P-type confinement layer, a P-type semiconductor material layer, a P-type heavily doped semiconductor material layer and an N-type material transmission layer and corresponding P-type ohmic electrodes and N-type ohmic electrodes.

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