A HALL SENSOR AND A METHOD FOR MANUFACTURING THE SAME

Abstract

The present invention provides a Hall sensor and a manufacturing method thereof, comprising a P-type substrate and an N-well active region, a P-type covering layer, an extraction electrode and at least four contact holes located on the P-type substrate; the P-type covering layer and the extraction electrode are located in the middle region of the N-well active region; the extraction electrode covers the P-type covering layer and is distributed in the middle region of the P-type covering layer; the at least four contact holes are distributed around the N-well active region and are respectively located at the outer ends of at least four interdigits of the extraction electrode. Therefore, when the Hall sensor is working, a depletion layer can be generated between the N-well active region and the P-type covering layer, thereby effectively reducing the hot carrier effect, improving the Gaussian distribution of impurities in the N-well active region, increasing the effective N-well depth, and reducing the N-well impurity concentration, thereby improving the sensitivity of the Hall device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor sensors, and more specifically, to a Hall sensor and a manufacturing method thereof. Background Art

[0002] The Hall sensor is a device that uses the Hall effect to achieve magneto-electric conversion. It can not only directly measure the magnetic field, but also indirectly measure signals such as distance, position, rotation angle, speed and current. In addition, Hall sensors have been widely used in various fields such as aerospace, biomedicine and industrial production due to their high precision, low power consumption, miniaturization and intelligence.

[0003] Traditional Hall sensors are mostly manufactured using CMOS technology, which not only has the advantages of simple process and low cost, but can also be integrated with control circuits and drive circuits on the same chip to achieve low power consumption, miniaturization and high reliability of the sensor microsystem. However, Hall sensors manufactured using CMOS technology still have the problem of low magnetic field sensitivity, which is not conducive to the application of Hall sensors. Summary of the invention

[0004] In view of this, the present invention provides a Hall sensor and a manufacturing method thereof to improve the magnetic field sensitivity of the Hall sensor.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A Hall sensor comprises a P-type substrate and an N-well active region, a P-type cover layer, an extraction electrode and at least four contact holes located on the P-type substrate, wherein the N-well active region and the extraction electrode each have at least four interdigitated fingers;

[0007] The P-type covering layer and the lead-out electrode are located in the middle area of ​​the N-well active area; the lead-out electrode covers the P-type covering layer and is distributed in the middle area of ​​the P-type covering layer; the at least four contact holes are distributed around the N-well active area and are respectively located at the outer ends of at least four interdigitated fingers of the lead-out electrode.

[0008] Optionally, the length of the contact hole in its extension direction is greater than or equal to the width of a finger of the lead-out electrode arranged corresponding to the contact hole.

[0009] Optionally, the P-type capping layer is implemented by implanting a lightly doped material of a laterally diffused metal oxide semiconductor.

[0010] Optionally, the shallowly doped material of the laterally diffused metal oxide semiconductor includes fluorine and boron.

[0011] A method for manufacturing a Hall sensor, comprising:

[0012] Providing a P-type substrate;

[0013] forming an N-well active region on the P-type substrate;

[0014] forming an extraction electrode in the middle region of the N-well active region, wherein the extraction electrode and the N-well active region both have at least four interdigitated fingers;

[0015] Injecting material into the middle region of the N-well active region to form a P-type cover layer, wherein the extraction electrode covers the P-type cover layer and is distributed in the middle region of the P-type cover layer;

[0016] At least four contact holes are formed around the N-well active region, and the at least four contact holes are respectively located at the outer ends of at least four interdigitated fingers of the extraction electrode.

[0017] Optionally, the length of the contact hole in its extension direction is greater than or equal to the width of a finger of the lead-out electrode arranged corresponding to the contact hole.

[0018] Optionally, injecting material into the middle region of the N-well active region to form a P-type capping layer includes:

[0019] A lightly doped material of a laterally diffused metal oxide semiconductor is used to perform material implantation in the middle region of the N-well active region to form a P-type capping layer.

[0020] Optionally, the shallowly doped material of the laterally diffused metal oxide semiconductor includes fluorine and boron.

[0021] Compared with the prior art, the technical solution provided by the present invention has the following advantages:

[0022] The Hall sensor and the manufacturing method thereof provided by the present invention include a P-type covering layer located in the middle area of ​​the N-well active area. Since the lead-out electrode covers the P-type covering layer and is distributed in the middle area of ​​the P-type covering layer, when the Hall sensor is working, a depletion layer can be generated between the N-well active area and the P-type covering layer, thereby effectively reducing the hot carrier effect, improving the Gaussian distribution of impurities in the N-well active area, increasing the effective N-well depth, reducing the N-well impurity concentration, and further improving the sensitivity of the Hall device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0024] Figure 1 A schematic diagram of the three-dimensional structure of a Hall sensor provided by an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of a top view of a Hall sensor provided by an embodiment of the present invention;

[0026] Figure 3 for Figure 2 The cross-sectional structure diagram of the Hall sensor along the cutting line AA' is shown;

[0027] Figure 4 A comparison diagram of simulation results of the relationship between the Hall voltage and the magnetic field of the Hall sensor provided by the embodiment of the present invention and the traditional Hall sensor;

[0028] Figure 5 A comparison diagram of simulation results of offset voltages of the Hall sensor provided by an embodiment of the present invention and a traditional Hall sensor;

[0029] Figure 6 A flowchart of a method for manufacturing a Hall sensor provided by one embodiment of the present invention. DETAILED DESCRIPTION

[0030] The above is the core idea of ​​the present invention. In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in combination with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] The embodiment of the present invention provides a Hall sensor, such as Figure 1 As shown, it includes a P-type substrate 1 and an N-well active region 2, a P-type cover layer 3, an extraction electrode 4 and at least four contact holes 5 located on the P-type substrate 1, wherein the N-well active region 2 and the extraction electrode 4 each have at least four interdigitated fingers.

[0032] The P-type cover layer 3 and the extraction electrode 4 are located in the middle area of ​​the N-well active area 2. The extraction electrode 4 covers the P-type cover layer 3 and is distributed in the middle area of ​​the P-type cover layer 3. At least four contact holes 5 are distributed around the N-well active area 2 and are respectively located at the outer ends of at least four interdigitated fingers of the extraction electrode 4.

[0033] In some embodiments of the present invention, optionally, the P-type substrate 1 is formed by performing P-type doping on a silicon substrate or the like; the N-well active region 2 is formed by performing low-concentration N-type doping on the P-type substrate 1; the lead-out electrode 4 is formed by performing P-type doping on a silicon dioxide layer formed by oxidizing the P-type substrate 1; and the P-type capping layer 3 is formed by injecting material into the middle region of the N-well active region 2. The contact hole 5 is a connection channel between the N-well active region 2 and an external circuit, and is formed by etching the N-well active region 2 and forming a conductive plug.

[0034] Optionally, the P-type capping layer 3 is implemented by implanting a lightly doped material of a laterally diffused metal oxide semiconductor. Further optionally, the lightly doped material of the laterally diffused metal oxide semiconductor includes fluorine and boron.

[0035] refer to Figure 1 When the external magnetic field is applied vertically to the Hall sensor along the Z direction, a pair of contact holes on the diagonal line is connected to a bias voltage or current, and the Hall effect occurs. A Hall voltage is output on the other pair of contact holes, and the size of the external magnetic field can be obtained based on the output Hall voltage.

[0036] As the process feature size decreases, the depth of the N-well becomes shallower and the impurity concentration of the N-well becomes higher, resulting in a lower and lower magnetic field sensitivity of the Hall sensor. Therefore, in the embodiment of the present invention, a P-type cover layer 3 is formed in the middle area of ​​the N-well active area 2. When the Hall sensor is working, a depletion layer is generated between the N-well active area 2 and the P-type cover layer 3, thereby effectively reducing the hot carrier effect, improving the Gaussian distribution of impurities in the N-well active area 2, increasing the effective N-well depth, and reducing the N-well impurity concentration, thereby improving the sensitivity of the Hall sensor.

[0037] Figure 4 The simulation results of the relationship between the Hall voltage and magnetic field of the Hall sensor provided by the embodiment of the present invention and the traditional Hall sensor are compared, wherein S1 is the relationship curve between the Hall voltage and magnetic field of the Hall sensor provided by the present invention, and S2 is the relationship curve between the Hall voltage and magnetic field of the traditional Hall sensor. Figure 4 It can be seen that the Hall sensor provided by the present invention can generate a Hall voltage that is 21mV higher than that of a conventional Hall sensor. It can be seen from the Hall voltage formula that, under the same bias voltage and magnetic field strength, a high Hall voltage means a high device sensitivity, that is, in the embodiment of the present invention, by using a lightly doped material of a laterally diffused metal oxide semiconductor, the sensitivity of the Hall sensor can be effectively improved.

[0038] In some embodiments of the present invention, Figure 2As shown, the length D1 of the contact hole 5 in its extension direction is greater than or equal to the width D2 of the interdigital fingers corresponding to the contact hole 5 in the lead-out electrode 4. The conventional Hall sensor adopts a short contact hole structure, which easily causes the contact hole to shift or rotate during the photolithography process, resulting in an asymmetric contact hole distribution structure and a large Hall offset voltage. In some embodiments of the present invention, by increasing the length of the contact hole 5, the contact hole 5 completely covers the interdigital fingers of the lead-out electrode 4, so that even if the contact hole 5 shifts or rotates, the contact hole 5 can always cover the interdigital fingers of the lead-out electrode 4, thereby reducing the influence of the uneven distribution of the bias current inside the Hall sensor and avoiding the generation of excessive offset voltage.

[0039] Figure 5 1 is a comparison diagram of simulation results of the offset voltage of the Hall sensor provided by the embodiment of the present invention and the traditional Hall sensor, wherein S3 is a simulation curve of the offset voltage of the traditional Hall sensor, and S4 is a simulation curve of the offset voltage of the Hall sensor provided by the present invention, as shown in FIG. Figure 5 As shown, under a bias voltage of 4V, the offset voltage of the Hall sensor provided by the embodiment of the present invention is reduced by 11mV compared with that of the traditional Hall sensor.

[0040] The embodiment of the present invention also provides a method for manufacturing a Hall sensor, such as Figure 6 As shown, including:

[0041] S101: providing a P-type substrate;

[0042] Optionally, the P-type substrate 1 is formed by performing P-type doping on a silicon substrate or the like.

[0043] S102: forming an N-well active region on a P-type substrate;

[0044] The N-well active region 2 is formed by performing low-concentration N-type doping on the P-type substrate 1 .

[0045] S103: forming an extraction electrode in the middle region of the N-well active region, wherein the extraction electrode and the N-well active region both have at least four interdigitated fingers;

[0046] The lead-out electrode 4 is formed by oxidizing the P-type substrate 1 to form a silicon dioxide layer and then performing P-type doping.

[0047] S104: injecting material into the middle region of the N-well active region to form a P-type cover layer, wherein at least four interdigitated fingers cover the P-type cover layer and are distributed in the middle region of the P-type cover layer;

[0048] The P-type cover layer 3 is formed by injecting material into the middle region of the N-well active region 2. Optionally, the P-type cover layer 3 is implemented by injecting material using a lightly doped material of a laterally diffused metal oxide semiconductor. That is, forming a P-type cover layer in the middle region of the N-well active region includes: forming a P-type cover layer in the middle region of the N-well active region using a lightly doped material of a laterally diffused metal oxide semiconductor. Further optionally, the lightly doped material of the laterally diffused metal oxide semiconductor includes fluorine and boron.

[0049] S105: forming at least four contact holes around the N-well active region, wherein the at least four contact holes are respectively located at the outer ends of at least four interdigitated fingers of the lead-out electrode.

[0050] The contact hole 5 is a connection channel between the N-well active region 2 and an external circuit, and is formed by etching the N-well active region 2 and forming a conductive plug.

[0051] When the Hall sensor is working, a depletion layer is generated between the N-well active region 2 and the P-type cover layer 3, which can effectively reduce the hot carrier effect, improve the Gaussian distribution of impurities in the N-well active region 2, increase the effective N-well depth, reduce the N-well impurity concentration, and thus improve the sensitivity of the Hall sensor.

[0052] In some embodiments of the present invention, the length D1 of the contact hole 5 in the extension direction thereof is greater than or equal to the width D2 of the interdigital fingers of the lead-out electrode 4 corresponding to the contact hole 5. In some embodiments of the present invention, the length of the contact hole 5 is increased so that the contact hole 5 completely covers the interdigital fingers of the lead-out electrode 4, so that even if the contact hole 5 is translated or rotated, the contact hole 5 can always cover the interdigital fingers of the lead-out electrode 4, thereby reducing the influence of the uneven distribution of the bias current inside the Hall sensor and avoiding the generation of an excessive offset voltage.

[0053] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0054] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A Hall sensor, characterized in that: It comprises a P-type substrate and an N-well active region, a P-type covering layer, an extraction electrode and at least four contact holes located on the P-type substrate, wherein the N-well active region and the extraction electrode each have at least four interdigitated fingers; The P-type cover layer and the extraction electrode are located in the middle area of ​​the N-well active area; the extraction electrode covers the P-type cover layer and is distributed in the middle area of ​​the P-type cover layer; the at least four contact holes are distributed around the N-well active area and are respectively located at the outer ends of at least four interdigitated fingers of the extraction electrode; The length of the contact hole in its extension direction is greater than or equal to the width of the forked fingers in the lead-out electrode corresponding to the contact hole; wherein the contact hole is rectangular, and the extension direction of the contact hole is perpendicular to the extension direction of the forked fingers in the lead-out electrode corresponding to the contact hole.

2. The Hall sensor according to claim 1, characterized in that: The P-type cover layer is realized by injecting a lightly doped material of a laterally diffused metal oxide semiconductor.

3. The Hall sensor according to claim 2, characterized in that: The shallowly doped material of the LDMOS includes fluorine and boron.

4. A method for manufacturing a Hall sensor, characterized in that: include: Providing a P-type substrate; forming an N-well active region on the P-type substrate; forming an extraction electrode in the middle region of the N-well active region, wherein the extraction electrode and the N-well active region both have at least four interdigitated fingers; Injecting material into the middle region of the N-well active region to form a P-type cover layer, wherein the extraction electrode covers the P-type cover layer and is distributed in the middle region of the P-type cover layer; At least four contact holes are formed around the N-well active region, and the at least four contact holes are respectively located at the outer ends of at least four interdigitated fingers of the extraction electrode; The length of the contact hole in its extension direction is greater than or equal to the width of the forked fingers in the lead-out electrode corresponding to the contact hole; wherein the contact hole is rectangular, and the extension direction of the contact hole is perpendicular to the extension direction of the forked fingers in the lead-out electrode corresponding to the contact hole.

5. The method according to claim 4, characterized in that Injecting material into the middle region of the N-well active region to form a P-type capping layer comprises: A lightly doped material of a laterally diffused metal oxide semiconductor is used to perform material implantation in the middle region of the N-well active region to form a P-type capping layer.

6. The method according to claim 5, characterized in that The shallowly doped material of the LDMOS includes fluorine and boron.

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