A simple battery management framework and method

The battery management architecture of the daisy-chain ISOSPI bus and the BMS management unit solves the complexity of multi-battery pack cascade design and achieves efficient management and improved reliability of the battery pack.

CN112259811BActive Publication Date: 2025-09-26LUOYANG LONGSHENG SCI & TECH
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Patent Information

Application Number
CN202011164817.4
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2020-10-27
Publication Date
2025-09-26
Estimated Expiration
2040-10-27

AI Technical Summary

Technical Problem

The existing battery management system is complex in design and has low reliability when multiple battery packs are cascaded. It requires additional overall battery management units and data acquisition units, resulting in a highly complex management architecture.

Method used

The daisy-chain ISOSPI bus and BMS management unit are used, connected through the SPI-ISOSPI chip and isolation transformer to achieve battery pack cascading, and the data acquisition unit is used for analog-to-digital conversion and communication. The BMS management unit performs unified management, automatically allocates and identifies addresses, and simplifies data communication design.

Benefits of technology

It achieves simple and efficient battery pack cascade management, improves scalability and communication reliability, and simplifies the design of battery management networks.

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Abstract

The present invention relates to the field of battery management technology and discloses a simple battery management architecture and method. The battery management architecture employed in the method includes: multiple battery pack levels, multiple data acquisition units, a daisy-chained ISOSPI bus, and a BMS management unit. The multiple battery pack levels are connected to the daisy-chained ISOSPI bus via corresponding multiple data acquisition units, and the daisy-chained ISOSPI bus is connected to the BMS management unit, thereby forming a cascaded management network for multiple battery packs. The present invention enables rapid integration of battery packs into the bus and management network. The architecture is simple, easy to implement, highly reliable, and improves the scalability of the battery management network, allowing for its application in a wider range of battery applications. The present invention has broad application prospects in various battery applications.
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Description

Technical Field

[0001] The present invention relates to the technical field of battery management, and in particular to a simple battery management framework and method. Background Art

[0002] Currently, electronic technology is developing rapidly, and various electronic products are developing towards portable, small and lightweight models, which has led to an increasing number of electrical products being powered by batteries. With the development of battery technology, people are using batteries more widely.

[0003] For batteries on the market, each battery pack is usually equipped with a battery data acquisition unit and a battery management unit. When multiple battery packs are cascaded, an additional overall battery management unit (BMS) is required to uniformly analyze and manage the data of each sub-battery management unit. The management architecture is in the form of 1 overall BMS management unit + N distributed BMS management units + N data acquisition units and battery packs. The design is complex and the reliability is low. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a simple battery management framework and method, thereby simplifying the design of the management framework when multiple battery packs are cascaded.

[0005] In order to realize the above-mentioned design, the present invention adopts the following technical solutions:

[0006] A simple battery management architecture includes: multiple battery pack levels, multiple data acquisition units, a daisy-chained ISOSPI bus, and a BMS management unit. The multiple battery pack levels are connected to the daisy-chained ISOSPI bus through corresponding multiple data acquisition units, and the daisy-chained ISOSPI bus is connected to the BMS management unit to form multiple battery packs cascaded and incorporated into a management network.

[0007] A simple battery management architecture, wherein the BMS management unit is composed of an MCU chip electrically connected to an isolation transformer via an SPI-ISOSPI chip.

[0008] A simple battery management framework, wherein each data acquisition unit is composed of an isolation transformer electrically connected to an acquisition chip via an SPI-ISOSPI chip and a four-wire SPI.

[0009] A simple battery management framework works as follows:

[0010] 1) The data acquisition unit 1 is integrated into the management bus, and the acquisition chip performs analog-to-digital conversion on the voltage and charge and discharge current information of each battery in the battery pack;

[0011] 2) Data is transmitted in the form of four-wire SPI communication. The battery collection chip is a four-wire SPI type.

[0012] 3) Use the SPI-ISOSPI chip to convert the four-wire SPI to two-wire SPI;

[0013] 4) Use isolation transformers to isolate the data, and connect the two-wire like-name ends of the secondary side of each isolation transformer from data acquisition unit 1 to data acquisition unit N in parallel in the form of a daisy chain bus, thereby forming a data monitoring network;

[0014] 5) The BMS management unit is integrated into the daisy-chain ISOSPI bus through ISOSPI, and the information of each sub-data acquisition unit is summarized and processed;

[0015] 6) Implement a battery management architecture consisting of 1 BMS management unit + N battery packs and data acquisition units.

[0016] A simple working method of a battery management architecture. The data acquisition unit is a sub-data acquisition unit information identification method. The sub-data acquisition units are merged into the bus one by one. The BMS management unit shakes hands with the sub-data units and assigns addresses. The first unit to be merged is assigned a low-order address first. After the allocation is successful, the data acquisition unit feedbacks the address setting success information; the subsequent merged units increase the address in sequence; or the upper computer controls the BMS management unit to manually assign addresses according to the connected sequence. The specific implementation process is as follows:

[0017] Receive the handshake signal from the BMS management unit, determine whether the address has been allocated, if the judgment is Y, return the allocated address information and send it to the BMS management unit; if the judgment is N, proceed to allocation n for allocation; Determine whether the allocation is successful, if the judgment is N, continue to allocation n for allocation; if the judgment is Y, return the allocated address information and send it to the BMS management unit;

[0018] After the addresses are allocated, the BMS management unit distinguishes the source of the data through the address bits, thereby realizing the identification of information of different sub-data acquisition units.

[0019] Due to the adoption of the above technical solution, the present invention has the following advantages:

[0020] A simple battery management architecture and method uses a data acquisition unit to convert the voltage of each battery cell and the battery pack's charge and discharge current information into analog-to-digital form, and simultaneously transmits this data to the bus via ISOSPI communication. This allows for a battery management architecture consisting of one BMS management unit, N battery packs, and a data acquisition unit.

[0021] This invention enables rapid integration of battery packs into a bus, with all battery pack data centrally processed by a single BMS management unit. The architecture is simple, easy to implement, reliable, and efficient. Parallel integration of battery packs into the management network improves the scalability of the battery management network. Automatic address allocation and identification simplify data communication design and enhance communication reliability, making this system promising for broad application in various battery applications. Its high scalability allows for its widespread adoption in a wider range of battery applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of a simple battery management architecture of the present invention.

[0023] Figure 2 Design an application diagram for a simple battery management architecture.

[0024] Figure 3 This is the address allocation diagram of the sub-data acquisition unit of a simple battery management architecture. DETAILED DESCRIPTION

[0025] The following further explains this patent with reference to the accompanying drawings. However, the scope of protection of this patent is not limited to specific implementation methods.

[0026] like Figure 1 、 2 As shown in Figure 3, a simple battery management architecture includes: multiple battery pack levels, multiple data acquisition units, a daisy-chain ISOSPI bus, and a BMS management unit. The multiple battery pack levels are connected to the daisy-chain ISOSPI bus through the corresponding multiple data acquisition units, and the daisy-chain ISOSPI bus is connected to the BMS management unit to form multiple battery packs cascaded and incorporated into the management network.

[0027] The BMS management unit is composed of an MCU chip electrically connected to an isolation transformer via an SPI-ISOSPI chip. Each data acquisition unit is composed of an isolation transformer electrically connected to an acquisition chip via an SPI-ISOSPI chip and a four-wire SPI.

[0028] The battery management architecture includes: multiple battery pack levels, multiple data acquisition units, a daisy-chain ISOSPI bus, and a BMS management unit. The multiple battery pack levels are connected to the daisy-chain ISOSPI bus through corresponding multiple data acquisition units, and the daisy-chain ISOSPI bus is connected to the BMS management unit to form multiple battery packs cascaded and incorporated into the management network.

[0029] The BMS management unit is composed of an MCU chip electrically connected to an isolation transformer via an SPI-ISOSPI chip. Each data acquisition unit is composed of an isolation transformer electrically connected to an acquisition chip via an SPI-ISOSPI chip and a four-wire SPI.

[0030] The data acquisition unit is responsible for performing analog-to-digital conversion on the voltage of each battery cell and the battery pack's charge and discharge current information, and simultaneously incorporating this data into the bus via ISOSPI communication. The BMS management unit is responsible for centrally managing and calculating the data from each battery pack to obtain overall system data. When additional battery packs are needed, data management for that battery pack can be achieved by simply incorporating the accompanying data acquisition unit into the ISOSPI bus. Furthermore, due to the inherent isolation characteristics of the ISOSPI bus, battery packs can be connected in any series or parallel configuration without having to consider bus level matching. This creates a battery management architecture consisting of one BMS management unit, N battery packs, and data acquisition units.

[0031] Example 1

[0032] Figure 2 In this example, the data acquisition unit 1 manages the bus as an example. The acquisition chip converts the voltage and charge / discharge current information of each battery cell in the battery pack into analog-to-digital form and transmits the data via four-wire SPI communication. Most of the dedicated battery acquisition chips commonly used on the market use four-wire SPI. An SPI-ISOSPI chip converts the four-wire SPI into a two-wire SPI, and an isolation transformer is used to isolate the data. The two-wire like-named secondary terminals of the isolation transformers from data acquisition units 1 to N are connected in parallel in a daisy-chain bus, thus forming a data monitoring network. The BMS management unit is integrated into the daisy-chain ISOSPI bus via ISOSPI, summarizing and processing the information of each sub-data acquisition unit. This realizes a battery management architecture consisting of one BMS management unit, N battery packs, and data acquisition units.

[0033] The key to this architecture design is identifying sub-data acquisition units. This is achieved by integrating each sub-data acquisition unit into the bus one by one. The BMS management unit then performs a handshake with the sub-data acquisition unit and assigns addresses. The first unit incorporated is assigned the lower-order address first. Upon successful assignment, the data acquisition unit reports a successful address setting. Subsequent units are then assigned addresses in ascending order. Alternatively, the BMS management unit can be controlled by a host computer to manually assign addresses based on the connected signals. After address allocation, the BMS management unit uses the address bits to distinguish the data source, thereby enabling identification of information from different sub-data acquisition units.

[0034] Through examples, it can be seen that this method can simply and efficiently connect battery packs in parallel to the management network, thereby improving the scalability of the battery management network. At the same time, through automatic address allocation and identification, it ensures the simplification of data communication design and improves the reliability of communication.

[0035] The framework is cleverly designed, simple and convenient in structure, and has high circuit reliability and scalability, and has broad application prospects in various battery applications.

Claims

1. A simple battery management architecture, characterized by: Includes multiple battery pack levels, multiple data acquisition units, daisy-chained ISOSPI bus, and BMS management unit; Multiple battery pack levels are respectively connected to the daisy-chain ISOSPI bus through corresponding multiple data acquisition units, and the daisy-chain ISOSPI bus is connected to the BMS management unit, forming a cascade of multiple battery packs into a management network; the BMS management unit is composed of an MCU chip electrically connected to an isolation transformer through an SPI-ISOSPI chip; each data acquisition unit is composed of an isolation transformer electrically connected to an acquisition chip through an SPI-ISOSPI chip and a four-wire SPI.

2. A method for operating a simple battery management architecture as claimed in claim 1, characterized in that: The steps as follows: 1) The data acquisition unit 1 is integrated into the management bus, and the acquisition chip performs analog-to-digital conversion on the voltage and charge and discharge current information of each battery in the battery pack; 2) Data is transmitted in the form of four-wire SPI communication. The battery collection chip is a four-wire SPI type. 3) Use the SPI-ISOSPI chip to convert the four-wire SPI to two-wire SPI; 4) Use isolation transformers to isolate the data, and connect the two-wire like-name ends of the secondary side of each isolation transformer from data acquisition unit 1 to data acquisition unit N in parallel in the form of a daisy chain bus, thereby forming a data monitoring network; 5) The BMS management unit is integrated into the daisy-chain ISOSPI bus through ISOSPI, and the information of each sub-data acquisition unit is summarized and processed; 6) Implement a battery management architecture consisting of 1 BMS management unit + N battery packs and data acquisition units.

3. The method for operating a simple battery management architecture according to claim 2, wherein: The data acquisition unit is a sub-data acquisition unit information identification method, which is to merge the sub-data acquisition units into the bus one by one, and the BMS management unit shakes hands with the sub-data unit and assigns addresses. The unit that is merged first is assigned a low-order address first. After the allocation is successful, the data acquisition unit feedbacks the address setting success information; the subsequent merged units increase the address in sequence; or the upper computer controls the BMS management unit to manually assign addresses according to the connected Shunx; the specific implementation process is as follows: Receive the handshake signal from the BMS management unit, determine whether the address has been allocated, if it is Y, return the allocated address information and send it to the BMS management unit; if it is N, go to allocation n for allocation; Determine whether the allocation is successful. If it is N, continue to allocate to N. If it is Y, return the allocation address information and send it to the BMS management unit. After the addresses are allocated, the BMS management unit distinguishes the source of the data through the address bits, thereby realizing the identification of information of different sub-data acquisition units.

Citation Information

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