DQ0 and Inverse DQ0 Transformations for Three-Phase Inverter, Motor, and Drive Designs

Abstract

The present disclosure relates to test and measurement equipment, and more specifically, to test and measurement equipment for motors and synchronous machines. A test and measurement device includes an interface configured to acquire a simulated three-phase signal from a device under test (DUT), and a processor programmed to execute instructions that cause the processor to perform a DC-AC-zero DQ0 conversion on the simulated three-phase signal to generate a DQ0 signal, and to measure the performance of the DUT based on the DQ0 signal. A method also includes acquiring the three-phase signal from the DUT, performing a DC-AC-zero DQ0 conversion on the three-phase signal to generate the DQ0 signal, and using the DQ0 signal to measure the performance of the DUT.

Description

[0001] Related applications

[0002] This application is a continuation of and claims priority from Indian Provisional Patent Application No. 201921027221 filed on July 8, 2019. Technical Field

[0003] The present disclosure relates to test and measurement equipment, and more particularly, to test and measurement equipment for motors and synchronous machines. Background Art

[0004] The behavior of a three-phase synchronous motor is usually described by rotating voltage and current equations, such as the following rotating voltage equations (1)-(3), where R, S, and T are three-phase AC signals, and V g is the corresponding gain.

[0005]

[0006] where w in It is 2*pi*f of the input R, S, T three-phase signal. "f" is the nominal frequency. The user can configure "f" to be the line frequency or any custom motor frequency of interest.

[0007] The voltage (V) and current (I) at the AC interface are usually separated, typically 120 degrees out of phase. These V and I components are time-varying, which means there is no representation of a steady-state operating point.

[0008] The Direct-to-Quadrature-to-Zero (DQ0) transform typically rotates the reference frame of AC waveforms to convert them to DC signals. This allows simplified calculations on the DC signals before performing the inverse transform to recover the actual three-phase AC result. The DQ0 transform also simplifies the analysis of synchronous motor performance.

[0009] Generally speaking, AC signals are real-world signals, but converting them to DC signals helps to get an abstract representation of the orthogonal transformation. DQ0 helps let the user know what the controller is seeing. This information helps the user understand more about what the controller is doing and allows the user to better tune the controller design.

[0010] Generally speaking, the DQ0 coordinate system is preferred for synchronous machines, and the α-β zero transformation is preferred for induction machines.

[0011] In current solutions, users rely on field-programmable gate array (FPGA)-based hardware to process sensor data to obtain DQ0 information and then check control information through multiple iterations. This solution involves complex and custom processing. Users must attempt to detect and / or measure the DQ-0 signal, which is practically impossible. Instead, a typical solution provides external stimulus to the controller to simulate the controller input signal and the analog-to-digital controller (ADC) output as the DQ0 signal.

[0012] Embodiments of the disclosed apparatus and methods address shortcomings in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 a cross-sectional functional diagram showing the relationship of the rotor and stator axes;

[0014] Figure 2 A diagram showing an embodiment of a system including a device under test;

[0015] Figure 3 A block diagram illustrating an embodiment of a test and measurement device;

[0016] Figure 4 shows a graphical depiction of three-phase voltage and current signals;

[0017] Figure 5 shows a graphical depiction of a three-phase voltage signal having two cycles;

[0018] Figure 6 shows a graphical depiction of a three-phase current signal having two cycles;

[0019] Figure 7 shows a graphical depiction of DQ0 transitions of a three-phase voltage signal according to an embodiment of the present disclosure;

[0020] Figure 8 shows a graphical depiction of DQ0 transitions of a three-phase current signal according to an embodiment of the present disclosure;

[0021] Figure 9 shows a graphical depiction of an inverse DQ0 transformation for obtaining a reconstructed three-phase voltage signal according to an embodiment of the present disclosure;

[0022] Figure 10 shows a graphical depiction of an inverse DQ0 transformation for obtaining a reconstructed three-phase current signal according to an embodiment of the present disclosure;

[0023] Figure 11 shows a phasor diagram of the three-phase voltages RST and DQ0 transformation at time t=0 according to an embodiment of the present disclosure;

[0024] Figure 12 shows a phasor diagram of the three-phase voltage RST and DQ0 transformation according to an embodiment of the present disclosure;

[0025] Figure 13 A flow chart illustrating a method for measuring the performance of a device under test using a DQ0 signal according to an embodiment of the present disclosure is shown;

[0026] Figure 14 shows an example embodiment of a user interface for receiving configuration settings from a user according to some embodiments of the present disclosure;

[0027] Figure 15 shows an example embodiment of a user interface for displaying results according to some embodiments of the present disclosure;

[0028] Figure 16 shows an example of a phasor diagram of an actual three-phase signal overlaid with a rotated DQ0 signal according to some embodiments of the present disclosure;

[0029] Figure 17 shows an example of a separated phasor diagram of the actual voltage and current DQ0 signals according to some embodiments of the present disclosure;

[0030] Figure 18 Examples of actual results and phasor diagrams of math DQ0 in the case of time-domain three-phase sinusoidal and PWM waveforms according to embodiments of the present disclosure are shown. DETAILED DESCRIPTION

[0031] In current solutions, users rely on field-programmable gate array (FPGA)-based hardware to process sensor data to obtain DQ0 information and then check control information through multiple iterations. This solution involves complex and custom processing.

[0032] Users must attempt to probe and / or measure the DQ-0 signal, which is practically impossible. They must access the signal received at the motor control microprocessor. This typically involves embedded control software, sensors, and a field-programmable gate array (FPGA). Alternatively, a typical solution involves providing an external stimulus to the motor controller to simulate the controller input signal and capture the analog-to-digital controller (ADC) output as the DQ0 signal.

[0033] The embodiments herein receive actual three-phase signals into the controller to perform DQ0 conversion. Users can use the probe connector to probe the three-phase voltage and current signals and perform the conversion to DQ0 without sensors. The controller executes instructions using these direct signals.

[0034] It should be noted that the term "controller" as used herein includes any type of processing element capable of executing instructions, including controllers, microcontrollers, processors (also known as microprocessors), digital signal processors, application specific integrated circuits (ASICs), etc.

[0035] Figure 1 A cross-sectional functional diagram showing the relationship of the rotor and stator axes in, for example, a motor is shown. The outer ring represents the stator 2. The inner ring represents the rotor 4. The points shown distributed around the rotor 4 represent the rotor poles 6. A permanent magnet (NS) may be located at the center. The DQ reference coordinate system of the D axis 16 and the Q axis 18 is fixed to the rotor of the motor. The axis of the field winding in the direction of the DC magnetic field is called the rotor direct axis or d-axis. The axis 90 degrees later than the d-axis is the quadrature axis (q-axis). Axes 10, 12, 14 represent the axes of the three-phase voltage and / or current signals (e.g. R, S, T). According to the coordinate system formula below, this transformation uses Figure 1 The three-phase signal shown in . When the q-axis and the a-axis are aligned at time t = 0, and the q-axis makes an angle θ with the a-axis at any time t, the following matrix formula (4) can be applied:

[0036] .

[0037] When the d-axis and the a-axis are aligned at time t=0, and the d-axis makes an angle θ with the a-axis at time t, the following matrix formula (5) may be applied.

[0038] The K value can be 2 / 3 or .

[0039] When K is 2 / 3, the third line of the matrix formula is 1 / 2. So "0" becomes 2 / 3 * 1 / 2 * (R+S+T).

[0040] When K is When the third line of the matrix formula is So "0" becomes * * (R+S+T).

[0041] .

[0042] The user can configure which method to use based on the motor controller design. In one embodiment, the system will allow the user to choose to use the formula aligned with the q-axis or the d-axis as the measurement configuration.

[0043] Based on the method we use to calculate the theta function, the theta in the matrix can be different from the theta of R, S, and T.

[0044] The angle θ is the angle between the rotating dq reference frame and the a-axis, where the a-axis is fixed to the stator frame and is defined by the position of the phase a winding. The angle θ at time t can be calculated using formula (6):

[0045]

[0046] Where ω is the rotational speed of the dq axis and is used as the synchronous speed in the embodiments herein. This transformation will allow the user to operate on the stator circuit voltage formula and transform it into qd-0 coordinates.

[0047] θ at time t in the matrix equation can be calculated using various methods. The first method is known as the three-phase PLL method. A PLL is typically embedded in the controller circuit of a three-phase motor. This method uses a software PLL to emulate the controller circuit's hardware PLL to adjust for the phase shift and delay introduced by the filter. Phase-adjusted θ is obtained by implementing a three-phase PLL. If a PLL is implemented in the motor controller circuit hardware, the acquired three-phase signal will have this effect. Users can choose to apply a software PLL, allowing the hardware PLL to be implemented and replicated within the measurement process.

[0048] The PLL takes as input one of the transformed "d(t)" or "q(t)" values. This is configurable in the measurement. The PLL output gives the corrected θ about the "d" or "q" axis. These axes can be configured as source inputs in the measurement.

[0049] The adjusted θ (which is the output of the PLL) is used back in the matrix formula and will be different from the θ of the three-phase RST signal. in This adjustment process continues until all samples of the RST signal have been processed, which adjusts one of the configured "d" or "q" given as the reference input to the PLL.

[0050] Another method is called the standard method. A typical choice for θ is ωt, where ω is 2*pi*f. This represents a fixed rotor angle for a synchronous motor. This is called the freewheeling θ method. In this method, the θ of the matrix is ​​compared to the θ of the three-phase RST signal. in This is a more ideal condition because θ is not adjusted based on the PLL or any feedback method.

[0051] This method has user-configurable θ(t). The user can give a θ function of time as an additional qualifier source for the measurement, either as an external or explicit clock. The measurement can use this to extract the θ value of the matrix. In this method, the θ of the matrix is ​​configured by the user and is different from the θ of the three-phase RST signal. in .

[0052] In the third method, called a configurable θ(t) function, the user can provide a θ function, which serves as an additional qualifier source for the measurement and can be used in the matrix equation. This θ waveform (which is equivalent to the PLL output) must be synchronized with the three-phase RST signal. The user can then use this θ value to calculate DQ0 at each sample point.

[0053] In the above method, "f" represents the fundamental frequency of the three-phase signal. However, the user can configure "f" to be the line frequency or any custom frequency value of interest.

[0054] The angle θ(t) is constructed based on the input three-phase RST waveform, and the θ(t) used in the matrix is ​​reset to zero every 2π radians, so it becomes like a ramp output. In the PLL method, one can adjust either the direct axis or the quadrature axis to zero, unlike the idle method above. The three-phase PLL method provides better frequency synchronization between the three-phase RST and DQ0 signals. The standard method is the simplest of all methods because it relies on hardware implementation for synchronization.

[0055] Furthermore, under equilibrium conditions, the value along the Z axis is zero, and therefore no flux is generated at all. This allows the dq transformation to be simplified to Equation (7):

[0056] .

[0057] In this formula (7), which is called the DQ0 or forward formula, K is a constant. Typical choices for the value of K are 2 / 3 and This makes the magnitude of the DQ quantity equal to the magnitude of the three-phase quantities.

[0058] For example, the interpretation of K may be different. When K is equal to 2 / 3, it means that the sinusoidal signal is balanced, and This means that this is a power-consistent system. In the embodiment herein, the DQ0 transformation takes as its input the three-phase (RST) time-domain voltages and currents from the motor drive input.

[0059] One can perform a backward DQ0 transform, also known as RST or the inverse of formula (8). The inverse transform uses the DQ0 signal calculated by the motor controller as its input to obtain the RST value as follows:

[0060] .

[0061] Figure 2An embodiment of the system is shown in which the device under test is a motor and drive train 24 controlled by an embedded controller 26. The motor receives power input from the main AC power supply at the drive input 20. These signals then undergo AC to DC conversion, as well as DC filtering and buffering, in the drive and drive output 22. These filtered and buffered signals are then converted back to AC and reach the motor and drive train 24.

[0062] In a typical system, a designer could theoretically attempt to sample, for example, encoder, speed, and torque signals 31 arriving at the motor controller 26, or analog input signals 33 to the motor controller 26. However, this approach is impractical because physically reaching these signal access points with a probe is extremely difficult. Therefore, rather than attempting to reach these signal access points, a typical approach involves providing an external stimulus to the controller, measuring the controller input signals, and capturing the output of an analog-to-digital converter (ADC) 32 within the controller. However, as mentioned previously, this typical approach also involves using an FPGA to generate the stimulated signals and sensors to capture the data (e.g., in the digital circuit / sensor block 36). Furthermore, the received signals only include the "stimulated" signals, not the actual signals that are present when the circuit is operating.

[0063] In contrast, the embodiments herein capture actual in-line signals and allow the controller to generate DQ0-transformed signals from these signals. These embodiments provide more accurate signal measurements and a simpler solution by enabling the controller to operate on in-line signals. The system captures these signals using connections at the driver input (shown as 28) or at the output of the driver and driver output 22 (shown as 30). In either case, these signals will include analog three-phase signals (R, S, T). One or both of the voltage and current three-phase signals can be captured using, for example, appropriate voltage and current probes, respectively. Controller 26 receives analog three-phase signals 33. The controller then executes instructions to calculate the DQ0 transformation discussed above using the forward formula. The transformation formula can be applied to the voltage and current three-phase signals separately to obtain DQ0 for voltage and DQ0 for current. DQ0 signal 35 can be provided back to the device under test as feedback. The three-phase analog signal at 30 comprises this feedback. As will be appreciated by those skilled in the art, controller 26 may also include PWM circuitry 34 to provide gate drive signals to the driver and driver output 22, as shown.

[0064] Figure 3A block diagram of a test and measurement device 40 is shown. The device receives an analog three-phase signal as input via an interface 42 (such as a probe interface) and acquires the analog three-phase signal, as shown. Typically, the probe interface may be one or more connectors on a cable. Interface 42 includes appropriate circuitry (not shown) for acquiring the three-phase signal, which may include signal conditioning circuitry, an analog-to-digital converter, memory, etc., as known to those skilled in the art. A processor / controller / processing element 44 performs a DQ0 transform on the acquired three-phase signal and generates a DQ0 signal. Processor 44 measures the performance of the device under test based on the DQ0 signal. Processor 44 may also perform an inverse DQ0 transform on the DQ0 signal and generate a reconstructed three-phase signal. The device may also include a memory 46 for storing instructions executed by the processor to perform the transform and for storing data. The device may also include a display 48 to allow the device to display data, as discussed below. The device may also include a user interface 49 for receiving configuration settings from a user. For example, as discussed above, the device may receive from the user, through the user interface 49, a selection of a method for calculating the angle at time t in the matrix formula.

[0065] This measurement allows for configurations where phase A is initially aligned with the d-axis or the q-axis. The user can see changes in the output results and phasor diagram based on the configuration.

[0066] Figures 4 to 12 shows the Figure 3 A graphical depiction of a signal captured by test and measurement equipment 40). Figure 4 Snapshots of three-phase RST voltage and current signals captured from a brushless DC motor device under test are shown. It should be noted that these example brushless DC motors merely provide examples of input and result signals and are not limited to this particular device under test.

[0067] Figure 5 The separated three-phase voltage RST signal is shown in Figure 6 The three-phase current RST signal is shown in FIG.

[0068] Applying the forward DQ0 transform produces Figure 7 The voltage waveforms shown in Figure 8 The current waveform shown in .

[0069] The application of backward and inverse DQ0 transformation results in Figure 9 and Figure 10 As a check on the conversion accuracy, Figure 9 Can be used with Figure 5 For comparison, Figure 10 Can be used with Figure 6However, typically, the user will want to see the inverse transformation to monitor the performance of the controller 26.

[0070] As mentioned before, the three-phase signals vary over time, which means that there is no steady-state operating point. Figure 1 , which shows three rotor shafts 10, 12, 14, one for each phase a 10, b 12, and c 14. In an induction motor, the d-axis is assumed to be aligned with the a-axis at t = 0 and rotates at synchronous speed (w). The DQ0 transformation results in the cancellation of all time-varying inductances in the three-phase voltage and current signals, as shown in Figure 11 As shown in .

[0071] exist Figure 11 In FIG, the rotating reference shows the overlapping vectors of the three-phase RST and DQ0 components at time t = 0. At 50, the a-axis and d-axis overlap on the 0-axis. The b-axis is shown at 45. The c-axis is at 47, and the q-axis is at 43.

[0072] exist Figure 12 In the figure, the rotating coordinate system vectors show the d-axis and q-axis changing for each sampling time. The zero axis is fixed at 62, and the a-axis and d-axis overlap at 60. The q-axis is at 64, the b-axis is at 66, and the c-axis is at 68. The sampling rate has been simulated to illustrate the rotational portion, although in an actual plot, the rate would likely be much slower. This is an indicative example of a rotating vector.

[0073] Figure 16 and 17 The actual rotating coordinate system of the actual DQ0 phasor diagram is shown. The plot update rate is equal to the product of the frequency of the three-phase RST signal and the number of such cycles in the acquisition.

[0074] Figure 18 An example of the actual result and phasor diagram of math DQ0 is shown, where Q of the time-domain three-phase sinusoidal and PWM waveforms is DC and D will be 0 because D is initially aligned with phase A. If phase A is initially aligned with Q, then D will be DC and Q will be zero.

[0075] Figure 13 A flow chart illustrating one embodiment of a method for applying forward and reverse transforms is shown. The method begins with a forward transform at 70 , where the system acquires an analog three-phase signal. The system may acquire one or both of the voltage and current analog three-phase signals. At 71 , the acquired analog three-phase signals are used to calculate a DQ0 transform. The system may separately calculate the DQ0 transforms for voltage and current at 71 .

[0076] The three-phase PLL simulation, which begins at 72, illustrates the three different approaches discussed above. If the three-phase PLL simulation is applied, the output θ is adjusted about the d-axis or q-axis at 73 and applied to the matrix formula. If the answer at 72 is "no," θ is either used as a user input or not used as a user input at 74. If not, processing continues to the idle method at 75, where the input θ is the same as the input signal. If θ is used as a user input, it is further adjusted at 76 based on an additional qualifier source. At 77, the output is selected in one of the three ways discussed above. These are then returned to 78.

[0077] Then, at 78 , the device can display a waveform plot of the DQ0 signal. This allows the designer to see what the controller sees so they can adjust the DUT's performance as desired. Furthermore, the system can measure the DUT's performance based on the DQ0 signal as desired by the system designer. These performance measurements include ripple (rms), peak-to-peak amplitude, DC average of the DQ0 component, magnitude (D, Q), Fast Fourier Transform plot of the DQ0 component, and total power of DQ0. After DQ0 conversion, the user can perform harmonic measurements and jitter analysis. Since DQ0 is expected to have a DC component, any changes in magnitude will result in higher-order harmonics and jitter. At 79 , this process continues until all samples have been processed. If processing is complete, the process proceeds to 84 ; if not, the process returns to 70 .

[0078] Figure 14 An example of a user interface 90 is shown that allows a system designer to select configuration settings for measurements they want to run on a device under test. Figure 15 An example of a user interface 92 for displaying measurement results is shown. The results shown here are the three-phase voltage, peak-to-peak amplitude, mean, and magnitude (D, Q) of the DQ0 signal, but can be any measurement of interest, such as selected from harmonic measurements, jitter analysis, or other measurements. Example user interfaces 90 and 92 can be Figure 3 A portion of the user interface 49 of the test and measurement device 40 is shown.

[0079] Return to Figure 13, when the DQ0 controller signal is acquired at 80, the inverse / reverse / backward transformation process begins. The system can acquire one or both of the voltage and current DQ0 signals. At 81, the inverse DQ0 transformation is calculated based on the DQ0 signal and a reconstructed three-phase RST signal is generated. The system can calculate the reconstructed three-phase RST signals for voltage and current respectively at 81. The system can generate a waveform diagram of the reconstructed three-phase signal at 82. This allows, for example, the system designer to compare the reconstructed three-phase signal from the inverse transformation with the analog three-phase RST signal acquired at 70 in order to monitor system performance. At 84, the system can also generate and display a phasor diagram of one or more signals, or based on measurement results of one or more signals, during the forward or reverse transformation process. Typically, the DQ0 signal can be acquired (i.e., received) from the output of 71. However, in some embodiments, the DQ0 signal can be acquired from an external source, such as through Figure 3 The interface 42 of the test and measurement equipment 40, in this case, may only need to perform the inverse transformation.

[0080] Aspects of the present disclosure may operate on specially created hardware, firmware, a digital signal processor, or a specifically programmed general-purpose computer including a processor operating according to programmed instructions. As used herein, the terms "controller" or "processor" are intended to include microprocessors, microcomputers, application-specific integrated circuits (ASICs), and dedicated hardware controllers. One or more aspects of the present disclosure may be embodied in computer-usable data and computer-executable instructions, such as in one or more program modules executed by one or more computers (including monitoring modules) or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc., which, when executed by a processor in a computer or other device, perform specific tasks or implement specific abstract data types. Computer-executable instructions may be stored on non-transitory computer-readable media, such as a hard disk, optical disk, removable storage media, solid-state memory, random access memory (RAM), etc. As will be appreciated by those skilled in the art, the functionality of the program modules may be combined or distributed among various aspects as desired. Furthermore, functionality may be embodied in whole or in part in firmware or hardware equivalents, such as integrated circuits and FPGAs. Certain data structures may be more efficiently used to implement one or more aspects of the present disclosure, and such data structures are contemplated within the scope of the computer-executable instructions and computer-usable data described herein.

[0081] In some cases, the disclosed aspects may be implemented using hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried by or stored on one or more non-transitory computer-readable media, which may be read and executed by one or more processors. Such instructions may be referred to as a computer program product. As discussed herein, a computer-readable medium refers to any medium that can be accessed by a computing device. By way of example and not limitation, a computer-readable medium may include computer storage media and communication media.

[0082] Computer storage media refers to any medium that can be used to store computer-readable information. By way of example, and not limitation, computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital video disc (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, and any other volatile or nonvolatile, removable or non-removable media implemented in any technology. Computer storage media does not include signals themselves or transient forms of signal transmission.

[0083] Communication media refers to any medium that can be used to communicate computer-readable information. By way of example, and not limitation, communication media can include coaxial cables, fiber optic cables, air, or any other medium suitable for communication of electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals.

[0084] In addition, the written description mentions specific features. It should be understood that the disclosure in this specification includes all possible combinations of those specific features. For example, when a specific feature is disclosed in the context of a particular aspect, that feature can also be used in the context of other aspects to the extent possible.

[0085] Furthermore, when a method having two or more defined steps or operations is referred to in this application, the defined steps or operations may be performed in any order or concurrently, unless the context excludes those possibilities.

[0086] Although certain aspects of the present disclosure have been illustrated and described for purposes of illustration, it will be appreciated that various modifications can be made without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is not to be restricted, except as in the appended claims.

[0087] Example

[0088] Illustrative examples of the disclosed technology are provided below. Implementations of the technology may include one or more of the examples described below, as well as any combination of the examples.

[0089] Example 1 is a test and measurement device, which includes an interface configured to acquire an analog three-phase signal from a device under test; and a processor programmed to execute instructions, wherein the instructions cause the processor to: perform a direct-to-cross-to-zero DQ0 conversion based on the analog three-phase signal and generate a DQ0 signal; and measure performance of the device under test based on the DQ0 signal.

[0090] Example 2 is the test and measurement device of Example 1, wherein measuring the performance of the device under test based on the DQ0 signal includes measuring at least one of ripple, peak-to-peak amplitude, DC average of the DQ0 component, a fast Fourier transform plot of the DQ0 component, magnitudes of D and Q, harmonic measurements, jitter analysis, and total power of DQ0.

[0091] Example 3 is the test and measurement device of any of Examples 1 and 2, further comprising a display, wherein the processor is programmed to execute instructions that cause the processor to display the DQ0 signal on the display.

[0092] Example 4 is the test and measurement device of any of Examples 1 to 3, wherein the processor is programmed to execute instructions that cause the processor to perform an inverse DQ0 transform based on the DQ0 signal and generate a reconstructed three-phase signal.

[0093] Example 5 is the test and measurement device of Example 4, further comprising a display, wherein the processor is programmed to execute instructions that cause the processor to display the reconstructed three-phase signal on the display.

[0094] Example 6 is the test and measurement device of Example 4, wherein the processor is programmed to execute instructions that cause the processor to generate a phasor diagram using at least one of the simulated three-phase signal, the DQ0 signal, and the reconstructed three-phase signal.

[0095] Example 7 is the test and measurement device of any of Examples 1 to 6, wherein the interface is configured to receive a simulated three-phase signal from a motor drive input or a drive output of the device under test.

[0096] Example 8 is the test and measurement device of any of Examples 1 to 7, wherein the interface is configured to receive the simulated three-phase voltage signal via the voltage probe and to receive the simulated three-phase current signal via the current probe.

[0097] Example 9 is the test and measurement device of any one of Examples 1 to 8, further comprising a display, wherein the processor is programmed to execute instructions that cause the processor to generate a phasor diagram using the simulated three-phase signal and the DQ0 signal, and display the phasor diagram on the display.

[0098] Example 10 is the test and measurement apparatus of any of Examples 1 to 9, wherein the DQ0 transform uses a constant equal to two-thirds or the square root of two-thirds.

[0099] Example 11 is a method including: acquiring a three-phase signal from a device under test; performing a direct-to-quadrature-to-zero DQ0 conversion on the three-phase signal to generate a DQ0 signal; and measuring performance of the device under test using the DQ0 signal.

[0100] Example 12 is the method of Example 11, further comprising generating a plot of the DQ0 signal.

[0101] Example 13 is the method of any of Example 11 or Example 12, wherein measuring the performance of the device under test using the DQ0 signal includes measuring at least one of ripple, peak-to-peak amplitude, a DC average of the DQ0 component, a fast Fourier transform of the DQ0 signal, magnitudes of D and Q, harmonic measurements, jitter analysis, and total power of DQ0.

[0102] Example 14 is the method of any of Examples 11 to 13, wherein acquiring the three-phase signal from the device under test includes receiving the three-phase signal from a motor drive input or a drive output of the device under test.

[0103] Example 15 is the method of any of Examples 11 to 14, further comprising: generating a phasor diagram using the acquired three-phase signals and the DQ0 signal; and displaying the phasor diagram.

[0104] Example 16 is a method of any one of Examples 11 to 15, wherein acquiring a three-phase signal from the device under test includes receiving a three-phase voltage signal and receiving a three-phase current signal from the device under test, and wherein performing a DQ0 transformation includes performing a DQ0 transformation on the three-phase voltage signal and the three-phase current signal, respectively.

[0105] Example 17 is the method of any of Examples 11 to 16, wherein the DQ0 transform uses a constant equal to two-thirds or the square root of two-thirds.

[0106] Example 18 is the method of any of Examples 11 to 17, further comprising performing an inverse DQ0 transform on the DQ0 signal to generate a reconstructed three-phase signal.

[0107] Example 19 is the method of Example 18, further comprising generating a map of the reconstructed three-phase signal.

[0108] Example 20 is the method of Example 18, further comprising: generating a phasor diagram using the DQ0 signal and the reconstructed three-phase signal; and displaying the phasor diagram.

[0109] Although particular embodiments have been shown and described for purposes of illustration, it will be appreciated that various modifications can be made without departing from the spirit and scope of the present disclosure. Therefore, the present invention is not to be limited, except as in the appended claims.

Claims

1. A test and measurement device comprising: an interface configured to acquire a time-varying analog three-phase signal from a device under test, wherein when acquiring the time-varying analog three-phase signal, the device under test includes a rotor that rotates relative to a stator; A processor programmed to execute instructions, the instructions causing the processor to: Performing a direct-to-quadrature-to-zero (DQ0) conversion based on the time-varying analog three-phase signal and generating a DQ0 signal, wherein the DQ0 conversion is performed for each sampling point of the collected time-varying three-phase analog signal; and measuring the performance of the device under test based on the DQ0 signal; as well as a display, wherein the processor is programmed to execute instructions that cause the processor to generate a phasor diagram using the DQ0 signal and to display the phasor diagram on the display; The processor is programmed to execute instructions, wherein the instructions enable the processor to update the phasor diagram on the display over time for each sampling point of the acquired time-varying analog three-phase signal when acquiring the time-varying three-phase analog signal.

2. The test and measurement device of claim 1 , wherein measuring the performance of the device under test based on the DQ0 signal comprises measuring at least one of ripple, peak-to-peak amplitude, a DC average value of the DQ0 component, a fast Fourier transform plot of the DQ0 component, magnitudes of D and Q, harmonic measurements, jitter analysis, and total power of DQ0. 3 . The test and measurement device of claim 1 , wherein the processor is programmed to execute instructions that cause the processor to display a waveform graph of the DQ0 signal on the display.

4. The test and measurement device of claim 1 , wherein the processor is programmed to execute instructions that cause the processor to perform an inverse DQ0 transform based on the DQ0 signal and generate a reconstructed three-phase signal. 5 . The test and measurement device of claim 4 , wherein the processor is programmed to execute instructions that cause the processor to display the reconstructed three-phase signal on the display.

6. The test and measurement device of claim 4, wherein the processor is programmed to execute instructions that cause the processor to generate a phasor diagram using at least one of the time-varying simulated three-phase signal and the reconstructed three-phase signal. 7 . The test and measurement device of claim 1 , wherein the interface is configured to receive a time-varying analog three-phase signal from a motor drive input or a drive output of a device under test. 8 . The test and measurement device of claim 1 , wherein the interface is configured to receive a time-varying simulated three-phase voltage signal via a voltage probe and to receive a time-varying simulated three-phase current signal via a current probe.

9. The test and measurement device of claim 1 , wherein the processor is programmed to execute instructions that cause the processor to generate a phasor diagram using the time-varying analog three-phase signal and the DQ0 signal, and to display the phasor diagram on the display.

10. The test and measurement device of claim 1, wherein the DQ0 transform uses a constant equal to two-thirds or the square root of two-thirds.

11. A method of testing and measuring, comprising: collecting a time-varying analog three-phase signal from the device under test, when collecting the time-varying analog three-phase signal, the device under test includes a rotor rotating relative to a stator; Performing a direct-to-quadrature-to-zero (DQ0) transformation on the time-varying analog three-phase signal to generate a DQ0 signal, wherein the DQ0 transformation is performed for each sampling point of the collected time-varying three-phase analog signal; Measuring the performance of the device under test using the DQ0 signal; generating a phasor diagram using the DQ0 signal, and displaying the phasor diagram on a display; as well as When the time-varying three-phase analog signal is collected, the phasor diagram on the display is updated over time for each sampling point of the collected time-varying analog three-phase signal.

12. The method of claim 11, further comprising generating a waveform diagram of a DQ0 signal on the display.

13. The method of claim 11 , wherein measuring the performance of the device under test using the DQ0 signal comprises measuring at least one of ripple, peak-to-peak amplitude, a DC average of the DQ0 component, a fast Fourier transform of the DQ0 signal, D and Q magnitudes, harmonic measurements, jitter analysis, and total power of DQ0. 14 . The method of claim 11 , wherein acquiring the time-varying analog three-phase signal from the device under test comprises receiving the time-varying analog three-phase signal from a motor drive input or a drive output of the device under test.

15. The method according to claim 11, Generating a phasor diagram using the DQ0 signal includes generating a phasor diagram using the collected time-varying analog three-phase signal and the DQ0 signal.

16. The method of claim 11, wherein acquiring a time-varying analog three-phase signal from the device under test comprises receiving a time-varying analog three-phase voltage signal and a time-varying analog three-phase current signal from the device under test, and wherein performing a DQ0 transformation comprises performing a DQ0 transformation on the time-varying analog three-phase voltage signal and the time-varying analog three-phase current signal, respectively.

17. The method of claim 11, wherein the DQ0 transform uses a constant equal to two-thirds or the square root of two-thirds.

18. The method of claim 11, further comprising performing an inverse DQ0 transform on the DQ0 signal to generate a reconstructed three-phase signal.

19. The method of claim 18, further comprising generating a plot of the reconstructed three-phase signal.

20. The method according to claim 18, Generating a phasor diagram using the DQ0 signal includes generating a phasor diagram using the DQ0 signal and the reconstructed three-phase signal.

21. A computer-readable medium comprising instructions which, when executed by a processor, cause the processor to perform the method of any one of claims 11 to 20.

22. A computer program product comprising instructions which, when executed by a processor, cause the processor to perform the method of any one of claims 11 to 20.

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