Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package and a method for manufacturing the same are provided. The semiconductor package may include a semiconductor chip and a lower redistribution structure, the semiconductor chip including a chip pad, and the lower redistribution structure including a lower redistribution insulation layer and a lower redistribution pattern. The lower redistribution insulation layer may include a top surface facing the semiconductor chip. The semiconductor package may also include a mold layer and a conductive pillar located in the mold layer, the mold layer being located on a side of the semiconductor chip and including a bottom surface facing the lower redistribution structure. The conductive pillar may include a bottom surface contacting the lower redistribution structure. The top surface of the lower redistribution insulation layer may be closer to the top surface of the conductive pillar than the top surface of the mold layer. The top surface of the mold layer may have a roughness greater than the roughness of the top surface of the conductive pillar.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0088519 filed on July 22, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a fan-out type semiconductor package and a method of manufacturing the same. Background Art

[0003] With the rapid growth of demand for portable devices in the recent electronic product market, it has been desired that the electronic components mounted on the electronic products be compact and light. In order to make the electronic components compact and light, the semiconductor packages mounted on the electronic components can be small and can process a large amount of data. Specifically, in highly integrated semiconductor chips with an increasing number of input / output (I / O) terminals, the distance between the I / O terminals is reduced, and therefore, interference occurs between the I / O terminals. In order to reduce the interference between the I / O terminals, a fan-out semiconductor package that enables the distance between the I / O terminals to be increased can be used. Summary of the Invention

[0004] The inventive concept provides a semiconductor package having improved reliability and a method of manufacturing the same.

[0005] According to some embodiments of the inventive concept, a semiconductor package is provided, which may include a semiconductor chip and a lower redistribution structure located on the semiconductor chip, the semiconductor chip including a chip pad. The lower redistribution structure may include a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the chip pad of the semiconductor chip, and the lower redistribution insulating layer may include a top surface facing the semiconductor chip. The semiconductor package may also include a mold layer and a conductive pillar located in the mold layer, the mold layer extending on a side of the semiconductor chip and including a bottom surface facing the lower redistribution structure and a top surface opposite to the bottom surface of the mold layer. The conductive pillar may include a bottom surface contacting the lower redistribution pattern and a top surface opposite to the bottom surface of the conductive pillar. The top surface of the conductive pillar may be spaced apart from the top surface of the lower redistribution insulating layer by a first distance, and the top surface of the mold layer may be spaced apart from the top surface of the lower redistribution insulating layer by a second distance that may be greater than the first distance. The top surface of the mold layer may have a roughness greater than the roughness of the top surface of the conductive pillar.

[0006] According to some embodiments of the inventive concept, a semiconductor package is provided, which may include: a lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern; a lower semiconductor chip located on the lower redistribution insulating layer and electrically connected to the lower redistribution pattern; and a conductive pillar located on the lower redistribution insulating layer and electrically connected to the lower redistribution pattern. The lower redistribution insulating layer may include a top surface facing the lower semiconductor chip and the conductive pillar, and the conductive pillar may include a bottom surface facing the lower redistribution structure and a top surface opposite the bottom surface of the conductive pillar. The semiconductor package may further include a mold layer extending over side surfaces of the lower semiconductor chip and side surfaces of the conductive pillar and including a bottom surface facing the lower redistribution structure and a top surface opposite the bottom surface of the mold layer. The top surface of the conductive pillar may be spaced apart from the top surface of the lower redistribution insulating layer by a first distance, and the top surface of the mold layer may be spaced apart from the top surface of the lower redistribution insulating layer by a second distance that may be greater than the first distance. The semiconductor package may further include an upper redistribution structure located on the mold layer and the lower semiconductor chip. The upper redistribution structure may include an upper redistribution insulating layer and an upper redistribution pattern, the upper redistribution insulating layer may extend over the top surface of the conductive pillar, and the upper redistribution pattern may extend through a portion of the upper redistribution insulating layer and contact the conductive pillar. The roughness of the top surface of the mold layer may be greater than the roughness of the top surface of the conductive pillar.

[0007] According to some embodiments of the inventive concept, a semiconductor package is provided, which may include a lower package, the lower package including: a lower semiconductor chip; a molding layer extending on a side surface of the lower semiconductor chip; a conductive pillar located in the molding layer; and a lower redistribution pattern electrically connecting the lower semiconductor chip to the conductive pillar. The semiconductor package may also include an upper package located on the lower package, and the upper package may include an upper semiconductor chip. The conductive pillar may include a top surface facing the upper package. The semiconductor package may also include an inter-package connector located between the lower package and the upper package, and the inter-package connector may contact the top surface of the conductive pillar. The molding layer may include a top surface facing the upper package, and the top surface of the conductive pillar may be recessed relative to the top surface of the molding layer toward the lower redistribution pattern. The roughness of the top surface of the molding layer may be greater than the roughness of the top surface of the conductive pillar.

[0008] According to some embodiments of the inventive concept, a method for manufacturing a semiconductor package is provided. The method may include: forming a lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern; and forming a conductive pillar on a portion of the lower redistribution pattern. The conductive pillar may include a bottom surface facing the lower redistribution structure and a top surface opposite to the bottom surface of the conductive pillar. The method may also include: forming a sacrificial layer on the top surface of the conductive pillar; disposing a semiconductor chip on the lower redistribution structure; forming a mold layer on the semiconductor chip, the conductive pillar, and the sacrificial layer; removing a portion of the mold layer by performing a polishing process to expose the sacrificial layer; and exposing the top surface of the conductive pillar by removing the sacrificial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the inventive concept will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a cross-sectional view of a semiconductor package according to an example embodiment of the inventive concept;

[0011] Figure 2 yes Figure 1 An enlarged cross-sectional view of region II in FIG.

[0012] Figure 3 is a cross-sectional view of a semiconductor package according to an example embodiment of the inventive concept;

[0013] Figure 4 is a cross-sectional view of a semiconductor package according to an example embodiment of the inventive concept;

[0014] Figure 5 yes Figure 4 An enlarged cross-sectional view of region V in FIG.

[0015] Figure 6 is a cross-sectional view of a semiconductor package according to an example embodiment of the inventive concept;

[0016] Figure 7 yes Figure 6 An enlarged cross-sectional view of region VII in FIG; and

[0017] Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 8D 、 Figure 8E 、 Figure 8F 、 Figure 8G 、 Figure 8H 、 Figure 8I 、 Figure 8J 、 Figure 8K 、 Figure 8L 、 Figure 8M 、 Figure 8N 、 Figure 8O、 Figure 8P 、 Figure 8Q 、 Figure 8R and Figure 8S are cross-sectional views illustrating sequential stages in a method of fabricating a semiconductor package according to example embodiments of the inventive concepts. DETAILED DESCRIPTION

[0018] Hereinafter, example embodiments will be described with reference to the accompanying drawings. In the accompanying drawings, like reference numerals denote like elements, and redundant descriptions thereof may be omitted.

[0019] Figure 1 is a cross-sectional view of a semiconductor package 10 according to an example embodiment of the inventive concepts. Figure 2 yes Figure 1 An enlarged cross-sectional view of region II in FIG.

[0020] Reference Figure 1 and Figure 2 , the semiconductor package 10 may include a redistribution structure 101 , a semiconductor chip 200 , a conductive pillar 160 , and a molding layer 250 .

[0021] The redistribution structure 101 may include a redistribution insulating layer 110 , a plurality of redistribution patterns (eg, a first redistribution pattern 120 , a second redistribution pattern 130 , and a third redistribution pattern 140 ), and an external electrode pad (or “external electrode pad”) 150 .

[0022] The redistribution insulating layer 110 may include a plurality of insulating layers, for example, a first insulating layer 111, a second insulating layer 113, and a third insulating layer 115. The first to third insulating layers 111, 113, and 115 may be formed of, for example, a material film including an organic compound. In an example embodiment, the first to third insulating layers 111, 113, and 115 may be formed of a material layer including an organic polymer material. In an example embodiment, the first to third insulating layers 111, 113, and 115 may include a photoimageable dielectric (PID) material capable of undergoing a photolithography process. For example, the first to third insulating layers 111, 113, and 115 may include photosensitive polyimide (PSPI). In an example embodiment, the first to third insulating layers 111, 113, and 115 may include an oxide or a nitride. For example, the first to third insulating layers 111, 113, and 115 may include silicon oxide or silicon nitride.

[0023] The first to third redistribution patterns 120, 130, and 140 may include respective first, second, and third conductor patterns 121, 131, and 141, and respective first, second, and third conductive via patterns 123, 133, and 143. Each of the first to third conductor patterns 121, 131, and 141 may be located on at least one selected from the top and bottom surfaces of a corresponding one of the first to third insulating layers 111, 113, and 115. The first to third conductive via patterns 123, 133, and 143 may penetrate through at least one selected from the first to third insulating layers 111, 113, and 115. The first to third conductive via patterns 123, 133, and 143 may be connected to at least one selected from the first to third conductor patterns 121, 131, and 141, or to the external electrode pad 150. As used herein, “element A is connected to element B” (or similar language) may mean that element A is electrically and / or physically connected to element B. In some embodiments, the first conductive line pattern 121 may extend on the surface of the first insulating layer 111, and the first conductive via pattern 123 may be as shown. Figure 1 1 and 150. In some embodiments, the second conductor pattern 131 may extend on the surface of the second insulating layer 113, and the second conductive via pattern 133 may be connected to both the first conductor pattern 121 and the external electrode pad 150. Figure 1 1 is connected to both the second conductor pattern 131 and the first conductor pattern 121. In some embodiments, the third conductor pattern 141 may extend on the surface of the third insulating layer 115, and the third conductive via pattern 143 may be as shown. Figure 1 , which is shown as being connected to both the third conductor pattern 141 and the second conductor pattern 131 .

[0024] A plurality of seed layers (e.g., a first seed layer 125, a second seed layer 135, and a third seed layer 145) may be disposed between the first to third insulating layers 111, 113, and 115 and the first to third conductive wire patterns 121, 131, and 141, respectively, and between the first to third insulating layers 111, 113, and 115 and the first to third conductive via patterns 123, 133, and 143, respectively. In example embodiments, the first to third seed layers 125, 135, and 145 may be formed using physical vapor deposition, and the first to third conductive wire patterns 121, 131, and 141 and the first to third conductive via patterns 123, 133, and 143 may be formed using electroless plating (chemical plating).

[0025] For example, the first to third seed layers 125, 135, and 145 may be selected from the group consisting of copper (Cu), titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), chromium (Cr), and aluminum (Al). However, the first to third seed layers 125, 135, and 145 are not limited to the above materials. In example embodiments, the first to third seed layers 125, 135, and 145 may include Cu / Ti in which Cu is stacked on Ti, or Cu / TiW in which Cu is stacked on TiW.

[0026] The first to third conductor patterns 121, 131, and 141 and the first to third conductive via patterns 123, 133, and 143 may include, but are not limited to, a metal such as Cu, Al, W, Ti, Ta, indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), or ruthenium (Ru), or an alloy thereof. In example embodiments, when Cu is used for the first to third conductor patterns 121, 131, and 141 and the first to third conductive via patterns 123, 133, and 143, at least a portion of the first to third seed layers 125, 135, and 145 may serve as a diffusion barrier.

[0027] The external electrode pad 150 may be arranged on the bottom surface of the redistribution structure 101. The external connector 190 may be arranged on the external electrode pad 150. The semiconductor package 10 may be electrically connected to a module substrate or a system board of an electronic product through the external connector 190 and mounted on the module substrate or the system board of the electronic product. The external electrode pad 150 may serve as an under-bump metallurgy (UBM) on which the external connector 190 is arranged.

[0028] In example embodiments, the external electrode pad 150 may have a uniform thickness overall. The bottom surface of the external electrode pad 150 on which the external connector 190 is arranged may be flat. For example, the external electrode pad 150 may include a metal such as Cu, Al, W, Ti, Ta, In, Mo, Mn, Co, Sn, Ni, Mg, Re, Be, Ga, or Ru, or an alloy thereof, but is not limited thereto. In some embodiments, the bottom surface of the external electrode pad 150 may directly contact the external connector 190, and the distance between the top surface and the bottom surface of the external electrode pad 150 may be as shown in FIG. Figure 1 The ones shown in are uniform.

[0029] The configuration of the redistribution structure 101 will be described in detail below.

[0030] The redistribution insulation layer 110 may include a first insulation layer 111, a second insulation layer 113, and a third insulation layer 115 sequentially stacked. The first redistribution pattern 120 may include a first wire pattern 121, a first conductive via pattern 123, and a first seed layer 125. The second redistribution pattern 130 may include a second wire pattern 131, a second conductive via pattern 133, and a second seed layer 135. The third redistribution pattern 140 may include a third wire pattern 141, a third conductive via pattern 143, and a third seed layer 145.

[0031] The first insulating layer 111 may include a first via opening ( Figure 8E VO1 in). The first seed layer 125 may be arranged on a portion of the top surface of the first insulating layer 111, the inner wall of the first via opening VO1, and a portion of the top surface of the external electrode pad 150, the portion of the top surface of the external electrode pad 150 being exposed through the first via opening VO1. A portion of the first seed layer 125 may be located between the first conductor pattern 121 and the top surface of the first insulating layer 111. Another portion of the first seed layer 125 may be arranged between the first conductive via pattern 123 and the external electrode pad 150, and may surround the sidewall of the first conductive via pattern 123. As used herein, “element A surrounds a side of element B” (or similar language) may mean that element A extends on that side of element B, but does not necessarily mean that element A completely surrounds that side of element B.

[0032] The first conductor pattern 121 and the first conductive via pattern 123 can be arranged on the first seed layer 125. The first conductor pattern 121 and the first conductive via pattern 123 can be integrally formed together using a plating process. The first conductor pattern 121 can be arranged on a portion of the first seed layer 125 located on the top surface of the first insulating layer 111 and the first conductive via pattern 123. The first conductive via pattern 123 can cover a portion of the first seed layer 125 located in the first via opening VO1 and can fill the first via opening VO1. The first conductive via pattern 123 can extend in the vertical direction, can extend through the first insulating layer 111, and can be connected to the first conductor pattern 121 and the external electrode pad 150. As used herein, "element A covers element B" (or similar language) can mean that element A extends on element B, but does not necessarily mean that element A completely covers element B. As used herein, "element A fills element B" (or similar language) can mean that element A is located in element B, but does not necessarily mean that element A completely fills element B. As used herein, “element A and element B are integrally formed together using process C” (or similar language) may mean that element A and element B are formed using a single process C and may form a single layer. The vertical direction may be the direction along which the first and second conductor patterns 121 and 131 are spaced apart from each other.

[0033] In example embodiments, the first conductive via pattern 123 may have a shape in which its width in the horizontal direction decreases in a direction from the first surface 118 of the redistribution insulation layer 110 toward the second surface 119 of the redistribution insulation layer 110 (or in a direction away from the semiconductor chip 200). In some embodiments, the first conductive via pattern 123 may be as follows: Figure 1 , having a width tapering toward the external electrode pad 150. The first surface 118 of the redistribution insulation layer 110 may be a top surface of the redistribution insulation layer 110, and the second surface 119 may be a bottom surface of the redistribution insulation layer 110 opposite to the top surface.

[0034] The second insulating layer 113 may be stacked on the first insulating layer 111, the second insulating layer 113 covering a portion of the first conductive pattern 121 and having a second via opening ( Figure 8E in VO2).

[0035] The second seed layer 135 may be arranged on a portion of the top surface of the second insulating layer 113, an inner wall of the second via opening VO2, and a portion of the top surface of the first conductor pattern 121, the portion of the top surface of the first conductor pattern 121 being exposed through the second via opening VO2. A portion of the second seed layer 135 may be located between the second conductor pattern 131 and the top surface of the second insulating layer 113. Another portion of the second seed layer 135 may be arranged between the second conductive via pattern 133 and the first conductive via pattern 121 and may surround the sidewall of the second conductive via pattern 133.

[0036] The second conductive via pattern 133 and the second conductor pattern 131 may be arranged on the second seed layer 135. The second conductive via pattern 133 and the second conductor pattern 131 may be formed integrally together using a plating process. The second conductor pattern 131 may be arranged on a portion of the second seed layer 135 located on the top surface of the second insulating layer 113 and the second conductive via pattern 133. The second conductive via pattern 133 may cover a portion of the second seed layer 135 located in the second via opening VO2 and may fill the second via opening VO2. The second conductive via pattern 133 may extend in a vertical direction, may extend through the second insulating layer 113, and may be connected to the second conductor pattern 131 and the first conductor pattern 121.

[0037] In example embodiments, the second conductive via pattern 133 may have a shape in which its width in the horizontal direction decreases in a direction from the first surface 118 of the redistribution insulation layer 110 toward the second surface 119 of the redistribution insulation layer 110. In some embodiments, the second conductive via pattern 133 may be as follows: Figure 1 , having a width that tapers toward the first conductor pattern 121 .

[0038] The third insulating layer 115 may be stacked on the second insulating layer 113 , the third insulating layer 115 covering a portion of the second conductive pattern 131 and having a third via opening ( Figure 8E in VO3).

[0039] The third seed layer 145 may be arranged on a portion of the top surface of the third insulating layer 115, an inner wall of the third via opening VO3, and a portion of the top surface of the second conductor pattern 131, the portion of the top surface of the second conductor pattern 131 being exposed through the third via opening VO3. A portion of the third seed layer 145 may be located between the third conductor pattern 141 and the top surface of the third insulating layer 115. Another portion of the third seed layer 145 may be arranged between the third conductive via pattern 143 and the second conductive via pattern 131 and may surround the sidewall of the third conductive via pattern 143.

[0040] The third conductive via pattern 143 and the third conductor pattern 141 may be arranged on the third seed layer 145. The third conductive via pattern 143 and the third conductor pattern 141 may be integrally formed together using a plating process. The third conductor pattern 141 may be arranged on a portion of the third seed layer 145 located on the top surface of the third insulating layer 115 and the third conductive via pattern 143. The third conductive via pattern 143 may cover a portion of the third seed layer 145 located in the third via opening VO3 and may fill the third via opening VO3. The third conductive via pattern 143 may extend in a vertical direction, may extend through the third insulating layer 115, and may be connected to the third conductor pattern 141 and the second conductor pattern 131.

[0041] In example embodiments, the third conductive via pattern 143 may have a shape in which its width in the horizontal direction decreases in a direction from the first surface 118 of the redistribution insulation layer 110 toward the second surface 119 of the redistribution insulation layer 110. In some embodiments, the third conductive via pattern 143 may be as follows: Figure 1 , having a width that tapers toward the second conductor pattern 131 .

[0042] A portion of the third conductor pattern 141 of the third redistribution pattern 140 may be arranged below the semiconductor chip 200 and may function as a pad to which the chip connector 230 is attached. In addition, another portion of the third conductor pattern 141 of the third redistribution pattern 140 may be spaced apart from the side surface of the semiconductor chip 200 in a horizontal direction and may function as a pad to which the conductive pillar 160 is attached.

[0043] Despite Figure 1 , the redistribution structure 101 is shown to include three insulating layers (i.e., first to third insulating layers 111, 113, and 115), three conductive line patterns (i.e., first to third conductive line patterns 121, 131, and 141), and three conductive via patterns (i.e., first to third conductive via patterns 123, 133, and 143), but embodiments of the inventive concept are not limited thereto. The number of insulating layers, conductive line patterns, and conductive via patterns may vary depending on the design of circuit routing in the redistribution structure 101.

[0044] The semiconductor chip 200 may be attached to the redistribution structure 101. For example, the semiconductor chip 200 may be mounted on the redistribution structure 101 in a flip-chip manner.

[0045] The semiconductor chip 200 may include a memory chip or a logic chip. The memory chip may include, for example, a volatile memory chip such as a dynamic random access memory (DRAM) or a static RAM (SRAM), or a non-volatile memory chip such as a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FeRAM), or a resistive RAM (RRAM). In some embodiments, the memory chip may include a high bandwidth memory (HBM) DRAM semiconductor chip. The logic chip may include, for example, a microprocessor, an analog device, or a digital signal processor.

[0046] The semiconductor chip 200 may include a semiconductor substrate 210 and a chip pad 220 in a surface of the semiconductor substrate 210 .

[0047] The semiconductor substrate 210 may include, for example, silicon (Si). The semiconductor substrate 210 may include a semiconductor element (e.g., germanium (Ge)) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The semiconductor substrate 210 may have an active side and an inactive side opposite to the active side. In example embodiments, the active side of the semiconductor substrate 210 may face the redistribution structure 101.

[0048] Semiconductor devices including various individual devices may be formed in the active side of the semiconductor substrate 210 of the semiconductor chip 200 .

[0049] The chip connector 230 may be disposed between the chip pad 220 of the semiconductor chip 200 and the third conductor pattern 141. The chip connector 230 may electrically connect the chip pad 220 of the semiconductor chip 200 to the third conductor pattern 141. The chip connector 230 may include, for example, at least one selected from a pillar structure, a solder bump, a solder ball, and a solder layer.

[0050] The semiconductor chip 200 can receive at least one selected from a control signal, a power signal, and a ground signal for the operation of the semiconductor chip 200 from outside the semiconductor package 10, or receive a data signal to be stored in the semiconductor chip 200, or can provide the data stored in the semiconductor chip 200 to the outside of the semiconductor package 10 through the chip connector 230, the first to third redistribution patterns 120, 130 and 140, the external electrode pad 150 and the external connector 190.

[0051] An underfill material layer 240 may be disposed between the semiconductor chip 200 and the redistribution structure 101 to surround the chip connector 230. The underfill material layer 240 may include, for example, an epoxy resin formed using a capillary underfill process. In example embodiments, the underfill material layer 240 may include a non-conductive film (NCF).

[0052] The mold layer 250 may be disposed on the top surface of the redistribution structure 101 (i.e., the first surface 118 of the redistribution insulation layer 110) and may cover at least a portion of the semiconductor chip 200 and the side surfaces of the conductive pillars 160. The mold layer 250 may include, for example, an epoxy molding compound (EMC). The mold layer 250 may not be limited to EMC and may include various materials such as epoxy materials, thermosetting materials, thermoplastic materials, and ultraviolet (UV) treated materials. In example embodiments, the mold layer 250 may include a material different from that of the redistribution insulation layer 110. For example, when the mold layer 250 is formed of EMC, the redistribution insulation layer is formed of a PID material such as PSPI.

[0053] In example embodiments, the mold layer 250 may cover a portion of the first surface 118 of the redistribution insulation layer 110 and the side surfaces of the semiconductor chip 200. A top surface 251 of the mold layer 250 may be coplanar with the top surface of the semiconductor chip 200. At this time, the top surface of the semiconductor chip 200 may be exposed to the outside. In some embodiments, the mold layer 250 may expose the top surface of the semiconductor chip 200.

[0054] The conductive pillars 160 may be spaced apart from the side surfaces of the semiconductor chip 200 in the horizontal direction, may have a pillar or column shape extending in the vertical direction, and may penetrate the mold layer 250. The conductive pillars 160 may be arranged on the third redistribution pattern 140, which functions as a pad. The conductive pillars 160 may be electrically connected to the semiconductor chip 200 through at least a portion of the first to third redistribution patterns 120, 130, and 140, and may be electrically connected to the external connector 190 through at least a portion of the first to third redistribution patterns 120, 130, and 140 and the external electrode pad 150. For example, the conductive pillars 160 may be electrically connected to the chip pad 220 of the semiconductor chip 200 through a portion of the third redistribution pattern 140 located below the conductive pillars 160, the second redistribution pattern 130, and a portion of the third redistribution pattern 140 located below the chip connector 230.

[0055] For example, the conductive pillar 160 may include Cu, but is not limited thereto. The conductive pillar 160 may include various conductive materials.

[0056] In example embodiments, the horizontal width of the conductive pillar 160 may be about 100 μm to about 250 μm.

[0057] The mold layer 250 may include a recess 257 for exposing the top surface 161 of the conductive pillar 160 and an inner wall 253 defined by the recess 257 of the mold layer 250 .

[0058] At this time, the top surface 161 of the conductive pillar 160 may be at a lower level (height) than the top surface 251 of the mold layer 250. In example embodiments, the vertical distance between the top surface 161 of the conductive pillar 160 and the top surface 251 of the mold layer 250 may be about 1 μm to about 100 μm. In other words, the depth of the recess 257 of the mold layer 250 may be about 1 μm to about 100 μm.

[0059] In some embodiments, as Figure 1 As shown in , the top surface 161 of the conductive pillar 160 may be spaced apart from the first surface 118 of the redistribution insulation layer 110 by a first distance d1, and the top surface 251 of the mold layer 250 may be spaced apart from the first surface 118 of the redistribution insulation layer 110 by a second distance d2 that is greater than the first distance d1. In some embodiments, the difference between the second distance d2 and the first distance d1 may be about 1 μm to about 100 μm. In some embodiments, as Figure 1 and Figure 2 As shown in FIG, the top surface 161 of the conductive pillar 160 may be recessed toward the redistribution insulation layer 110 relative to the top surface 251 of the mold layer 250 .

[0060] In example embodiments, the horizontal width of the recess 257 of the mold layer 250 may be equal to that of the top surface 161 of the conductive pillar 160 , and the top surface 161 of the conductive pillar 160 may be completely exposed by the recess 257 of the mold layer 250 .

[0061] In example embodiments, the horizontal width of the recess 257 of the mold layer 250 may be different from the horizontal width of the top surface 161 of the conductive pillar 160. For example, the horizontal width of the recess 257 of the mold layer 250 may be greater than the horizontal width of the top surface 161 of the conductive pillar 160, and the top surface 161 of the conductive pillar 160 may be completely exposed by the recess 257 of the mold layer 250. Alternatively, the horizontal width of the recess 257 of the mold layer 250 may be less than the horizontal width of the top surface 161 of the conductive pillar 160, and the top surface 161 of the conductive pillar 160 may be partially exposed by the recess 257 of the mold layer 250.

[0062] In example embodiments, the roughness of the top surface 251 of the mold layer 250 may be greater than the roughness of the top surface 161 of the conductive pillar 160. For example, the arithmetic mean roughness (Ra) of the top surface 251 of the mold layer 250 may be approximately two to eight times the Ra of the top surface 161 of the conductive pillar 160.

[0063] The roughness of the top surface 251 of the mold layer 250 may be greater than the roughness of the inner wall 253 of the mold layer 250. The term "roughness" as used herein may refer to an arithmetic mean roughness (Ra).

[0064] Figure 3 is a cross-sectional view of a semiconductor package 10 a according to an example embodiment of the inventive concepts.

[0065] In addition to the mold layer 250a, Figure 3 The semiconductor package 10a can be compared with the reference Figure 1 and Figure 2 For ease of description, the description will focus on the semiconductor package 10a and the semiconductor package 10a of reference. Figure 1 and Figure 2 The differences between the semiconductor packages 10 are described.

[0066] Reference Figure 3 The semiconductor package 10a may include a redistribution structure 101, a semiconductor chip 200, a conductive pillar 160, and a mold layer 250a. The mold layer 250a may cover the side surfaces and top surfaces of the semiconductor chip 200 and the side surfaces of the conductive pillars 160. The mold layer 250a may include a planarized top surface. The top surface 251a of the mold layer 250a may be at a higher level (height) than the top surface of the semiconductor chip 200. The top surface 251a of the mold layer 250a may also be at a higher level than the top surface 161 of the conductive pillars 160.

[0067] Figure 4 is a cross-sectional view of a semiconductor package 10 b according to an example embodiment of the inventive concepts. Figure 5 yes Figure 4 An enlarged cross-sectional view of region V in FIG.

[0068] In addition to the semiconductor package 10b further including an upper redistribution structure 401 and an upper semiconductor chip 500, Figure 4 and Figure 5 The semiconductor package 10b shown in FIG. Figure 1 and Figure 2 For ease of description, the description will focus on the semiconductor package 10b and the semiconductor package 10b of reference. Figure 1 and Figure 2 The differences between the semiconductor packages 10 are described.

[0069] Reference Figure 4 and Figure 5 The semiconductor package 10 b may include a redistribution structure 101 , a semiconductor chip 200 , a conductive pillar 160 , a mold layer 250 , an upper redistribution structure 401 , an upper semiconductor chip 500 , and an upper mold layer 550 .

[0070] The redistribution structure 101 may include a redistribution insulating layer 110 , first to third redistribution patterns 120 , 130 , and 140 , and an external electrode pad 150 . Figure 4 The redistribution structure 101 can be compared with the reference Figure 1 and Figure 2 The redistribution structure 101 described is substantially the same or similar. Figure 4 and Figure 5 The semiconductor chip 200, the conductive pillar 160 and the mold layer 250 shown in FIG. Figure 1 and Figure 2 The semiconductor chip 200 , conductive pillars 160 , and mold layer 250 described are substantially the same or similar.

[0071] The upper redistribution structure 401 may include an upper redistribution insulating layer 410 and a plurality of upper redistribution patterns (eg, first and second upper redistribution patterns 420 and 430 ). The plurality of upper redistribution patterns may be electrically connected to the third redistribution pattern 140 of the redistribution structure 101 through conductive pillars 160 .

[0072] The upper redistribution insulating layer 410 may include a plurality of upper insulating layers sequentially stacked on the semiconductor chip 200 and the mold layer 250, for example, a first upper insulating layer 411 and a second upper insulating layer 413. For example, the first upper insulating layer 411 and the second upper insulating layer 413 may include a PID material, for example, photosensitive polyimide. In some embodiments, the first upper insulating layer 411 and the second upper insulating layer 413 may include an oxide or a nitride.

[0073] The first and second upper redistribution patterns 420 and 430 may include respective first and second upper conductor patterns 421 and 431 and respective first and second upper conductive via patterns 423 and 433. Each of the first and second upper conductor patterns 421 and 431 may be disposed on at least one selected from the top surface and the bottom surface of a corresponding one of the first and second upper insulating layers 411 and 413. The first and second upper conductive via patterns 423 and 433 may penetrate at least one selected from the first and second upper insulating layers 411 and 413. The first and second upper conductive via patterns 423 and 433 may be connected to at least one selected from the first and second upper conductor patterns 421 and 431 or the top surface 161 of the conductive pillar 160.

[0074] For example, the upper redistribution insulation layer 410 may include a first upper insulation layer 411 and a second upper insulation layer 413 sequentially stacked on the semiconductor chip 200 and the mold layer 250 .

[0075] The first upper insulating layer 411 may cover the top surface of the semiconductor chip 200 and the top surface 251 of the mold layer 250. The first upper insulating layer 411 may fill the recess ( Figure 2 257 in the figure). The portion of the first upper insulating layer 411 that fills the recess of the mold layer 250 can cover the inner wall 253 of the mold layer 250 and the top surface 161 of the conductive pillar 160. Since the first upper insulating layer 411 fills the recess of the mold layer 250, the contact area between the first upper insulating layer 411 and the mold layer 250 increases. Therefore, the adhesion strength of the first upper insulating layer 411 to the mold layer 250 can be increased, and delamination of the first upper insulating layer 411 can be reduced or possibly prevented.

[0076] The first upper redistribution pattern 420 may include a first upper wire pattern 421 , a first upper conductive via pattern 423 , and a first upper seed layer 425 . The second upper redistribution pattern 430 may include a second upper wire pattern 431 , a second upper conductive via pattern 433 , and a second upper seed layer 435 .

[0077] The first upper insulating layer 411 may include a via opening exposing a portion of the top surface 161 of the conductive pillar 160. The first upper seed layer 425 may be disposed on a portion of the top surface of the first upper insulating layer 411, an inner wall of the via opening of the first upper insulating layer 411, and a portion of the top surface 161 of the conductive pillar 160, the portion of the top surface 161 of the conductive pillar 160 being exposed through the via opening of the first upper insulating layer 411. A portion of the first upper seed layer 425 may be located between the first upper wire pattern 421 and the top surface of the first upper insulating layer 411, and another portion of the first upper seed layer 425 may be disposed between the first upper conductive via pattern 423 and the top surface 161 of the conductive pillar 160 to surround the sidewall of the first upper conductive via pattern 423.

[0078] The first upper conductor pattern 421 and the first upper conductive via pattern 423 can be arranged on the first upper seed layer 425. The first upper conductor pattern 421 and the first upper conductive via pattern 423 can be formed integrally together using a plating process. The first upper conductor pattern 421 can be arranged on a portion of the first upper seed layer 425 located on the top surface of the first upper insulating layer 411 and the first upper conductive via pattern 423. The first upper conductive via pattern 423 can cover a portion of the first upper seed layer 425 located in the via opening of the first upper insulating layer 411 and can fill the via opening of the first upper insulating layer 411. The first upper conductive via pattern 423 can extend in a vertical direction, can penetrate the first upper insulating layer 411, and can electrically connect the first upper conductor pattern 421 to the conductive pillar 160.

[0079] In example embodiments, the first upper conductive via pattern 423 may have a shape in which its horizontal width increases as the distance from the top surface 161 of the conductive pillar 160 increases. In some embodiments, the first upper conductive via pattern 423 may be as follows: Figure 4 160 is shown to have a width that tapers toward the conductive pillar 160 .

[0080] In example embodiments, the first upper conductive via pattern 423 may have a horizontal width of about 25 μm to about 45 μm.

[0081] In example embodiments, a horizontal width of a bottom end of the first upper conductive via pattern 423 adjacent to the conductive pillar 160 may be about 10% to about 45% of a horizontal width of the conductive pillar 160 .

[0082] A second upper insulating layer 413 may be stacked on the first upper insulating layer 411 , the second upper insulating layer 413 covering a portion of the first upper conductive line pattern 421 and having a via opening exposing another portion of the first upper conductive line pattern 421 .

[0083] The second upper seed layer 435 may be disposed on a portion of the top surface of the second upper insulating layer 413, an inner wall of the via opening of the second upper insulating layer 413, and a portion of the top surface of the first upper conductive pattern 421, the portion of the top surface of the first upper conductive pattern 421 being exposed through the via opening of the second upper insulating layer 413. A portion of the second upper seed layer 435 may be located between the second upper conductive pattern 431 and the top surface of the second upper insulating layer 413, and another portion of the second upper seed layer 435 may be disposed between the second upper conductive via pattern 433 and the first upper conductive pattern 421 to surround a sidewall of the second upper conductive via pattern 433.

[0084] The second upper conductive via pattern 433 and the second upper conductor pattern 431 may be arranged on the second upper seed layer 435. The second upper conductive via pattern 433 and the second upper conductor pattern 431 may be integrally formed together using a plating process. The second upper conductor pattern 431 may be arranged on a portion of the second upper seed layer 435 located on the top surface of the second upper insulating layer 413 and the second upper conductive via pattern 433. The second upper conductive via pattern 433 may cover a portion of the second upper seed layer 435 located in the via opening of the second upper insulating layer 413 and may fill the via opening of the second upper insulating layer 413. The second upper conductive via pattern 433 may extend in a vertical direction, may penetrate the second upper insulating layer 413, and may electrically connect the second upper conductor pattern 431 to the first upper conductor pattern 421.

[0085] The upper semiconductor chip 500 may be attached to the upper redistribution structure 401. For example, the upper semiconductor chip 500 may be mounted on the upper redistribution structure 401 in a flip-chip manner. The upper semiconductor chip 500 may include a semiconductor substrate 510 and a chip pad 520. A chip connector 530 may be disposed between the chip pad 520 of the upper semiconductor chip 500 and the second upper redistribution pattern 430 of the upper redistribution structure 401. The chip connector 530 may electrically connect the chip pad 520 of the upper semiconductor chip 500 to the second upper redistribution pattern 430. An underfill material layer 540 may be disposed between the upper semiconductor chip 500 and the upper redistribution structure 401 to surround the chip connector 530. An upper mold layer 550 covering at least a portion of the upper semiconductor chip 500 may be disposed on the upper redistribution structure 401.

[0086] In an example embodiment, the semiconductor chip 200 and the upper semiconductor chip 500 may be of different types. For example, when the semiconductor chip 200 is a logic chip, the upper semiconductor chip 500 may be a memory chip. In an example embodiment, the semiconductor package 10b may include a system-in-package (SIP) in which different types of semiconductor chips are electrically connected to each other and operate as a single system. In an example embodiment, the semiconductor chip 200 and the upper semiconductor chip 500 may be of the same type, and both the semiconductor chip 200 and the upper semiconductor chip 500 may be memory chips or logic chips.

[0087] Figure 6 is a cross-sectional view of a semiconductor package 10 c according to an example embodiment of the inventive concepts. Figure 7 yes Figure 6 For the convenience of description, the redundant descriptions given above may be briefly described or omitted.

[0088] Reference Figure 6 and Figure 7 , the semiconductor package 10c may include a lower package 11L and an upper package 11U located on the lower package 11L. The semiconductor package 10c may be a package-on-package type in which the upper package 11U is attached to the lower package 11L.

[0089] The lower package 11L may include a redistribution structure 101, a semiconductor chip 200, a conductive pillar 160, and a molding layer 250. The lower package 11L may be similar to the reference Figure 1 and Figure 2 The semiconductor packages 10 described are substantially the same or similar.

[0090] The upper package 11U may include an upper redistribution structure 401, an upper semiconductor chip 500, a chip connector 530, an underfill material layer 540, and an upper mold layer 550. The upper semiconductor chip 500, the chip connector 530, the underfill material layer 540, and the upper mold layer 550 may be the same as those already described with reference to FIG. Figure 4 and Figure 5 The upper semiconductor chip 500 , chip connector 530 , underfill material layer 540 , and upper molding layer 550 are described as being substantially the same or similar.

[0091] The upper redistribution structure 401 of the upper package 11U may include an upper redistribution insulating layer 410 , a plurality of upper redistribution patterns (eg, first and second upper redistribution patterns 420 and 430 ), and an electrode pad 450 .

[0092] For example, the upper redistribution insulation layer 410 may include a first upper insulation layer 411 and a second upper insulation layer 413 sequentially stacked on the lower package 11L.

[0093] For example, the first upper redistribution pattern 420 may include a first upper wire pattern 421, a first upper conductive via pattern 423, and a first upper seed layer 425. The first upper wire pattern 421 may extend along the top surface of the first upper insulating layer 411, and the first upper conductive via pattern 423 may partially penetrate the first upper insulating layer 411 and extend in a vertical direction between the first upper wire pattern 421 and the electrode pad 450. A portion of the first upper seed layer 425 may be located between the first upper wire pattern 421 and the first upper insulating layer 411, and another portion of the first upper seed layer 425 may be arranged between the first upper conductive via pattern 423 and the electrode pad 450 to surround the sidewalls of the first upper conductive via pattern 423.

[0094] For example, the second upper redistribution pattern 430 may include a second upper conductor pattern 431, a second upper conductive via pattern 433, and a second upper seed layer 435. The second upper conductor pattern 431 may extend along the top surface of the second upper insulating layer 413, and the second upper conductive via pattern 433 may penetrate the second upper insulating layer 413 and extend in a vertical direction between the second upper conductor pattern 431 and the first upper conductor pattern 421. A portion of the second upper seed layer 435 may be located between the second upper conductor pattern 431 and the second upper insulating layer 413, and another portion of the second upper seed layer 435 may be arranged between the second upper conductive via pattern 433 and the first upper conductor pattern 421 to surround the sidewalls of the second upper conductive via pattern 433.

[0095] The upper package 11U may be electrically and / or physically connected to the lower package 11L via an inter-package connector 600 between the upper package 11U and the lower package 11L. The inter-package connector 600 may contact the electrode pads 450 and the conductive pillars 160 of the upper redistribution structure 401 and electrically connect the electrode pads 450 of the upper redistribution structure 401 to the conductive pillars 160.

[0096] In example embodiments, the inter-package connector 600 may fill the recess ( Figure 2 257 in the figure). The inter-package connector 600 can cover the inner wall 253 of the mold layer 250 and the top surface 161 of the conductive pillar 160. Since the inter-package connector 600 fills the recess of the mold layer 250, the contact area between the inter-package connector 600 and the mold layer 250 can be increased, and thus the adhesive strength between the inter-package connector 600 and the mold layer 250 can be increased.

[0097] Figures 8A to 8S is a cross-sectional view of sequential stages in a method of manufacturing a semiconductor package according to an example embodiment of the inventive concept. Figures 8A to 8S Description of manufacturing Figure 4 Method of manufacturing a semiconductor package 10b.

[0098] Reference Figure 8A , a cover layer 320 is formed on the carrier substrate 310 to which the release film 311 is attached. The cover layer 320 may include a redistribution insulating layer 110 ( Figure 4 The cover layer 320 may include the same insulating material as the insulating material of the redistribution insulating layer 110, or include an insulating material different from the insulating material of the redistribution insulating layer 110. For example, the cover layer 320 may include a material film including an organic compound. In example embodiments, the cover layer 320 may include photosensitive polyimide. In some embodiments, the cover layer 320 may include oxide or nitride.

[0099] The carrier substrate 310 may include a material that is stable with respect to a baking process and an etching process. In the case where the carrier substrate 310 is subsequently separated and removed by laser ablation, the carrier substrate 310 may include a transparent substrate. Alternatively, in the case where the carrier substrate 310 is separated and removed by heating, the carrier substrate 310 may include a heat-resistant substrate. In an example embodiment, the carrier substrate 310 may include a glass substrate. In an example embodiment, the carrier substrate 310 may include a heat-resistant organic polymer material such as polyimide, poly(ether ether ketone) (PEEK), poly(ether sulfone) (PES), or poly(phenylene sulfide) (PPS), but is not limited thereto.

[0100] The release film 311 may include, for example, a laser reactive layer that reacts to laser radiation and evaporates, making the carrier substrate 310 removable. The release film 311 may include, for example, a carbon material layer. For example, the release film 311 may include an amorphous carbon layer (ACL), a hydrocarbon having a relatively high carbon content of about 85 wt% to about 99 wt% based on the total weight, or a spin-on hard mask (SOH) including derivatives thereof.

[0101] Reference Figure 8B , an external electrode pad 150 is formed on the cover layer 320. To form the external electrode pad 150, a conductive material film may be formed on the cover layer 320 and patterned. The external electrode pad 150 may be formed to have a uniform thickness on the top surface of the cover layer 320, and the bottom surface of the external electrode pad 150 in contact with the top surface of the cover layer 320 may be flat.

[0102] In example embodiments, the external electrode pad 150 may include a single metal material. In example embodiments, the external electrode pad 150 may have a multi-layer structure in which a plurality of layers respectively include different metal materials.

[0103] Reference Figure 8CAfter forming the external electrode pad 150, the first insulating layer 111 including the first via opening VO1 exposing a portion of the external electrode pad 150 is formed. For example, to form the first insulating layer 111, an insulating material film covering the external electrode pad 150 and the cover layer 320 may be formed, and a portion of the insulating material film may be removed using exposure and development to form the first via opening VO1. The portion of the external electrode pad 150 may be exposed through the first via opening VO1.

[0104] For example, to form the first via opening VO1, reactive ion etching (RIE) using plasma, laser drilling, etc. may be performed. The first via opening VO1 may have a shape in which a horizontal width decreases downward (toward the external electrode pad 150).

[0105] Reference Figure 8D ,exist Figure 8C A first seed layer 125 , a first conductive wire pattern 121 , and a first conductive via pattern 123 are formed on the resulting structure.

[0106] In detail, a seed metal film is formed on the top surface of the first insulating layer 111, the inner wall of the first insulating layer 111 provided by the first via opening VO1, and the external electrode pad 150 exposed by the first via opening VO1. For example, the seed metal film can be formed using physical vapor deposition. After the seed metal film is formed, a photoresist pattern including an opening is formed and a plating process is performed using the seed metal film as a seed to form the first wire pattern 121 and the first conductive via pattern 123. Thereafter, the photoresist pattern is removed, and the portion of the seed metal film exposed by the removal of the photoresist pattern is removed. As a result of removing the seed metal film, a first seed layer 125 can be formed between the top surface of the first insulating layer 111 and the first wire pattern 121, between the first conductive via pattern 123 and the inner wall of the first insulating layer 111 (the inner wall is provided by the first via opening VO1), and between the first conductive via pattern 123 and the external electrode pad 150. The first seed layer 125 , the first conductive wire pattern 121 , and the first conductive via pattern 123 may form a first redistribution pattern 120 .

[0107] Reference Figure 8E , can be used with reference Figure 8C and Figure 8D The process described is basically the same or similar to the process described in Figure 8DA second insulating layer 113 including a second via opening VO2, a second redistribution pattern 130, a third insulating layer 115 including a third via opening VO3, and a third redistribution pattern 140 are sequentially formed on the resulting structure. The first to third insulating layers 111, 113, and 115 and the first to third redistribution patterns 120, 130, and 140 may form a redistribution structure 101. Although Figure 8E A single redistribution structure 101 formed on the top surface of the capping layer 320 is shown, but in some embodiments, a plurality of redistribution structures 101 spaced apart from each other in a horizontal direction may be formed.

[0108] Specifically, a second seed layer 135 may be formed to cover the top surface of the second insulating layer 113, the inner wall of the second insulating layer 113 defining the second via opening VO2, and the portion of the first conductor pattern 121 exposed by the second via opening VO2. The second conductor pattern 131 may extend along the top surface of the second insulating layer 113, and the second conductive via pattern 133 may fill the second via opening VO2. The second seed layer 135, the second conductor pattern 131, and the second conductive via pattern 133 may form a second redistribution pattern 130.

[0109] A third seed layer 145 may be formed to cover the top surface of the third insulating layer 115, the inner wall of the third insulating layer 115 defining the third via opening VO3, and the portion of the second conductor pattern 131 exposed by the third via opening VO3. The third conductor pattern 141 may extend along the top surface of the third insulating layer 115, and the third conductive via pattern 143 may fill the third via opening VO3. The third seed layer 145, the third conductor pattern 141, and the third conductive via pattern 143 may form a third redistribution pattern 140.

[0110] Reference Figure 8F A first photoresist pattern 341 is formed on the first surface 118 of the redistribution insulation layer 110. The first photoresist pattern 341 may include an opening 342 exposing a portion of the third conductive line pattern 141 of the third redistribution pattern 140. The opening 342 of the first photoresist pattern 341 may define a portion where the conductive pillar 160 (in the subsequent process) is formed. Figure 8G in the area.

[0111] Reference Figure 8G and Figure 8F, a conductive pillar 160 is formed in the opening 342 of the first photoresist pattern 341. The conductive pillar 160 may be formed on a portion of the third wire pattern 141 of the third redistribution pattern 140 (the portion exposed by the opening 342 of the first photoresist pattern 341) to at least partially fill the opening 342 of the first photoresist pattern 341. The conductive pillar 160 may include Cu, but is not limited thereto.

[0112] Reference Figure 8H and Figure 8G , a polishing process may be performed on the first photoresist pattern 341 and the conductive pillar 160 until a planarized surface is obtained throughout the top surface of the first photoresist pattern 341 and the top surface of the conductive pillar 160. For example, etch-back or chemical mechanical polishing (CMP) may be performed to obtain the planarized surface. Due to the polishing process, the top surface of the first photoresist pattern 341 may be coplanar with the top surface of the conductive pillar 160. In example embodiments, when CMP is used to polish the conductive pillar 160 and the first photoresist pattern 341, CMP conditions (e.g., pressure and rotation speed of the polishing head and type of slurry) may be controlled so that the planarized surface of the conductive pillar 160 is not too rough.

[0113] Reference Figure 8I A second photoresist pattern 343 is formed on the planarized top surface of the first photoresist pattern 341. The second photoresist pattern 343 may include an opening 344 exposing the top surface of the conductive pillar 160.

[0114] For example, the opening 344 of the second photoresist pattern 343 may have the same horizontal width as the horizontal width of the top surface of the conductive pillar 160 and may completely expose the top surface of the conductive pillar 160. In example embodiments, the opening 344 of the second photoresist pattern 343 may have a horizontal width different from the horizontal width of the top surface of the conductive pillar 160.

[0115] Reference Figure 8J and Figure 8I , a sacrificial layer 345 is formed in the opening 344 of the second photoresist pattern 343. The sacrificial layer 345 may cover the top surface of the conductive pillar 160 exposed by the opening 344 of the second photoresist pattern 343. In example embodiments, the sacrificial layer 345 may include an organic film, such as an organic solderability preservative (OSP), but is not limited thereto. For example, the sacrificial layer 345 may include an insulating material. For example, the sacrificial layer 345 may include at least one selected from silicon oxide, silicon nitride, and silicon carbide.

[0116] For example, when the opening 344 of the second photoresist pattern 343 has the same horizontal width as the top surface of the conductive pillar 160 , the sacrificial layer 345 may have the same horizontal width as the top surface of the conductive pillar 160 .

[0117] Reference Figure 8K and Figure 8J , the first photoresist pattern 341 and the second photoresist pattern 343 are removed. For example, the first photoresist pattern 341 and the second photoresist pattern 343 may be removed using a stripping process.

[0118] Reference Figure 8L , the semiconductor chip 200 is attached to the redistribution structure 101. The semiconductor chip 200 may be attached to the redistribution structure 101 such that the chip pad 220 faces the redistribution structure 101. The chip pad 220 of the semiconductor chip 200 may be connected to the third wire pattern 141 of the third redistribution pattern 140 through the chip connector 230.

[0119] After the semiconductor chip 200 is attached to the redistribution structure 101, an underfill material layer 240 is formed to fill the space between the semiconductor chip 200 and the redistribution structure 101. The underfill material layer 240 may surround the chip connector 230. For example, after the semiconductor chip 200 is attached to the redistribution structure 101, the underfill material layer 240 may be formed using a capillary underfill process. In an example embodiment, the underfill material layer 240 may be formed by attaching a non-conductive film to the chip pad 220 of the semiconductor chip 200 and attaching the semiconductor chip 200 to the redistribution structure 101.

[0120] Reference Figure 8M After forming the underfill material layer 240, a mold layer 250 is formed to mold the semiconductor chip 200. The mold layer 250 may cover the semiconductor chip 200, the conductive pillars 160, and the sacrificial layer 345. The mold layer 250 may cover the side and top surfaces of the semiconductor chip 200 and the side and top surfaces of the sacrificial layer 345.

[0121] Reference Figure 8N and Figure 8M , a polishing process, for example, CMP, may be performed on the mold layer 250 and the sacrificial layer 345 so that a planarized surface is obtained over the top surface of the sacrificial layer 345. As a result of the polishing process, the top surface of the sacrificial layer 345 may be exposed and may be coplanar with the top surface of the mold layer 250. In example embodiments, in order to grind the mold layer 250 having relatively high rigidity using CMP, the CMP may be performed under relatively high pressure and rotation speed of the polishing head.

[0122] The polishing process may be performed to expose the sacrificial layer 345. For example, the polishing process may be performed to remove a portion of the sacrificial layer 345 but not another portion of the sacrificial layer 345 so that the top surface of the conductive pillar 160 is not exposed.

[0123] In example embodiments, a polishing process may be performed to expose the top surface of the semiconductor chip 200. In this case, the top surface of the semiconductor chip 200, the top surface of the mold layer 250, and the top surface of the sacrificial layer 345 may be coplanar with each other. In example embodiments, a polishing process may be performed to remove a portion of the mold layer 250 so that the top surface of the sacrificial layer 345 is exposed and the top surface of the semiconductor chip 200 is not exposed.

[0124] Reference Figure 8O and Figure 8N , the sacrificial layer 345 may be removed to expose the top surface of the conductive pillar 160. As a result of removing the sacrificial layer 345, an opening exposing the conductive pillar 160 may be formed in the mold layer 250. For example, the sacrificial layer 345 may be removed using wet cleaning.

[0125] Since the sacrificial layer 345 is removed, the exposed top surface of the conductive pillar 160 is at a level lower than that of the top surface of the mold layer 250. The top surface of the conductive pillar 160 may have a roughness less than that of the top surface of the mold layer 250 that has undergone the polishing process.

[0126] Reference Figure 8P , a first upper insulating layer 411 is formed on the semiconductor chip 200 and the mold layer 250. To form the first upper insulating layer 411, an insulating material film may be formed to cover the top surface of the mold layer 250 and the top surface of the semiconductor chip 200 and to fill the recess 257 of the mold layer 250 (see FIG. Figure 2 ), and then the insulating material film may be partially removed by performing exposure and development, so that a via opening exposing a portion of the top surface of the conductive pillar 160 may be formed.

[0127] To form the via opening of the first upper insulating layer 411 , for example, RIE or laser drilling may be performed The via opening of the first upper insulating layer 411 may have a shape in which a horizontal width decreases toward a top surface of the conductive pillar 160 .

[0128] After forming the first upper insulating layer 411, a first upper redistribution pattern 420 is formed. In detail, a seed metal film is formed on the top surface of the first upper insulating layer 411, the inner wall of the first upper insulating layer 411 defining the via opening of the first upper insulating layer 411, and the portion of the top surface of the conductive pillar 160 exposed by the via opening of the first upper insulating layer 411. For example, the seed metal film can be formed using physical vapor deposition. After forming the seed metal film, a first upper conductor pattern 421 and a first upper conductive via pattern 423 are formed by forming a photoresist pattern including an opening and performing a plating process using the seed metal film as a seed. Thereafter, the photoresist pattern is removed, and the portion of the seed metal film exposed by the removal of the photoresist pattern is removed. As a result of removing the seed metal film, a first upper seed layer 425 can be formed between the top surface of the first upper insulating layer 411 and the first upper conductor pattern 421, between the first upper conductive via pattern 423 and the inner wall of the first upper insulating layer 411, and between the first upper conductive via pattern 423 and the conductive pillar 160.

[0129] After forming the first upper redistribution pattern 420, the second upper insulating layer 413 may be formed using a process substantially the same as or similar to the process used to form the first upper insulating layer 411, and the second upper redistribution pattern 430 may be formed using a process substantially the same as or similar to the process used to form the first upper redistribution pattern 420. The first upper insulating layer 411, the first upper redistribution pattern 420, the second upper insulating layer 413, and the second upper redistribution pattern 430 may form an upper redistribution structure 401.

[0130] Reference Figure 8Q , the upper semiconductor chip 500 is attached to the upper redistribution structure 401. The upper semiconductor chip 500 may be attached to the upper redistribution structure 401 such that the chip pad 520 faces the upper redistribution structure 401. The chip pad 520 of the upper semiconductor chip 500 may be connected to the second upper conductive wire pattern 431 of the second upper redistribution pattern 430 through a chip connector 530.

[0131] After attaching the upper semiconductor chip 500 to the upper redistribution structure 401 , an underfill material layer 540 is formed to fill the space between the upper semiconductor chip 500 and the upper redistribution structure 401 and to surround the chip connectors 530 .

[0132] After forming the underfill material layer 540 , an upper mold layer 550 is formed to mold the upper semiconductor chip 500 . The upper mold layer 550 may cover side surfaces of the upper semiconductor chip 500 .

[0133] Reference Figure 8R and Figure 8QAfter forming the upper molding layer 550, the carrier substrate 310 is removed. For example, the carrier substrate 310 with the release film 311 attached thereto is removed. Figure 8Q For example, in order to separate the carrier substrate 310 , a laser beam or heat may be irradiated to the release film 311 .

[0134] After separating the carrier substrate 310, the cover layer 320 is removed so that the external electrode pads 150 are exposed. For example, the cover layer 320 may be removed using an etching process.

[0135] After removing the cover layer 320, the external connector 190 may be attached. The external connector 190 may include, for example, solder balls or bumps.

[0136] Reference Figure 8S After forming the external connector 190, the singulation process can be performed to complete Figure 4 The semiconductor package 10b is cut along the scribe line SL in the singulation process. Figure 8R The resulting structure.

[0137] If the conductive pillars are exposed by a CMP process (during which the conductive pillars and the mold layer are ground together), the conductive pillars may be sheared or may be contaminated due to CMP residues. However, according to an embodiment of the inventive concept, the conductive pillars 160 are protected by the sacrificial layer 345 (in the CMP process) during the CMP process. Figure 8J Therefore, damage to the conductive pillars 160 and contamination by CMP residues can be reduced or prevented, and the reliability of the semiconductor package can be improved.

[0138] In addition, since the top surface of the conductive pillar 160 is at a level lower than that of the top surface of the mold layer 250, the conductive pillar 160 can be used as an alignment key, and thus, when forming the first upper redistribution pattern 420 (in Figure 8P The accuracy of alignment key recognition is improved when forming the first upper redistribution pattern 420. Furthermore, the conductive pillars 160 are protected by the sacrificial layer 345 and are therefore not deformed during CMP and are used as alignment keys. Therefore, the accuracy of alignment key recognition can be improved when forming the first upper redistribution pattern 420. Since the accuracy of alignment key recognition is improved when forming the first upper redistribution pattern 420 using the conductive pillars 160 as alignment keys, the electrical characteristics of the semiconductor package are not degraded due to misalignment.

[0139] While the inventive concept has been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the inventive concept. Therefore, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims

1. A semiconductor package, comprising: Semiconductor chips, including chip pads; a lower redistribution structure located on the semiconductor chip, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to a chip pad of the semiconductor chip, and the lower redistribution insulating layer including a top surface facing the semiconductor chip; a molding layer extending on a side of the semiconductor chip and including a bottom surface facing the lower redistribution structure and a top surface opposite to the bottom surface of the molding layer; as well as a conductive pillar located in the mold layer, the conductive pillar comprising a bottom surface contacting the lower redistribution pattern and a top surface opposite to the bottom surface of the conductive pillar, wherein the top surface of the conductive pillar is spaced apart from the top surface of the lower redistribution insulation layer by a first distance, and the top surface of the mold layer is spaced apart from the top surface of the lower redistribution insulation layer by a second distance greater than the first distance, and The roughness of the top surface of the molding layer is greater than the roughness of the top surface of the conductive pillar.

2. The semiconductor package according to claim 1, wherein A side surface of the molding layer includes an upper portion defining a recess above a top surface of the conductive pillar, and The upper portion of the side surface of the mold layer has a roughness smaller than a roughness of a top surface of the mold layer.

3. The semiconductor package according to claim 2, wherein The width of the recess of the molding layer in the horizontal direction is equal to the width of the top surface of the conductive pillar in the horizontal direction.

4. The semiconductor package according to claim 1, wherein An arithmetic mean roughness of a top surface of the mold layer is two to eight times greater than an arithmetic mean roughness of a top surface of the conductive pillar.

5. The semiconductor package according to claim 1, wherein The semiconductor chip includes a bottom surface facing the lower redistribution insulating layer, and a chip pad of the semiconductor chip is located on the bottom surface of the semiconductor chip, and A bottom surface of the conductive pillar faces a top surface of the lower redistribution insulation layer.

6. The semiconductor package according to claim 5, further comprising: a chip connector located between a chip pad of the semiconductor chip and a portion of the lower redistribution pattern extending on a top surface of the lower redistribution insulating layer; as well as An underfill material layer, wherein the chip connector is located in the underfill material layer.

7. The semiconductor package according to claim 1, wherein The semiconductor chip includes a bottom surface facing the lower redistribution insulating layer and a top surface opposite to the bottom surface of the semiconductor chip, and The top surface of the molding layer is coplanar with the top surface of the semiconductor chip.

8. The semiconductor package according to claim 1, wherein The semiconductor chip includes a bottom surface facing the lower redistribution insulating layer, and The molding layer extends over the top surface of the semiconductor chip.

9. The semiconductor package according to claim 1, further comprising an upper redistribution structure located on the molding layer and the semiconductor chip. in, The upper redistribution structure includes: an upper redistribution insulating layer extending over a top surface of the mold layer, a top surface of the conductive pillar, and an upper portion of a side surface of the mold layer, the upper portion of the side surface of the mold layer extending from the top surface of the mold layer to the top surface of the conductive pillar; and The upper redistribution pattern includes a portion located in the upper redistribution insulation layer and contacting a top surface of the conductive pillar.

10. The semiconductor package according to claim 1, wherein The side surface of the mold layer includes an upper portion not covered by the conductive pillar, and the upper portion of the side surface of the mold layer and the top surface of the conductive pillar define a recess, and The semiconductor package further includes a connector located on the top surface of the conductive pillar, wherein the connector extends on the upper portion of the side surface of the molding layer.

11. The semiconductor package according to claim 1, wherein A distance between a top surface of the conductive pillar and a top surface of the mold layer is 1 μm to 100 μm.

12. A semiconductor package, comprising: a lower redistribution structure comprising a lower redistribution insulating layer and a lower redistribution pattern; a lower semiconductor chip positioned on the lower redistribution insulating layer and electrically connected to the lower redistribution pattern; a conductive pillar located on the lower redistribution insulating layer and electrically connected to the lower redistribution pattern, the lower redistribution insulating layer including a top surface facing the lower semiconductor chip and the conductive pillar, and the conductive pillar including a bottom surface facing the lower redistribution structure and a top surface opposite to the bottom surface of the conductive pillar; a molding layer extending on side surfaces of the lower semiconductor chip and side surfaces of the conductive pillars and including a bottom surface facing the lower redistribution structure and a top surface opposite to the bottom surface of the molding layer, wherein the top surface of the conductive pillars is spaced apart from a top surface of the lower redistribution insulation layer by a first distance, and the top surface of the molding layer is spaced apart from a top surface of the lower redistribution insulation layer by a second distance greater than the first distance; and an upper redistribution structure located on the molding layer and the lower semiconductor chip, the upper redistribution structure comprising an upper redistribution insulating layer and an upper redistribution pattern, the upper redistribution insulating layer extending on a top surface of the conductive pillar, and the upper redistribution pattern extending through a portion of the upper redistribution insulating layer and contacting the conductive pillar, The roughness of the top surface of the molding layer is greater than the roughness of the top surface of the conductive pillar.

13. The semiconductor package according to claim 12, wherein The side surface of the mold layer includes an upper portion not covered by the conductive pillar, and the upper portion of the side surface of the mold layer and the top surface of the conductive pillar define a recess, and The upper redistribution insulating layer extends on the upper portion of the side surface of the mold layer. 14 . The semiconductor package of claim 12 , further comprising an upper semiconductor chip on the upper redistribution structure and electrically connected to the conductive pillars through the upper redistribution pattern.

15. The semiconductor package according to claim 12, wherein The lower redistribution insulation layer includes multiple insulation layers, a lower redistribution pattern including a plurality of wire patterns and a plurality of conductive via patterns respectively located on the plurality of insulating layers, each of the plurality of conductive via patterns extending through a corresponding one of the plurality of insulating layers and electrically connected to a corresponding one of the plurality of wire patterns, and Each of the plurality of conductive via patterns has a width that decreases as a distance from a lower semiconductor chip increases.

16. The semiconductor package according to claim 12, wherein The upper redistribution pattern includes an upper conductive via pattern located in the upper redistribution insulation layer and contacting the top surface of the conductive pillar, and The upper conductive via pattern has a width that increases with increasing distance from a top surface of the conductive pillar.

17. The semiconductor package according to claim 16, wherein The upper redistribution pattern further includes an upper seed layer extending on side surfaces of the upper conductive via pattern and between the upper conductive via pattern and top surfaces of the conductive pillars.

18. A semiconductor package, comprising: a lower package comprising a lower semiconductor chip, a mold layer extending on a side surface of the lower semiconductor chip, conductive pillars in the mold layer, and a lower redistribution pattern electrically connecting the lower semiconductor chip to the conductive pillars; an upper package located on the lower package, the upper package including an upper semiconductor chip, wherein the conductive pillar includes a top surface facing the upper package; and The inter-package connector is located between the lower package and the upper package, and the inter-package connector contacts the top surface of the conductive pillar. wherein the mold layer includes a top surface facing the upper package, and the top surface of the conductive pillar is recessed relative to the top surface of the mold layer toward the lower redistribution pattern, and The roughness of the top surface of the mold layer is greater than the roughness of the top surface of the conductive pillar.

19. The semiconductor package according to claim 18, wherein The side surface of the mold layer includes an upper portion not covered by the conductive pillar, and the upper portion of the side surface of the mold layer and the top surface of the conductive pillar define a recess, and The inter-package connector extends on the upper portion of the side surface of the molding layer.

20. The semiconductor package according to claim 18, wherein The molding layer includes an epoxy molding compound, and The conductive pillars include copper.

21. A method for manufacturing a semiconductor package, the method comprising: forming a lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern; forming a conductive pillar on a portion of the lower redistribution pattern, the conductive pillar including a bottom surface facing the lower redistribution structure and a top surface opposite to the bottom surface of the conductive pillar; forming a sacrificial layer on a top surface of the conductive pillar; disposing a semiconductor chip on the lower redistribution structure; forming a molding layer on the semiconductor chip, the conductive pillars, and the sacrificial layer; removing a portion of the mold layer and exposing the sacrificial layer by performing a polishing process; as well as by removing the sacrificial layer to expose the top surface of the conductive pillar, The roughness of the top surface of the molding layer is greater than the roughness of the top surface of the conductive pillar.

22. The method according to claim 21, further comprising forming an upper redistribution structure on the semiconductor chip and the molding layer, in, The steps of forming the upper redistribution structure include: forming an upper insulating layer extending on a top surface of the mold layer and a top surface of the conductive pillar and including a via opening exposing a portion of the top surface of the conductive pillar; and An upper conductive line pattern and an upper conductive via pattern are formed, wherein the upper conductive line pattern extends on a top surface of the upper insulating layer, and the upper conductive via pattern is located in the via opening and connected to a top surface of the conductive pillar.

23. The method according to claim 22, further comprising forming an upper seed layer on the top surface of the upper insulating layer, on the inner side surface of the upper insulating layer, and on the portion of the top surface of the conductive pillar, wherein The inner side surface of the upper insulating layer defines a via opening of the upper insulating layer, and The upper conductive line pattern and the upper conductive via pattern are integrally formed using a single plating process.

24. The method according to claim 21, wherein The sacrificial layer has a first width in a horizontal direction, the conductive pillar has a second width in the horizontal direction, and the second width is equal to the first width.

25. The method according to claim 21, wherein The sacrificial layer includes an organic solderability preservative.

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