Semiconductor substrate and method for manufacturing the same

Abstract

The present invention provides a semiconductor substrate and a manufacturing method thereof, the semiconductor substrate comprising: a first dielectric layer having a first through hole in the first dielectric layer; a first electroplating layer having a first channel layer in the first through hole and a first pad layer extending from the first channel layer to the upper surface of the first dielectric layer; wherein the ratio between the thickness of the first pad layer and the opening width of the first through hole is greater than or equal to 1. The technical solution of the present invention can at least avoid the problem of depression of the electroplated surface of the through hole.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more specifically, to a semiconductor substrate and a method for manufacturing the semiconductor substrate. Background Art

[0002] In semiconductor substrate design, for example, when the thickness of the dielectric layer is thicker (insulated), the degree of depression 14 (dimple) of the electroplated surface of the through hole (via, also called blind hole) 12 will increase, such as Figure 1A As shown. Due to the concave electroplating surface, the laser 20 is scattered when shooting the concave surface 14 during the laser drilling process, resulting in the erosion of the side wall 18 of the upper through hole 16, and the hole opening is abnormal, and the through hole opening produces a hole break 30, as shown. Figure 1B Therefore, the bottleneck currently encountered is that hole breakage will occur at the position where the through-holes are stacked, which will greatly reduce the electrical properties of the through-holes and have an impact on the yield of about 50-60%.

[0003] In the current technology, the depression caused by the basic characteristics of the electroplating solution during through-hole electroplating is unavoidable unless a newer type of electroplating solution is used. If a newer electroplating solution is used, there are concerns about cost and reliability, and the demand cannot be met in a timely manner. In addition, although the depressed surface can be flattened by grinding, the uneven surface of the substrate itself will cause the total thickness variation (TTV) to increase after grinding. Although the depression condition can also be improved by increasing the electroplating current density, this requires a higher cost. Summary of the invention

[0004] In view of the above problems in the related art, the present invention provides a semiconductor substrate and a method for manufacturing the semiconductor substrate, which can at least avoid the problem of depression on the electroplated surface of the through hole.

[0005] An embodiment of the present invention provides a semiconductor substrate, comprising: a first dielectric layer having a first through hole in the first dielectric layer; a first electroplating layer having a first channel layer in the first through hole and a first pad layer extending from the first channel layer to an upper surface of the first dielectric layer, wherein the ratio between the thickness of the first pad layer and the opening width of the first through hole is greater than or equal to 1.

[0006] According to an embodiment of the present invention, the semiconductor substrate further comprises: a second dielectric layer, located on the first dielectric layer, and having a second through hole located in the second dielectric layer and above the first through hole; a second electroplating layer, having a second channel layer located in the second through hole and a second pad layer extending from the second channel layer to the upper surface of the second dielectric layer, wherein the thickness of the second pad layer is greater than the thickness of the first pad layer.

[0007] According to an embodiment of the present invention, the semiconductor substrate further comprises a second dielectric layer, the second dielectric layer is located on the first dielectric layer and has a second through hole located in the second dielectric layer and above the first through hole, wherein the opening width of the second through hole is greater than the opening width of the first through hole.

[0008] According to an embodiment of the present invention, a ratio between an opening width of the second through hole and an opening width of the first through hole is 1.25.

[0009] According to an embodiment of the present invention, the opening width of the first through hole is greater than 20 μm, the sidewall of the second through hole is laterally offset compared to the sidewall of the first through hole, and the distance of the lateral offset is greater than or equal to 2.5 μm.

[0010] According to an embodiment of the present invention, the second through hole has an inclined side wall, wherein the inclination degree of the side wall is the same at each circumferential position of the second through hole.

[0011] According to an embodiment of the present invention, the semiconductor substrate further comprises a third dielectric layer, the third dielectric layer is located on the second dielectric layer and has a third through hole located in the third dielectric layer and above the second through hole, wherein the opening width of the third through hole is greater than the opening width of the second through hole.

[0012] According to an embodiment of the present invention, the opening width of the first through hole is less than 20 μm, and the thickness of the first pad layer is in the range of 7 μm to 10 μm.

[0013] According to an embodiment of the present invention, an upper surface of the first channel layer of the first electroplating layer is flush with an upper surface of the first pad layer and is flat.

[0014] According to an embodiment of the present invention, the semiconductor substrate is an antenna substrate, and the first electroplating layer is electrically connected to an antenna in the antenna substrate.

[0015] An embodiment of the present invention provides a method for manufacturing a semiconductor substrate, comprising: providing a first dielectric layer; forming a first through hole in the first dielectric layer; electroplating a first electroplating layer above the first through hole, the first electroplating layer having a first channel layer located in the first through hole and a first pad layer extending from the first channel layer to the upper surface of the first dielectric layer. The ratio between the thickness of the first pad layer and the opening width of the first through hole is greater than or equal to 1.

[0016] According to an embodiment of the present invention, the method also includes: forming a second dielectric layer on the first dielectric layer; forming a second through hole in the second dielectric layer and above the first through hole using laser shooting; electroplating a second electroplating layer above the second through hole, the second electroplating layer having a second channel layer located in the second through hole and extending from the second channel layer to a second pad layer located on the upper surface of the second dielectric layer, wherein the thickness of the second pad layer is greater than the thickness of the first pad layer.

[0017] According to an embodiment of the present invention, the method also includes: forming a second dielectric layer on the first dielectric layer; using laser shooting to form a second through hole in the second dielectric layer and above the first through hole, wherein the opening width of the second through hole is greater than the opening width of the first through hole, and the laser of the laser shooting is limited to the range of the second through hole.

[0018] According to an embodiment of the present invention, a ratio between an opening width of the second through hole and an opening width of the first through hole is 1.25.

[0019] According to an embodiment of the present invention, the opening width of the first through hole is greater than 20 μm, the sidewall of the second through hole is laterally offset compared to the sidewall of the first through hole, and the distance of the lateral offset is greater than or equal to 2.5 μm.

[0020] According to an embodiment of the present invention, the second through hole has an inclined side wall, wherein the inclination degree of the side wall is the same at each circumferential position of the first through hole.

[0021] According to an embodiment of the present invention, the method further includes: forming a third dielectric layer on the second dielectric layer; forming a third through hole in the third dielectric layer and above the second through hole, wherein an opening width of the third through hole is greater than an opening width of the second through hole.

[0022] According to an embodiment of the present invention, the opening width of the first through hole is less than 20 μm, and the thickness of the first pad layer is in the range of 7 μm to 10 μm.

[0023] According to an embodiment of the present invention, an upper surface of the first channel layer of the first electroplating layer is flush with an upper surface of the first pad layer and is flat.

[0024] According to an embodiment of the present invention, the semiconductor substrate is an antenna substrate, and the first electroplating layer is electrically connected to an antenna in the antenna substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0026] Figure 1A and Figure 1B It is a schematic diagram of the problems of depression and hole breakage in forming through holes in the prior art.

[0027] Figure 2A and Figure 2B is a schematic diagram of a semiconductor substrate according to an embodiment of the present invention.

[0028] Figure 34 is a graph showing how the thickness of the pad layer and the electroplating layer vary with the opening width of the through hole according to an embodiment of the present invention.

[0029] Figure 4 is a schematic diagram of a semiconductor substrate according to an embodiment of the present invention.

[0030] Figure 5 is a flow chart of a method for manufacturing a semiconductor substrate according to an embodiment of the present invention.

[0031] Figure 6 is a schematic diagram of a semiconductor substrate according to an embodiment of the present invention.

[0032] Figure 7 yes Figure 6 Schematic diagram of laser shooting of an embodiment.

[0033] Figure 8 is a flow chart of a method for manufacturing a semiconductor substrate according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The following disclosure provides many different embodiments or examples for realizing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. Moreover, the present invention may repeatedly refer to numbers and / or letters in various examples. This repetition is only for simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0035] According to an embodiment of the present invention, a semiconductor substrate having a through hole formed therein is provided. Figure 2A 1 is a schematic diagram of a semiconductor substrate 100 according to an embodiment of the present invention. Figure 2AAs shown, the semiconductor substrate 100 includes a first dielectric layer 102, and the first through hole 104 is located in the first dielectric layer 102. The semiconductor substrate 100 also includes a first electroplating layer 106 formed above the first through hole 104, the first electroplating layer 106 has a first channel layer 108 and a first pad layer 109, the first channel layer 108 is located in the first through hole 104, and the first pad layer 109 extends from the first channel layer 108 to the upper surface of the first dielectric layer 102. The first electroplating layer 106 can be formed of a conductive metal material. The first pad layer 109 has a thickness y1, and the first through hole 104 has an opening width x. In the prior art, for example, due to the basic characteristics of the electroplating solution, the surface of the first electroplating will be concave. The present invention flattens the concave by increasing the thickness of the first pad layer 109, thereby solving the hole breakage problem caused by the surface concave. In some embodiments, the ratio between the thickness y1 of the first pad layer and the opening width x of the first through hole is greater than or equal to 1, that is, the thickness y1 of the first pad layer 109 is greater than or equal to 1: the opening width x of the first through hole 104. Due to the increase in the thickness of the first pad layer 109, the upper surface of the first channel layer 108 of the formed first electroplating layer 106 and the upper surface of the first pad layer 109 may be flat and flush with each other.

[0036] The thickness of the first pad layer 109 can be increased by increasing the time of the first electroplating layer forming process. The first pad layer 109 with increased thickness can also be formed through multiple process stages. Figure 2B As shown, a first portion 1061 of the first electroplating layer 106 can be formed in a first process stage. After the first process stage, a second portion 1062 of the first electroplating layer 106 is formed above the first portion 1061. Then similarly, a third portion 1063 and a fourth portion 1064 are stacked and formed above the second portion 1062 in a third and fourth process stages, respectively. Each of the first portion 1061 to the fourth portion 1064 has a channel layer located in the first through hole 104 and a pad layer extending from the channel layer to the upper surface of the first dielectric layer 102. Thus, a first pad layer 109 with an increased thickness can be formed, and a first electroplating layer 106 with a flat upper surface is obtained.

[0037] The semiconductor substrate 100 may be any type of semiconductor substrate. In some embodiments, the semiconductor substrate 100 may be an antenna substrate, and in such embodiments, the first electroplating layer 106 is electrically connected to an antenna in the antenna substrate.

[0038] Figure 3 1 is a graph showing the thickness of the first pad layer and the first electroplating layer respectively changing with the opening width of the first through hole according to an embodiment of the present invention. Wherein, y1 represents the thickness of the first pad layer 109, and y2 represents the total thickness of the first electroplating layer 106 ( Figure 2B), x represents the opening width of the first through hole 104. In some embodiments, the opening width of the first through hole can be less than 20 μm. The thickness of the dielectric layer can be about 10 μm. The thickness of the first pad layer can be in the range of 7 μm to 10 μm. In other embodiments, the thickness of the first pad layer 109 can also be configured by other appropriate methods, and the present invention is not limited thereto.

[0039] Figure 4 Schematic diagram of a semiconductor substrate according to an embodiment of the present invention. Figure 4 As shown, the semiconductor substrate 200 may include a second dielectric layer 202 located on the first dielectric layer 102. The second dielectric layer 202 has a second through hole 204 located above the first through hole 104. The second electroplating layer 206 is located above the second through hole 204. The second electroplating layer 206 has a second channel layer 208 and a second pad layer 209, the second channel layer 208 is located in the second through hole 204, and the second pad layer 209 extends from the second channel layer 208 to the upper surface of the second dielectric layer 202. As described above, due to the large thickness of the first pad layer 109, the upper surface of the first electroplating layer 106 is flat. Thereby, the second through hole 204 stacked above the first through hole 104 will not cause a hole breakage problem. In this embodiment, the thickness of the second pad layer 209 can be greater than the thickness of the first pad layer 109.

[0040] In addition, the through hole and electroplated conductive structure (e.g., the first through hole 104, the second through hole 204, the first electroplating layer 106, and the second electroplating layer 206) provided by the present invention have no changes in other aspects of the structure (e.g., the pad layer) except that the thickness of the first pad layer 109 is increased. In some embodiments, the opening width of the first through hole 104 is equal to the opening width of the second through hole 204. In some embodiments, the opening width of any one of the first through hole 104 and the second through hole 204 may be less than 20 μm.

[0041] Figure 5 1 is a flow chart of a method for manufacturing a semiconductor substrate according to an embodiment of the present invention. Figure 5 As shown, in step S502, a first dielectric layer is provided and a first through hole is formed in the first dielectric layer.

[0042] At step S504, a first electroplating layer is electroplated over the first through hole. The first electroplating layer has a first channel layer located in the first through hole and a first pad layer extending from the first channel layer to the upper surface of the first dielectric layer. The ratio between the thickness of the first pad layer and the opening width of the first through hole is formed to be greater than or equal to 1.

[0043] Then, at step S506, a second dielectric layer may be formed on the first dielectric layer, and a second through hole may be formed in the second dielectric layer and above the first through hole by laser shooting.

[0044] At step S508, a second electroplating layer is electroplated above the second through hole. The second electroplating layer has a second channel layer located in the second through hole and a second pad layer extending from the second channel layer to the upper surface of the second dielectric layer. The thickness of the second pad layer is greater than the thickness of the first pad layer.

[0045] Figure 6 is a schematic diagram of a semiconductor substrate according to another embodiment of the present invention. Figure 6 As shown, the semiconductor substrate 600 includes a first dielectric layer 602 and a first through hole 604 located in the first dielectric layer 602. The first through hole 604 may be similar to Figure 2A The semiconductor substrate 600 further includes a second dielectric layer 612 located on the first dielectric layer 602, and the second dielectric layer 612 has a second through hole 614 located in the second dielectric layer 612 and above the first through hole 602. In the present embodiment, the opening width x2 of the second through hole 614 is greater than the opening width x1 of the first through hole 604, so the sidewall of the second through hole 614 is laterally offset compared to the sidewall of the first through hole 604.

[0046] In some embodiments, the ratio of the opening width x2 of the second through hole 614 to the opening width x1 of the first through hole 604 is 1.25. In some embodiments, the opening width x1 of the first through hole 604 may be greater than 20 μm, in which case the sidewall of the second through hole 614 may be laterally offset from the sidewall of the first through hole 604 by a distance greater than or equal to 2.5 μm.

[0047] In the existing semiconductor substrate design, the through-hole size in each dielectric layer is the same, so the depression generated during the electroplating of the through-hole will cause the laser reflection to cause the hole to break (such as Figure 1A and Figure 1B ), affecting the process yield. The present invention configures the opening width x2 of the second through hole 614 to be larger than the opening width x1 of the first through hole 604, that is, adopts a design in which the opening width of the through hole is expanded layer by layer, so that during the formation of the second through hole 604, the position of the laser reflection caused by the laser 20 shooting at the recessed part still falls within the opening area of ​​the second through hole 604 above, so that the hole breakage problem caused by the recess can be avoided. Figure 7 shown.

[0048] exist Figure 6 In the illustrated embodiment, the semiconductor substrate 600 has a plurality of stacked through holes. Figure 64 stacked through holes are shown in FIG. 1 , but the present invention is not limited thereto, and the number of through holes can be other numbers. Figure 6 , the semiconductor substrate 600 further includes a third dielectric layer 622 located on the second dielectric layer 612, and the third dielectric layer 622 includes a third through hole 624 located above the second through hole 614. The opening width x3 of the third through hole 624 is also greater than the opening width x2 of the second through hole 614. The fourth dielectric layer 632 is located on the third dielectric layer 622, and the fourth dielectric layer 632 includes a fourth through hole 634 located above the third through hole 624. The opening width x4 of the fourth through hole 634 is also greater than the opening width x3 of the third through hole 624. As described above, the opening widths x1 to x4 of the first through hole 604 to the fourth through hole 634 are increased and expanded layer by layer, which can avoid the problem of broken holes caused by depressions.

[0049] Figure 8 1 is a flow chart of a method for manufacturing a semiconductor substrate according to an embodiment of the present invention. Figure 8 As shown, in step S802, a first dielectric layer is provided and a first through hole is formed in the first dielectric layer.

[0050] At step S804, a first electroplating layer is electroplated over the first through hole. The first electroplating layer has a first channel layer located in the first through hole and a first pad layer extending from the first channel layer to the upper surface of the first dielectric layer. The ratio between the thickness of the first pad layer and the opening width of the first through hole is formed to be greater than or equal to 1.

[0051] Then, at step S806, a second dielectric layer is formed on the first dielectric layer, and a second through hole is formed in the second dielectric layer and above the first through hole by laser shooting. The opening width of the second through hole is greater than the opening width of the first through hole, and the laser of the laser shooting is limited to the range of the second through hole.

[0052] As mentioned above, due to the depressions produced during through-hole electroplating, laser reflection may cause hole breakage (such as Figure 1A and Figure 1B ), affecting the process yield. The present invention configures the opening width of the second through hole to be larger than the opening width of the first through hole, that is, the opening width of the through hole is designed to expand outward layer by layer, so that during the formation of the second through hole, the position of the laser reflection caused by the depression still falls within the opening area of ​​the second through hole above, so the problem of broken holes caused by the depression can be avoided.

[0053] Then, after step S806, a third dielectric layer may be formed on the second dielectric layer, and a third through hole may be formed in the third dielectric layer and above the second through hole. The opening width of the third through hole is greater than the opening width of the second through hole.

[0054] In summary, the present invention utilizes the method of increasing the thickness of the pad layer to level the depression of the electroplating layer, thereby avoiding the hole breakage problem caused by the depression. The present invention also increases the opening width of the through hole layer by layer, thereby avoiding the hole breakage problem of the through hole. The present invention can solve the hole breakage problem of the substrate, reduce the yield loss by 50-60%, and make the qualified rate of the semiconductor substrate greater than 90%.

[0055] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that the present invention can be easily used as a basis to design or change other processing and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced in the present invention. Those skilled in the art should also be aware that these equivalent structures do not deviate from the spirit and scope of the present invention, and can be subjected to various changes, substitutions and changes without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor substrate, characterized in that: include: a first dielectric layer having a first through hole located in the first dielectric layer; a first electroplating layer, comprising a first channel layer located in the first through hole and a first pad layer extending from the first channel layer to the upper surface of the first dielectric layer, wherein a ratio between a thickness of the first pad layer and an opening width of the first through hole is greater than or equal to 1; A second dielectric layer, located on the first dielectric layer, and having a second through hole located in the second dielectric layer and above the first through hole, wherein an opening width of the second through hole is greater than an opening width of the first through hole, and a top surface of the first pad layer located below the second through hole has a depression; The second electroplating layer has a second channel layer located in the second through hole and two pad layers extending from the second channel layer to the upper surface of the second dielectric layer, and the second channel layer fills the recess of the first pad layer below.

2. The semiconductor substrate according to claim 1, wherein: The ratio of the opening width of the second through hole to the opening width of the first through hole is 1.

25.

3. The semiconductor substrate according to claim 1, wherein: The opening width of the first through hole is less than 20 μm, and the thickness of the first pad layer is in a range of 7 μm to 10 μm.

4. The semiconductor substrate according to claim 1, wherein: The semiconductor substrate is an antenna substrate, and the first electroplating layer is electrically connected to an antenna in the antenna substrate.

5. A method for manufacturing a semiconductor substrate, characterized in that: include: providing a first dielectric layer; forming a first through hole in the first dielectric layer; Electroplating a first electroplating layer above the first through hole, the first electroplating layer having a first channel layer located in the first through hole and a first pad layer extending from the first channel layer to the upper surface of the first dielectric layer, wherein the top surface of the first pad layer has a recess, and a ratio between a thickness of the first pad layer and an opening width of the first through hole is greater than or equal to 1; forming a second dielectric layer on the first dielectric layer; Using laser shooting to form a second through hole exposing the recess of the first pad layer in the second dielectric layer and above the first through hole, wherein the opening width of the second through hole is greater than the opening width of the first through hole, and the laser of the laser shooting is limited to the range of the second through hole; A second electroplating layer is electroplated over the second through hole, wherein the second electroplating layer has a second channel layer located in the second through hole and a second pad layer extending from the second channel layer to the upper surface of the second dielectric layer, and the second channel layer fills the recess of the first pad layer below.

6. The method for manufacturing a semiconductor substrate according to claim 5, wherein: The thickness of the second pad layer is greater than the thickness of the first pad layer.

7. The method for manufacturing a semiconductor substrate according to claim 5, wherein: The ratio of the opening width of the second through hole to the opening width of the first through hole is 1.

25.

8. The method for manufacturing a semiconductor substrate according to claim 5, wherein: The opening width of the first through hole is less than 20 μm, and the thickness of the first pad layer is in a range of 7 μm to 10 μm.

Images