Semiconductor package and method of manufacturing the same

Abstract

A semiconductor package includes: a first package; a second package, the second package is located on the first package, the second package includes a second package substrate, a first semiconductor chip and a second semiconductor chip located on the second package substrate, and a second molding component located on the second package substrate and covering the first semiconductor chip and the second semiconductor chip; a filling component, the filling component is located between the first package and the second package; a first through hole, the first through hole penetrates the second package substrate, the first through hole is located between the first semiconductor chip and the second semiconductor chip; a second through hole, the second through hole penetrates the second molding component, the second through hole is connected to the first through hole, wherein the filling component has an extension portion arranged in the first through hole and the second through hole.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0094349 filed in the Korean Intellectual Property Office on August 2, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor package and a method of manufacturing the same. Background Art

[0004] In the semiconductor industry, semiconductor devices and electronic products using semiconductor devices increasingly require high performance, fast operating speed and compact size. In response to this trend, many stacking methods have been developed. For example, multiple semiconductor chips can be stacked on a single substrate, or a package can be stacked on another package. Package on package (POP) is an integrated circuit packaging method that vertically stacks various semiconductor chips to achieve high-density chip stacking. Compared with conventional packages made of one semiconductor chip, POP technology can integrate semiconductor chips with various functions on a smaller area. Summary of the invention

[0005] According to an exemplary embodiment of the present invention, a semiconductor package may include: a first package; a second package, the second package is located on the first package, the second package includes a second package substrate, a first semiconductor chip and a second semiconductor chip located on the second package substrate, and a second molding component located on the second package substrate and covering the first semiconductor chip and the second semiconductor chip; a filling component, the filling component is located between the first package and the second package; a first through hole, the first through hole penetrates the second package substrate, the first through hole is located between the first semiconductor chip and the second semiconductor chip; a second through hole, the second through hole penetrates the second molding component, the second through hole is connected to the first through hole, wherein the filling component has an extension portion arranged in the first through hole and the second through hole.

[0006] According to an exemplary embodiment of the present invention, a semiconductor package may include: a lower package, the lower package including a lower package substrate, a lower semiconductor chip located on the lower package substrate, and a lower molding component located on the lower package substrate and covering the lower semiconductor chip; an upper package, the upper package is located on the lower package, the upper package includes an upper package substrate, a first upper semiconductor chip and a second upper semiconductor chip located on the upper package substrate, and an upper molding component located on the upper package substrate and covering the upper semiconductor chips; an interposer substrate, the interposer substrate is located between the upper package substrate and the lower semiconductor chip; and a bottom filling component, the bottom filling component fills the space between the interposer substrate and the upper package substrate, wherein the bottom filling component includes a protrusion extending through the upper package substrate and the upper molding component toward the top surface of the upper molding component, wherein the upper molding component includes a first section arranged between the upper package substrate and the protrusion.

[0007] According to an exemplary embodiment of the present invention, a method for manufacturing a semiconductor package may include: forming a first through hole penetrating a packaging substrate; coating a molding member on the packaging substrate to form a molding part; forming a second through hole penetrating the molding part and connected to the first through hole; mounting the packaging substrate on a package; and placing a bottom filling member in the first through hole and the second through hole to fill a space between the packaging substrate and the package.

[0008] According to an exemplary embodiment of the present invention, a semiconductor package may include: a first package; a second package, the second package overlapping the first package when viewed in a top view, the second package including a packaging substrate and a first semiconductor chip and a second semiconductor chip arranged on the packaging substrate; and a filling component, the filling component being arranged between the first package and the second package, wherein the filling component includes a segment extending in a vertical direction relative to a surface of the first package, the segment extending in an opening in the packaging substrate and between the first semiconductor chip and the second semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A A cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept is illustrated.

[0010] Figure 1B Illustrated Figure 1A An enlarged view of part A of FIG.

[0011] Figure 1C A top view showing a semiconductor package according to an exemplary embodiment of the inventive concept is illustrated.

[0012] Figure 2A A cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept is illustrated.

[0013] Figure 2B Illustrated Figure 2A An enlarged view of part B.

[0014] Figure 3 A cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept is illustrated.

[0015] Figure 4 A cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept is illustrated.

[0016] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 A cross-sectional view illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept is illustrated.

[0017] Fig.11 A cross-sectional view illustrating a method of manufacturing a semiconductor package of which an upper package includes neither a first through hole nor a second through hole is illustrated.

[0018] Fig.12 , Fig.13 and Fig.14 A cross-sectional view illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept is illustrated. DETAILED DESCRIPTION

[0019] Hereinafter, a semiconductor package according to exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0020] Figure 1A A cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept is illustrated. Figure 1B Illustrated Figure 1A An enlarged view of part A of FIG. Figure 1C illustrates a top view showing a semiconductor package according to an exemplary embodiment of the inventive concept, Figure 1A Corresponding to the Figure 1C For ease of description, Figure 1C Illustration of the upper molded part is omitted. Figure 2A A cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept is illustrated. Figure 2B Illustrated Figure 2A An enlarged view of part B.

[0021] Reference Figures 1A to 1C , a lower package 100 may be provided. The lower package 100 may include a lower package substrate 110 , a lower semiconductor chip 120 , a lower molding member 130 , and an interposer substrate 200 .

[0022] The lower package substrate 110 may be a printed circuit board (PCB) having a signal pattern on its top surface. Alternatively, the lower package substrate 110 may have a structure in which one or more dielectric layers and one or more wiring layers are alternately stacked. The lower package substrate 110 may have a first substrate pad 112 and a second substrate pad 114 on its top surface.

[0023] The external terminal 105 may be disposed under the lower package substrate 110. For example, the external terminal 105 may be disposed on a terminal pad 116 disposed on the bottom surface of the lower package substrate 110. The external terminal 105 may include a solder ball or a solder bump, and based on the type of the external terminal 105, the lower package 100 may have one of a ball grid array (BGA) type, a fine ball grid array (FBGA) type, and a land grid array (LGA) type.

[0024] The lower semiconductor chip 120 may be disposed on the lower package substrate 110. When viewed in a top view, the lower semiconductor chip 120 may be disposed on the central portion of the lower package substrate 110. The lower semiconductor chip 120 may have a bottom surface facing the lower package substrate 110 and a top surface opposite to the bottom surface. For example, the bottom surface of the lower semiconductor chip 120 may be closer to the lower package substrate 110 than the top surface of the lower semiconductor chip 120. The bottom surface of the lower semiconductor chip 120 may be an active surface, and the top surface of the lower semiconductor chip 120 may be an inactive surface. The lower semiconductor chip 120 may be mounted on the top surface of the lower package substrate 110. For example, the lower semiconductor chip 120 may be a flip chip mounted on the lower package substrate 110. In this case, the lower semiconductor chip 120 may be electrically connected to the lower package substrate 110 by a chip terminal 124 such as a solder ball or a solder bump disposed on the bottom surface of the lower semiconductor chip 120. The chip terminal 124 may be disposed between the first substrate pad 112 of the lower package substrate 110 and the lower chip pad 122 disposed on the bottom surface of the lower semiconductor chip 120. Flux 126 may fill the space between the lower semiconductor chip 120 and the lower package substrate 110. However, the inventive concept is not limited thereto, and the lower semiconductor chip 120 may be mounted on the lower package substrate 110 by bonding wires. In this specification, the phrase "electrically connected / coupled to" may include "directly or indirectly electrically connected / coupled to". The lower semiconductor chip 120 may be, for example, a logic chip or a memory chip. The memory chip may be, for example, a dynamic random access memory (DRAM), a NAND flash memory, a NOR flash memory, a phase change RAM (PRAM), a resistive RAM (ReRAM), or a magnetoresistive RAM (MRAM). Alternatively, the lower semiconductor chip 120 may be a non-memory chip, such as an application processor. The lower semiconductor chip 120 may be electrically connected to the external terminal 105 through the lower package substrate 110. Figure 1A Only one lower semiconductor chip 120 is shown, but the lower semiconductor chip 120 may be provided in plural.

[0025] The interposer substrate 200 may be disposed on the lower semiconductor chip 120. The interposer substrate 200 may include a dielectric substrate or a silicon substrate. The interposer substrate 200 may be attached to the top surface of the lower semiconductor chip 120. The width of the interposer substrate 200 may be greater than the width of the lower semiconductor chip 120. In this case, the interposer substrate 200 may protrude out of one side of the lower semiconductor chip 120. The interposer substrate 200 may also protrude out of two opposite sides of the lower semiconductor chip 120. Alternatively, Figure 1ADifferent from the one shown in FIG. 1 , the width of the interposer substrate 200 may be equal to or less than the width of the lower semiconductor chip 120. The interposer substrate 200 may have a third substrate pad 202 and a fourth substrate pad 204 on its top surface. The interposer substrate 200 may be mounted on the lower package substrate 110. For example, the interposer substrate 200 may be wire-bonded to the lower package substrate 110. In this case, the interposer substrate 200 may be electrically connected to the lower package substrate 110 via a first bonding wire 220. The first bonding wire 220 may connect the fourth substrate pad 204 on the top surface of the interposer substrate 200 to the second substrate pad 114 on the top surface of the lower package substrate 110.

[0026] The adhesive layer 210 may be disposed between the lower semiconductor chip 120 and the interposer substrate 200. The adhesive layer 210 may contact the top surface of the lower semiconductor chip 120 and the bottom surface of the interposer substrate 200. The adhesive layer 210 may attach the lower semiconductor chip 120 and the interposer substrate 200. Therefore, the lower semiconductor chip 120 and the interposer substrate 200 may be rigidly combined to improve the structural stability of the semiconductor package.

[0027] The lower molding member 130 may be disposed on the lower package substrate 110. On the top surface of the lower package substrate 110, the lower molding member 130 may surround the lower semiconductor chip 120 and the interposer substrate 200. For example, the lower molding member 130 may cover the side surface of the lower semiconductor chip 120, the side surface of the interposer substrate 200, and the top surface of the interposer substrate 200. When the interposer substrate 200 protrudes out of one side of the lower semiconductor chip, the lower molding member 130 may cover the exposed bottom surface of the interposer substrate 200. For example, the lower semiconductor chip 120 and the interposer substrate 200 may be embedded in the lower molding member 130 on the lower package substrate 110.

[0028] The upper package 300 may be disposed on the lower package 100 . The upper package 300 may include an upper package substrate 310 , an upper semiconductor chip 320 , and an upper molding member 330 .

[0029] The upper package substrate 310 may be disposed on the interposer substrate 200. The upper package substrate 310 may be vertically spaced apart from the lower molding component 130. The width of the upper package substrate 310 may be the same as the width of the lower package substrate 110 and the width of the lower molding component 130. For example, the upper package substrate 310, the lower package substrate 110, and the lower molding component 130 may have side surfaces 310a, 110a, and 130a located on the same plane, respectively. The upper package substrate 310 may be a PCB having a signal pattern on its top surface. Alternatively, the upper package substrate 310 may have a structure in which one or more dielectric layers are alternately stacked with one or more wiring layers.

[0030] The upper package substrate 310 may have first through holes TH1 vertically penetrating therethrough. Figure 1C As illustrated, the first through holes TH1 may be located at a central portion of the upper package substrate 310. The first through holes TH1 may be located on the lower semiconductor chip 120, and may overlap the lower semiconductor chip 120 when viewed in a plan view. Figure 1C Only one first through hole TH1 is shown, but the inventive concept is not limited thereto. A plurality of first through holes TH1 may be provided. A width W1 of the first through hole TH1 may be in the range of about 100 μm to about 200 μm.

[0031] The upper package substrate 310 may be mounted on the interposer substrate 200. For example, the connection terminal 305 may be disposed below the upper package substrate 310. The connection terminal 305 may penetrate the lower molding member 130 and may be coupled to the third substrate pad 202 of the interposer substrate 200. The connection terminal 305 may include a solder ball or a solder bump.

[0032] One or more upper semiconductor chips 320 may be disposed on the upper package substrate 310. When viewed in a top view, the upper semiconductor chips 320 may be spaced apart from each other. Figure 1C As shown, the first through hole TH1 may be located between the upper semiconductor chips 320. The upper semiconductor chips 320 may each have a bottom surface facing the upper package substrate 310 and a top surface opposite to the bottom surface. For example, the bottom surface of each upper semiconductor chip 320 may be closer to the upper package substrate 310 than the top surface of each upper semiconductor chip 320. The bottom surface of each upper semiconductor chip 320 may be a passive surface, and the top surface of each upper semiconductor chip 320 may be an active surface. The upper semiconductor chip 320 may be mounted on the top surface of the upper package substrate 310. For example, the upper semiconductor chip 320 may be wire bonded to the upper package substrate 310. In this case, the upper semiconductor chip 320 may be electrically connected to the upper package substrate 310 by a second bonding wire 324. The second bonding wire 324 may connect the fifth substrate pad 312 disposed on the top surface of the upper package substrate 310 to the upper chip pad 322 disposed on the top surface of the upper semiconductor chip 320. The upper semiconductor chips 320 may each be attached to the top surface of the upper package substrate 310 by an upper adhesive layer. However, the inventive concept is not limited thereto, and the upper semiconductor chip 320 may be a flip chip mounted on the upper package substrate 310. The upper semiconductor chip 320 may be, for example, a logic chip or a memory chip. The upper semiconductor chip 320 may be electrically connected to the external terminal 105 of the lower package substrate 110 through the upper package substrate 310 and the interposer substrate 200. Figure 1A Two upper semiconductor chips 320 are shown, but one or three or more upper semiconductor chips 320 may be provided.

[0033] The upper molding member 330 may be disposed on the upper package substrate 310. The upper molding member 330 may surround the upper semiconductor chip 320 on the top surface of the upper package substrate 310. For example, the upper semiconductor chip 320 may be embedded in the upper molding member 330 on the upper package substrate 310.

[0034] The upper molding part 330 may have a second through hole TH2 vertically penetrating therethrough. When viewed in a top view, the second through hole TH2 may be located at a central portion of the upper molding part 330. The second through hole TH2 may be located between the upper semiconductor chips 320. The width W2 of the second through hole TH2 may be in a range of about 100 μm to about 200 μm. When viewed in a top view, the second through hole TH2 may overlap with the first through hole TH1. The width W2 of the second through hole TH2 may be less than the width W1 of the first through hole TH1, and the second through hole TH2 may extend into the first through hole TH1. For example, the upper molding part 330 may include a first segment 332 extending along the inner wall of the first through hole TH1 of the upper package substrate 310, and the second through hole TH2 may have an inner wall spaced apart from the inner wall of the first through hole TH1. For example, the inner wall of the second through hole TH2 may be spaced apart from the inner wall of the first through hole TH1 by the segment 332. In addition, the inner wall of the second through hole TH2 may be located within the first through hole TH1. For example, the upper molding part 330 may extend into the first through hole TH1 of the upper package substrate 310 , and the second through hole TH2 of the upper molding part 330 may be located inside the first through hole TH1 when viewed in a plan view.

[0035] The upper molding part 330 may extend onto the bottom surface 310b of the upper package substrate 310. For example, the upper molding part 330 may have a second section 334 starting from the bottom end of the first section 332 and extending along the bottom surface 310b of the upper package substrate 310. In this case, the second section 334 of the upper molding part 330 may protrude downward from the bottom surface 310b of the upper package substrate 310. In other words, the second section 334 of the upper molding part 330 may be disposed below the bottom surface 310b of the upper package substrate 310. The second section 334 of the upper molding part 330 may cover a portion of the bottom surface 310b of the upper package substrate 310.

[0036] In an exemplary embodiment of the inventive concept, the upper package substrate 310 and the upper molding member 330 may share a single through hole TH. Figure 2A and Figure 2BAs illustrated, the through hole TH may include a first through hole TH1' that penetrates the upper packaging substrate 310 and a second through hole TH2' that penetrates the upper molding part 330. When viewed in a top view, the first through hole TH1' and the second through hole TH2' may have the same shape. The first through hole TH1' and the second through hole TH2' may be spatially connected to each other. The width W1' of the first through hole TH1' may be the same as the width W2' of the second through hole TH2'. In this case, the first through hole TH1' may overlap with the second through hole TH2', and the first through hole TH1' may have an inner wall that is coplanar with the inner wall of the second through hole TH2'. For example, the first through hole TH1' and the second through hole TH2' may be spatially connected to have the same planar shape. In this case, the upper molding part 330 may not extend into the first through hole TH1'. The following description returns to reference Figure 1A and Figure 1B Embodiment of the invention.

[0037] The bottom filling component 400 may be disposed between the upper package 300 and the lower package 100. The bottom filling component 400 may fill the space between the upper package substrate 310 and the lower molding component 130. The bottom filling component 400 may contact the connection terminals 305. For example, the bottom filling component 400 may contact the opposite sides of the respective connection terminals 305. The bottom filling component 400 may have a side surface 400a coplanar with the side surface 110a of the lower package substrate 110, the side surface 130a of the lower molding component 130, the side surface 310a of the upper package substrate 310, and the side surface 330a of the upper molding component 330. The bottom filling component 400 may contact the top surface 130b of the lower molding component 130 and the bottom surface 310b of the upper package substrate 310. The bottom filling part 400 may have an extension section 405 extending from between the lower package 100 and the upper package 300 to penetrate the upper package substrate 310 and the upper molding part 330. The extension section 405 may fill the first through hole TH1 and the second through hole TH2. In the first through hole TH1, the extension section 405 may be spaced apart from the inner wall of the first through hole TH1 by the first section 332 of the upper molding part 330. For example, the extension section 405 may penetrate the first section 332 and the second section 334 of the upper molding part 330, wherein the first section 332 fills the first through hole TH1, and may extend toward the top surface of the upper molding part 330. The bottom filling part 400 may include a dielectric material having a thermal expansion coefficient different from that of the lower package 100 and the upper package 300. The bottom filling part 400 may include an epoxy molding compound (EMC).

[0038] like Figure 2A and Figure 2BAs illustrated, when the first through hole TH1' and the second through hole TH2' have the same planar shape, the extension section 405 of the bottom filling part 400 may contact the inner wall of the first through hole TH1' and may also contact the inner wall of the second through hole TH2'. Figure 1A Embodiment of the invention.

[0039] Generally, one or both of the lower package 100 and the upper package 300 may suffer from warpage caused by heat generated when manufacturing or using the semiconductor package. For example, one or both of the lower package 100 and the upper package 300 may be bent into a U-shape having a concave shape at its center (such as a smiling face) or a convex inverted U-shape (such as a sad face).

[0040] The warping of the semiconductor package can be alleviated by the bottom filling component 400 that fills the space between the lower package 100 and the upper package 300. The thermal expansion coefficient of the bottom filling component 400 may be different from the thermal expansion coefficients of the lower package 100 and the upper package 300. The bottom filling component 400 may have a thermal expansion coefficient that can compensate for the warping of one or both of the lower package 100 and the upper package 300. For example, the bottom filling component 400 can compensate for the difference in thermal expansion coefficient between the upper and lower portions of the semiconductor package. As a result, the semiconductor package according to the exemplary embodiment of the inventive concept is less likely to be warped due to heat, thereby improving its structural stability.

[0041] In an exemplary embodiment of the present invention, the bottom filling component 400 may include a dielectric material with high thermal conductivity. For example, the bottom filling component 400 may include a dielectric material based on an acrylic polymer, an epoxy polymer, or a polyurethane polymer. Alternatively, the bottom filling component 400 may include a thermal interface material (TIM), such as a heat dissipation paste. Therefore, the bottom filling component 400 can efficiently dissipate the heat generated from the lower semiconductor chip 120. The bottom filling component 400 can penetrate the upper package 300 and be exposed on the top surface of the upper package 300, so that the heat generated from the lower semiconductor chip 120 and the upper semiconductor chip 320 can be easily discharged from the semiconductor package. As a result, the semiconductor package according to the exemplary embodiment of the present invention improves the heat dissipation efficiency. In addition, the bottom filling component 400 can be attached to the upper package 300 and the interposer substrate 200.

[0042] Figure 3 A cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept is illustrated. Figure 1A and Figure 1B The same components as those discussed may be assigned the same reference numerals, and thus, for ease of description, their repeated descriptions will be omitted or abridged. Figure 1A and Figure 1B The differences between the embodiment and other embodiments.

[0043] Reference Figure 3 , the semiconductor package may not include an interposer substrate. For example, Figure 1A The interposer substrate 200 is provided.

[0044] A lower package 100 may be provided. The lower package 100 may include a lower package substrate 110 , a lower semiconductor chip 120 , and a lower molding member 130 .

[0045] The lower molding member 130 may be disposed on the lower package substrate 110. The lower molding member 130 may surround the lower semiconductor chip 120 on the top surface of the lower package substrate 110. For example, the lower molding member 130 may cover the side surface and the top surface of the lower semiconductor chip 120.

[0046] The upper package 300 may be disposed on the lower package 100 . The upper package 300 may include an upper package substrate 310 , an upper semiconductor chip 320 , and an upper molding member 330 .

[0047] The upper package substrate 310 may be disposed on the lower molding part 130. In this case, the upper package substrate 310 may be vertically spaced apart from the lower molding part 130. The upper package substrate 310 may have a first through hole TH1 vertically penetrating therethrough. The first through hole TH1 may be located at a central portion of the upper package substrate 310. The first through hole TH1 may be located on the lower semiconductor chip 120 and may overlap with the lower semiconductor chip 120 when viewed in a top view.

[0048] The upper package substrate 310 may be mounted on the lower package substrate 110. For example, the connection terminal 305' may be disposed below the upper package substrate 310. When viewed in a top view, the connection terminal 305' may be located outside the lower semiconductor chip 120. For example, the connection terminal 305' may be disposed on the opposite side of the lower semiconductor chip 120. The connection terminal 305' may be spaced apart from the side surface of the lower semiconductor chip 120. The connection terminal 305' may be arranged in an opening OP formed in the lower molding part 130. The opening OP may vertically penetrate the lower molding part 130 to expose the second substrate pad 114 of the lower package substrate 110. For example, the connection terminal 305' may penetrate the lower molding part 130 and may be connected to the second substrate pad 114 of the lower package substrate 110. The lower molding part 130 may be disposed between the connection terminal 305' and the side surface of the lower semiconductor chip 120.

[0049] One or more upper semiconductor chips 320 may be disposed on the upper package substrate 310 . The first through holes TH1 may be located between the upper semiconductor chips 320 .

[0050] The upper molding part 330 may be disposed on the upper package substrate 310. On the top surface of the upper package substrate 310, the upper molding part 330 may cover the upper semiconductor chip 320. The upper molding part 330 may have a second through hole TH2 vertically penetrating therethrough. The second through hole TH2 may be located between the upper semiconductor chips 320 and may be spatially connected to the first through hole TH1. The shapes of the first through hole TH1 and the second through hole TH2 may be the same as those of the reference 1. Figure 1A or Figure 2A The first through hole and the second through hole in question have the same or similar shapes.

[0051] The bottom filling component 400 may be disposed between the upper package 300 and the lower package 100. The bottom filling component 400 may fill the space between the upper package substrate 310 and the lower molding component 130. The bottom filling component 400 may contact the connection terminal 305'. The bottom filling component 400 may have a side surface 400a coplanar with the side surfaces of the lower package substrate 110 (e.g., 110a), the lower molding component 130 (e.g., 130a), the upper package substrate 310 (e.g., 310a), and the upper molding component 330 (e.g., 330a). The bottom filling component 400 may have an extension section 405 extending from between the lower package 100 and the upper package 300 to penetrate the upper package substrate 310 and the upper molding component 330. The extension section 405 may fill the first through hole TH1 and the second through hole TH2.

[0052] Already referred to Figure 3 The configuration of a semiconductor package without an interposer substrate is described. However, the present inventive concept is not limited thereto, and Figure 3 The lower package included in the semiconductor package of the present invention may be variously changed in shape. For example, the lower package may include a fan-out type semiconductor package.

[0053] Figure 4 A cross-sectional view showing a semiconductor package according to an exemplary embodiment of the inventive concept is illustrated.

[0054] Reference Figure 4 , the interposer substrate 200 may be disposed on the lower package 100 .

[0055] The interposer substrate 200 may be located on the lower molding part 130. The interposer substrate 200 may be vertically spaced apart from the lower molding part 130. The interposer substrate 200 may have a third through hole TH3 vertically penetrating therethrough. The third through hole TH3 may be located at a central portion of the interposer substrate 200. The third through hole TH3 may be located on the lower semiconductor chip 120 and, when viewed in a top view, may overlap with the lower semiconductor chip 120. A width W3 of the third through hole TH3 may be in a range of about 100 μm to about 200 μm.

[0056] The interposer substrate 200 may be mounted on the lower package substrate 110. For example, the first connection terminal 307 may be disposed below the interposer substrate 200. When viewed in a top view, the first connection terminal 307 may be located outside the lower semiconductor chip 120. For example, the first connection terminal 307 may be disposed on the opposite side of the lower semiconductor chip 120. The first connection terminal 307 may be placed in an opening OP formed in the lower molding part 130. The first connection terminal 307 may penetrate the lower molding part 130 and may be connected to the second substrate pad 114 of the lower package substrate 110.

[0057] The upper package 300 may be disposed on the interposer substrate 200. The upper package 300 may include an upper package substrate 310, an upper semiconductor chip 320, and an upper molding member 330.

[0058] The upper package substrate 310 may be disposed on the interposer substrate 200. The upper package substrate 310 may be vertically spaced apart from the interposer substrate 200. The upper package substrate 310 may have a first through hole TH1 vertically penetrating therethrough. The first through hole TH1 may be located at a central portion of the upper package substrate 310. The first through hole TH1 may be located on the lower semiconductor chip 120 and may overlap with the lower semiconductor chip 120 when viewed in a top view.

[0059] The upper package substrate 310 may be mounted on the interposer substrate 200. For example, the second connection terminal 309 may be disposed below the upper package substrate 310. The second connection terminal 309 may be coupled to a substrate pad of the interposer substrate 200 and may electrically connect the interposer substrate 200 and the upper package substrate 310.

[0060] One or more upper semiconductor chips 320 may be disposed on the upper package substrate 310. The first through holes TH1 may be located between the upper semiconductor chips 320.

[0061] The upper molding part 330 may be disposed on the upper package substrate 310. On the top surface of the upper package substrate 310, the upper molding part 330 may cover the upper semiconductor chip 320. The upper molding part 330 may have a second through hole TH2 vertically penetrating therethrough. The second through hole TH2 may be located between the upper semiconductor chips 320 and spatially connected to the first through hole TH1. The shapes of the first through hole TH1 and the second through hole TH2 may be respectively similar to those of the reference Figure 1A or Figure 2A The first through hole and the second through hole in question have the same or similar shapes.

[0062] The bottom filler part 400 may be disposed between the upper package 300 and the lower package 100. The bottom filler part 400 may include a first bottom filler part 410 filling a space between the upper package 300 and the interposer substrate 200 and a second bottom filler part 420 filling a space between the interposer substrate 200 and the lower package 100. Here, for ease of description, the first bottom filler part 410 and the second bottom filler part 420 are arbitrarily divided and are formed of substantially the same material to constitute a single integral component.

[0063] The first bottom filling part 410 may fill the space between the upper package substrate 310 and the interposer substrate 200. The first bottom filling part 410 may enclose the second connection terminal 309 between the upper package substrate 310 and the interposer substrate 200. The first bottom filling part 410 may have a first extension section 415 extending from between the interposer substrate 200 and the upper package 300 to penetrate the upper package substrate 310 and the upper molding part 330. The first extension section 415 may fill the first through hole TH1 and the second through hole TH2.

[0064] The second bottom filling component 420 may fill the space between the interposer substrate 200 and the lower molding component 130. The second bottom filling component 420 may enclose the first connection terminal 307 between the interposer substrate 200 and the lower molding component 130. For example, the second bottom filling component 420 may enclose the upper portion of the first connection terminal 307. The second bottom filling component 420 may have a second extension section 425 extending from between the interposer substrate 200 and the lower package 100 to penetrate the interposer substrate 200. The second extension section 425 may fill the third through hole TH3. The second extension section 425 may penetrate the third through hole TH3 and may be connected to the first bottom filling component 410.

[0065] According to an exemplary embodiment of the inventive concept, the bottom fill component 400 may fill the space between the lower package 100 and the interposer substrate 200, and may also fill the space between the upper package 300 and the interposer substrate 200. The second extension section 425 connects the first bottom fill component 410 filling the space between the lower package 100 and the interposer substrate 200 to the second bottom fill component 420 filling the space between the upper package 300 and the interposer substrate 200. Therefore, the bottom fill component 400 may rigidly attach the lower package 100, the interposer substrate 200, and the upper package 300, so that the semiconductor package may have improved structural stability.

[0066] Figures 5 to 10 A cross-sectional view illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept is illustrated.

[0067] Reference Figure 5 , the lower package 100 can be manufactured. The lower package 100 can be configured as Figure 1A and Figure 1B The lower package discussed is the same or similar. For example, the lower semiconductor chip 120 can be mounted on the lower package substrate 110. For example, the lower semiconductor chip 120 can be a flip chip mounted on the lower package substrate 110. The interposer substrate 200 can be attached to the top surface of the lower semiconductor chip 120. The interposer substrate 200 can be attached to the lower semiconductor chip 120 by an adhesive layer 210. The interposer substrate 200 can be mounted on the lower package substrate 110. The interposer substrate 200 can be wire bonded to the lower package substrate 110. For example, the first bonding wire 220 can be used to connect the fourth substrate pad 204 of the interposer substrate 200 to the second substrate pad 114 of the lower package substrate 110. The lower molding part 130 can be formed on the lower package substrate 110. For example, the molding member can be coated on the lower package substrate 110. The molding member can cover the lower semiconductor chip 120 and the interposer substrate 200. The molding member can be cured to form the lower molding part 130.

[0068] Reference Figure 6 , an upper package substrate 310 may be provided. The upper package substrate 310 may undergo a first process to form a first through hole TH1. For example, the first process may include mechanical drilling. When viewed in a top view, the first through hole TH1 may be located at a central portion of the upper package substrate 310. The width of the first through hole TH1 may be in a range of about 100 μm to about 200 μm. When the width of the first through hole TH1 is less than 100 μm, it may not be easy to inject a bottom filling member in a subsequent process (see Fig.10 of 430).

[0069] The upper semiconductor chip 320 may be mounted on the upper package substrate 310. The upper semiconductor chip 320 may be spaced apart from the first through holes TH1. The upper semiconductor chip 320 may be wire-bonded to the upper package substrate 310. In an exemplary embodiment of the inventive concept, the first process of forming the first through holes TH1 may be performed after the upper semiconductor chip 320 is mounted on the upper semiconductor substrate 310.

[0070] Reference Figure 7 , an upper molding part 330 may be formed on the upper package substrate 310. For example, a molding member may be coated on the upper package substrate 310. The molding member may cover the upper package substrate 310 and the upper semiconductor chip 320. At this stage, as shown in FIG. Figure 7As shown by the downward arrow in , the molding member may be introduced into the first through hole TH1. For example, a portion of the molding member may fill the first through hole TH1, or may pass through the first through hole TH1 and then flow onto the bottom surface 310b of the upper package substrate 310. For example, a portion of the molding member may overlap the bottom surface 310b of the upper package substrate 310 on the opposite side of the first through hole TH1.

[0071] The molded member may be cured to form an upper molded part 330. A first section 332 of the upper molded part 330 (see also Figure 1A ) may fill the first through hole TH1, or the second section 334 of the upper molding member 330 (see also Figure 1A ) may protrude onto the bottom surface 310b of the upper package substrate 310. Thus, the upper package 300 may be formed.

[0072] In an exemplary embodiment of the present inventive concept, the molding member may fill the first through holes TH1 but may not flow onto the bottom surface 310 b of the upper package substrate 310 . For example, the upper molding part 330 may not protrude onto the bottom surface 310 b of the upper package substrate 310 .

[0073] Reference Figure 8 , the upper molding part 330 may undergo a second process to form the second through hole TH2. For example, the second process may include laser drilling or mechanical drilling. The width of the second through hole TH2 may be smaller than the width of the first through hole TH1. The width of the second through hole TH2 may be in the range of about 100 μm to about 200 μm. When viewed in a top view, the second through hole TH2 may be formed to be located inside the first through hole TH1. For example, the second process may be performed on the upper portion of the upper molding part 330 and the first segment 332 and the second segment 334 of the upper molding part 330, wherein the first segment 332 fills the first through hole TH1.

[0074] Reference Fig. 9 , the upper package 300 can be mounted on the lower package 100. The upper package 300 can be aligned to the lower package 100. A connecting terminal 305 can be set between the upper package 300 and the lower package 100. The connecting terminal 305 may include a solder ball or a solder bump. The connecting terminal 305 can be set in an opening of the third substrate pad 202 of the lower molding part 130 that exposes the interposer substrate 200. Thereafter, the connecting terminal 305 can be subjected to a reflow process to mount the upper package substrate 310 on the interposer substrate 200. In this case, the upper package substrate 310 can be spaced apart from the top surface of the lower molding part 130. For example, the upper package substrate 310 can be spaced apart from the top surface of the lower molding part 130 by the connecting terminal 305.

[0075] Reference Fig.10, a bottom filling member may be formed between the upper package 300 and the lower package 100 (see Figure 1A For example, the bottom filling member 430 may fill the space between the upper package 300 and the lower package 100. Fig.10 As shown by the arrow in , the bottom filling member 430 may be introduced from the outside into the second through hole TH2 of the upper molding member 330. The flow direction FD1 of the bottom filling member 430 may pass through the second through hole TH2 and the first through hole TH1. For example, the bottom filling member 430 may flow through the second through hole TH2 and the first through hole TH1 to reach the space between the upper package substrate 310 and the lower molding member 130, and then flow outward from the space.

[0076] When manufacturing Figure 4 In the illustrated semiconductor package, the underfill member 430 may flow through the second through holes TH2 and the first through holes TH1 to fill the space between the upper package 300 and the interposer substrate 200. The underfill member 430 may flow through the third through holes TH3 to fill the space between the interposer substrate 200 and the lower package 100.

[0077] According to an exemplary embodiment of the inventive concept, since the second through hole TH2 is formed at the central portion of the upper package 300, the bottom filling member 430 may have a reduced flow length FL1. Therefore, the bottom filling member 430 may have a low flow resistance, may flow easily, and may prevent overflow due to the flow resistance of the bottom filling member 430 at the inlet TH2a of the second through hole TH2. Therefore, unnecessary use of the bottom filling member 430 may be prevented. In addition, the easy introduction of the bottom filling member 430 may reduce the generation of a void such as an air gap between the upper package substrate 310 and the lower molding part 130.

[0078] The bottom filling member 430 may continue to be introduced until the bottom filling member 430 completely fills the space between the upper package substrate 310 and the lower molding part 130. For example, the bottom filling member 430 may flow toward the side surface of the semiconductor package, such as the side surface 310a of the upper package substrate 310 and the side surface 130a of the lower molding part 130. When the bottom filling member 430 reaches the side surface of the semiconductor package, the introduction of the bottom filling member 430 may be stopped. Therefore, the bottom filling member 430 may be prevented from flowing to the outside of the semiconductor package, and as a result, unnecessary consumption of the bottom filling member 430 may be avoided. The bottom filling member 430 may completely fill the space between the upper package substrate 310 and the lower molding part 130, and may encapsulate the connection terminal 305.

[0079] When neither the first through hole TH1 nor the second through hole TH2 is formed on the upper package 300 , a gap may occur between the upper package 300 and the lower package 100 . Fig.11 A cross-sectional view illustrating a method of manufacturing a semiconductor package of which an upper package includes neither a first through hole nor a second through hole is illustrated.

[0080] Reference Fig.11 , the first through hole may not be included in the upper package substrate 510 of the upper package 500 including the upper semiconductor chip 520, and the second through hole may not be included in the upper molding member 530 of the upper package 500. Fig.11 As shown by the arrow in , the bottom filling component 430' can be introduced from the outside into the space between the upper package substrate 510 and the lower molding component 130. The flow direction FD2 of the bottom filling component 430' can be from one side of the semiconductor package to the other side. In this case, the bottom filling component 430' will have an increased flow length FL2 and a high flow resistance. Therefore, the bottom filling component 430' may overflow on one side of the semiconductor package (for example, a side used as an inlet for introducing the bottom filling component 430'), and a gap such as an air gap may appear between the upper package substrate 510 and the lower molding component 130.

[0081] Return to reference Figure 1A , can be Fig.10 The bottom filling member 430 is subjected to a curing process. The bottom filling member 430 may be cured to form the bottom filling part 400. Thereafter, the external terminal 105 may be formed on the bottom surface of the lower package substrate 110. Through the above process, a Figure 1A The semiconductor package shown.

[0082] Figure 12 to Figure 14 A cross-sectional view illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the inventive concept is illustrated.

[0083] Reference Fig.12 , an upper packaging substrate 310 may be provided.

[0084] The upper semiconductor chip 320 may be mounted on the upper package substrate 310 . The upper semiconductor chips 320 may be disposed to be spaced apart from each other. The upper semiconductor chip 320 may be wire-bonded to the upper package substrate 310 .

[0085] The upper molding part 330 may be formed on the upper package substrate 310. For example, a molding member may be coated on the upper package substrate 310. The molding member may cover the upper package substrate 310 and the upper semiconductor chip 320. The molding member may be cured to form the upper molding part 330. Thus, the upper package 300 may be formed.

[0086] Reference Fig.13 , the upper package 300 may undergo a third process to form a through hole TH. The through hole TH may vertically penetrate the upper molding part 330 and the upper package substrate 310. The through hole TH may include a first through hole TH1' that penetrates the upper package substrate 310 and a second through hole TH2' that penetrates the upper molding part 330. The third process may include mechanical drilling. The through hole TH may be formed in a single process. Alternatively, the third process of forming the through hole TH may include a first process of forming the second through hole TH2' and a second process of forming the first through hole TH1'. In this case, the first process may be performed by laser drilling or mechanical drilling, and the second process may be performed by mechanical drilling. When viewed in a top view, the through hole TH may be formed between the central portion of the upper package substrate 310 and the upper semiconductor chip 320.

[0087] Reference Fig.14 , the upper package 300 may be mounted on the lower package 100. The upper package 300 may be aligned to the lower package 100. A connection terminal 305 may be provided between the upper package 300 and the lower package 100. Then, the connection terminal 305 may be subjected to a reflow process to mount the upper package substrate 310 on the interposer substrate 200. In this case, the upper package substrate 310 may be spaced apart from the top surface of the lower molding part 130.

[0088] An underfill member may be formed between the upper package 300 and the lower package 100 (see Figure 2A For example, the bottom filling member 430 may fill the space between the upper package 300 and the lower package 100. Fig.14 As shown by an arrow, the underfill member 430 may be introduced from the outside into the through hole TH of the upper package 300. The underfill member 430 may pass through the through hole TH and then may flow to the outside of the semiconductor package.

[0089] According to an exemplary embodiment of the inventive concept, the upper molding part 330 may extend into the through hole TH but may not protrude to the bottom surface of the upper package substrate 310 (see Figure 2B 310b). Therefore, the upper package 300 may have a substantially flat bottom surface and may have a low flow resistance of the bottom filling member 430. Therefore, the bottom filling member 430 may be easily introduced to fill the space between the upper package substrate 310 and the lower molding part 130, which may reduce the generation of a void such as an air gap between the upper package substrate 310 and the lower molding part 130.

[0090] Return to reference Figure 2A , can be Fig.14The bottom filling member 430 is subjected to a curing process. The bottom filling member 430 may be cured to form the bottom filling part 400. Thereafter, the external terminal 105 may be formed on the bottom surface of the lower package substrate 110. Through the above process, a Figure 2A The semiconductor package shown.

[0091] The semiconductor package according to the exemplary embodiment of the inventive concept may include an underfill component that can compensate for the difference in thermal expansion coefficient between the upper and lower portions of the semiconductor package. Therefore, the semiconductor package can ensure reduced warpage caused by heat and improved structural stability. In addition, the underfill component can effectively dissipate heat generated from the lower semiconductor chip and can rigidly attach the upper package and the lower package.

[0092] According to the method for manufacturing a semiconductor package of an exemplary embodiment of the present invention, a through hole can be formed in the central portion of the upper package so that the bottom filling member can have a low flow resistance, the bottom filling member can flow easily, and the bottom filling member does not overflow. Therefore, the bottom filling member can be prevented from being used unnecessarily. In addition, because the bottom filling member is easily introduced through the through hole, the generation of a gap such as an air gap between the upper package substrate and the lower molding component can be reduced.

[0093] Although the inventive concepts have been described with reference to exemplary embodiments of the inventive concepts, persons skilled in the art will recognize that changes may be made in form and details without departing from the spirit and scope of the inventive concepts.

Claims

1. A semiconductor package, comprising: a first package; a second package, the second package being located on the first package, the second package comprising a second package substrate, a first semiconductor chip and a second semiconductor chip located on the second package substrate, and a second molding member located on the second package substrate and covering the first semiconductor chip and the second semiconductor chip; a filling component, the filling component being located between the first packaging component and the second packaging component; a first through hole, the first through hole penetrating the second packaging substrate, the first through hole being located between the first semiconductor chip and the second semiconductor chip; and a second through hole, the second through hole penetrating the second molding part, the second through hole being connected to the first through hole, and wherein the filling component has an extension portion disposed in the first through hole and the second through hole, wherein the width of the first through hole is greater than the width of the second through hole, and a portion of the second molding member extends into the first through hole and covers an inner wall of the first through hole, Wherein, in the first through hole, the extension portion is spaced apart from the inner wall of the first through hole, and the portion of the second molding member is located between the extension portion and the inner wall of the first through hole.

2. The semiconductor package according to claim 1, wherein: The extension portion passes through the second package substrate and the second molding member, and the extension portion extends toward a top surface of the second molding member.

3. The semiconductor package according to claim 1, wherein: The portion of the second molding member extends from the inner wall of the first through hole toward the bottom surface of the second package substrate, and The portion of the second molding member protrudes from the bottom surface of the second package substrate.

4. The semiconductor package according to claim 1, wherein: Each of the first through hole and the second through hole has a width of 100 μm to 200 μm.

5. The semiconductor package according to claim 1, wherein: The thermal expansion coefficient of the filling member is greater than a thermal expansion coefficient of the second molding member and a thermal expansion coefficient of the second package substrate.

6. The semiconductor package according to claim 1, wherein: The first package comprises: a first packaging substrate; a third semiconductor chip, the third semiconductor chip being located on the first packaging substrate; and a first molding member, the first molding member being located on the first packaging substrate and covering the third semiconductor chip, The second package is electrically connected to the first package substrate through a plurality of connection terminals located between the first package substrate and the second package substrate.

7. The semiconductor package according to claim 6, wherein: The filling member surrounds a side surface of the connection terminal.

8. The semiconductor package according to claim 6, wherein: The first package further includes an interposer substrate located on the third semiconductor chip, the interposer substrate being embedded in the first molding member, At least one of the connection terminals is coupled to the interposer substrate.

9. The semiconductor package according to claim 6, wherein The second package has the same width as the first package, and A side surface of the second package, a side surface of the first package, and a side surface of the filling part are coplanar with each other.

10. A semiconductor package, comprising: a lower package, the lower package comprising a lower package substrate, a lower semiconductor chip located on the lower package substrate, and a lower molding member located on the lower package substrate and covering the lower semiconductor chip; an upper package, the upper package being located on the lower package, the upper package comprising an upper package substrate, a first upper semiconductor chip and a second upper semiconductor chip located on the upper package substrate, and an upper molding member located on the upper package substrate and covering the upper semiconductor chips; an interposer substrate located between the upper package substrate and the lower semiconductor chip; and a bottom filling component that fills a space between the interposer substrate and the upper package substrate, wherein the bottom filling part includes a protrusion extending through the upper package substrate and the upper molding part toward a top surface of the upper molding part, and wherein the upper molding member comprises a first section disposed between the upper package substrate and the protrusion, Wherein, the upper package substrate has a first through hole penetrating the upper package substrate, wherein the upper molding part has a second through hole penetrating the upper molding part, the second through hole is connected to the first through hole, and the protrusion of the bottom filling part is disposed inside the first through hole and the second through hole, The width of the second through hole is smaller than the width of the first through hole, and the second through hole extends into the first through hole. The first section of the upper molding member covers an inner wall of the first through hole, and the protrusion of the bottom filling member is spaced apart from the inner wall of the first through hole by the first section.

11. The semiconductor package according to claim 10, wherein: The upper molding member further includes a second segment extending from a bottom end of the first segment along a bottom surface of the upper package substrate.

12. The semiconductor package according to claim 10, wherein: Each of the first through hole and the second through hole has a width of 100 μm to 200 μm.

13. The semiconductor package according to claim 10, wherein: When viewed in a plan view, the first through-hole and the second through-hole are located between the first upper semiconductor chip and the second upper semiconductor chip.

14. A method for manufacturing a semiconductor package, the method comprising: forming a first through hole penetrating the package substrate; applying a molding member on the package substrate to form a molding part, wherein when forming the molding part, the molding member is introduced into the first through hole; forming a second through hole penetrating the molded part and connected to the first through hole; Mounting the packaging substrate on a packaging component; and placing an underfill member in the first through hole and the second through hole to fill a space between the package substrate and the package, The second through hole is formed to penetrate the molding member in the first through hole.

15. The method according to claim 14, wherein: The molding member protrudes onto a bottom surface of the package substrate.

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