Electrostatic discharge with parasitic compensation

Abstract

The present disclosure relates to electrostatic discharge with parasitic compensation. For example, a circuit for preventing device failure includes a first rail, an electrostatic discharge (ESD) protection circuit arrangement, a second rail, an ESD switch circuit arrangement, a bias circuit arrangement, and a signal limiter. The first rail is for one or more first electrical components formed in a first portion of a substrate. The second rail is for one or more second electrical components formed in a second portion of the substrate. The first portion of the substrate forms an emitter of a parasitic transistor, and the second portion of the substrate forms a collector of the parasitic transistor. The bias circuit arrangement is configured to output a bias voltage at the emitter of the parasitic transistor when the ESD switch circuit arrangement is on. The signal limiter is electrically coupled to the first rail and the emitter of the parasitic transistor.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to techniques for preventing damage associated with electrostatic discharge (ESD) in electronic circuits. BACKGROUND

[0002] To prevent damage from electrostatic discharge (ESD), electronic manufacturers often include ESD protection circuitry in electronic devices and components such as integrated circuits (ICs) and printed circuit boards (PCBs). For example, an IC having a ground pin and a cascaded voltage pin (i.e., a pin having a different supply voltage) can include ESD protection circuitry to protect a functional circuit between the various pin combinations from positive and negative ESD stress. Upon detecting a voltage event (e.g., an overvoltage or voltage spike exceeding a threshold) between two pins caused by, for example, an ESD event, the ESD protection circuitry directs current caused by the voltage event away from the functional circuitry to, for example, ground. SUMMARY

[0003] Generally, the present invention is directed to providing techniques for compensating for a parasitic component of an electrical component formed in a substrate. For example, a circuit can include a biasing circuitry configured to output a bias voltage at an emitter of a parasitic transistor when an electrostatic discharge (ESD) switching element is on. In this way, the biasing circuitry can help prevent the parasitic transistor from causing damage during an ESD event.

[0004] In one example, a circuit includes a first rail for forming one or more first electrical components in a first portion of a substrate, ESD protection circuitry electrically coupled between the first rail and a reference rail, where the ESD protection circuitry is configured to generate a conductive path between the first rail and the reference rail during an ESD event, a second rail for forming one or more second electrical components in a second portion of the substrate, where the first portion of the substrate forms an emitter of a parasitic transistor and the second portion of the substrate forms a collector of the parasitic transistor, ESD switching circuitry electrically coupled between the second rail and the reference rail, where the ESD switching circuitry is configured to turn on to generate the conductive path between the second rail and the reference rail during the ESD event, biasing circuitry configured to output a bias voltage at the emitter of the parasitic transistor when the ESD switching circuitry is on, and a signal limiter configured to electrically couple the first rail and the emitter of the parasitic transistor.

[0005] In another example, a method includes generating, by an ESD protection circuitry, a conductive path between a first rail and a reference rail during an ESD event, where the first rail is configured for one or more first electrical components formed in a first portion of a substrate; turning on, during the ESD event, an ESD switch circuitry electrically coupled between a second rail and the reference rail to generate a conductive path between the second rail and the reference rail, where the second rail is configured for one or more second electrical components formed in a second portion of the substrate, where the first portion of the substrate forms an emitter of a parasitic transistor and the second portion of the substrate forms a collector of the parasitic transistor; and outputting a bias voltage at the emitter of the parasitic transistor when the ESD switch circuitry is turned on, where a signal limiter is electrically coupled the first rail and the emitter of the parasitic transistor.

[0006] In another example, a system includes a reference rail; one or more first electrical components formed in a first portion of a substrate; a first rail for the one or more first electrical components; an electrostatic discharge (ESD) protection circuitry electrically coupled between the first rail and the reference rail, where the ESD protection circuitry is configured to generate a conductive path between the first rail and the reference rail during an ESD event; one or more second electrical components formed in a second portion of the substrate, where the first portion of the substrate forms an emitter of a parasitic transistor and the second portion of the substrate forms a collector of the parasitic transistor; a second rail for the one or more second electrical components; an ESD switch circuitry electrically coupled between the second rail and the reference rail, where the ESD switch circuitry is configured to turn on to generate a conductive path between the second rail and the reference rail during an ESD event; a bias circuitry configured to output a bias voltage at the emitter of the parasitic transistor when the ESD switch circuitry is turned on; and a signal limiter configured to be electrically coupled the first rail and the emitter of the parasitic transistor.

[0007] The details of these and other examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description, drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0008] FIG. 1A is a block diagram illustrating an example system for electrostatic discharge with parasitic compensation in accordance with one or more techniques of the present disclosure.

[0009] FIG. 1B is a block diagram illustrating an example system for electrostatic discharge with parasitic compensation in accordance with one or more techniques of the present disclosure, with a bias circuitry coupled to a reference rail.

[0010] FIG. 1Cis a block diagram illustrating an example system for electrostatic discharge with parasitic compensation having a bias circuit device coupled to an ESD switch circuit device, in accordance with one or more techniques of the present disclosure.

[0011] FIG. 1D is a block diagram illustrating an example system for electrostatic discharge with parasitic compensation having a bias circuit device coupled to a second rail, in accordance with one or more techniques of the present disclosure.

[0012] FIG. 2A is a conceptual diagram illustrating a cross-section of an example system for electrostatic discharge with parasitic compensation, in accordance with one or more techniques of the present disclosure.

[0013] FIG. 2B is a conceptual diagram illustrating a first example bias circuit device of a system for electrostatic discharge with parasitic compensation having FIG. 2A

[0014] FIG. 3 is a conceptual diagram illustrating a second example bias circuit device with parasitic compensation, in accordance with one or more techniques of the present disclosure.

[0015] FIG. 4 is a conceptual diagram illustrating a third example bias circuit device with parasitic compensation, in accordance with one or more techniques of the present disclosure.

[0016] FIG. 5 is a conceptual diagram illustrating a bias circuit device with parasitic compensation for an ESD protection circuit device having a switching element, in accordance with one or more techniques of the present disclosure.

[0017] FIG. 6 is a block diagram illustrating an example circuit for electrostatic discharge with parasitic compensation for a plurality of parasitic transistors, in accordance with one or more techniques of the present disclosure.

[0018] FIG. 7 is a flow diagram illustrating a process for preventing device failure, in accordance with the present disclosure. DETAILED DESCRIPTION

[0019] It is an object of the present disclosure to provide techniques for utilizing parasitics in electrostatic discharge (ESD) protection compensation circuits. For example, ESD stress can occur between any two subgroups of product pins. ESD qualification of a product can emphasize the selection of these subgroups, also referred to as pin combinations. A parasitic transistor (e.g., an NPN bipolar transistor) can be biased by ESD stress in some of these pin combinations by the base / emitter junction of the parasitic transistor being forward biased while the base / collector junction of the parasitic transistor is reverse biased. This biasing of the parasitic transistor can result in damage to the parasitic transistor. ​

[0020] Some systems can limit damage caused by parasitic transistors by adjusting the parasitic transistors. For example, such systems can adjust the parasitic transistors to increase the base doping and increase the base width of the parasitic transistors to reduce the current gain. Some systems can apply a guard ring around the emitter. However, such systems can only help to reduce damage caused by parasitic transistors. Moreover, compared to systems that omit the guard ring and increase the base width, the guard ring and increased base width can increase cost and layout and / or substrate planning complexity. Furthermore, compared to systems that do not adjust the parasitic transistors, the increased base doping impacts technology development and increases development costs. Moreover, adjusting the parasitic transistors and using a guard ring can not be feasible for applications that use relatively high voltages (e.g., higher than 50 volts). For example, in applications that use relatively high voltages, increasing the base doping is not feasible because increasing the base doping can contradict the breakdown voltage requirements of the junction isolation.

[0021] According to the techniques described herein, a system can be configured to provide a bias voltage during ESD stress and apply the bias voltage to the possible emitter of one or more parasitic transistors. Applying the bias voltage to the emitter of the parasitic transistors can prevent the emitter / base of each parasitic transistor from being forward biased, thus preventing the activation and damage of the one or more parasitic transistors. Applying the bias voltage can also be used in applications that use relatively high voltages (e.g., even for breakdown of the collector / base junction of the parasitic bipolar transistor). Such a system can help to prevent current injection from the emitter to the base compared to systems that do not apply the bias voltage. Applying the bias voltage can be effective without any distance requirements (e.g., area cost, layout / substrate planning complexity, etc.).

[0022] FIG. 1A is a block diagram of an example system 100A for electrostatic discharge with parasitic compensation according to one or more techniques of the present disclosure. As FIG. 1A As shown in the example, the system 100A can include a first rail 102, one or more first electrical components 104 (also referred to herein as “first electrical components 104”), an ESD protection circuit 106, a reference rail 108, a second rail 112, one or more second electrical components 114 (also referred to herein as “second electrical components 114”), an ESD switch circuit 116, a parasitic transistor 120, a signal limiter 124, and a bias circuit 126. The first rail 102 can be a power rail, an input / output (I / O) rail, or another rail. The second rail 112 can be a power rail, an I / O rail, or another rail. The electrical components 104 can include analog, digital, or analog and digital elements formed in a first portion of a substrate. Similarly, the electrical components 114 can include analog, digital, or analog and digital elements formed in a second portion of the substrate.

[0023] The ESD protection circuit device 106 can be configured to generate a conductive path between the first rail 102 and the reference rail 108 during an ESD event. As used herein, an ESD event can refer to a situation in which a voltage at the first rail 102 exceeds a threshold value, a voltage at the second rail 112 exceeds a threshold value, a voltage at the reference rail 108 exceeds a threshold value, or a voltage at another rail exceeds a threshold value. The ESD protection circuit device 106 can be configured to electrically couple the first rail 102 (e.g., a voltage rail) and the reference rail 108 (e.g., a ground, ground plane, or reference node) during an ESD event. The ESD protection circuit device 106 can include a diode (e.g., a Zener diode) configured to electrically couple the first rail 102 and the reference rail 108 during an ESD event. The ESD protection circuit device 106 can include a switching element configured to electrically couple the first rail 102 and the reference rail 108 during an ESD event. Examples of switching elements can include, but are not limited to, silicon controlled rectifiers (SCRs), field effect transistors (FETs), and bipolar junction transistors (BJTs). Examples of FETs can include, but are not limited to, junction field effect transistors (JFETs), metal oxide semiconductor FETs (MOSFETs), double-gate MOSFETs, FinFETs, insulated gate bipolar transistors (IGBTs), any other type of FET, or any combination thereof. Examples of MOSFETs can include, but are not limited to, PMOS, NMOS, DMOS, or any other type of MOSFET, or any combination thereof. Examples of BJTs can include, but are not limited to, PNP, NPN, heterojunction, or any other type of BJT, or any combination thereof. The switching element can be voltage controlled and / or current controlled. Examples of current controlled switching elements can include, but are not limited to, gallium nitride (GaN) MOSFETs, BJTs, or other current controlled elements. As shown, the ESD protection circuit device 106 can be coupled between the first rail 102 and the reference rail 108.

[0024] The ESD switch circuit device 116 can be configured to generate a conductive path between the second rail 112 and the reference rail 108 during an ESD event. For example, the ESD switch circuit device 116 can be configured to electrically couple the second rail 112 (e.g., a voltage rail) and the reference rail 108 (e.g., a ground, ground plane, or reference node) during an ESD event. The ESD switch circuit device 116 can include a switch or switching element configured to electrically couple the second rail 112 and the reference rail 108 during an ESD event. In some examples, the ESD switch circuit device 116 can include a PN-type device (e.g., a Zener diode or avalanche diode) in which a P-junction (e.g., an anode) is electrically coupled to the reference rail 108. As shown, the ESD switch circuit device 116 can be coupled between the second rail 112 and the reference rail 108.

[0025] The parasitic transistor 120 can be a parasitic structure that results from forming the first electrical component 104 and the second electrical component 114. For example, the first electrical component 104 can be formed in a first portion of the substrate that forms an emitter of the parasitic transistor 120, and the second electrical component 114 can be formed in a second portion of the substrate that forms a collector of the parasitic transistor 120.

[0026] The signal limiter 124 can be configured to electrically couple the first rail 102 and the emitter of the parasitic transistor 120. In some examples, the signal limiter 124 includes a diode that includes an anode electrically coupled to the first rail 102 and a cathode electrically coupled to the emitter of the parasitic transistor 120. In some examples, the signal limiter 124 includes a resistive element (e.g., a resistor) that includes a first node electrically coupled to the first rail 102 and a second node electrically coupled to the emitter of the parasitic transistor 120.

[0027] The ESD protection circuitry 106 can be configured to drive the voltage at the first rail 102 to be less than the voltage at the reference rail 108 when the ESD protection circuitry 106 generates a conductive path between the first rail 102 and the reference rail 108 during an ESD event. According to the techniques described herein, the biasing circuitry 126 can be configured to output a bias voltage at the emitter of the parasitic transistor 120 when the ESD switch circuitry 116 is on. In some examples, the biasing circuitry 126 can be configured to output a bias voltage that is greater than the voltage at the reference rail 108 during an ESD event. For example, the biasing circuitry 126 can be configured to output a voltage that is greater than the voltage at the reference rail 108. For example, the biasing circuitry 126 can be configured to output a voltage that is derived from the voltage at the first rail 102, the voltage at the second rail 112, the gate voltage at the switching element of the ESD switch circuitry 116, a regulated voltage, or another voltage that is greater than the voltage at the reference rail 108. In some examples, the biasing circuitry 126 can be configured to output a bias voltage to correspond to the voltage at the reference rail 108 during an ESD event. For example, the biasing circuitry 126 can be configured to output a voltage at the reference rail 108. In this way, the biasing circuitry 126 can prevent damage to the parasitic transistor 120.

[0028] FIG. 1B FIG. 1 IB is a block diagram illustrating an example system 100B with parasitic compensation of electrostatic discharge, according to one or more techniques of this disclosure, with biasing circuitry 126 coupled to the reference rail 108. In the example of FIG. 11B, the biasing circuitry 126 can output a voltage at the emitter of the parasitic transistor 120 that is derived from the voltage at the reference rail 108 during an ESD event. FIG. 1B

[0029] In some examples, the biasing circuitry 126 can be configured to output a voltage at the emitter of the parasitic transistor 120 that is greater than the voltage at the reference rail 108 during an ESD event. For example, the biasing circuitry 126 can be configured to output a voltage that is greater than the voltage at the reference rail 108. For example, the biasing circuitry 126 can be configured to output a voltage that is derived from the voltage at the first rail 102, the voltage at the second rail 112, the gate voltage at the switching element of the ESD switch circuitry 116, a regulated voltage, or another voltage that is greater than the voltage at the reference rail 108. In some examples, the biasing circuitry 126 can be configured to output a bias voltage to correspond to the voltage at the reference rail 108 during an ESD event. For example, the biasing circuitry 126 can be configured to output a voltage at the reference rail 108. In this way, the biasing circuitry 126 can prevent damage to the parasitic transistor 120.FIG. 1C is a block diagram illustrating an example system 100C for electrostatic discharge with parasitic compensation according to one or more techniques of this disclosure, with a biasing circuit device coupled to the ESD switch circuit device 116. In FIG. 1C In examples, the biasing circuit device 126 can output a voltage to the emitter of the parasitic transistor 120 during an ESD event from a gate voltage applied to a gate of a switching element of the ESD switch circuit device 116.

[0030] FIG. 1D is a block diagram illustrating an example system 100D for electrostatic discharge with parasitic compensation according to one or more techniques of this disclosure, with a biasing circuit device coupled to the second rail 112. In FIG. 1D In examples, the biasing circuit device 126 can output a voltage to the emitter of the parasitic transistor 120 during an ESD event from a voltage at the second rail 112.

[0031] FIG. 2A is a conceptual diagram illustrating a cross-section of an example system 200 for electrostatic discharge with parasitic compensation according to one or more techniques of this disclosure. The VDD 202, diode 206, Vhigh 212, active ESD clamp 216, VSS 208, parasitic transistor 220, diode 224, and biasing circuit device 226 can be examples of the first rail 102, ESD protection circuit device 106, second rail 112, ESD switch circuit device 116, reference rail 108, parasitic transistor 120, signal limiter 124, and biasing circuit device 126, respectively, in FIGS. 1A-1D In examples, the first portion 232 can represent a portion of a substrate for a first electrical component, diode 206 (e.g., a Zener NPN), while the second portion 234 can represent a portion of the substrate for a second electrical component, transistor 217 (e.g., an n-channel lateral diffusion metal oxide semiconductor (NLDMOS)). In FIG. 2A In examples, the first portion 232 includes an N-type layer 240 (e.g., an n+ buried layer (BL)), and the second portion 234 includes an N-type layer 242. In this example, the N-type layer 240 and the N-type layer 242 are separated by a deep trench isolation (DTI) 243. As shown, the N-type layer 240 and the N-type layer 242 can be formed on a common P-type layer, such as but not limited to a P-type substrate 244. While FIG. 2A In examples, the first portion 232 includes an N-type layer 240 (e.g., an n+ buried layer (BL)), and the second portion 234 includes an N-type layer 242. In this example, the N-type layer 240 and the N-type layer 242 are separated by a deep trench isolation (DTI) 243. As shown, the N-type layer 240 and the N-type layer 242 can be formed on a common P-type layer, such as but not limited to a P-type substrate 244. While FIG. 2A While examples of

[0032] In FIG. 2AIn the illustrated example, ESD protection circuitry between VDD 202 and VSS 208 is provided by diode 206, which includes parasitic transistor 207 (e.g., a Zener NPN). As shown, parasitic transistor 207 includes an emitter electrically coupled to VDD 202, a collector electrically coupled to the emitter of parasitic transistor 220, and a base electrically coupled to VSS 208.

[0033] FIG. 2A The presence of parasitic transistor 220 (e.g., a parasitic substrate NPN bipolar transistor “Ql”) is shown. Parasitic transistor 220 can include N-type layer 240 (e.g., an n+BL region) and N-type layer 242 (e.g., an n+BL region), which are separated by DTI 243. N-type layer 240 can form the emitter of parasitic transistor 220. N-type layer 242 can form the collector of parasitic transistor 220. P-type substrate 244 can form the base of parasitic transistor 220. In this example, N-type layer 240 can form the isolation of diode 206 (e.g., the emitter and base of parasitic transistor 207), and N-type layer 242 is connected to the drain terminal of transistor 217 (e.g., an nLDMOS) of active ESD clamer 216. However, in other examples, the parasitic transistor can be formed from different electrical components.

[0034] In FIG. 2A In the illustrated example, the cathode of diode 206 (which is coupled to the emitter of parasitic transistor 207) is connected to VDD 202 along with the isolation of diode 206 (e.g., N-type layer 240) that is coupled to the collector of parasitic transistor 207. Thus, a positive ESD stress at Vhigh 212 can cause current 250 to flow from Vhigh 212, through transistor 217 and diode 206, to VDD 202. For example, current 250 can cause N-type layer 240 to be at a voltage corresponding to VDD 202. Transistor 217 can electrically couple Vhigh 212 to VSS 208. As such, current 250 can cause N-type layer 242 to be at a voltage corresponding to Vhigh 212. Parasitic transistor 220 can include N-type layer 240, N-type layer 242, and P-type substrate 244 (which is connected to VSS 208). In this way, an ESD stress at Vhigh 212 can cause current 250, which can cause current 252 to flow through parasitic transistor 220, resulting in damage to P-type substrate 244, N-type layer 240, and / or N-type layer 242.

[0035] According to the techniques described herein, the biasing circuit device 226 (e.g., an nLDMOS transistor) can be configured to output a bias voltage at the emitter of the parasitic transistor 220 when the transistor 217 is turned on, which causes a current 254. In this way, the biasing circuit device 226 can prevent current 252 from flowing through the parasitic transistor 220 to prevent potential damage to the P-type substrate 244, the N-type layer 240, and / or the N-type layer 242.

[0036] FIG. 2B is a conceptual diagram illustrating a first example biasing circuit device 226 of a system 200 for electrostatic discharge (ESD) with parasitic compensation according to one or more techniques of the present disclosure. FIG. 2A is a conceptual diagram illustrating a first example biasing circuit device 226 of a system 200 for electrostatic discharge (ESD) with parasitic compensation according to one or more techniques of the present disclosure. FIG. 2B An example is shown of how the parasitic transistor 220 exists in the circuit device and how the biasing conditions of the parasitic transistor 220 arise during ESD stress. In other examples, different electrical components can be used to form the parasitic transistor.

[0037] ESD protection devices can be located between Vhigh 212 and VSS 208 and between VDD 202 and VSS 208. In the example shown, an active ESD clamp 216 is located between Vhigh 212 and VSS 208, and a diode 206 (e.g., a Zener diode) is located between VDD 202 and VSS 208. FIG. 2B ESD protection devices can be located between Vhigh 212 and VSS 208 and between VDD 202 and VSS 208. In the example shown, an active ESD clamp 216 is located between Vhigh 212 and VSS 208, and a diode 206 (e.g., a Zener diode) is located between VDD 202 and VSS 208.

[0038] If a positive ESD stress occurs on the pin of Vhigh 212 relative to the pin of VDD 202, which is at ESD stress ground, ESD current can flow along ESD current 250, for example, through the active ESD clamp 216 between Vhigh 212 and VSS 202, along the VSS metal line, and through the diode 206 between VDD 202 and VSS 208. In this example, there is a voltage drop of about 100 volts across the active ESD clamp 216, and a voltage drop of about 1.7 volts across the diode 206, which is forward biased under this stress condition. The P-type substrate 244 connected to VSS 208 can thereby be forward biased by about 1.7 volts compared to the N-type layer 240 of the parasitic transistor 207, while the N-type layer 242 of the active ESD clamp 216 is at a high voltage of about 100 volts. As such, the base and / or emitter junction of the parasitic transistor 220 is turned on, while the collector is at a high potential, which can result in current 252. However, current 252 can cause strong heating in the P-type substrate 244 and / or the N-type layer 242, which is reverse biased by about 100 volts in this example. FIG. 2A , FIG. 2BThe examples shown are for illustration only. In some examples, there are many power and I / O pins that are connected to equivalent parasitic bipolar transistors and can also generate such critical ESD stress conditions.

[0039] According to the techniques described herein, the biasing circuit 226 can be configured to output a bias voltage at the emitter of the parasitic transistor 220 via the diode 227 when the transistor 217 is turned on, which causes the current 254. For example, the biasing circuit device 226 can include a switching element that couples the Vhigh 212 to the emitter of the parasitic transistor 220 during an ESD event. The diode 227 can connect the bias voltage (e.g., about 10-100 volts) to the N-type layer 240 of the diode 206 during an ESD event. As such, the biasing circuit device 226 can reverse bias the emitter and / or base junction of the parasitic transistor 220 to prevent the current 252. The diode 224 can provide biasing during normal operation when the VDD 202 is, for example, 5 volts. In this way, the biasing circuit device 226 can prevent the current 252 from flowing through the parasitic transistor 220 to prevent potential damage to the P-type substrate 244, the N-type layer 240, and / or the N-type layer 242.

[0040] FIG. 3 is a conceptual diagram illustrating a second example biasing circuit device 326 with parasitic compensation according to one or more techniques of the present disclosure. For purposes of illustration only, reference is made to FIGS. 1A-1D and FIGS. 2A-2B are described FIG. 3 . The VDD 302, diode 306, Vhigh 312, active ESD clamp 316, VSS 308, parasitic transistor 320, diode 324, and biasing circuit device 326 can be examples of the first rail 102, ESD protection circuit device 106, second rail 112, ESD switch circuit device 116, reference rail 108, parasitic transistor 120, signal limiter 124, and biasing circuit device 126 in FIG. 4 , FIG. 1A .

[0041] If a positive ESD stress occurs on the pin of the Vhigh 312 relative to the pin of the VDD 302, which is at ESD stress ground, the ESD current can flow along the ESD current path 350, for example, through the active ESD clamp 316 between the Vhigh 312 and the VSS 308, along the VSS metal line, and through the diode 306 (which includes the parasitic transistor 307 (e.g., a Zener NPN)) between the VDD 302 and the VSS 308. As such, the base and / or emitter junction of the parasitic transistor 320 is on, while the collector is at a high potential, which can result in the parasitic current 352.

[0042] However, inFIG. 1B In the example, bias circuitry 326 may be coupled to VSS 308. For instance, bias circuitry 326 may include a switching element that couples VSS 308 to the emitter of parasitic transistor 320 via diode 327 during an ESD event, causing a current 354. Thus, bias circuitry 326 can output a bias voltage (e.g., approximately 1.7 volts) at VSS 308 to the emitter of parasitic transistor 320. In this way, bias circuitry 326 prevents current 352 from flowing through parasitic transistor 320, potentially preventing damage.

[0043] FIG. 3 This is a conceptual diagram illustrating a third exemplary bias circuit device 426 with parasitic compensation according to one or more technologies of this disclosure. Reference is made, for example, to the diagram for illustrative purposes only. FIG. 4 , FIGS. 1A-1D and FIGS. 2A-2B describe FIG. 3 VDD402, diode 406, Vhigh 412, active ESD clamp 416, VSS 408, parasitic transistor 420, diode 424, and bias circuit device 426 may be FIG. 4 , FIG. 5 Examples of the first track 102, ESD protection circuit device 106, second track 112, ESD switching circuit device 116, reference track 108, parasitic transistor 120, signal limiter 124 and bias circuit device 126.

[0044] If positive ESD stress occurs on the pin of Vhigh 412 relative to the pin of VDD 402 (which is ESD stress grounded), ESD current can flow along ESD current path 450, for example, through the active ESD clamp 416 between Vhigh 412 and VSS 408, along the VSS metal line, and through the Zener diode 407 between VDD 402 and VSS 408. This causes the base and / or emitter junction of the parasitic transistor 420 to be on, while the collector is at a high potential, resulting in parasitic current 452.

[0045] However, in FIG. 1AIn the example of FIG. 5, the biasing circuitry 426 can couple the gate of the active ESD clamp 416 to the emitter of the parasitic transistor 420 during an ESD event. For example, the biasing circuitry 426 can include a switching element that couples the gate of the active ESD clamp 416 to the emitter of the parasitic transistor 420 via the diode 427 during an ESD event, which causes the current 454. As such, the biasing circuitry 426 can output a bias voltage (e.g., about 10 volts) at the gate of the active ESD clamp 416 to the emitter of the parasitic transistor 420. In this manner, the biasing circuitry 426 can prevent the current 452 from flowing through the parasitic transistor 420 to potentially prevent damage.

[0046] FIG. 1B is a conceptual diagram illustrating biasing circuitry with parasitic compensation for ESD protection circuitry with a switching element, in accordance with one or more techniques of the present disclosure. For example only for purposes of illustration, reference is made to FIG. 5 , FIG. 6 , FIGS. 1A-1D and FIGS. 2A-2B describe FIG. 3 . The VDD 502, the switching element 506, the Vhigh 512, the active ESD clamp 516, the VSS 508, the parasitic transistor 520, the diode 524, and the biasing circuitry 526 can be examples of the first rail 102, the ESD protection circuitry 106, the second rail 112, the ESD switch circuitry 116, the reference rail 108, the parasitic transistor 120, the signal limiter 124, and the biasing circuitry 126, respectively, in FIG. 4 , FIG. 5 .

[0047] In this example, the ESD protection circuitry between the VDD 502 and the VSS 508 is provided by the switching element 506 that includes the parasitic transistor 507. As shown, the parasitic transistor 507 includes an emitter electrically coupled to the VDD 502, a collector electrically coupled to the emitter of the parasitic transistor 520, and a base electrically coupled to the VSS 508. The switching element 506 is electrically coupled between the VDD 502 and the VSS 508 and is configured to generate a conductive path between the VDD 502 and the VSS 508 during an ESD event. If a positive ESD stress occurs at the pin of the Vhigh 512 relative to the pin of the VDD 502, which is at ESD stress ground, an ESD current can flow along the ESD current path 550, for example, through the active ESD clamp 516 between the Vhigh 512 and the VSS 508, along the VSS metal line, and through the switching element 506 between the VDD 502 and the VSS 508.

[0048] However, in FIG. 6In the example of FIG. 6, biasing circuitry 526 can be configured to output a bias voltage at the emitter of parasitic transistor 520 when the ESD switch circuitry is on. For example, biasing circuitry 526 can be configured to couple the gate of active ESD clamp 516 to the emitter of parasitic transistor 520 during an ESD event. In some examples, biasing circuitry 526 can be configured to couple Vhigh 512 to the emitter of parasitic transistor 520 during an ESD event. In some examples, biasing circuitry 526 can be configured to couple VSS 508 to the emitter of parasitic transistor 520 during an ESD event. In this way, biasing circuitry 526 can prevent current from flowing through parasitic transistor 520 to potentially prevent damage.

[0049] FIG. 1A is a block diagram illustrating example circuitry for parasitic compensation of electrostatic discharge for a plurality of parasitic transistors, in accordance with one or more techniques of the present disclosure. For illustrative purposes only, reference is made to FIG. 1B , FIG. 6 , FIG. 6 , FIG. 6 and FIG. 6 described FIG. 7 . Supply1 602A, HV supply 612, active clamp 616, GND 608, diode 624A, and biasing circuitry 626 can be examples of first rail 102, second rail 112, ESD switch circuitry 116, reference rail 108, signal limiter 124, and biasing circuitry 126, respectively, of FIGS. 1A-1D , FIG. 2A . As shown, Supply1 602A is coupled to the gate of active clamp 616, and GND 608 is coupled to the source of active clamp 616. FIG. 2B Examples of FIG. 6 further include Supply2 602B and diode 624B. While examples of FIG. 3 Examples of FIG. 6 illustrate HV supply 612 and two power supplies (e.g., Supply1 602A and Supply2 602B), other examples can include HV supply 612 and more than two power supplies.

[0050] The active clamp 616 can include a pass element 670 and a trigger circuit arrangement 672. The pass element 670 can include a control node, a first node electrically coupled to the HV power supply 612, and a second node electrically coupled to the GND 608. The trigger circuit arrangement 672 can include one or more trigger elements 674 arranged in a series string and a resistive element 676. As used herein, a trigger element can include, for example, but is not limited to, one or more of a Zener diode, a thyristor, a bipolar transistor, an avalanche diode, a MOS transistor, a forward biased diode, or another trigger element. As shown, a first end of the series string of trigger elements 674 can be electrically coupled to the HV power supply 612, and a second end of the series string is electrically coupled to the control node of the pass element 670. The resistive element 676 (e.g., a resistor) can include a first node electrically coupled to the control node of the pass element 670 and a second node electrically coupled to the GND 608. In some examples, the active clamp 616 can include a resistor-capacitor (RC) trigger element.

[0051] The bias circuit arrangement 626 can include a source follower element 660 (e.g., an nLDMOS transistor) and a diode 662. The diode 662 can include an anode electrically coupled to the GND 608 and a cathode electrically coupled to a second node of the source follower element 660. The source follower element 660 can include a control node electrically coupled to the control node of the pass element 670, a first node electrically coupled to the HV power supply 612, and a second node electrically coupled to an anode of the diode 627A. In some examples, the second node of the source follower element 660 can electrically couple the anodes of more than one diode to one or more emitters of the parasitic transistors. For example, the bias circuit arrangement 626 can be configured to output a bias voltage at the emitter of the first parasitic transistor 620A via the diode 627A and output a bias voltage at the emitter of the second parasitic transistor 620B via the diode 627B when the ESD switch circuit arrangement is on. In FIG. 4 In examples, the bias circuit arrangement 626 can output a bias voltage at the emitter of the third parasitic transistor 620C via the diode 627C when the ESD switch circuit arrangement is on.

[0052] In FIG. 5In the example of FIG. 6, the source follower element 660 generates an ESD bias voltage. The gate terminal of the source follower element 660 can be connected to a trigger signal (e.g., the output of the trigger circuitry 672) of the active clamp 616. However, in other cases, the bias circuitry 626 can be connected differently. For example, the bias circuitry 626 can be connected to Supplyl 602A, Supply2602B, the HV supply 612, GND 608, or another rail or node. The drain of the source follower element 660 can be connected to the HV supply 612. The source follower element 660 can allow the bias voltage to be available (e.g., simultaneously) in response to triggering the active clamp 616.

[0053] FIG. 6 is a flowchart illustrating a process for preventing device failure according to the present disclosure. For purposes of illustration only, reference is made to FIG. 7 , ​ , ​ , ​ , ​ , ​ and ​ discuss ​ During an ESD event, the ESD protection circuitry 106 generates a conductive path between the first rail 102 and the reference rail 108 (702). In some examples, the first rail 102 is configured for one or more first electrical components 104 formed in a first portion of a substrate. The ESD switch circuitry 116, which is electrically coupled between the second rail 112 and the reference rail 108, turns on during an ESD event to generate a conductive path between the second rail 112 and the reference rail 108 (704). In some examples, the second rail 112 is configured for one or more second electrical components 114 formed in a second portion of the substrate. In some examples, the first portion of the substrate forms an emitter of the parasitic transistor 120, and the second portion of the substrate forms a collector of the parasitic transistor 120. When the ESD switch circuitry 116 turns on, the bias circuitry 126 outputs a bias voltage at the emitter of the parasitic transistor 120 (706). In some examples, the signal limiter 124 is electrically coupled the first rail 108 and the emitter of the parasitic transistor 120.

[0054] The following examples can illustrate one or more aspects of the present disclosure.

[0055] Example 1. A circuit comprising: a first rail for one or more first electrical components formed in a first portion of a substrate; an electrostatic discharge (ESD) protection circuitry electrically coupled between the first rail and a reference rail, wherein the ESD protection circuitry is configured to generate a conductive path between the first rail and the reference rail during an ESD event; a second rail for one or more second electrical components formed in a second portion of the substrate, wherein the first portion of the substrate forms an emitter of a parasitic transistor and the second portion of the substrate forms a collector of the parasitic transistor; an ESD switch circuitry electrically coupled between the second rail and the reference rail, wherein the ESD switch circuitry is configured to turn on to generate a conductive path between the second rail and the reference rail during the ESD event; a biasing circuitry configured to output a bias voltage at the emitter of the parasitic transistor when the ESD switch circuitry turns on; and a signal limiter configured to electrically couple the first rail and the emitter of the parasitic transistor.

[0056] Example 2. The circuit of example 1, wherein the signal limiter comprises a diode, the diode comprising an anode electrically coupled to the first rail and a cathode electrically coupled to the emitter of the parasitic transistor.

[0057] Example 3. The circuit of any combination of examples 1-2, wherein the signal limiter comprises a resistive element, the resistive element comprising a first node electrically coupled to the first rail and a second node electrically coupled to the emitter of the parasitic transistor.

[0058] Example 4. The circuit of any combination of examples 1-3, wherein the first portion of the substrate comprises a first N-type layer; and the second portion of the substrate comprises a second N-type layer.

[0059] Example 5. The circuit of any combination of examples 1-4, wherein the first N-type layer and the second N-type layer are separated by a deep trench isolation.

[0060] Example 6. The circuit of any combination of examples 1-5, wherein the first N-type layer and the second N-type layer are formed on a common P-type layer.

[0061] Example 7. The circuit of any combination of examples 1-6, wherein the ESD protection circuitry comprises a diode, the diode comprising an anode electrically coupled to the reference rail and a cathode electrically coupled to the first rail.

[0062] Example 8. The circuit of any combination of examples 1-7, wherein the diode is a Zener diode.

[0063] Example 9. The circuit of any combination of examples 1-8, wherein the parasitic transistor is a first parasitic transistor, and the diode comprises a second parasitic transistor comprising an emitter electrically coupled to the first rail, a collector electrically coupled to the emitter of the first parasitic transistor, and a base electrically coupled to the reference rail.

[0064] Example 10. The circuit of any combination of examples 1-9, wherein the ESD protection circuitry comprises a switching element comprising a first node electrically coupled to the reference rail and a second node electrically coupled to the first rail, and wherein to generate the conductive path between the first rail and the reference rail during the ESD event, the switching element is configured to turn on.

[0065] Example 11. The circuit of any combination of examples 1-10, wherein when the ESD protection circuitry generates the conductive path between the first rail and the reference rail during the ESD event, the ESD protection circuitry drives a voltage at the first rail to be less than a voltage at the reference rail; and wherein the biasing circuitry is configured to output a bias voltage greater than the voltage at the reference rail during the ESD event.

[0066] Example 12. The circuit of any combination of examples 1-11, wherein the ESD switch circuitry comprises: a pass element comprising a control node, a first node electrically coupled to the second rail, and a second node electrically coupled to the reference rail.

[0067] Example 13. The circuit of any combination of examples 1-12, wherein the biasing circuitry comprises: a diode comprising an anode and a cathode, the cathode of the diode electrically coupled to the emitter of the parasitic transistor; and a source follower element comprising a control node electrically coupled to the control node of the pass element, a first node electrically coupled to the second rail, and a second node electrically coupled to the anode of the diode.

[0068] Example 14. The circuit of any combination of examples 1-13, wherein the ESD switch circuitry comprises: a trigger circuit comprising one or more trigger elements arranged in a series string, wherein a first end of the series string is electrically coupled to the second rail, and a second end of the series string is electrically coupled to the control node of the pass element; and a resistive element comprising a first node electrically coupled to the control node of the pass element, and a second node electrically coupled to the reference rail.

[0069] Example 15. The circuit of any combination of examples 1-14, wherein the ESD switch circuitry comprises an RC trigger element.

[0070] Example 16. The circuit of any combination of examples 1-15, wherein the parasitic transistor is a first parasitic transistor, wherein the biasing circuitry is further configured to output a bias voltage at an emitter of a second parasitic transistor via a second diode when the ESD switch circuitry is on.

[0071] Example 17. The circuit of any combination of examples 1-16, wherein the ESD switch circuitry comprises a switching element configured to turn on during an ESD event; or the ESD switch circuitry comprises a PN-type device having a P-junction electrically coupled to the reference rail.

[0072] Example 18. The circuit of any combination of examples 1-17, wherein the first rail is a power rail, the second rail is a power rail, or the first rail and the second rail are power rails; or wherein the first rail is an input / output (I / O) rail, the second rail is an I / O rail, or the first rail and the second rail are I / O rails.

[0073] Example 19. A method comprising: generating, by electrostatic discharge (ESD) protection circuitry, a conductive path between a first rail and a reference rail during an ESD event, wherein the first rail is configured for forming one or more first electrical components in a first portion of a substrate; turning on, during the ESD event, ESD switch circuitry electrically coupled between a second rail and the reference rail to generate a conductive path between the second rail and the reference rail, wherein the second rail is configured for forming one or more second electrical components in a second portion of the substrate, wherein the first portion of the substrate forms an emitter of a parasitic transistor and the second portion of the substrate forms a collector of the parasitic transistor; and outputting a bias voltage at the emitter of the parasitic transistor when the ESD switch circuitry is on, wherein a signal limiter is electrically coupled the first rail and the emitter of the parasitic transistor.

[0074] Example 20. A system comprising: a reference rail; one or more first electrical components formed in a first portion of a substrate; a first rail for the one or more first electrical components; electrostatic discharge (ESD) protection circuitry electrically coupled between the first rail and the reference rail, wherein the ESD protection circuitry is configured to generate a conductive path between the first rail and the reference rail during an ESD event; one or more second electrical components formed in a second portion of the substrate, wherein the first portion of the substrate forms an emitter of a parasitic transistor and the second portion of the substrate forms a collector of the parasitic transistor; a second rail for the one or more second electrical components; ESD switch circuitry electrically coupled between the second rail and the reference rail, wherein the ESD switch circuitry is configured to turn on to generate a conductive path between the second rail and the reference rail during the ESD event; bias circuitry configured to output a bias voltage at the emitter of the parasitic transistor when the ESD switch circuitry is turned on; and a signal limiter configured to electrically couple the first rail and the emitter of the parasitic transistor.

[0075] Various aspects are described herein. These and other aspects are within the scope of the following claims.

Claims

1. A circuit comprising: a first rail for one or more first electrical components formed in a first portion of a substrate; an electrostatic discharge (ESD) protection circuitry electrically coupled between the first rail and a reference rail, wherein the ESD protection circuitry is configured to generate a conductive path between the first rail and the reference rail during an ESD event; a second rail for one or more second electrical components formed in a second portion of the substrate, wherein the first portion of the substrate forms an emitter of a parasitic transistor, the second portion of the substrate forms a collector of the parasitic transistor, and a base of the parasitic transistor is connected to the reference rail; an ESD switch circuitry electrically coupled between the second rail and the reference rail, wherein the ESD switch circuitry is configured to turn on to generate a conductive path between the second rail and the reference rail during the ESD event; a biasing circuitry configured to output a bias voltage at the emitter of the parasitic transistor when the ESD switch circuitry turns on; and a signal limiter configured to electrically couple the first rail and the emitter of the parasitic transistor.

2. The circuit of claim 1, wherein the signal limiter comprises a diode including an anode electrically coupled to the first rail and a cathode electrically coupled to the emitter of the parasitic transistor.

3. The circuit of claim 1, wherein the signal limiter comprises a resistive element including a first node electrically coupled to the first rail and a second node electrically coupled to the emitter of the parasitic transistor.

4. The circuit of claim 1, wherein the first portion of the substrate comprises a first N-type layer; and wherein the second portion of the substrate comprises a second N-type layer.

5. The circuit of claim 4, wherein the first N-type layer and the second N-type layer are separated by a deep trench isolation.

6. The circuit of claim 4, wherein the first N-type layer and the second N-type layer are formed on a common P-type layer.

7. The circuit of claim 1, wherein the ESD protection circuitry comprises a diode including an anode electrically coupled to the reference rail and a cathode electrically coupled to the first rail.

8. The circuit of claim 7, wherein the diode is a Zener diode.

9. The circuit of claim 7, wherein the parasitic transistor is a first parasitic transistor, and wherein the diode is connected between an emitter and a base of a second parasitic transistor, the second parasitic transistor including an emitter electrically coupled to the first rail, a collector electrically coupled to the emitter of the first parasitic transistor, and a base electrically coupled to the reference rail. ​ 10. The circuit of claim 1, wherein the ESD protection circuit device comprises a switching element, the switching element comprising a first node electrically coupled to the reference rail and a second node electrically coupled to the first rail, and wherein to generate the conductive path between the first rail and the reference rail during the ESD event, the switching element is configured to turn on.

11. The circuit of claim 1, wherein when the ESD protection circuit device generates the conductive path between the first rail and the reference rail during the ESD event, the ESD protection circuit device drives a voltage at the first rail to be less than a voltage at the reference rail; and wherein the biasing circuit device is configured to output the bias voltage greater than the voltage at the reference rail during the ESD event.

12. The circuit of claim 1, wherein the ESD switch circuit device comprises: a pass element comprising a control node, a first node electrically coupled to the second rail, and a second node electrically coupled to the reference rail.

13. The circuit of claim 12, wherein the biasing circuit device comprises: a diode comprising an anode and a cathode, the cathode of the diode electrically coupled to the emitter of the parasitic transistor; and a source follower element comprising a control node electrically coupled to the control node of the pass element, a first node electrically coupled to the second rail, and a second node electrically coupled to the anode of the diode.

14. The circuit of claim 12, wherein the ESD switch circuit device comprises: a trigger circuit device comprising one or more trigger elements arranged in a series string, wherein a first end of the series string is electrically coupled to the second rail and a second end of the series string is electrically coupled to the control node of the pass element; and a resistive element comprising a first node electrically coupled to the control node of the pass element and a second node electrically coupled to the reference rail.

15. The circuit of claim 12, wherein the ESD switch circuit device comprises an RC trigger element.

16. The circuit of claim 1, wherein the parasitic transistor is a first parasitic transistor, wherein the biasing circuit device is further configured to output the bias voltage at an emitter of a second parasitic transistor via a second diode when the ESD switch circuit device turns on.

17. The circuit of claim 1, wherein the ESD switch circuit device comprises a switching element configured to turn on during the ESD event; or wherein the ESD switch circuit device comprises a PN-type device having a P-junction electrically coupled to the reference rail.

18. The circuit of claim 1, wherein the first rail and the second rail are each a power rail; or wherein the first rail and the second rail are each an I / O rail.

19. A method of preventing device failure, comprising: To generate a conductive path between a first rail and a reference rail during an electrostatic discharge (ESD) event, where the first rail is configured for one or more first electrical components formed in a first portion of a substrate; To turn on an ESD switch circuit device electrically coupled between a second rail and the reference rail to generate a conductive path between the second rail and the reference rail during the ESD event, where the second rail is configured for one or more second electrical components formed in a second portion of the substrate, where the first portion of the substrate forms an emitter of a parasitic transistor, the second portion of the substrate forms a collector of the parasitic transistor, and a base of the parasitic transistor is connected to the reference rail; and To output a bias voltage at the emitter of the parasitic transistor when the ESD switch circuit device is turned on, where a signal limiter is electrically coupled the first rail and the emitter of the parasitic transistor.

20. A system to prevent device failure, comprising: a reference rail; one or more first electrical components formed in a first portion of a substrate; a first rail for the one or more first electrical components; an electrostatic discharge (ESD) protection circuit device electrically coupled between the first rail and the reference rail, where the ESD protection circuit device is configured to generate a conductive path between the first rail and the reference rail during an ESD event; one or more second electrical components formed in a second portion of the substrate, where the first portion of the substrate forms an emitter of a parasitic transistor, the second portion of the substrate forms a collector of the parasitic transistor, and a base of the parasitic transistor is connected to the reference rail; a second rail for the one or more second electrical components; an ESD switch circuit device electrically coupled between the second rail and the reference rail, where the ESD switch circuit device is configured to turn on to generate a conductive path between the second rail and the reference rail during the ESD event; a bias circuit device configured to output a bias voltage at the emitter of the parasitic transistor when the ESD switch circuit device is turned on; and a signal limiter configured to electrically couple the first rail and the emitter of the parasitic transistor.

Images