Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device and a method for manufacturing the same are provided. The semiconductor memory device includes: electrode structures, each electrode structure including a horizontal electrode stacked on a substrate; a vertical electrode located between the electrode structures and extending along the horizontal electrode; a first contact connected to an end of the electrode structure to the horizontal electrode; a second contact connected to an upper portion of the vertical electrode; and a first interconnect structure connected to a top surface of the second contact. The first interconnect structure includes a first sub-interconnect line and a second sub-interconnect line. The first sub-interconnect line extends in a first direction and contacts the top surface of the second contact. The second sub-interconnect line extends in a second direction intersecting the first direction and contacts the first sub-interconnect line.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2019-0092568, filed on July 30, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor devices and methods of manufacturing the same, and more particularly to three-dimensional non-volatile memory devices. Background Technology

[0004] High integration levels are required in semiconductor devices to meet the demands for superior performance and low cost. In the case of semiconductor memory devices, integration level is particularly crucial as it significantly influences product price. In traditional two-dimensional semiconductor memory devices, integration level is heavily influenced by the level of fine patterning technology, as it is primarily determined by the area occupied by each memory cell. However, the extremely expensive processing equipment required to increase pattern fineness places practical limitations on increasing the integration level of two-dimensional semiconductor memory devices. Summary of the Invention

[0005] Embodiments of the inventive concept provide a semiconductor device including an interconnect structure that enables easy connection of vertical electrodes to each other.

[0006] According to an embodiment of the inventive concept, a semiconductor memory device may include a substrate; a plurality of electrode structures located on the substrate, wherein each of the plurality of electrode structures may include horizontal electrodes stacked on top of each other on the substrate; a vertical electrode located between the plurality of electrode structures and extending along the horizontal electrodes; a first contact connected to the horizontal electrodes at an end of the plurality of electrode structures; a second contact connected to the upper portion of the vertical electrode; and a first interconnect structure connected to the top surface of the second contact, the first interconnect structure including a first sub-interconnect and a second sub-interconnect. The first sub-interconnect may extend in a first direction and contact the top surface of the second contact. The second sub-interconnect may extend in a second direction intersecting the first direction. The second sub-interconnect may contact the first sub-interconnect.

[0007] According to an embodiment of the inventive concept, a semiconductor memory device may include a substrate; a plurality of electrode structures located on the substrate, wherein each of the plurality of electrode structures may include horizontal electrodes stacked on top of each other on the substrate; vertical electrodes located between the plurality of electrode structures and extending along the horizontal electrodes and extending in a first direction; first contacts connected to the horizontal electrodes at the ends of the plurality of electrode structures; second contacts connected to the upper portions of the vertical electrodes, wherein the top surface of the second contacts may be substantially at the same horizontal height as the top surface of the first contacts, and the spacing between the second contacts in the first direction may be greater than the spacing between the first contacts in the first direction; and a first interconnect structure connected to the top surface of the second contacts.

[0008] According to embodiments of the inventive concept, a semiconductor memory device may include: a substrate including a cell array region and a peripheral circuit region; a plurality of electrode structures located on the substrate, wherein each of the plurality of electrode structures includes a horizontal electrode stacked on top of each other on the substrate; a peripheral transistor located in the peripheral circuit region; a vertical structure penetrating the electrode structures; a stud connected to the upper portion of the vertical structure; a vertical electrode located between the plurality of electrode structures, wherein the vertical electrode extends along the horizontal electrode and in a first direction; a first contact connected to the horizontal electrode at an end of the plurality of electrode structures; a second contact connected to the upper portion of the vertical electrode; and an extended pad connecting... The first contact has a top surface; a third contact connected to a peripheral transistor, wherein the top surface of the third contact may be at the same horizontal level as the top surfaces of the first and second contacts; a peripheral pad connected to the top surface of the third contact; a first interconnect structure connected to the top surface of the second contact, wherein the top surface of the first interconnect structure may be substantially at the same horizontal level as the top surfaces of the extended pad and the peripheral pad; and a second interconnect structure located on the first interconnect structure and connected to the first interconnect structure via a first via, wherein the top surface of the second interconnect structure may be substantially at the same horizontal level as the top surface of the stud.

[0009] According to embodiments of the inventive concept, a method of manufacturing a semiconductor memory device may include forming a plurality of electrode structures on a substrate, wherein each of the plurality of electrode structures may include horizontal electrodes sequentially stacked on the substrate; forming a vertical structure that penetrates the electrode structure and includes a channel pattern; forming a vertical electrode between the plurality of electrode structures, wherein the vertical electrode extends along the horizontal electrodes; forming a first contact at an end of the plurality of electrode structures connected to the horizontal electrode; and forming a second contact connected to the upper portion of the vertical electrode. The formation of the second contact and the formation of the first contact may be performed simultaneously. Attached Figure Description

[0010] The exemplary embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting exemplary embodiments described herein.

[0011] Figure 1 This is a plan view illustrating a semiconductor memory device according to an embodiment of the inventive concept.

[0012] Figure 2 This is a plan view showing the first interconnect structure and the second interconnect structure.

[0013] Figure 3 This is a plan view of the first interconnect structure.

[0014] Figure 4 This is a plan view of the second interconnection structure.

[0015] Figure 5A , Figure 5B and Figure 5C They are along Figure 1 The cross-sectional views taken from lines A-A', B-B', and C-C'.

[0016] Figure 6 , Figure 13 and Figure 15 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the inventive concept.

[0017] Figure 7A and Figure 7B They are along Figure 6 The cross-sectional view taken from lines A-A' and B-B'.

[0018] Figure 8 , Figure 9 and Figure 10 This illustrates an embodiment based on the inventive concept. Figure 7A and Figure 7B Enlarged cross-sectional views of parts e1, e2, and e3.

[0019] Figure 11 and Figure 12 This illustrates another embodiment based on the inventive concept. Figure 7A and Figure 7B Enlarged cross-sectional views of parts e1, e2, and e3.

[0020] Figure 14A and Figure 14B They are respectively along Figure 13 The cross-sectional view taken from lines A-A' and B-B'.

[0021] Figure 16A and Figure 16B They are respectively along Figure 15The cross-sectional view taken from lines A-A' and B-B'.

[0022] Figure 17 This is a cross-sectional view showing a semiconductor memory device according to an embodiment of the inventive concept.

[0023] Figure 18 This is a cross-sectional view showing a semiconductor memory device according to an embodiment of the inventive concept. Detailed Implementation

[0024] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments.

[0025] Figure 1 This is a plan view illustrating a semiconductor memory device according to an embodiment of the inventive concept. Figure 2 This is a plan view showing the first interconnect structure and the second interconnect structure. Figure 3 This is a plan view of the first interconnect structure. Figure 4 This is a plan view of the second interconnection structure. Figure 5A , Figure 5B and Figure 5C They are along Figure 1 The cross-sectional views taken from lines A-A', B-B', and C-C'.

[0026] Reference Figures 1 to 4 , Figure 5A , Figure 5B and Figure 5C A semiconductor memory device comprising a cell array region CR and a peripheral circuit region PR can be provided. As an example, the semiconductor memory device may be a flash memory device. The cell array region CR may be a region in which a plurality of memory cells are disposed. The peripheral circuit region PR may be a region in which word line drivers, sense amplifiers, row and column decoders, and control circuitry are disposed. For ease of illustration, the peripheral circuit region PR is shown as being located in one of the side regions of the cell array region CR; however, in some embodiments, the peripheral circuit region PR may further include portions of at least one of the other side regions of the cell array region CR. As an example, the peripheral circuit region PR may be provided to surround the cell array region CR.

[0027] The cell array region CR may include an electrode structure SS, in which horizontal electrodes GP are sequentially stacked on the semiconductor substrate 100. An insulating layer 120 may be disposed between the horizontal electrodes GP. In other words, the horizontal electrodes GP and the insulating layer 120 may be stacked alternately and repeatedly on the semiconductor substrate 100. A buffer layer 111 may be disposed between the bottommost horizontal electrode GP and the semiconductor substrate 100. As an example, the insulating layer 120 and the buffer layer 111 may include a silicon oxide layer and / or a silicon oxynitride layer. The buffer layer 111 may be thinner than the insulating layer 120.

[0028] In this embodiment, the bottommost horizontal electrode may be the gate electrode of a ground select transistor (e.g., a portion of a ground select line). The topmost horizontal electrode and the second topmost horizontal electrode may be used as gate electrodes of a string select transistor (e.g., a portion of a string select line). The horizontal electrodes between the bottommost horizontal electrode and the second topmost horizontal electrode may be used as cell gate electrodes (e.g., some of the word lines). Although six horizontal electrodes are shown, the number of horizontal electrodes may be greater than or less than six.

[0029] Each horizontal electrode GP in the electrode structure SS may extend in a first direction D1. The electrode structures SS may be spaced apart from each other in a second direction D2, and a separation pattern 145 may be inserted between the electrode structures SS. Each of the separation patterns 145 may extend in the first direction D1. As an example, the separation pattern 145 may be formed of at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, or may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0030] Vertical electrodes 140 may be provided connected to the semiconductor substrate 100 to penetrate the separator pattern 145. The vertical electrodes 140 may serve as a common source line. In embodiments, each of the vertical electrodes 140 may have a plate-like pattern extending in a first direction D1. In some embodiments, the vertical electrodes 140 may include a plurality of contacts penetrating a separator pattern 145.

[0031] The vertical electrode 140 may be formed of at least one of polycrystalline silicon, a metal, and a conductive metal nitride, or may include at least one of polycrystalline silicon, a metal, and a conductive metal nitride. When the vertical electrode 140 comprises doped polycrystalline silicon, the vertical electrode 140 may have a second conductivity type different from the conductivity type of the semiconductor substrate 100. The second conductivity type may be, for example, n-type. When the vertical electrode 140 comprises a metallic material (e.g., tungsten, titanium, tantalum, and their nitrides), a metal silicide layer (e.g., tungsten silicide layer) may be further disposed between the vertical electrode 140 and the semiconductor substrate 100.

[0032] The individual impurity regions SR connected to the vertical electrode 140 can be disposed in the upper part of the semiconductor substrate 100. Each of the individual impurity regions SR can extend along the vertical electrode 140 or in the first direction D1. The individual impurity regions SR can serve as a common source region. The individual impurity regions SR can have a second conductivity type different from the conductivity type of the semiconductor substrate 100.

[0033] The vertical structures VS can be configured to penetrate the electrode structure SS and be connected to the semiconductor substrate 100. Each of the vertical structures VS can have a cylindrical shape, the width of which decreases in the downward direction. The vertical structures VS can be arranged two-dimensionally on the semiconductor substrate 100. In this specification, the expression "the elements are arranged two-dimensionally" will be used to indicate that, when viewed in a plan view, the elements are configured to form a plurality of columns and a plurality of rows extending in two orthogonal directions (e.g., a first direction D1 and a second direction D2, respectively). For example, each column of the vertical structures VS may include a plurality of vertical structures VS arranged along the first direction D1, and multiple columns of vertical structures VS may be arranged in each of the electrode structures SS. In embodiments, as Figure 1 As shown, nine vertical structures VS can be arranged in an electrode structure SS, but the inventive concept is not limited to this example. For example, the number of columns arranged in each electrode structure SS can be greater than, equal to, or less than nine. In an embodiment, the vertical structures VS constituting the odd-numbered columns can be arranged to be offset relative to the vertical structures VS constituting the even-numbered columns in a first direction D1.

[0034] like Figures 5A to 5C As shown, each vertical structure VS may include an insulating fill layer 139, a channel pattern CP, and a data storage layer DS. In an embodiment, the insulating fill layer 139 may be cylindrical in shape, and the channel pattern CP and the data storage layer DS may be sequentially disposed on the insulating fill layer 139. Alternatively, the insulating fill layer 139 may not be provided. The insulating fill layer 139 may include, for example, a silicon oxide layer.

[0035] The channel pattern CP can be formed of or may include a polycrystalline semiconductor material. The channel pattern CP can be undoped (e.g., intrinsic state) or lightly doped to have a first conductivity type or a second conductivity type. As an example, the channel pattern CP can be formed of or may include polycrystalline silicon. Alternatively, the channel pattern CP can be formed of or may include germanium or silicon-germanium. In some embodiments, the channel pattern CP may include a conductive layer (e.g., a metal, a conductive metal nitride, a silicide) or a nanostructure (e.g., a carbon nanotube or graphene). The shape of the channel pattern CP can resemble a tube with a closed bottom. In some embodiments, a semiconductor pattern can be formed between the channel pattern CP and the semiconductor substrate 100. As an example, the semiconductor pattern can be a single-crystal silicon pattern formed by an epitaxial process.

[0036] The data storage layer DS may include a barrier insulating layer adjacent to the horizontal electrode GP, a tunnel insulating layer adjacent to the channel pattern CP, and a charge storage layer between the barrier insulating layer and the tunnel insulating layer. The barrier insulating layer may be formed of at least one of a high-k dielectric material (e.g., alumina or hafnium oxide) or may include at least one of a high-k dielectric material (e.g., alumina or hafnium oxide). The barrier insulating layer may be a multilayer structure comprising multiple thin layers. As an example, the barrier insulating layer may include a first barrier insulating layer and a second barrier insulating layer, and each of the first and second barrier insulating layers may be formed of alumina and / or hafnium oxide or may include alumina and / or hafnium oxide. All the first and second barrier insulating layers may extend along the channel pattern CP or extend in a vertical direction, but in some embodiments, a portion of the first barrier insulating layer may extend into the region between the horizontal electrode GP and the insulating layer 120.

[0037] The charge storage layer can be a charge trapping layer or an insulating layer comprising conductive nanoparticles. The charge trapping layer can include, for example, a silicon nitride layer. The tunnel insulating layer can be formed of at least one of silicon oxide and a high-k dielectric material (e.g., hafnium oxide or aluminum oxide), or can include at least one of silicon oxide and a high-k dielectric material (e.g., hafnium oxide or aluminum oxide). The charge storage layer and the tunnel insulating layer can extend along the channel pattern CP or in a vertical direction. The data storage layer DS can be a tubular pattern open at the top and bottom.

[0038] The pad pattern 128 may be disposed on the upper part of the vertical structure VS. The pad pattern 128 may be formed of at least one of doped polysilicon and a metallic material, or may include at least one of doped polysilicon and a metallic material. The side surface of the pad pattern 128 may contact the inner surface of the data storage layer DS and the top surface of the channel pattern CP. The insulating layer 120 may include an uppermost insulating layer 121 covering the pad pattern 128. Hereinafter, the uppermost insulating layer 121 will be described as part of the insulating layer 120.

[0039] The cell array region CR may include an extension region ER, which is disposed adjacent to the peripheral circuit region PR. In the extension region ER, the horizontal electrodes GP may have exposed ends (e.g., pads) forming a stepped structure. In the extension region ER, the side surface of the end of each insulating layer 120 may be aligned with the side surface of the end of a corresponding horizontal electrode in the horizontal electrodes GP disposed below it.

[0040] In the extended region ER, a dummy vertical structure DVS can be provided to penetrate the electrode structure SS. In an embodiment, the dummy vertical structure DVS can be connected to the semiconductor substrate 100. The width of the dummy vertical structure DVS can be greater than the width of the vertical structure VS. Alternatively, the dummy vertical structure DVS can have substantially the same dimensions as the vertical structure VS. The dummy vertical structure DVS can have substantially the same stacked structure as the vertical structure VS and can comprise the same material as the vertical structure VS.

[0041] The insulating separator pattern 19 may be configured to penetrate some of the horizontal electrodes GP and extend in a first direction D1. In an embodiment, the insulating separator pattern 19 may be disposed between the vertical electrodes 140 to separate at least one of the horizontal electrodes GP serving as gate electrodes for a string select transistor in a second direction D2. For example, the insulating separator pattern 19 may be configured to penetrate the uppermost horizontal electrode and the second uppermost horizontal electrode among the horizontal electrodes GP. The insulating separator pattern 19 may be formed of at least one of a silicon oxide layer and a silicon nitride layer, or may include at least one of a silicon oxide layer and a silicon nitride layer.

[0042] In the extended region ER, a dummy partition pattern 142 may be provided between the vertical electrodes 140. The dummy partition pattern 142 may penetrate the electrode structure SS in the extended region ER. The dummy partition pattern 142 may be formed simultaneously with the vertical electrodes 140 and may include the same layer as the vertical electrodes 140. The dummy partition pattern 142 may extend in the first direction D1 and may be connected to the insulating partition pattern 19. The dummy partition pattern 142 may be formed of at least one of silicon oxide and silicon oxynitride, or may include at least one of silicon oxide and silicon oxynitride.

[0043] An interlayer insulating layer 131 can be provided to cover the extended region ER and the peripheral circuit region PR. The interlayer insulating layer 131 can be formed of a silicon oxide layer or may include a silicon oxide layer.

[0044] A peripheral transistor PT can be disposed on the semiconductor substrate 100 and in the peripheral circuit region PR. An upper interlayer insulating layer 131 can cover the peripheral transistor PT. The peripheral transistor PT may include a peripheral gate electrode PG and a peripheral impurity region PS adjacent to the peripheral gate electrode PG. The peripheral transistor PT can be a PMOS transistor and / or an NMOS transistor, and the conductivity type of the peripheral impurity region PS can be determined according to the type of transistor. In an embodiment, the peripheral impurity region PS can be an n-type impurity region. A lower interlayer insulating layer 130 can be disposed in the peripheral circuit region PR to cover the peripheral transistor PT. The lower interlayer insulating layer 130 can be disposed between the peripheral gate electrode PG and the upper interlayer insulating layer 131.

[0045] A first upper insulating layer 11 can be provided to cover the electrode structure SS and the upper interlayer insulating layer 131. First to third contacts CT1, CT2, and CT3 can be provided to penetrate the first upper insulating layer 11. As will be explained in the description of the manufacturing method, the first to third contacts CT1, CT2, and CT3 can be structures formed simultaneously by the same deposition process. The first to third contacts CT1, CT2, and CT3 can have top surfaces at the same horizontal level. For example, the top surfaces of the first to third contacts CT1, CT2, and CT3 can be at the same horizontal level as the top surface of the first upper insulating layer 11. The first to third contacts CT1, CT2, and CT3 can be formed of at least one of tungsten, titanium, and their nitrides, or can include at least one of tungsten, titanium, and their nitrides. For example, the first to third contacts CT1, CT2, and CT3 can be configured to have a bilayer structure including a titanium nitride layer and a tungsten layer.

[0046] The first contact CT1 can be connected to the end of the horizontal electrode GP in the extension region ER. The second contact CT2 can be connected to the upper part of the vertical electrode 140. The third contact CT3 can be connected to the peripheral transistor PT in the peripheral circuit region PR. As an example, the third contact CT3 can be connected to the peripheral gate electrode PG or the peripheral impurity region PS.

[0047] like Figures 1 to 3As shown, the second contact CT2 can have a different shape than the first contact CT1 and the third contact CT3. As an example, the first contact CT1 and the third contact CT3 can be circular or square with substantially the same width in the first direction D1 and the second direction D2, and the first width W1 of the second contact CT2 in the first direction D1 can be greater than the second width W2 in the second direction D2. For example, the second contact CT2 can be a strip or an ellipse with its major axis parallel to the first direction D1.

[0048] The second spacing distance d2 between the second contact elements CT2 in the first direction D1 can be greater than the first spacing distance d1 between the first contact elements CT1 in the first direction D1. As an example, the second spacing distance d2 can be approximately 10 to 20 times the first spacing distance d1. In embodiments, the second spacing distance d2 can be in the range of approximately 60 μm to approximately 120 μm. The first spacing distance d1 can be in the range of approximately 0.3 μm to approximately 0.11 μm.

[0049] The second upper insulating layer 12 can be disposed on the first upper insulating layer 11. The first interconnect structure 30 can be disposed in the second upper insulating layer 12. Figure 1 and Figure 3 As shown, when viewed in a plan view, the first interconnect structure 30 can have a grid shape. For example, the first interconnect structure 30 may include a first sub-interconnect line 31 extending in a first direction D1 and a second sub-interconnect line 32 extending in a second direction D2. The first sub-interconnect line 31 may overlap with the vertical electrode 140, respectively. The first sub-interconnect line 31 may be connected to the second contact CT2 and may be electrically connected to the vertical electrode 140 via the second contact CT2. The second sub-interconnect line 32 may overlap with two or more columns of the vertical structure VS. The vertical structure VS overlapping with the second sub-interconnect line 32 may be connected to the third interconnect line without the studs described below.

[0050] In the extended region ER, a first extended pad 35 and a first intermediate interconnect 38 may be disposed in the second upper insulating layer 12. The first extended pad 35 and the first intermediate interconnect 38 may be connected to the top surface of the first contact CT1. The first intermediate interconnect 38 may be used to apply voltage to the horizontal electrode GP through the first contact CT1. In the peripheral circuit region PR, a first peripheral pad 37 may be disposed in the second upper insulating layer 12. The first peripheral pad 37 may be connected to the top surface of the third contact CT3.

[0051] In an embodiment, each of the first interconnect structure 30, the first extended pad 35, the first intermediate interconnect line 38, and the first peripheral pad 37 may include a titanium nitride layer and a tungsten layer. The titanium nitride layer may be provided to cover the side and bottom surfaces of the tungsten layer.

[0052] The third upper insulating layer 13 and the fourth upper insulating layer 14 can be sequentially disposed on the second upper insulating layer 12. The first via V1 can be disposed in the third upper insulating layer 13. The second interconnect structure 40 can be disposed in the fourth upper insulating layer 14. For example... Figure 1 , Figure 2 and Figure 4 As shown, the second interconnect structure 40 may have a grid shape. In an embodiment, the second interconnect structure 40 may include a third sub-interconnect line 41 extending in a first direction D1 and a fourth sub-interconnect line 42 extending in a second direction D2. The third sub-interconnect line 41 may overlap with the first sub-interconnect line 31. The fourth sub-interconnect line 42 may overlap with the second sub-interconnect line 32. The fourth sub-interconnect line 42 may be electrically connected to the second sub-interconnect line 32 through a first via V1. In an embodiment, the first via V1 may not be provided between the third sub-interconnect line 41 and the first sub-interconnect line 31, but in some embodiments, the first via V1 may be provided between the third sub-interconnect line 41 and the first sub-interconnect line 31.

[0053] The second intermediate interconnect 46, the second extended pad 45, the second peripheral pad 47, and the third intermediate interconnect 48 can be disposed in the fourth upper insulating layer 14. In a plan view, the second intermediate interconnect 46 can be disposed on both sides of the second interconnect structure 40, and in a cross-sectional view, the second intermediate interconnect 46 can overlap with some vertical electrodes 140. The end of the second intermediate interconnect 46 can extend to the adjacent cell block. The second extended pad 45 can be disposed on the first extended pad 35 and in the extended region ER, and can be electrically connected to the first extended pad 35 through the first via V1. The second peripheral pad 47 can be electrically connected to the first peripheral pad 37 through the first via V1. The third intermediate interconnect 48 can be electrically connected to the first peripheral pad 37 in the extended region ER through the first via V1. The third intermediate interconnect 48 can be used to apply voltage to the horizontal electrode GP through the first contact CT1.

[0054] In an embodiment, each of the second interconnect structure 40, the second extended pad 45, the second intermediate interconnect line 46, the third intermediate interconnect line 48, and the second peripheral pad 47 may include a titanium layer, a titanium nitride layer, or a tungsten layer. As an example, the titanium nitride layer may cover the side and bottom surfaces of the tungsten layer, and the titanium layer may cover the side and bottom surfaces of the titanium nitride layer. The first via V1 and the components disposed thereon (e.g., the second interconnect structure 40, the second extended pad 45, the second intermediate interconnect line 46, the third intermediate interconnect line 48, or the second peripheral pad 47) may be formed using a dual-etching process.

[0055] Studs ST can be provided to penetrate the first upper insulating layer to the fourth upper insulating layers 11, 12, 13, and 14 and connect to the pad pattern 128 of the vertical structure VS. The studs ST can be individually connected to the vertical structures VS, but the studs ST may not be provided on some of the vertical structures VS that overlap with the first interconnect structure 30, as described above. The studs ST may comprise the same material as the second interconnect structure 40.

[0056] The fifth upper insulating layer 15 and the sixth upper insulating layer 16 can be sequentially disposed on the fourth upper insulating layer 14. A second via V2 can be disposed in the fifth upper insulating layer 15. Third interconnects 51 and 52 and a fourth interconnect 56 can be disposed in the sixth upper insulating layer 16. The third interconnects 51 and 52 can be electrically connected to the stud ST via the second via V2. The fourth interconnect 56 can be connected to the second interconnect structure 40 via the second via V2. The width of each fourth interconnect 56 in the first direction D1 can be greater than the width of each third interconnect 51 and 52 in the first direction D1. As an example, the width of each fourth interconnect 56 can be approximately 3 to approximately 8 times the width of each third interconnect 51 and 52. A pair of third interconnects 51 and 52 can be disposed in a row of a vertical structure VS arranged along the second direction D2. In this embodiment, the odd-numbered vertical structures of the vertical structures VS forming a row can be connected to the (3a) interconnect 51, and the even-numbered vertical structures of the vertical structures VS forming a row can be connected to the (3b) interconnect 52. The size of each second via V2 connected to the fourth interconnect 56 can be larger than the size of each second via V2 connected to the third interconnects 51 and 52, but the inventive concept is not limited to this example.

[0057] The upper interconnect 58 may be disposed in the sixth upper insulating layer 16. The upper interconnect 58 may be connected to the second intermediate interconnect 46 via the second via V2. As an example, the third interconnects 51 and 52, the fourth interconnect 56, and the upper interconnect 58 may be formed of copper or may include copper layers.

[0058] The vertical electrodes 140 can be electrically connected to each other using the first interconnect structure 30 and the second interconnect structure 40 according to the embodiments of the inventive concept. Furthermore, the first to third contacts CT1, CT2, and CT3 can be formed with top surfaces at the same horizontal level, which allows for a more efficient arrangement of the higher interconnect lines disposed on the first to third contacts CT1, CT2, and CT3.

[0059] Figure 6 , Figure 13 and Figure 15 This is a plan view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the inventive concept. Figure 7A and Figure 7BThey are along Figure 6 The cross-sectional view taken from lines A-A' and B-B'. Figure 14A and Figure 14B They are along Figure 13 The cross-sectional view taken from lines A-A' and B-B'. Figure 16B and Figure 16B They are along Figure 15 The cross-sectional view taken from lines A-A' and B-B'.

[0060] Reference Figure 6 , Figure 7A and Figure 7B A semiconductor substrate 100 comprising a cell array region CR and a peripheral circuit region PR can be provided. The cell array region CR may include an extension region ER, which is configured to be adjacent to the peripheral circuit region PR. As an example, the semiconductor substrate 100 may be a single-crystal silicon substrate. In an embodiment, the semiconductor substrate 100 may be doped to have a first conductivity type. Here, the first conductivity type may be p-type. A peripheral transistor PT may be formed on the peripheral circuit region PR. The formation of the peripheral transistor PT may include forming a peripheral impurity region PS and a peripheral gate electrode PG. The conductivity type of the peripheral impurity region PS may be determined according to the type of the peripheral transistor PT. After the peripheral transistor PT is formed, a lower interlayer insulating layer 130 may be formed to cover the peripheral transistor PT. In an embodiment, the lower interlayer insulating layer 130 may be formed of a silicon oxide layer or may include a silicon oxide layer.

[0061] A buffer layer 111 can be formed on the cell array region CR, and then a sacrificial layer and an insulating layer 120 can be formed alternately and repeatedly on the buffer layer 111. The buffer layer 111 can be a silicon oxide layer. In an embodiment, the buffer layer 111 can be formed by a thermal oxidation process. The sacrificial layer and the insulating layer 120 can be formed of different materials that have etch selectivity relative to each other. For example, the material of the insulating layer 120 can be selected to limit and / or prevent over-etching of the insulating layer 120 during the etching of the sacrificial layer using a specific etch formulation.

[0062] A vertical structure VS connected to the semiconductor substrate 100 can be formed to penetrate the sacrificial layer and the insulating layer 120. A dummy vertical structure DVS and the vertical structure VS can be formed in the extended region ER. The formation of the vertical structure VS may include forming a vertical via penetrating the sacrificial layer and the insulating layer 120 and exposing the semiconductor substrate 100 through an anisotropic etching process, and sequentially depositing a data storage layer DS, a channel pattern CP, and an insulating fill layer 139 to fill the vertical via. Each of the data storage layer DS, the channel pattern CP, and the insulating fill layer 139 can be formed by at least one of chemical vapor deposition, atomic layer deposition, and sputtering processes. The channel pattern CP can be formed to penetrate the data storage layer DS. The insulating fill layer 139 can be formed to completely fill the vertical via, in which the data storage layer DS and the channel pattern CP are formed. Subsequently, the upper portion of the insulating fill layer 139 and the channel pattern CP can be removed to form a vertically recessed region, and then a pad pattern 128 can be formed to fill the vertically recessed region, respectively. The pad pattern 128 may be formed of at least one of doped polysilicon and metal, or may include at least one of doped polysilicon and metal.

[0063] The uppermost insulating layer 121 can be formed to cover the pad pattern 128. Hereinafter, the uppermost insulating layer 121 will be described as part of the insulating layer 120. The sacrificial layer and the insulating layer 120 can be patterned to form a stepped structure on the extended region ER. Next, the upper interlayer insulating layer 131 can be formed to cover the cell array region CR and the peripheral circuit region PR. The upper interlayer insulating layer 131 can be formed of silicon oxide or may include silicon oxide.

[0064] Separating trenches 141 and 143 can be formed to penetrate the sacrificial layer and the insulating layer 120. Separating trenches 141 and 143 may include a first separating trench 141 and a second separating trench 143, the first separating trench 141 extending in a first direction D1 to pass through the cell array region CR, and the second separating trench 143 locally disposed within the extended region ER. Separating trenches 141 and 143 can be formed to expose the top surface of the semiconductor substrate 100. Separating trenches 141 and 143 can be formed by an anisotropic etching process.

[0065] The sacrificial layer can be replaced by a horizontal electrode GP. For example, the sacrificial layer exposed by the separating trenches 141 and 143 can be removed, and then the horizontal electrode GP can be formed in the empty area formed by removing the sacrificial layer. In an embodiment, an etching solution containing phosphoric acid can be used to perform the removal of the sacrificial layer. In an embodiment, a barrier insulating layer can be formed to conformally cover the empty area formed by removing the sacrificial layer before forming the horizontal electrode GP.

[0066] The dummy separation pattern 142 can be formed to fill the second separation trench 143. The dummy separation pattern 142 can be formed of a silicon oxide layer or may include a silicon oxide layer. Cell impurity regions SR can be formed in the upper portion of the semiconductor substrate 100 exposed through the first separation trench 141. The cell impurity regions SR can extend in a first direction D1 and can be spaced apart from each other in a second direction D2. The cell impurity regions SR can have a second conductivity type different from the conductivity type of the semiconductor substrate 100. The second conductivity type can be, for example, n-type.

[0067] A separator pattern 145 and a vertical electrode 140 may be formed in a first separator trench 141, wherein the vertical electrode 140 may penetrate the separator pattern 145 and be connected to the semiconductor substrate 100. The vertical electrode 140 may be a plate-like pattern extending in a first direction D1. In an embodiment, the separator pattern 145 may be formed in the shape of a spacer covering the side surface of the separator trench 141, and the vertical electrode 140 may be formed to fill the separator trench 141 in which the separator pattern 145 is formed. In some embodiments, the formation of the vertical electrode 140 may include forming a contact hole penetrating the separator pattern 145 and filling the contact hole with a conductive material. The separator pattern 145 may be formed to include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The vertical electrode 140 may be formed to include at least one of doped polysilicon, a metal, and a conductive metal nitride.

[0068] In the case where the vertical electrode 140 comprises doped polysilicon, the vertical electrode 140 may, for example, be doped in situ to have a second conductivity type different from that of the semiconductor substrate 100. The second conductivity type may, for example, be n-type.

[0069] The first upper insulating layer 11 may be formed to cover both the cell array region CR and the peripheral circuit region PR. In an embodiment, the first upper insulating layer 11 may be formed of silicon oxide or may include silicon oxide. The first to third contacts CT1, CT2 and CT3 may be formed to penetrate the first upper insulating layer 11. The method of forming the first to third contacts CT1, CT2 and CT3 will be described in more detail below.

[0070] Figure 8 , Figure 9 and Figure 10 This illustrates an embodiment based on the inventive concept. Figure 7A and Figure 7B Enlarged cross-sectional views of parts e1, e2, and e3. (Refer to...) Figure 7A , Figure 7B and Figure 8A first hole S1 can be formed to penetrate the first upper insulating layer 11 and expose the vertical electrode 140. A second hole S2 can be formed to penetrate the first upper insulating layer 11 and the upper interlayer insulating layer 131 and expose the horizontal electrode GP. The first hole S1 and the second hole S2 can be formed simultaneously by the same etching process.

[0071] Reference Figure 7A , Figure 7B and Figure 9 A spacer layer can be formed to cover the first hole S1 and the second hole S2. The spacer layer can be formed of silicon nitride or may include silicon nitride. Subsequently, a third hole S3 can be formed to partially expose the peripheral transistor PT. In an embodiment, the third hole S3 can be formed to penetrate the first upper insulating layer 11, the upper interlayer insulating layer 131, the lower interlayer insulating layer 130, and the peripheral gate capping layer PH to expose the peripheral gate electrode PG. An anisotropic etching process can be performed to remove the lower portion of the spacer layer, thus forming a spacer pattern SP to expose the top surface of the vertical electrode 140 and the top surface of the horizontal electrode GP. The formation of the spacer pattern SP may include a cleaning process.

[0072] A barrier layer 73 can be formed to conformally cover the first to third holes S1, S2, and S3. The barrier layer 73 can be formed of, for example, at least one of titanium, tantalum, and their conductive nitrides, or can include, for example, at least one of titanium, tantalum, and their conductive nitrides. In an embodiment, the barrier layer 73 can be formed by sequentially stacking a titanium layer and a titanium nitride layer.

[0073] Reference Figure 7A , Figure 7B and Figure 10 A metal layer 74 can be formed on the barrier layer 73 to fill the first to third holes S1, S2 and S3, and then a planarization process can be performed to form the first to third contacts CT1, CT2 and CT3. The metal layer 74 can be formed of, for example, tungsten or may include tungsten.

[0074] Figure 11 and Figure 12 This illustrates another embodiment based on the inventive concept. Figure 7A and Figure 7B Enlarged cross-sectional views of parts e1, e2, and e3. For the sake of brevity, previously described elements may be identified by the same reference numerals without repeating their descriptions.

[0075] Reference Figure 7A , Figure 7B and Figure 11 The first hole S1, the second hole S2, and the third hole S3 can be formed simultaneously using the same etching process. (Refer to...) Figure 7A , Figure 7B and Figure 12A barrier layer 73 and a metal layer 74 can be sequentially formed to fill the first hole S1, the second hole S2, and the third hole S3. In this embodiment, references can be omitted. Figures 8 to 10 The formation of the spacer pattern SP is described.

[0076] Reference Figure 13 , Figure 14A and Figure 14B A second upper insulating layer 12 may be formed on the first upper insulating layer 11. The second upper insulating layer 12 may be formed of, for example, silicon oxide or may include silicon oxide. A first interconnect structure 30 may be formed in the second upper insulating layer 12. A first extended pad 35, a first peripheral pad 37, and a first intermediate interconnect 38 may be formed together with the first interconnect structure 30 in the second upper insulating layer 12. The first interconnect structure 30, the first extended pad 35, the first peripheral pad 37, and the first intermediate interconnect 38 may be referred to as a first upper conductive layer. The formation of the first upper conductive layer may include patterning the second upper insulating layer 12 to form recessed regions, and filling the recessed regions with a conductive material. The first upper conductive layer may include a conductive metal nitride layer (e.g., a titanium nitride layer or a tantalum nitride layer) and a metal layer (e.g., a tungsten layer). In embodiments, the first upper conductive layer may have a bilayer structure including a titanium nitride layer and a tungsten layer.

[0077] Reference Figure 15 , Figure 16A and Figure 16B A third upper insulating layer 13 and a fourth upper insulating layer 14 may be sequentially formed on the second upper insulating layer 12. The third upper insulating layer 13 and the fourth upper insulating layer 14 may be formed of, for example, silicon oxide or may include, for example, silicon oxide. A first via V1 may be formed in the third upper insulating layer 13, and a second interconnect structure 40, a second intermediate interconnect line 46, a second extended pad 45, a second peripheral pad 47, and a third intermediate interconnect line 48 may be formed in the fourth upper insulating layer 14. The second interconnect structure 40, the second intermediate interconnect line 46, the second extended pad 45, the second peripheral pad 47, and the third intermediate interconnect line 48 may be referred to as the second upper conductive layer.

[0078] The first via V1 and the second upper conductive layer can be formed using a dual etching process (specifically, using the same deposition process). For example, the process of forming the first via V1 and the second upper conductive layer may include forming a first recessed region and a second recessed region that penetrate the third upper insulating layer 13 and the fourth upper insulating layer 14, respectively, and then simultaneously filling the first and second recessed regions using a deposition process. In an embodiment, the deposition process may include sequentially forming a first metal layer, a conductive metal nitride layer, and a second metal layer. The first via V1 and the second upper conductive layer may have a three-layer structure including a titanium layer, a titanium nitride layer, and a tungsten layer. In this case, compared to a two-layer structure, the first via V1 and the second upper conductive layer may further include a titanium layer. Alternatively, the first via V1 and the second upper conductive layer may be formed using a separate deposition process.

[0079] A stud ST can be formed to penetrate the first upper insulating layer to the fourth upper insulating layers 11, 12, 13, and 14 and connect to the pad pattern 128. Forming the stud ST may include forming through-holes penetrating the first upper insulating layer to the fourth upper insulating layer 11, 12, 13, and 14, and filling the through-holes with a conductive material. The stud ST may include a conductive metal nitride layer and / or a metal layer. As an example, the stud ST may include a titanium nitride layer and a tungsten layer. The stud ST can be formed using the same deposition process as the second upper conductive layer and can be formed from the same material as the second upper conductive layer.

[0080] Refer again Figure 1 , Figure 5A , Figure 5B and Figure 5C A fifth upper insulating layer 15 may be formed on the fourth upper insulating layer 14. As an example, the fifth upper insulating layer 15 may be formed of silicon oxide or may include silicon oxide. A second via V2 may be formed in the fifth upper insulating layer 15. The second via V2 may include a conductive metal nitride layer and / or a metal layer. A sixth upper insulating layer 16 may be formed on the fifth upper insulating layer 15. As an example, the sixth upper insulating layer 16 may be formed of silicon oxide or may include silicon oxide. Third interconnects 51 and 52 and a fourth interconnect 56 may be formed in the sixth upper insulating layer 16. As an example, the third interconnects 51 and 52 and the fourth interconnect 56 may include a copper layer.

[0081] Figure 17This is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the inventive concept. For brevity, previously described elements may be identified by the same reference numerals without repeating their description. A first peripheral circuit region PR1 and a second peripheral circuit region PR2 may be arranged such that a cell array region CR is interposed therebetween. The first peripheral circuit region PR1 and the second peripheral circuit region PR2 may be, for example, a decoder region. A first peripheral transistor PT1 may be disposed on the first peripheral circuit region PR1, and a second peripheral transistor PT2 may be disposed on the second peripheral circuit region PR2. The first peripheral transistor PT1 may be electrically connected to the second peripheral transistor PT2 via an upper interconnect 57 and a fourth intermediate interconnect 49. The fourth intermediate interconnect 49 may be disposed on the cell array region CR and may overlap with a plurality of vertical structures VS. The fourth intermediate interconnect 49 may be connected to the upper interconnect 57 via a second via V2. The upper interconnect 57 may be electrically connected to the first peripheral transistor PT1 and the second peripheral transistor PT2 via the second via V2, a second peripheral pad 47, a first via V1, a first peripheral pad 37, and a third contact CT3.

[0082] Figure 18 This is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the inventive concept. In this embodiment, the cell array region may be disposed on the peripheral circuit region. As an example, the horizontal electrode GP may be disposed on the intermediate conductive pattern 201, and the vertical structure VS and the vertical electrode 140 may be connected to the upper part of the intermediate conductive pattern 201. The lower insulating layer 270 may be disposed between the semiconductor substrate 100 and the intermediate conductive pattern 201, and the peripheral transistor PT may be disposed in the lower insulating layer 270. The peripheral transistor PT may be connected to the cell array region via the fourth contact CT4 and the peripheral interconnect 290. At least one of the vertical electrodes 140 may be configured to penetrate the intermediate conductive pattern 201 and may be connected to the peripheral interconnect 290, but the inventive concept is not limited to this example.

[0083] According to embodiments of the inventive concept, an interconnection structure can be configured to easily connect vertical electrodes to each other.

[0084] Although exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that variations in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor memory device, comprising: Substrate; Multiple electrode structures are located on the substrate, each of the multiple electrode structures including horizontal electrodes stacked on the substrate; A vertical electrode, which is located between the plurality of electrode structures and extends along the horizontal electrode; A first contact element is connected to the horizontal electrode at the end of the plurality of electrode structures; The second contact is connected to the upper part of the vertical electrode; as well as A first interconnect structure is connected to the top surface of the second contact, the first interconnect structure including a first sub-interconnect line and a second sub-interconnect line. The first sub-interconnect extends in a first direction and contacts the top surface of the second contact. The second sub-interconnect extends in a second direction intersecting the first direction, and the second sub-interconnect contacts the first sub-interconnect. The first sub-interconnect and the second sub-interconnect are located at the same horizontal height relative to the substrate.

2. The semiconductor memory device according to claim 1, wherein, The top surface of the first contact and the top surface of the second contact are at the same horizontal height.

3. The semiconductor memory device according to claim 1, wherein, Each of the second contacts has a width in the first direction that is greater than its width in the second direction.

4. The semiconductor memory device according to claim 1, wherein, The spacing between the second contacts in the first direction is greater than the spacing between the first contacts in the first direction.

5. The semiconductor memory device according to claim 4, wherein, The spacing between the second contacts in the first direction is 10 to 20 times the spacing between the first contacts in the first direction.

6. The semiconductor memory device according to claim 1, wherein, When viewed in a plan view, the first interconnect structure has a grid shape.

7. The semiconductor memory device according to claim 1, further comprising: A vertical structure that penetrates the plurality of electrode structures, the vertical structure including a channel pattern, wherein The first sub-interconnect overlaps with the horizontal electrode, and The second sub-interconnect line overlaps with the vertical structure.

8. The semiconductor memory device according to claim 7, further comprising: A second interconnect structure is located on top of the first interconnect structure, wherein The second interconnect structure includes a third sub-interconnect and a fourth sub-interconnect. The third sub-interconnect line overlaps with the first sub-interconnect line and extends parallel to the first sub-interconnect line. The fourth sub-interconnect overlaps with the second sub-interconnect and extends parallel to the second sub-interconnect.

9. The semiconductor memory device according to claim 8, further comprising: The first via connects the second sub-interconnect to the fourth sub-interconnect.

10. The semiconductor memory device of claim 8, further comprising: A stud, which is coupled to the upper part of the vertical structure. The top surface of the second interconnect structure and the top surface of the stud are located at the same horizontal height.

11. The semiconductor memory device of claim 10, further comprising: The second via is located on the second interconnect structure; A third interconnect line extends in the second direction and is connected to the stud through the second via; as well as A fourth interconnect line extends in the second direction and is connected to the second interconnect structure through the second via, wherein The width of each of the fourth interconnects in the first direction is greater than the width of each of the third interconnects in the first direction.

12. The semiconductor memory device according to claim 1, further comprising: Peripheral transistors; as well as The third contact element, in which The semiconductor memory device includes a cell array region and a peripheral circuit region. The plurality of electrode structures are located in the unit array region. The peripheral transistor is located in the peripheral circuit region. The third contact is connected to the peripheral transistor, and The top surface of the third contact is at the same horizontal height as the top surface of the second contact.

13. The semiconductor memory device according to claim 1, wherein, The first contact and the second contact include spacer patterns surrounding the side surfaces of the first contact and the second contact.

14. The semiconductor memory device of claim 13, further comprising: Peripheral transistors; An interlayer insulating layer that covers the peripheral transistor; as well as The third contact penetrates the interlayer insulating layer and connects to the peripheral transistor, wherein The semiconductor memory device includes a cell array region and a peripheral circuit region. The electrode structure is located in the unit array region. The peripheral transistor is located in the peripheral circuit region. The third contact includes a metal layer and a barrier layer covering the side surface of the metal layer, and The barrier layer contacts the interlayer insulation layer.

15. A semiconductor memory device, comprising: Substrate; Multiple electrode structures are located on the substrate, each of the multiple electrode structures including horizontal electrodes stacked on the substrate; A vertical electrode is located between the plurality of electrode structures and extends along the horizontal electrode, the vertical electrode extending in a first direction; A first contact element is connected to the horizontal electrode at the end of the plurality of electrode structures; The second contact is connected to the upper part of the vertical electrode. The top surface of the second contact is at the same horizontal height as the top surface of the first contact, and the spacing between the second contacts in the first direction is greater than the spacing between the first contacts in the first direction. as well as A first interconnect structure is connected to the top surface of the second contact. The first interconnect structure includes a first sub-interconnect line and a second sub-interconnect line. The first sub-interconnect line extends in the first direction and contacts the top surface of the second contact. The second sub-interconnect line extends in a second direction that intersects the first direction and contacts the first sub-interconnect line. The first sub-interconnect line and the second sub-interconnect line are located at the same horizontal height relative to the substrate.

16. The semiconductor memory device of claim 15, further comprising: A second interconnect structure is located on top of the first interconnect structure, wherein The second interconnect structure includes a third sub-interconnect and a fourth sub-interconnect. The third sub-interconnect overlaps with the first sub-interconnect and extends parallel to the first sub-interconnect, and The fourth sub-interconnect overlaps with the second sub-interconnect and extends parallel to the second sub-interconnect.

17. The semiconductor memory device of claim 15, further comprising: Peripheral transistors; as well as The third contact is connected to the peripheral transistor, wherein The semiconductor memory device includes a cell array region and a peripheral circuit region. The plurality of electrode structures are located in the unit array region. The peripheral transistor is located in the peripheral circuit region, and The top surface of the third contact is at the same horizontal height as the top surface of the second contact.

18. The semiconductor memory device of claim 15, further comprising: Peripheral transistors; An interlayer insulating layer that covers the peripheral transistor; as well as The third contact penetrates the interlayer insulating layer and connects to the peripheral transistor, wherein The first contact and the second contact include spacer patterns surrounding the side surfaces of the first contact and the second contact; The semiconductor memory device includes a cell array region and a peripheral circuit region. The plurality of electrode structures are located in the unit array region. The peripheral transistor is located in the peripheral circuit region. The third contact includes a metal layer and a barrier layer covering the side surface of the metal layer, and The barrier layer contacts the interlayer insulation layer.

19. A semiconductor memory device, comprising: The substrate includes a cell array region and a peripheral circuit region; Multiple electrode structures are located on the substrate, each of the multiple electrode structures including horizontal electrodes stacked on the substrate; A peripheral transistor located in the peripheral circuit region; A vertical structure that penetrates the plurality of electrode structures; A stud, which is connected to the upper part of the vertical structure; A vertical electrode is located between the plurality of electrode structures and extends along the horizontal electrode in a first direction; A first contact element is connected to the horizontal electrode at the end of the plurality of electrode structures; The second contact is connected to the upper part of the vertical electrode; Extended pads are connected to the top surface of the first contact; A third contact is connected to the peripheral transistor, and the top surface of the third contact is at the same horizontal height as the top surfaces of the first contact and the second contact. The peripheral pads are connected to the top surface of the third contact. A first interconnect structure is connected to the top surface of the second contact, and the top surface of the first interconnect structure is at the same horizontal height as the top surface of the extended pad and the top surface of the peripheral pad. as well as A second interconnect structure is located on the first interconnect structure and connected to the first interconnect structure through a first via. The top surface of the second interconnect structure is at the same horizontal level as the top surface of the stud. The first interconnect structure includes a first sub-interconnect line and a second sub-interconnect line. The first sub-interconnect line extends in the first direction and contacts the top surface of the second contact. The second sub-interconnect line extends in the second direction intersecting the first direction and connects the first sub-interconnect lines to each other. The first sub-interconnect line and the second sub-interconnect line are located at the same horizontal height relative to the substrate.

20. The semiconductor memory device of claim 19, wherein, The spacing between the second contacts in the first direction is greater than the spacing between the first contacts in the first direction.

21. The semiconductor memory device of claim 19, wherein The second interconnect structure includes a third sub-interconnect and a fourth sub-interconnect. The third sub-interconnect overlaps with the first sub-interconnect and extends parallel to the first sub-interconnect, and The fourth sub-interconnect overlaps with the second sub-interconnect and extends parallel to the second sub-interconnect.

22. The semiconductor memory device of claim 19, further comprising: The second via is located on the second interconnect structure; A third interconnect line extends in a second direction intersecting the first direction and is connected to the stud through the second via; as well as A fourth interconnect line extends in the second direction and is connected to the second interconnect structure through the second via. Wherein, the width of each of the fourth interconnects in the first direction is greater than the width of each of the third interconnects in the first direction.

23. A method for manufacturing a semiconductor memory device, comprising: A plurality of electrode structures are formed on a substrate, each of the plurality of electrode structures comprising horizontal electrodes sequentially stacked on the substrate; A vertical structure is formed that penetrates the electrode structure and includes a channel pattern; A vertical electrode is formed between the plurality of electrode structures, and the vertical electrode extends along the horizontal electrode; A first contact element connected to the horizontal electrode is formed at the end of the plurality of electrode structures; as well as A second contact is formed, connected to the upper part of the vertical electrode; the formation of the second contact and the formation of the first contact are performed simultaneously. The method further includes forming a first interconnect structure connected to the top surface of the second contact, the first interconnect structure including a first sub-interconnect line and a second sub-interconnect line, the first sub-interconnect line extending in a first direction and contacting the top surface of the second contact, the second sub-interconnect line extending in a second direction intersecting the first direction, the second sub-interconnect line contacting the first sub-interconnect line, and the first sub-interconnect line and the second sub-interconnect line being located at the same horizontal height relative to the substrate.

24. The method of claim 23, further comprising: An extended pad is formed that connects to the top surface of the first contact. The first interconnect structure and the extended pad are formed simultaneously.

25. The method of claim 23, further comprising: A peripheral transistor and a third contact are formed in the peripheral circuit region of the semiconductor memory device, wherein... The peripheral transistor is connected to the third contact. The semiconductor memory device includes a cell array region and a peripheral circuit region. The plurality of electrode structures are formed in the unit array region. The third contact and the second contact are formed simultaneously.

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