Charge balanced power device and method for manufacturing a charge balanced power device

Abstract

Embodiments of the present disclosure relate to charge balanced power devices and methods for manufacturing charge balanced power devices. A charge balanced power device includes a semiconductor body having a first conductivity type. A trench gate extends in the semiconductor body from a first surface toward a second surface. A body region has a second conductivity type opposite the first conductivity type and faces the first surface of the semiconductor body and extends on first and second sides of the trench gate. A source region having the first conductivity type extends in the body region and faces the first surface of the semiconductor body. A drain terminal extends on the second surface of the semiconductor body. The device further includes first and second columnar regions having a second conductivity that extend in the semiconductor body adjacent the first and second sides of the trench gate and are spaced apart from the body region and spaced apart from the drain terminal.

Description

Technical Field

[0001] This disclosure relates to a charge-balanced power device and a method for manufacturing the charge-balanced power device. Background Technology

[0002] This disclosure specifically, but not exclusively, relates to vertically conducting power devices (e.g., power MOS devices or IGBT (Insulated Gate Bipolar Transistor) type devices or BJT (Bipolar Junction Transistor) devices or bipolar diodes or Schottky diodes), and the following description relates to this field of application only for the purpose of simplifying its illustration.

[0003] Vertical current MOSFET devices are used in a variety of applications that typically require low heat dissipation, even when operating under high current conditions. In practice, these devices should have low on-state source-drain resistance (i.e., low Rdson) while being able to withstand high reverse bias voltage (high BVdss).

[0004] In vertical current devices, the requirements for the two parameters mentioned above (Rdson and BVdss) conflict. To obtain a high reverse voltage, it is generally considered necessary to increase the thickness of the semiconductor substrate carrying the current (i.e., by increasing the thickness of the epitaxial layer grown on the substrate) and / or increase the resistivity of the epitaxial layer itself. In either case, there is an increase in Rdson because the increase in thickness requires a longer current path in the on-state, while the higher resistivity of the epitaxial layer leads to higher resistance to current flow.

[0005] To reduce the source-drain resistance in the on-state, a pillar structure can be used that increases the bulk-drain boundary, allowing full utilization of the epitaxial layer volume. This technique enables the use of more heavily doped epitaxial layers, resulting in lower resistivity at the same reverse voltage, thereby reducing the Rdson component (defined below as the on-state epitaxial resistance Repi) due to the epitaxial layer.

[0006] This type of structure presupposes the creation of trench gate terminals, which are separated from each other by P-type pillars, for example, as... Figure 1 As shown in the diagram.

[0007] In particular, Figure 1The invention relates to an N-channel device 1 having an epitaxial layer 3a grown on a substrate 3b, both being N-type; the epitaxial layer 3a accommodates a P-type pillar 2 beneath a body region 4. The body region 4 is P-type and includes a doped portion (P+) to facilitate electrical contact. A source region 5 is formed in electrical contact with the body region 4, while a gate region 6 extends in depth within the epitaxial layer 3a between the body regions 4. Drain metallization extends on the side of the substrate 3b opposite to the side on which the epitaxial layer 3a extends.

[0008] Gate region 6 includes a metallized region 6a completely surrounded by a corresponding gate oxide layer 6b. Metallized region 8 is electrically connected to source region 5 and body region 4 (partially 4a), and is electrically insulated from gate region 6 via gate oxide layer 6b.

[0009] In devices with columnar structures, charge balance or charge compensation can be achieved between the dopant of the P-type pillar 2 and the charge of the N-type epitaxial layer 3a, so that the total charge of pillar 2 relative to epitaxial layer 3a will be equal and have opposite signs. Charge balance alone is insufficient. Additionally, the charge of epitaxial layer 3a (N) equal to the charge of pillar 2 (P) should be included within certain values ​​(depending on the 3D structure of the device). These conditions ensure complete depletion of free carriers in both epitaxial layer 3a and pillar 2, providing a carrier-free region that acts as an insulating layer. This enables high reverse voltage values ​​(breakdown voltages), where the electric spread field has a profile that runs through the region including epitaxial layer 3a and pillar 2, and this profile is virtually uniform in both amplitude and direction. In particular, the device can be biased so that the electric field approaches the critical electric field, which is the maximum electric field that the PN junction can withstand at the interface, beyond which avalanche conduction (breakdown) is triggered.

[0010] Using the concept of charge balance, a high concentration of dopant can be selected in epitaxial layer 3a, which is properly balanced by the dopant in the pillars. However, this selection has limitations because calibrating the pillar spacing to ensure that the entire epitaxial region (including pillar 2) is completely depleted is crucial.

[0011] Another type of charge-balancing device can be obtained by replacing the pillars with P-type doping with MOS capacitors. Figure 2A and Figure 2B The corresponding technical solutions for implementing superjunction VDMOS 1' and 1" are shown respectively. Figure 2A and Figure 2B The diagram in the middle is related to Figure 1 The same elements are designated by the same reference numerals and will not be described again below.

[0012] Similar to a PN junction, when a MOS capacitor is negatively biased relative to the epitaxial layer, a depletion region is induced in the epitaxial layer 3a. The fixed positive charge of ionized donor atoms in the depletion region cancels out the negative charge (electrons) on the conductive field plate. Unlike the charge balance in a PN junction, in a superjunction VDMOS, the capacitor with buried electrode 11 ( Figure 2A This electrode 11 is used to induce depletion in the drift region of the epitaxial layer 3a. Typically, this electrode 11 is provided buried beneath the gate metallization 6a and completely surrounded by the oxide layer 6b (a solution also known as a "split gate trench"), or provided using a buried field plate 14 in a dual-trench design 16. Figure 2B (The solution shown in the diagram).

[0013] exist Figure 2A and Figure 2B In both embodiments, the total charge of the epitaxial layer 3a should meet the charge balance criterion; that is, the drift region should be completely depleted before the vertical junction formed by the host, epitaxial layer and substrate (reference numerals 4, 3a and 3b, respectively) reaches its critical electric field and establishes carrier transport through the avalanche effect.

[0014] In addition, Figure 2A and Figure 2B In the two cases shown, polysilicon electrodes 11 and 14 are electrically connected to the lowest potential, i.e., the source potential. Figure 2A From a manufacturing perspective, this aspect is particularly complex in the proposed solution. The gate electrode and the field plate must coexist within the same trench, but they must be electrically insulated. Furthermore, it is important to intermittently interrupt the gate electrode to make contact on the field plate. This complicates the overall system's fabrication and reliability.

[0015] Unlike superjunctions with PN junctions (where the P-type charge must meet a charge balance criterion), in MOS-inductive superjunctions, the only requirement is that the field plate insulation withstands the full clamping voltage of the dielectric at the bottom of the trench through which the device passes, a criterion that fixes the oxide thickness in the range of a few micrometers.

[0016] Therefore, it is important to pay special attention to preventing the thinning of the bottom corners of the groove and to prevent the formation of defects caused by stress along the edges and bottom corners of the groove.

[0017] In examples of prior art with field plates, the horizontal dimension of the trench will increase with increasing breakdown voltage, while the internal polysilicon electrode forces an additional dimension increase.

[0018] In summary, the trenches come to exhibit a horizontal dimension exceeding the epitaxial portion included between the trenches. Clearly, this causes greater consumption in the horizontal region of the final device, which does not contribute to conduction and should therefore be considered parasitic. Summary of the Invention

[0019] also, Figure 2A The solution is limited by the parasitic capacitance that forms between the buried field plate and the drain terminal below (which is charged and discharged every time the device is turned on and off, resulting in a significant drawback in terms of power consumption and delay).

[0020] In summary, it is believed that an alternative solution with known solutions is needed, which would be able to overcome the above-mentioned disadvantages in order to further reduce the on-state source-drain resistance (Rdson) without negatively affecting the breakdown voltage.

[0021] According to this disclosure, a charge-balanced power device and a process for manufacturing the charge-balanced power device are provided.

[0022] In one or more embodiments, a charge-balanced power device is provided, comprising a semiconductor body having a first conductivity type. The semiconductor body has a first surface and a second surface opposing each other along a first direction. A trench gate extends in the semiconductor body from the first surface toward the second surface. A body region has a second conductivity type opposite to the first conductivity type, and the body region faces the first surface of the semiconductor body and extends on a first side and a second side of the trench gate. The first side and the second side are opposite each other along a second direction transverse to the first direction. A source region having the first conductivity type extends in the body region and faces the first surface. A drain terminal extends on the second surface of the semiconductor body. A first columnar region and a second columnar region having the second conductivity type extend adjacent to the first side and the second side of the trench gate, respectively, in the semiconductor body, and the first columnar region and the second columnar region are spaced apart from the body region and spaced apart from the drain terminal.

[0023] In one or more embodiments, a process for manufacturing a charge-balanced power device is provided, the process comprising: forming a trench gate in a semiconductor body having a first conductivity type and having a first surface and a second surface opposite to each other along a first direction, the trench gate extending from the first surface toward the second surface; forming a body region in the semiconductor body on a first side and a second side of the trench gate, the first side and the second side of the trench gate being opposite to each other along a second direction transverse to the first direction, the body region facing the first surface of the semiconductor body and having a second conductivity type opposite to the first conductivity type; forming a source region having the first conductivity type in the body region and facing the first surface; forming a drain terminal on the second surface of the semiconductor body; and forming a first columnar region and a second columnar region having the second conductivity type adjacent to the first side and the second side of the trench gate in the semiconductor body, the first columnar region and the second columnar region being spaced apart from the body region and spaced apart from the drain terminal.

[0024] In one or more embodiments, a device is provided comprising a substrate having a first conductivity type. The substrate has opposing first and second surfaces. An epitaxial layer is disposed on the first surface of the substrate, and the epitaxial layer has a first conductivity type. A trench gate extends toward the substrate into the epitaxial layer. A first pillar-shaped region and a second pillar-shaped region are disposed on opposing sides of the trench gate in the epitaxial layer and spaced apart from the first surface of the substrate. The first pillar-shaped region and the second pillar-shaped region have a second conductivity type opposite to the first conductivity type. Attached Figure Description

[0025] To better understand this disclosure, embodiments thereof will now be described by way of non-limiting examples and with reference to the accompanying drawings, in which:

[0026] Figure 1 , Figure 2A and Figure 2B These are the corresponding cross-sectional views of a known power MOS device;

[0027] Figure 3 This is a cross-sectional view of an example embodiment of a MOS device according to the present disclosure;

[0028] Figures 4-12 yes Figure 3 A cross-sectional view of half of the device during successive manufacturing steps;

[0029] Figure 13 This is a cross-sectional view of another example of a MOS device according to an embodiment of the present disclosure; and

[0030] Figure 14A and Figure 14B yes Figure 13A cross-sectional view of half of the device during an intermediate manufacturing step. Detailed Implementation

[0031] Figure 3 A portion of a charge-compensated MOS device 20 is shown in a triaxial system (Cartesian system) with mutually orthogonal axes X, Y, and Z.

[0032] The MOS device 20 includes an N-type epitaxial layer 22 (e.g., silicon) covering an N+ type (e.g., also silicon) substrate 21. The epitaxial layer 22 extends along the Z-axis between an upper surface or face 22a and a lower surface or face 22b, which are opposite each other along the Z-axis. The thickness of the epitaxial layer 22, measured in the Z-direction between the upper surface 22a and the lower surface 22b, is, for example, between 6 μm and 13 μm. The epitaxial layer 22 is doped (e.g., at 5.10 μm to 10 μm). 16 cm -3 Up to 1.5·10 16 cm -3 The resistivity of the epitaxial layer 22 is designed to be between 0.15 Ω·cm and 0.35 Ω·cm within a certain range.

[0033] The lower surface 22b is in direct contact with the upper surface 21a of the substrate 21, while the lower surface 21b of the substrate 21 (opposite to surface 21a along the Z-axis) is in contact with the drain metallization 24. Therefore, the substrate 21 and the drain metallization 24 together form the drain terminal of the MOS device 20. Thus, the MOS device 20 is a vertical channel device.

[0034] The MOS device 20 also includes one or more trench-type gate regions 28 (in Figure 3 Two gate regions 28 are illustrated by way of example. In particular, each gate region 28 includes a gate conductive region 28a completely surrounded by a corresponding gate dielectric layer 28b. The gate conductive region 28a may be, for example, a metallic material or doped polysilicon. The gate dielectric layer 28b may be, for example, an oxide, such as SiO2.

[0035] As an example, each trench accommodating the corresponding gate region 28 has a depth (between 4 μm and 10 μm) measured along the Z direction from the surface 22a, and a width (between 0.5 μm and 1.5 μm) measured along the X direction. Along the X direction, the distance (also referred to as the pitch) between the gate region 28 and the gate region 28 immediately following (or preceding) it is, for example, between 1.2 μm and 4 μm.

[0036] In each gate region 28, a gate dielectric layer 28b extends along the Z-axis at a depth in the epitaxial layer 22 to completely cover the walls and bottom of the corresponding trench. Each gate conductive region 28a extends along the Z-axis at a depth in the epitaxial layer 22 and is electrically insulated from the epitaxial layer 22 by the gate dielectric layer 28b. The thickness of each gate conductive region 28a, measured along the Z-direction, is, for example, between 0.4 μm and 1.1 μm. Each gate conductive region 28a extends between its upper and lower sides; in one embodiment, the upper side of each gate conductive region 28a is aligned with surface 22a such that the lower side of each gate conductive region 28a reaches a depth in the corresponding trench that is between 0.4 μm and 1.1 μm from surface 22a.

[0037] The P-type body region 25 extends within the epitaxial layer 22 alongside each gate region 28 (in the X direction) and faces the upper surface 22a of the epitaxial layer 22. The maximum depth reached by each body region 25 in the epitaxial layer 22 in the Z direction is equal to or less than the depth reached by each gate conductive region 28a (i.e., in a non-limiting example, equal to or less than 0.4 μm to 1.1 μm).

[0038] In a manner known per se, the main body region 25 also accommodates an N-type source region 26 facing the upper surface 22a.

[0039] Electrical contact regions (e.g., metallized regions) 27 extend over and are in electrical contact with the body region 25 and the source region 26 to bias them during use.

[0040] P-type columnar regions 30 extend in the epitaxial layer 22 to face each gate region 28 laterally. In other words, the columnar regions 30 extend along the X-direction-opposite sides of each gate region 28. Specifically, the columnar regions 30 are bordered and adjacent to the gate dielectric layer 28b of the respective gate region 28. In the active region (i.e., the region forming the conductive channel in use), the columnar regions 30 extend at a distance (along the Z-direction) from both the upper body region 25 and the lower drain terminal.

[0041] In particular, the columnar region 30 is a mirror image of each other with respect to the axis of symmetry passing through the geometric center of the gate region 28.

[0042] Each columnar region 30 has a value of 0.5·10 12 cm -2 and 5.10 12 cm -2 The charge within the range is designed to locally compensate for the doping of the epitaxial layer 22.

[0043] In addition, according to Figure 3In this embodiment, the columnar regions 30 are connected to each other at the bottom of the gate region 28 via P-type regions 30'. Furthermore, the regions 30' extend a certain distance from the underlying drain terminal, such that the columnar regions 30 and the connection portions 30' are completely contained within the epitaxial layer 22. Each connection region 30' has a doping value equal to that of the columnar region 30. In the following figures, the set of columnar regions 30 and connection regions 30' is also designated by reference numeral 36.

[0044] according to Figure 3 In one embodiment, each gate region 28a is partially surrounded by a corresponding region 36 having a conductivity (P) opposite to that of the epitaxial layer (N). In this respect, it can be noted that the entire region 36 is electrically disconnected at a certain distance from both the body region 25 and the substrate 21 (which, from an electrical point of view, forms part of the drain terminal).

[0045] Figure 3 Distance d in B This represents the distance (measured along Z) between each columnar region 30 and the main body region 25 above it. Figure 3 Distance d in E This represents the distance (measured along Z) between each columnar region 30 and the upper surface 22a of the epitaxial layer 22. Figure 3 Distance d in G This represents the gap (measured along Z) between each columnar region 30 and the lower side of the gate conductive region 28a. As an example, d E Within the range of 1μm and 2μm, and d G The distance is in the range between 0.4 μm and 0.8 μm. Therefore, the distance d B The range is from 0.6 μm to 1.2 μm. It can be noted that due to the non-uniform concentration of the dopant in the host, the distance d... B This can vary relative to the aforementioned values, resulting in a body region with a non-uniform shape and an increasing depth at a distance from the gate trench. Specifically, in the case where the body has a configuration presenting a groove above the corresponding columnar region 30, this distance d... B It can be larger than 1.2 μm. For example, d B It can be between 0.6μm and 1.8μm.

[0046] If the distance d GIf the value is equal to 0, or if region 30 is in contact with body 25 in the active region, the MOSFET (which can only conduct when the drain bias is above zero) will no longer exist. This occurs because the N-type inversion region (formed in body 25 due to the forward bias of gate conductive region 28a and starting from source region 26) does not terminate in the N-type region (this fact will guarantee electrical continuity), but terminates in the P-type region (i.e., region 30), no longer subject to the electrostatic control of gate conductive region 28a.

[0047] The distance d between each columnar region 30 and the main body region 25 above it is B (Also measured along Z) has a value equal to or greater than d. G The value of .

[0048] exist Figure 3 The figure is marked with d in the attached diagram. S The distance between each connection region 30' (the bottom of the corresponding region 36) and the upper surface 21a of the substrate 21 is between 0.4 μm and 1 μm. (Distance d) S Measured along the Z-axis. Typically, to ensure that the epitaxial layer 22 is exhausted in the region between each connection region 30' and the substrate 21 during use, a distance d is made. S The choice of the value (in addition, it will be apparent to those skilled in the art that if region 36 is too close to substrate 21 or the drain terminal, the breakdown value will have an undesirable sharp drop).

[0049] Obtain as described below Figure 3 Region 36 of the MOS device 20, and for simplicity, in Figures 4-12 The representation is only relative to region 36.

[0050] refer to Figure 4 After growing an epitaxial layer 22 on a substrate 21 (not shown in its entirety) of a semiconductor wafer, a mask etching step (using a mask 39, for example, SiO2) is performed to form a trench 40 in the epitaxial layer 22. The trench 40 (which will form a trench gate at the end of the fabrication step) is defined by a bottom 40' and sidewalls 40'". The bottom 40' terminates at a distance from the substrate 21.

[0051] Then, using the same mask 39, implantation of P-type dopant material (e.g., boron, indicated by arrow 41) is performed to position the dopant material at the bottom 40' of trench 40 to form implantation region 42 in epitaxial layer 22.

[0052] Then( Figure 5Using the same mask 39, the step of forming a multilayer 44 in the trench 40 is performed to completely cover the sidewalls 40” and bottom 40’ of the trench 40. The multilayer 44 includes a first oxide layer 44a, a silicon nitride (Si3N4) layer 44b on the first oxide layer 44a, and a second oxide layer 44c on the silicon nitride layer 44b. Specifically, the first oxide layer is grown or deposited by known techniques (e.g., thermal oxidation or CVD) until a thickness of a certain nanometer (e.g., 10 nm) is reached. The silicon nitride layer 44b is deposited by known techniques (e.g., CVD) until a thickness of a certain nanometer (e.g., 20 nm) is reached. The second oxide layer 44c is deposited by known techniques (e.g., CVD) until a thickness of approximately 10 nm to 30 nm is reached.

[0053] Then, Figure 6 The wafer is subjected to an ion implantation process (e.g., using heavy ions such as As, Ar, etc.) with an inclination α relative to the sidewalls 40” of the trench 40. In this manner, the ion beam 45 bombards a portion of the multilayer 44, which extends along the sidewalls 40” near the upper surface 22a of the epitaxial layer 22. Specifically, the inclination α is chosen so that the ions will bombard a region of the second oxide layer 44c, which extends approximately 1 μm-2 μm from the surface 22a of the epitaxial layer 22 toward the bottom 40’ of the trench 40. This extension substantially corresponds to a distance d. E .

[0054] The above-described ion implantation process is performed on the two sidewalls 40” of the trench 40.

[0055] Alternatively, a similar ion implantation process may be performed on the bottom 40' of the trench 40.

[0056] The aforementioned implantation step has the function of locally causing damage to the second oxide layer 44c; for this purpose, the implantation conditions are selected in an appropriate manner to disrupt the second oxide layer 44c at the molecular bond and stoichiometric levels, so as to facilitate its removal in subsequent steps. As an example, the implantation energy is in the range of 20 keV to 40 keV, and the implantation process is carried out at a temperature between 30°C and 50°C.

[0057] Then, Figure 7 The process involves a wet chemical etching step using HF or BHF vapor, which selectively removes the second oxide layer 44c. Figure 6 The area undergoing injection during the process. In fact, in Figure 6 The etching rate of the implanted oxide during the step is higher than that in the step. Figure 6 The corresponding etching rate for unimplanted oxides in this step is much higher (potentially reaching a ratio of 100:1 in HF vapor).

[0058] This exposes a selective region of the silicon nitride layer 44b, which extends near the surface 22a in the trench 40 and at the bottom of the trench.

[0059] It can be noted that, due to Figure 6 The implantation step is performed without a mask, thus allowing the portion of oxide layer 44c extending outside trench 40 (on the front side of the wafer) to be selectively etched. Therefore, in Figure 7 During the process, these external parts are also removed.

[0060] Next, Figure 8 Further chemical etching is then performed to remove the exposed silicon nitride layer 44b. This step can be performed, for example, using wet etching with H3PO4.

[0061] Then, an etching step (e.g., wet isotropic etching) is performed in HF to completely remove the exposed portions of the second oxide layer 44c and layer 44a. Thus, within the trench 40, a double layer 44a-44b still covers a portion of the sidewall 44”, without reaching the surface 22a of the epitaxial layer 22, and frees the bottom 40'. Specifically, the epitaxial layer 22 is exposed in the region of the sidewall 44” near the surface 22a and the bottom 40'. Next, Figure 9 The thermal oxidation step (e.g., via LOCOS technology) enables the growth of a corresponding silicon oxide protective layer 48 in the exposed region of the epitaxial layer 22 within the trench 40 (i.e., between surface 22a and the bilayer 44a-44b). This protective layer 48 has a thickness, for example, between 80 nm and 120 nm, measured along the X-axis. A protective layer 49, similar to layer 48, is also grown at the bottom 40' of the trench 40.

[0062] Then, Figure 10 The double layers 44a-44b are completely removed by a dual etching step, which includes etching of layer 44b (Si3N4) using H3PO4 and etching of layer 44a (SiO2) using HF. This second etching also partially removes the protective layers 48 / 49; however, given the greater thickness of the protective layers 48 / 49 relative to the oxide layer 44a, complete removal of the oxide layer 44a has no significant impact on the protective layers 48 / 49. The region of the epitaxial layer 22 between the protective layer 48 and the bottom 40' of the trench 40 is thus exposed via the trench 40.

[0063] Next, Figure 11An implantation step of P-type dopant material (e.g., boron) is performed to form a columnar region 30 in the portion of the sidewall 40” not protected by the protective layer 48 / 49 (i.e., the portion extending between the protective layer 48 and the bottom 40' of the trench 40).

[0064] The injection is performed at an injection angle β of approximately 8° (relative to the inclination of the sidewall 40” on which the injection occurs), and the injection is repeated on both sidewalls 40” of the trench 40.

[0065] As an example, the injection energy is selected within the range of 10 keV and 25 keV, and the injection process is carried out at a temperature within the range of 3°C and 20°C. Therefore, injection regions 52 are formed at the two sidewalls 40” of the trench 40, each injection region having an injection energy of 10 keV and a temperature of 25 keV and a temperature of 3°C and 20°C. 13 cm -2 and 10 14 cm -2 The dopant concentration between.

[0066] exist Figure 11 In this step, the protective layer 49 protects the bottom of the trench 40 from unwanted dopant injection, which is the reflection of dopant ions that strike the sidewall 40” during injection but are not completely absorbed by the sidewall 40” or released by the sidewall 40” in an undesirable manner.

[0067] Figure 11 The injection step can be adapted to form Figure 11 Instead of a p-type doped region of type 52, another process is used, namely, region 52 extends along the sidewall 40” of the trench 40 in the epitaxial layer 22 between the guard layer 48 and the bottom 40’ of the trench 40. For example, these additional processes include, for example:

[0068] The diffusion process of boron into epitaxial layer 22 is initiated from borosilicate glass (BSG) using RTP (Rapid Thermal Processing) technology, as described by M. Miyake, “Diffusion of Boron into Silicon from Borosilicate Glass Using Rapid Thermal Processing”, J. Electrochem. Soc. 1991, Vol. 138, No. 10, pp. 3031-3039.

[0069] Doping processes performed via PIII (plasma immersion implantation); and

[0070] Doping processes using MLP (monolayer doping) technology.

[0071] Replaced by the above process Figure 11 In the case of steps that lead to the formation of protective layer 49, the steps that lead to the formation of protective layer 49 can be omitted; therefore, protective layer 49 is not formed in this case.

[0072] at last, Figure 12 Protective layers 48 and 49, as well as mask 39, were completely removed.

[0073] Then, a heat treatment or thermal annealing step is performed to promote the diffusion of dopants in implanted regions 42 and 52, thereby forming a reference. Figure 3 The area described is 36.

[0074] The additional step of filling the trench 40 with the gate dielectric region 28b and the gate conductive region 28a is carried out in a manner known per se and will not be described further herein. Similarly, the remaining fabrication steps of device 20 (forming the body region 25, source region 26, etc.) are carried out. These steps, known per se, will not be described further.

[0075] It can be noted that the annealing step to form region 36 can be performed at the end of the manufacturing process in order to simultaneously activate the... Figure 11 All dopants injected in subsequent steps (e.g., dopants in the body and / or source regions).

[0076] The steps of forming metallization 27 enable the formation of Figure 3 MOS device 30.

[0077] Figure 13 This is a cross-sectional view of a portion of a charge-compensated type MOS device 50 according to another embodiment of the present disclosure in a triaxial reference system X, Y, Z.

[0078] The MOS device 50 includes an N-type structure layer 52 (e.g., silicon) covering an N++ type substrate 51 (also silicon, for example). The structure layer 52 is formed by a first epitaxial layer 52' ​​extending over the substrate 51 and a second epitaxial layer 52” extending over the first epitaxial layer 52'. The first epitaxial layer 52' ​​is N+ type, and the second epitaxial layer 52” is N- type. The doping density of the first epitaxial layer 52' ​​is approximately 10% greater than the doping density of the second epitaxial layer 52”. The structure layer 52 extends along the Z-axis between an upper surface or face 52a and a lower surface or face 52b, which are opposite each other along the Z-axis. The thickness of the structure layer 52, measured along the Z-axis between the upper surface 52a and the lower surface 52b, is, for example, between 6 μm and 14 μm. The thicknesses of the first epitaxial layer and the second epitaxial layers 52', 52” are approximately the same.

[0079] The lower surface 52b is in direct contact with the upper surface 51a of the substrate 51, while the lower surface 51b of the substrate 51 (opposite to surface 51a along the Z-axis) is in contact with the drain metallization 54. Therefore, the substrate 51 and the drain metallization 54 together form the drain terminal of the MOS device 50.

[0080] The MOS device 50 also includes one or more trench-type gate regions 58 (in Figure 13 Two gate regions 58 are illustrated by way of example. Specifically, each gate region 58 includes a gate conductive region 58a completely surrounded by a corresponding dielectric layer 58b (which forms the gate dielectric of the transistor at the gate conductive region 58a). The gate conductive region 58a can be, for example, a metallic material or doped polysilicon. The dielectric layer 58b is, for example, an oxide, such as SiO2.

[0081] Each trench extends within the depth of structure 52, through the entire thickness of structure 52, and partially penetrates into the underlying substrate 51, terminating within substrate 51. It can be noted that only the dielectric layer 58b (not the gate conductive region 58a) extends within substrate 51.

[0082] As an example, each trench accommodating the corresponding gate region 58 has a depth (between 4 μm and 10 μm) measured along the Z direction from the surface 52a, and a width (between 0.5 μm and 1.5 μm) measured along the X direction. Along the X direction, the distance (also referred to as the pitch) between the gate region 58 and the gate region 58 immediately following (or preceding) it is, for example, between 1.2 μm and 4 μm.

[0083] In each gate region 58, a dielectric layer 58b extends at a depth (along the Z) in the structural layer 52 to completely cover the sidewalls and bottom of the corresponding trench.

[0084] The thickness of each gate conductive region 58a, measured along the Z-direction, is, for example, between 0.4 μm and 1.1 μm. Each gate conductive region 58a extends between its upper and lower sides. In one embodiment, the upper side of each gate conductive region 58a is aligned with surface 52a such that the lower side of each gate conductive region 58a reaches a depth in the corresponding trench, which is between 0.4 μm and 1.1 μm starting from surface 52a. A P-type body region 55 extends within the structural layer 52 alongside each gate region 58 (along the X-direction) and faces the upper surface 52a of the structural layer 52. Along the Z-direction, the maximum depth reached by each body region 55 in the structural layer 52 (measured in contact with the sidewalls of the trench where the body region 55 is adjacent to it) is equal to or less than the depth reached by each gate conductive region 58a (i.e., in a non-limiting example, equal to or less than 0.4 μm to 1.1 μm).

[0085] In a manner known per se, the main body region 55 also accommodates an N-type source region 56 facing the upper surface 52a.

[0086] Electrical contact regions (e.g., metallized regions) 57 extend over and electrically contact the body region 25 and the source region 26 to bias them during use.

[0087] P-type columnar regions 60 extend in structural layers 52 (specifically, in the first and second epitaxial layers 52', 52") laterally facing each gate region 58. In other words, columnar regions 60 extend along the X-direction-opposite sides of each gate region 58. Specifically, columnar regions 60 are boundaryd and adjacent to the gate dielectric layer 58b of the respective gate region 58. Columnar regions 60 extend at a distance (along the Z-direction) from both the upper body region 55 and the lower drain terminal.

[0088] Each columnar region 60 extends partly in the first epitaxial layer 52' ​​and partly in the second epitaxial layer 52'. The portion of the columnar region 60 extending in the first epitaxial layer 52' ​​has a p-charge or is doped (e.g., in 0.5·10⁻⁶). 12 cm -2 Up to 5.10 12 cm -2 Within the range), the portion of columnar region 60 extending in the second epitaxial layer 52” has P+ doping (e.g., up to 10%).

[0089] Compared to epitaxy obtained using a single concentration, the presence of the first and second epitaxial layers 52' and 52'" allows for an increase in the average concentration of the entire epitaxial layer 52. This enables a decrease in Ron while maintaining a constant BV value. Furthermore, according to... Figure 13 In this embodiment, because the gate dielectric layer 58b of the gate region 58 penetrates into the substrate 51, the pillar region 60 at the bottom of the gate region 58 does not resemble... Figure 3 They are connected to each other as shown in the diagram. According to... Figure 13 In one embodiment, two columnar regions 60 extend along the opposing sidewalls of each gate region 58, at a distance from both the upper body region and the lower drain region. Each columnar region 60 has a conductivity (P) opposite to the conductivity (N) of the structural layer 52 that completely encompasses the columnar region 60.

[0090] Figure 13 Distance d in B (The distance measured along Z between each columnar region 60 and the main body region 55 above it) corresponds to Figure 3 Distance d in B(The distance measured along Z between each columnar region 30 and the main region above it); therefore, the same considerations and dimensions discussed above apply.

[0091] same, Figure 13 Distance d in E (The distance measured along Z between each columnar region 60 and the upper surface 52a of the structural layer 52) also corresponds to Figure 3 Distance d in E (The distance along Z between each columnar region 30 and the upper surface 22a of the epitaxial layer 22), and therefore the same considerations and dimensions discussed above apply.

[0092] If already targeted Figure 3 Described, Figure 13 Distance d in G The gap (measured along Z) between each columnar region 60 and the underside of the gate conductive region 58a is indicated. As an example, d G The distance d is within the range of 0.4 μm to 0.8 μm. B Having equal to or greater than d G The value of .

[0093] Figure 13 Distance d in S This represents the distance (along the Z) between the bottom of each columnar region 60 and the upper surface 51a of the substrate 51, and has a value, for example, between 0.4 μm and 0.8 μm. Typically, this distance d is set to ensure that the structural layer 52 is exhausted in the area between each columnar region 60 and the substrate 51 during use. S The choice of the value (in addition, it will be apparent to those skilled in the art that if the columnar region 60 is too close to the substrate 51 (drain terminal), the breakdown value will have an undesirable sharp drop).

[0094] MOS device 50 is similar to reference Figures 4-12 The MOS device 30 is manufactured in the manner described.

[0095] The formation of structural region 52 anticipates biepitaxy growth with corresponding doping. The formation of columnar region 60 is based on... Figure 14A and Figure 14B Obtained through the process, Figure 14A and Figure 14B The diagram illustrates a structural layer 52 in an intermediate manufacturing step, the structural layer 52 having a trench 70, the trench 70 having a bottom 70' and sidewalls 70'. The trench 70 accommodates, according to reference... Figures 5-10 The protective layer 48 formed as described is therefore identified by the same reference numerals in the figures.

[0096] Specifically, two consecutive implantations are performed, wherein the first implantation is of a P-type (e.g., boron) dopant material. Figure 14A ), so as to form a P-doped implantation region 72 at a portion of the sidewall 70” of the desired columnar region 60 in the trench 70.

[0097] Appropriately and in a manner obvious to those skilled in the art, the injection angle γ (the angle between the injection direction indicated by arrow 74 and the sidewall 70” where the injection is performed) is selected to comply with the previously stated distance d. B d G d E and d S The constraints described. Injection is performed on both sides 70” of the trench 70.

[0098] Then( Figure 14B A second implantation of a P-type dopant material (e.g., boron) is performed, with the angle δ>γ defined as the angle between the implantation direction indicated by the arrow and the sidewall 70” where the implantation is performed. The angle δ is selected in an appropriate manner (which is obvious to those skilled in the art) to comply with the previous requirements for distance d. B d G d E and d S The constraints described are applied, and P-type dopant material is implanted only at the second epitaxial layer 52” (i.e., at the P+ doped portion where the columnar region 60 is to be formed).

[0099] The annealing step makes in Figure 14A and Figure 14B The dopant material injected during the process can be activated and diffused.

[0100] Finally, it is evident that modifications and changes can be made to the devices and manufacturing processes described herein without departing from the scope of this disclosure.

[0101] Specifically, techniques other than LOCOS oxidation can be used to form the protective layer 48, such as non-conformal deposition techniques using atomic layer deposition (ALD) with SiO2, or non-conformal sputtering of SiO2. The use of silicon oxide is advantageous because it can be selectively etched relative to silicon and is easy to handle; however, other materials, such as Si3N4 or titanium, can be used for the protective layer 48. Furthermore, the material of the multilayer 44 can differ from those indicated, as long as the corresponding selective etching characteristics described previously are retained.

[0102] Furthermore, although this disclosure has been explicitly described with reference to silicon as a semiconductor material, other semiconductor materials such as SiC may also be used to fabricate MOS devices 20, 50.

[0103] The advantages provided by this disclosure are clearly apparent from the foregoing description.

[0104] In particular, the presence of zones 30 and 60 prevents any degradation of BV.

[0105] Furthermore, it overcame the previous reference Figure 2A and Figure 2B Technical difficulties in labeling.

[0106] The various embodiments described above can be combined to provide other embodiments. These and other changes can be made to the embodiments based on the specific embodiments described above. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed as including all possible embodiments and the full scope of equivalents to these claims. Therefore, the claims are not limited by the disclosure.

Claims

1. A charge balance power device, comprising: a semiconductor body having a first conductivity type, the semiconductor body having a first surface and a second surface opposite each other along a first direction; a trench gate extending in the semiconductor body from the first surface toward the second surface; a body region having a second conductivity type opposite the first conductivity type, the body region facing the first surface of the semiconductor body and extending on first and second sides of the trench gate, the first and second sides being opposite each other along a second direction transverse to the first direction; a source region having the first conductivity type, extending in the body region and facing the first surface; a drain terminal extending on the second surface of the semiconductor body; and first and second columnar regions having the second conductivity type and extending in the semiconductor body adjacent the first and second sides of the trench gate, respectively, the first and second columnar regions being spaced apart from the body region and from the drain terminal, the first and second columnar regions being electrically disconnected from the body region, wherein the first and second columnar regions are separated from a gate conductive region of the trench gate by a gate dielectric layer of the trench gate, wherein the gate conductive region extends in the first direction from the first surface of the semiconductor body toward the second surface to a first depth in the semiconductor body, the first and second columnar regions extending in the first direction from a second depth in the semiconductor body, the second depth being greater than the first depth, and wherein the drain terminal includes a substrate of semiconductor material having the first conductivity type extending in contact with the second surface of the semiconductor body and a drain metallization extending in electrical contact with the substrate, wherein the trench gate passes completely through the semiconductor body and terminates within the substrate.

2. The charge balance power device of claim 1, wherein the first and second columnar regions are spaced apart from the body region by a first distance between 0.6 pm and 1.8 pm in the first direction and from the drain terminal by a second distance between 0.4 pm and 0.8 pm in the first direction.

3. The charge balance power device of claim 1, wherein the first and second columnar regions are spaced apart from the first surface of the semiconductor body by a distance between 1 pm and 2 pm in the first direction.

4. The charge balance power device of claim 1, wherein the gate dielectric layer completely surrounds the gate conductive region and the first and second columnar regions extend adjacent the gate dielectric layer.

5. The charge balance power device of claim 1, wherein a difference between the second depth and the first depth is between 0.4 pm and 0.8 pm. ​ 6. The charge balance power device of claim 1, wherein the columnar regions are mirror images of one another with respect to a symmetry axis passing through a geometric center of the trench gate.

7. The charge balance power device of claim 1, wherein the semiconductor body comprises a first epitaxial region and a second epitaxial region, the first epitaxial region extending in contact with the substrate and having a first doping concentration, the second epitaxial region extending over the first epitaxial region and having a second doping concentration lower than the first doping concentration, the first and second columnar regions extending in the first and second epitaxial regions and having a third doping concentration in the first epitaxial region and a fourth doping concentration in the second epitaxial region higher than the third doping concentration.

8. A method for fabricating a charge balance power device, comprising: forming a trench gate in a semiconductor body, the semiconductor body having a first conductivity type and having a first surface and a second surface opposite one another along a first direction, the trench gate extending from the first surface toward the second surface; forming a body region in the semiconductor body on first and second sides of the trench gate, the first and second sides of the trench gate opposite one another along a second direction transverse to the first direction, the body region facing the first surface of the semiconductor body and having a second conductivity type opposite the first conductivity type; forming a source region in the body region and facing the first surface, the source region having the first conductivity type; forming a drain terminal on the second surface of the semiconductor body; and forming first and second columnar regions having the second conductivity type in the semiconductor body adjacent the first and second sides of the trench gate, the first and second columnar regions spaced apart from the body region and spaced apart from the drain terminal, the first and second columnar regions electrically disconnected from the body region, wherein the first and second columnar regions are separated from a gate conductive region of the trench gate by a gate dielectric layer of the trench gate, wherein the gate conductive region extends in the first direction from the first surface of the semiconductor body toward the second surface to a first depth in the semiconductor body, the first and second columnar regions extending in the first direction from a second depth in the semiconductor body, the second depth greater than the first depth, and wherein the drain terminal comprises a substrate of semiconductor material having the first conductivity type extending in contact with the second surface of the semiconductor body and a drain metallization extending in electrical contact with the substrate, wherein the trench gate passes entirely through the semiconductor body and terminates within the substrate.

9. The method of claim 8, wherein forming the first and second columnar regions comprises: ​ forming a trench in the semiconductor body extending from the first surface toward the second surface; forming a mask on sidewalls of the trench; exposing a portion of the semiconductor body in the trench by removing a portion of the mask proximate the first surface; forming a protective region on the exposed portion of the semiconductor body in the trench, the protective region being selectively etchable relative to the mask; removing the mask and exposing a portion of the semiconductor body in the trench not covered by the protective region; and introducing a dopant species having the second conductivity type into the semiconductor body through the trench and on the portion of the semiconductor body not covered by the protective region.

10. The method of claim 9, wherein forming the mask comprises: forming a multi-layer mask including a first mask layer extending in contact with the semiconductor body in the trench, a second mask layer on the first mask layer, and a third mask layer on the second mask layer, wherein the first and third mask layers are selectively removable relative to the second mask layer, removing a portion of a mask layer and forming the protective region includes: removing a portion of the third mask layer proximate the first surface to expose a portion of the second mask layer; exposing a corresponding portion of the first mask layer by removing the portion of the second mask layer previously exposed; exposing a corresponding portion of the semiconductor body in the trench by removing the portion of the first mask layer previously exposed and the third mask layer; and forming the protective region by locally oxidizing the portion of the semiconductor body previously exposed.

11. The method of claim 10, wherein introducing a dopant species into the semiconductor body through the trench includes one of: a tilted implant of a dopant species having the second conductivity type; a method of diffusing a dopant species having the second conductivity type starting from borosilicate glass and by rapid thermal annealing; a method of doping by plasma immersion ion implantation; and a method of doping using a single layer doping technique.

12. A device comprising: a substrate having a first conductivity type, the substrate having a first surface and a second surface, the first surface and the second surface opposite each other along a first direction; an epitaxial layer on the first surface of the substrate, the epitaxial layer having the first conductivity type; a trench gate extending into the epitaxial layer toward the substrate; a body region on the epitaxial layer and abutting sides of the trench gate, the body region having a second conductivity type opposite the first conductivity type; a source region on the body region and adjacent to the sides of the trench gate, the source region having the first conductivity type; a drain metallization on the second surface of the substrate; and a protective region on the body region in the trench, the protective region being selectively etchable relative to the trench gate. a first columnar region and a second columnar region on opposite sides of the trench gate in the epitaxial layer and spaced apart from the first surface of the substrate, the opposite sides opposite each other along a second direction transverse to the first direction, the first columnar region and the second columnar region having a second conductivity type opposite the first conductivity type, the first columnar region and the second columnar region spaced apart from the body region and from the drain metallization, the first columnar region and the second columnar region electrically disconnected from the body region, wherein the first columnar region and the second columnar region are separated from a gate conductive region of the trench gate by a gate dielectric layer of the trench gate, wherein the gate conductive region extends into the substrate along the first direction from the first surface of the substrate toward the second surface to a first depth, the first columnar region and the second columnar region extending along the first direction from a second depth in the substrate, the second depth greater than the first depth, and wherein the drain metallization extends in electrical contact with the substrate, and wherein the trench gate passes entirely through the epitaxial layer and terminates within the substrate.

13. The device of claim 12, wherein the first columnar region and the second columnar region are spaced apart from the body region by a distance between 0.6 pm and 1.8 pm.

14. The device of claim 12, wherein the first columnar region and the second columnar region are spaced apart from the first surface of the substrate by a distance between 0.4 pm and 0.8 pm.

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