Switch-mode power supply

Abstract

Embodiments of this disclosure relate to a switch-mode power supply. A switch-mode power supply includes a voltage ramp generation circuit that generates a voltage ramp signal. The voltage ramp generation circuit includes at least three capacitors selectively connected in parallel. The capacitors are selected based on the value of the internal power supply voltage of the switch-mode power supply.

Description

[0001] Priority Statement

[0002] This application claims priority to French patent application No. 1908469, filed on July 25, 2019, the entire contents of which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure generally relates to electronic systems, and more particularly to circuitry for powering such systems. More specifically, this disclosure relates to switch-mode power supplies (SMPS). Background Technology

[0004] Several types of power supply circuits exist that enable the supply of current / voltage pairs to electronic circuits, devices, or systems, or more generally to loads. Linear power supplies and switching-mode power supplies are examples of power supply circuits.

[0005] A switch-mode power supply is a power supply circuit that is typically able to deliver DC voltage from another DC voltage source. Although switch-mode power supplies are typically DC / DC converters, some switch-mode power supplies may include a rectifier stage, enabling them to accept AC voltage as input, such as from a power transmission line.

[0006] It is expected that this will at least partially improve certain aspects of known switch-mode power supplies.

[0007] High-performance switch-mode power supplies are needed in this field.

[0008] In this field, there is a need for switch-mode power supplies that consume less power. Summary of the Invention

[0009] The embodiments overcome all or part of the drawbacks of known switch-mode power supplies.

[0010] An embodiment provides a switch-mode power supply, including a voltage ramp generation circuit comprising at least three capacitors connected in parallel, wherein the at least three capacitors can be selected based on the value of the internal power supply voltage of the switch-mode power supply.

[0011] According to an embodiment, a current ramp generation circuit is implemented during the low-power operation mode of the switch-mode power supply.

[0012] According to an embodiment, the low-power operation mode is an operation mode that is modulated by pulse frequency.

[0013] According to an embodiment, the current ramp generation circuit is implemented during the high-power operation phase of the switch-mode power supply.

[0014] According to an embodiment, the high-power operating mode is a pulse width modulation operating mode.

[0015] According to an embodiment, the internal power supply voltage has an average value equal to the input voltage of the switch-mode power supply.

[0016] According to an embodiment, the at least three selectable capacitors can be selected via a switch.

[0017] Another embodiment provides a method for operating a switch-mode power supply, wherein the slope of a voltage ramp delivered by a voltage ramp generation circuit is modified according to the value of the internal power supply voltage of the switch-mode power supply.

[0018] According to an embodiment, the slope increases when the internal power supply voltage decreases.

[0019] According to an embodiment, the slope decreases when the internal power supply voltage increases.

[0020] According to an embodiment, the slope is modified by adjusting the capacitance of the voltage ramp generation circuit.

[0021] According to an embodiment, the method is used during the low-power mode of a switch-mode power supply.

[0022] According to an embodiment, the method is used during the high-power mode of a switch-mode power supply. Attached Figure Description

[0023] In the following non-limiting description of specific embodiments taken in conjunction with the accompanying drawings, the foregoing and other features and advantages are discussed in detail, wherein:

[0024] Figure 1 A switch-mode power supply is schematically shown in boxes.

[0025] Figure 2 An embodiment of a switch-mode power supply during the low-power phase is schematically shown in box form;

[0026] Figure 3 An embodiment of a switch-mode power supply during the high-power phase is schematically shown in box form;

[0027] Figure 4 The diagram is shown schematically in the form of a box. Figure 2 and Figure 3 Examples of ramp generator circuits for each part of a switch-mode power supply; and

[0028] Figure 5 The control is schematically shown in box form. Figure 4 An example of a circuit. Detailed Implementation

[0029] In different figures, the same elements are designated using the same reference numerals. Specifically, structural and / or functional elements common to different embodiments may be designated using the same reference numerals and may have the same structural, dimensional, and material properties.

[0030] For clarity, only those steps and elements useful for understanding the described embodiments are shown and described in detail.

[0031] Throughout this disclosure, the term “connection” is used to specify a direct electrical connection between circuit elements without any intermediate elements other than conductors, while the term “coupling” is used to specify an electrical connection between circuit elements that can be a direct connection or a connection via one or more other elements.

[0032] In the following description, unless otherwise stated, when referring to terms defining absolute position (such as the terms "front", "back", "top", "bottom", "left", "right", etc.) or relative position (such as the terms "above", "below", "upper", "lower", etc.) or direction (such as the terms "horizontal", "vertical", etc.), reference is made to the orientation of the accompanying drawings.

[0033] The terms “about,” “approximately,” “substantially,” and “approximately” are used herein to specify a tolerance of plus or minus 10%, preferably plus or minus 5%, for the value under discussion.

[0034] Figure 1 The switch-mode power supply 1 (SMPS) is shown very schematically in the form of a block diagram.

[0035] A switch-mode power supply (SMPS) 1 is a power supply circuit capable of supplying a new DC voltage Vout from a DC voltage Vin. The SMPS 1 can supply power to a load coupled to its output, i.e., receive the voltage Vout. Therefore, depending on the value of the input voltage to be converted, the SMPS has several different operating modes. For example, the SMPS 1 includes at least two operating modes.

[0036] The first operating mode is a low-power operating mode, or low-consumption mode, in which the switch-mode power supply operates with pulse frequency modulation (PFM). This operating mode is used when the load connected to the output of the switch-mode power supply 1 requires low current (e.g., less than 30mA). Combined with... Figure 2 This operating mode is described.

[0037] The second operating mode is the high-power operating mode, or high-power consumption operating mode, in which the switch-mode power supply operates using pulse-width modulation (PWM). This operating mode is used when the load connected to the output of switch-mode power supply 1 requires a high current (e.g., greater than 30mA). Combined with... Figure 3 This operating mode is described.

[0038] The switch-mode power supply 1 may also include other operating modes, such as, for example, forced conduction mode or bypass operating mode.

[0039] Figure 2 A portion of the switch-mode power supply 1, including an inductor Coil, a capacitor Cext, and a control circuit architecture 10, is schematically shown in box form when the switch-mode power supply 1 is in a low-power operation mode.

[0040] One terminal of the inductor Coil is coupled (preferably connected) to the output node of the circuit architecture 10. The other terminal of the inductor Coil delivers the output voltage Vout of the switch-mode power supply 1.

[0041] One electrode of capacitor Cext is coupled (preferably connected) to the terminal of inductor Coil, which delivers the output voltage Vout. The other electrode of capacitor Cext is coupled (preferably connected) to a reference node, such as a node that receives ground.

[0042] The control circuit architecture 10 includes an N-channel MOS transistor 11N and a P-channel MOS transistor 11P. Transistors 11P and 11N are connected in series. More specifically, the drain of transistor 11N is coupled (preferably, connected) to the drain of transistor 11P. The source of transistor 11P is coupled (preferably, connected) to a terminal receiving the input voltage Vin. The source of transistor 11N is coupled (preferably, connected) to a terminal receiving a low supply voltage VSS. The low supply voltage VSS is, for example, a reference voltage such as ground. The output node S of the circuit architecture 10 is defined by the junction of transistors 11N and 11P. In other words, node S is coupled (preferably, connected) to the drains of transistors 11N and 11P.

[0043] The circuit architecture 10 also includes a state machine (CMD) 12, configured to deliver signals GP and GN, enabling control of the gates of transistors 11P and 11N. State machine 12 also delivers a reset signal RST_RAMP. State machine 12 receives the signals START and DPulse as inputs.

[0044] The circuit architecture 10 also includes a comparator circuit 13, configured to compare the output voltage Vout of the switch-mode power supply 1 with a reference voltage Vref. The comparator circuit 13 outputs a START signal.

[0045] The circuit architecture 10 also includes a comparator circuit 14, configured to compare a reference voltage Vref with a ramp voltage Vramp. The comparator circuit 14 outputs a signal DPulse.

[0046] Circuit architecture 10 also includes circuit 15 for generating a reference voltage Vref. Circuit 15 receives a voltage Vbg as input and outputs a voltage Vref. Voltage Vbg is a general reference voltage of the switch-mode power supply 1, which varies slightly with temperature. Voltage Vbg is, for example, the bandgap voltage.

[0047] Circuit architecture 10 also includes circuitry or ramp generator circuitry 16 for generating a voltage ramp. Circuitry 16 receives the signal RST_RAMP as input and the internal power supply voltage VDD of the switch-mode power supply 1. The internal power supply voltage VDD has the same average value as the input voltage Vin, but is generally less noisy. Depending on the variation, the internal power supply voltage VDD equals the input voltage Vin. Circuitry 16 outputs a voltage Vramp. Figure 4 Circuit 16 will be described in detail.

[0048] Switch-mode power supply 1 operates as follows in low-power mode.

[0049] During low-power mode, capacitor Cext periodically charges and discharges at a set power. The charging and discharging frequency of capacitor Cext, or the duration of the charging and discharging periods, is variable and controlled by the START signal. The amount of power sent to capacitor Cext is controlled by the DPulse signal. The charging and discharging periods consist of a first phase that charges capacitor Cext and a second phase that discharges capacitor Cext. During the charging phase, transistor 11P is turned on while transistor 11N is turned off. During the discharging phase, transistor 11N is turned on while transistor 11P is turned off.

[0050] More specifically, capacitor Cext discharges due to the load connected to the output of switch-mode power supply 1, consuming power. Once the power stored in capacitor Cext drops below a minimum threshold, the signal START turns transistor 11P on and transistor 11N off to charge capacitor Cext via inductor Coil using the input voltage Vin. More specifically, once the output voltage Vout is less than the reference voltage Vref, the signal START detects that the capacitor no longer stores sufficient power. When capacitor Cext stores the minimum power threshold, voltage Vref corresponds to the voltage across capacitor Cext. The more power consumed by the output load of switch-mode power supply 1, the higher the frequency of the frequency pulses sent to the capacitor.

[0051] To set the amount of power sent to capacitor Cext in each new charging period, the signal DPulse defines the duration TON during which transistor 11P is turned on during the charging phase.

[0052] Figure 3A portion of the switch-mode power supply 1 is schematically shown in box form when operating in high-power mode. This portion includes the inductor Coil, the capacitor Cext, and the control circuit architecture 10' of the switch-mode power supply 1.

[0053] Circuit architecture 10' includes and about Figure 2 The circuit architecture described uses 10 common components. These components will not be described in detail below.

[0054] In circuit architecture 10', control signals GP, GN and signal RST_RAMP are generated by state machine 12' (CMD), which receives PWM signal and clock signal CK as input.

[0055] In circuit architecture 10', comparator circuit 13 delivers the error voltage Verr, which is output, to the input of comparator circuit 14' (replacing comparator circuit 14). Comparator circuit 14' receives the voltage Vramp delivered by ramp generator circuit 16 at its second input. Comparator circuit 14' outputs a PWM signal.

[0056] The operating mode of switch-mode power supply 1 during high-power mode is as follows.

[0057] During high-power mode, capacitor Cext is periodically charged and discharged with a variable power. The duration of the charging and discharging phases is constant and set by the clock signal CK. During the charging phase, transistor 11P is on while transistor 11N is off. During the discharging phase, transistor 11N is on while transistor 11P is off. The duration of the charging and discharging phases is variable and controlled by a PWM signal. In other words, the duty cycle of the transistors' on and off states is adjusted by the PWM signal.

[0058] The PWM signal is obtained by comparing the error voltage Verr, which represents the difference between the output voltage Vout and the reference voltage Vref, with the voltage Vramp delivered by circuit 16. Once the error is too high, the PWM signal commands a phase of charging the capacitor Cext.

[0059] Figure 4 The combination is shown in more detail. Figure 2 and Figure 3 The circuitry for generating voltage ramp 16 of the described architecture 10 and 10'.

[0060] Circuit 16 includes a resistor Rramp, which receives an internal power supply voltage VDD at one of its terminals. A second terminal of the resistor Rramp is coupled (preferably connected) to node A. The resistor Rramp has a resistance value denoted as Rramp.

[0061] Circuit 16 further includes an operational amplifier 161 having a first input (+) coupled (preferably connected) to node A and a second input (-) receiving a power supply voltage VDD divided by two (VVD / 2). The operational amplifier 161 is powered using an internal power supply voltage VDD. The output control circuit 16 of the operational amplifier 161 includes a first current mirror circuit 162.

[0062] Circuit 162 includes two N-type MOS transistors 162A and 162B, whose gates are coupled to each other (preferably connected to each other) and coupled to the output of operational amplifier 161. The drain of transistor 162A is coupled (preferably connected) to node A, and its source is coupled (preferably connected) to a reference node, for example, a node receiving ground. The drain of transistor 162B is coupled (preferably connected) to node B, and its source is coupled (preferably connected) to a reference node, for example, a node receiving ground.

[0063] Circuit 16 also includes a second current mirror circuit 163. Circuit 163 includes two P-type MOS transistors 163B and 163C. The gates of transistors 163B and 163C are coupled (preferably connected) to each other and are coupled (preferably connected) to node B. The sources of transistors 163B and 163C are coupled (preferably connected) to each other and receive an internal power supply voltage VDD. The drain of transistor 163B is coupled (preferably connected) to node B. The drain of transistor 163C is coupled (preferably connected) to node C, which delivers the voltage Vramp. In other words, node C is the output node of circuit 16.

[0064] Circuit 16 also includes a capacitor CrampHP1. The first electrode of capacitor CrampHP1 is coupled (preferably connected) to node C, while the second electrode of capacitor CrampHP1 is coupled (preferably connected) to a reference node (e.g., a node receiving ground).

[0065] Circuit 16 also includes a capacitor CrampHP2, selectable by switch 164HP. The first electrode of capacitor CrampHP2 is coupled (preferably connected) to a terminal of switch 164HP, while the second electrode of capacitor CrampHP2 is coupled (preferably connected) to a reference node (e.g., a node receiving ground). The second terminal of switch 164HP is coupled (preferably connected) to node C. Switch 164HP is controlled by signal CMDHP.

[0066] Circuit 16 further includes n capacitors CrampLP1, CrampLP2, ..., CrampLPn, selected by switches 164LP1, 164LP2, ..., 164LPn, respectively, where n is preferably an integer in the range of 2 to 8. The first electrode of each capacitor CrampLPi (where i varies from 1 to n) is coupled (preferably connected) to the terminal of its associated switch 164LPi, while the second electrode of each capacitor CrampLPi is coupled (preferably connected) to a reference node (e.g., a node receiving ground). The second terminal of switch 164LPi is coupled (preferably connected) to node C. Switch 164LPi is controlled by the signal CMDLPi.

[0067] Circuit 16 also includes a switch 165, a coupling node C, and a reference node (e.g., a node receiving ground). Switch 165 is controlled by the signal RST_RAMP.

[0068] Circuit 16 operates as follows. Capacitor CrampHP1 and (multiple) selected capacitors CrampHP2, CrampLP1, CrampLP2, ..., CrampLPn are gradually charged by current I. The voltage Vramp changes according to the voltage ramp. The larger the general capacitance Cramp of capacitor CrampHP1 and the selected capacitors CrampHP2, CrampLP1, CrampLP2, ..., CrampLPn, the smaller the slope of the ramp followed by Vramp. Turning off switch 165 allows the voltage Vramp to be reset.

[0069] The following generates information about Figure 2 The signal DPulse is described. At the start of each charging period for capacitor Cext, i.e., when transistor 11P is turned off, the voltage Vramp is zero. During the charging period, the voltage Vramp changes according to a ramp. Comparator circuit 14 compares the voltage Vramp with a reference voltage Vref. As long as the voltage Vramp is less than the reference voltage Vref, signal DPulse controls the turn-on of transistor 11P and the turn-off of transistor 11N, and capacitor Cext charges. Once the voltage Vramp exceeds the voltage Vref, signal DPulse controls the turn-off of transistor 11P and the turn-on of transistor 11N, and capacitor Cext discharges. Therefore, the charging duration TON of capacitor Cext is defined by the duration required for voltage Vramp to exceed voltage Vref. The duration TON is defined by the following formula:

[0070]

[0071] Signals CMDHP, CMDLP1 to CMDLPn are controlled by circuit 17 (in Figure 4 (not shown in the image) generated, combined Figure 5 An embodiment of this control circuit is described. The states of signals CMDHP, CMDLP1 to CMDLPn depend on the value of the internal power supply voltage VDD. More specifically, the voltage VDD can fall within several different value ranges, and depending on its value, some signals CMDHP, CMDLP1 to CMDLPn are activated, while others are not. Specifically, when the power supply voltage VDD decreases, the general-purpose capacitor Cramp increases.

[0072] The advantage of using a voltage ramp generation circuit of type 16 is that the slope of its output voltage ramp can be modulated according to the setpoint voltage (in this case, the internal power supply voltage VDD).

[0073] During the low-power mode of the switch-mode power supply 1, the advantage of using circuit 16 is that it enables a reduction in power loss in the inductor Coil. In fact, during the charging period of capacitor Cext, the voltage seen by the inductor Coil is equal to the difference between the output voltage Vout and the input voltage Vin, which has the same average value as the internal supply voltage VDD. Therefore, during the charging period, the current Imax entering the inductor Coil is equal to:

[0074]

[0075] Where L is the value of inductance Coil.

[0076] The current Imax depends on the voltage VDD. To reduce this voltage Imax and limit power loss, the capacitor Cramp should be gradually reduced as the voltage VDD increases. Therefore, the power loss is limited.

[0077] Figure 5 It shows about Figure 3 The described control circuit 17, or an example of a circuit for generating control signals CMDHP, and CMDLP1, ..., CMDLPn, is described herein. The circuit 17 described herein is capable of... Figure 3 The circuit 16 is coupled to the circuit 17, which includes three capacitors CrampLP1 to CrampLP3.

[0078] Between the node receiving voltage VDD and the node receiving voltage VSS, circuit 17 includes resistors R1 to R5 connected in series. As an example, the resistance values ​​of resistors R1 to R5 are all equal.

[0079] Circuit 17 also includes four comparator circuits C1 through C4 (CMP). Each comparator circuit receives a comparison voltage Vscale at one of its inputs. Comparator circuits C1 through C4 receive a voltage present at the junction of two resistors R1 through R5 at a second input. More specifically, circuit C1 receives the voltage at the junction of resistors R1 and R2; circuit C2 receives the voltage at the junction of resistors R2 and R3; circuit C3 receives the voltage at the junction of resistors R3 and R4; and circuit C4 receives the voltage at the junction of resistors R4 and R5.

[0080] The outputs of circuits C1 through C4 are sent to compiler circuit 171 (digital), which enables the determination of value intervals including the voltage VDD. The compiler circuit outputs a digital signal VDD_DIGIT, which includes information relative to the range including the voltage VDD.

[0081] Circuit 17 also includes a decoding circuit 172 (scaling), configured to output control signals CMDHP, CMDLP1, CMDLP2, and CMDLP3. Circuit 172 receives the signal VDD_DIGIT as input and the signal LPM, which indicates activation of the low-power mode of the switch-mode power supply 1. Circuit 17 enables the setting of... Figure 4 The value of the general capacitor Cramp is described.

[0082] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to those skilled in the art.

[0083] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

[0084] Such changes, modifications, and improvements are intended to be part of this disclosure and are intended to fall within the spirit and scope of the invention. Therefore, the foregoing description is by way of example only and is not intended to be limiting. The invention is defined solely by the appended claims and their equivalents.

Claims

1. A method for operating a switch-mode power supply, comprising: A voltage ramp generation circuit is used to generate a voltage ramp, wherein the voltage ramp has a slope, and wherein the slope is set by a capacitor. The capacitor is adjusted based on the value of the power supply voltage used in the ramp generation circuit of the switch-mode power supply, wherein the adjustment of the capacitor modifies the slope of the voltage ramp. In response to a decrease in the power supply voltage, the capacitance increases, and the slope of the voltage ramp decreases. In response to an increase in the power supply voltage, the capacitance decreases, and the slope of the voltage ramp increases.

2. The method according to claim 1, wherein when the switch-mode power supply is in a low-power operation mode, the capacitor is adjusted, the low-power operation mode being an operation mode modulated by a pulse frequency.

3. The method of claim 2, wherein the low-power operation mode is achieved by operating the switch-mode power supply modulated at a pulse frequency.

4. The method according to claim 1, wherein when the switch-mode power supply is in a high-power operation mode, the capacitor is adjusted, the high-power operation mode being a pulse width modulation operation mode.

5. The method of claim 4, wherein the high-power operation mode is achieved by operating the switch-mode power supply with pulse width modulation.

6. The method of claim 1, wherein the power supply voltage has an average value equal to the input voltage of the switch-mode power supply.

7. The method of claim 1, wherein the capacitance is provided by capacitor CrampHP1 and a plurality of selectable capacitors, and wherein adjusting the capacitance comprises: In response to the value of the power supply voltage, the connection of one or more capacitors among the plurality of selectable capacitors is selected.

8. The method of claim 7, wherein the option comprises: Select one or more of the plurality of selectable capacitors and connect them in parallel with the capacitor CrampHP1.

9. A switch-mode power supply, comprising: A ramp generation circuit is configured to generate a voltage ramp with a slope set by capacitors, wherein the ramp generation circuit includes at least three capacitors connected in parallel, the at least three capacitors being optionally connected in parallel with capacitor CrampHP1 to provide the capacitance, and wherein the selection of the connection of the at least three capacitors is performed in response to the value of the power supply voltage of the ramp generation circuit of the switch-mode power supply to adjust the slope of the voltage ramp, wherein the selection includes: selecting one or more of the at least three capacitors to be connected in parallel with capacitor CrampHP1, wherein in response to a decrease in the power supply voltage, the capacitance increases and the slope of the voltage ramp decreases, wherein in response to an increase in the power supply voltage, the capacitance decreases and the slope of the voltage ramp increases.

10. The power supply of claim 9, wherein the ramp generation circuit is used during the low-power operation mode of the switching mode power supply using pulse frequency modulation.

11. The power supply of claim 9, wherein the ramp generation circuit is used during the high-power operation mode of the switching mode power supply using pulse width modulation.

12. The power supply according to claim 9: The switching-mode power charging operation in response to a decrease in the power supply voltage is controlled using pulse frequency modulation, wherein the slope setting of the voltage ramp is used for: the on-time duration of charging within a period set by a variable frequency; and The switching mode power charging operation in response to the increase of the power supply voltage is controlled using pulse width modulation, wherein the slope setting of the voltage ramp is used to determine the on-time duration for charging within a period of time set by a fixed frequency.

13. The power supply of claim 9 further includes a switching circuit, one end of which is connected to the capacitor CrampHP1 and the other end of which is connected to the at least three capacitors, the switching circuit being controlled to selectively connect the at least three capacitors in parallel with the capacitor CrampHP1 to provide the capacitance.

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