Storage device and electronic device

Abstract

A novel storage device is provided. One embodiment of the present invention is a storage device including a plurality of memory cells, one memory cell including a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor through a node SN. Information written through the first transistor is held in the node SN. By using an OS transistor as the first transistor, a holding capacitor need not be formed. By providing a low relative permittivity region outside the memory cell, noise from the outside can be reduced, and stable operation can be achieved.

Description

Technical Field

[0001] One aspect of the present invention relates to a storage device.

[0002] Furthermore, one aspect of the invention relates to an object, method, or manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition of matter. One aspect of the invention relates to a method of driving it or a method of manufacturing it.

[0003] In this specification and other materials, a semiconductor device refers to any device capable of operating by utilizing the properties of semiconductors. Storage devices, display devices, electro-optical devices, energy storage devices, semiconductor circuits, and electronic devices sometimes include semiconductor devices. Furthermore, storage devices, display devices, electro-optical devices, energy storage devices, semiconductor circuits, and electronic devices may also be referred to as semiconductor devices. Background Technology

[0004] Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, while oxide semiconductors (OS) are attracting attention as other materials. Among oxide semiconductors, in addition to single-metal oxides such as indium oxide and zinc oxide, multi-metal oxides are also known. Among multi-metal oxides, research on In-Ga-Zn oxides (hereinafter also referred to as IGZO) is particularly active.

[0005] Through research on IGZO, CAAC (c-axis aligned crystalline) and nc (nanocrystalline) structures, which are neither single-crystal nor amorphous, were discovered in oxide semiconductors (see Non-Patent Documents 1 to 3). Non-Patent Documents 1 and 2 disclose a technique for manufacturing transistors using oxide semiconductors with CAAC structures. Non-Patent Documents 4 and 5 disclose oxide semiconductors with lower crystallinity than CAAC and nc structures, which also exhibit minute crystals.

[0006] Transistors using IGZO as the active layer have extremely small off-state currents (see Non-Patent Document 6), and LSIs and displays that utilize this characteristic are known (see Non-Patent Documents 7 and 8).

[0007] In addition, a variety of semiconductor devices have been proposed that utilize transistors containing oxide semiconductors in their channel formation regions (hereinafter also referred to as "OS transistors" or "OS-FETs").

[0008] Patent Document 1 discloses an example of using an OS transistor in a memory cell (memory element) of a memory device. The current flowing between the source and drain of an OS transistor in the off-state (also known as "off-state current") is very small, thus reducing or eliminating the need for a holding capacitor in the memory element. By reducing or eliminating the holding capacitor in the memory element, a highly integrated memory device can be realized.

[0009] [Preliminary Technology Documents]

[0010] [Patent Literature]

[0011] [Patent Document 1] Japanese Patent Application Publication No. 2012-256400

[0012] [Non-patent literature]

[0013] [Non-Patent Literature 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, pp. 183-186

[0014] [Non-Patent Literature 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, number 4S, p. 04ED18-1-04ED18-10

[0015] [Non-Patent Literature 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, pp. 151-154

[0016] [Non-Patent Literature 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, pp. Q3012-Q3022

[0017] [Non-Patent Literature 5] S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, pp. 155-164

[0018] [Non-Patent Literature 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p. 021201-1-021201-7

[0019] [Non-Patent Literature 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, pp. T216-T217

[0020] [Non-Patent Literature 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, pp. 626-629 Summary of the Invention

[0021] The technical problem that the invention aims to solve

[0022] However, when the holding capacitor is reduced or removed, problems such as reduced data retention time and susceptibility to operating noise from adjacent storage elements occur.

[0023] One objective of this invention is to provide a semiconductor device with high integration density. Furthermore, one objective of this invention is to provide a semiconductor device with high operating speed. Furthermore, one objective of this invention is to provide a semiconductor device capable of retaining data for extended periods. Furthermore, one objective of this invention is to provide a semiconductor device with reduced power consumption. Furthermore, one objective of this invention is to provide a novel semiconductor device.

[0024] The description of multiple objectives does not preclude their existence. One aspect of the invention does not necessarily have to achieve all of the above objectives. Objectives beyond those described above will naturally be apparent from the specification, drawings, claims, etc., and these objectives may also be objectives of one aspect of the invention.

[0025] means of solving technical problems

[0026] One aspect of the present invention is a storage device comprising multiple storage cells, each storage cell including a first transistor and a second transistor. One of the source and drain of the first transistor is electrically connected to the gate of the second transistor via a node SN. Information written through the first transistor is stored in the node SN. By using an OS transistor as the first transistor, a holding capacitor is not required. A low relative permittivity region is provided outside the storage cell.

[0027] Furthermore, one aspect of the present invention is a memory device comprising a memory cell, a first region, a first word line, a second word line, a first bit line, and a second bit line. The memory cell includes a first transistor and a second transistor. The semiconductor layer of the first transistor comprises a metal oxide. The first region includes a plurality of gaps. The first bit line and the second bit line extend in a first direction. The first word line and the second word line extend in a second direction. The gate of the first transistor is electrically connected to the first word line. One of the source and drain of the first transistor is electrically connected to the gate of the second transistor. The other of the source and drain of the first transistor is electrically connected to the first bit line. One of the source and drain of the second transistor is electrically connected to the second word line. The other of the source and drain of the second transistor is electrically connected to the second bit line. The first region includes a region extending in the first direction, and in the region extending in the first direction, the plurality of gaps are all included in a region extending in a direction intersecting the first direction.

[0028] Furthermore, one aspect of the present invention is a memory device comprising a memory cell, a first region, a first word line, a second word line, a first bit line, a second bit line, and a first conductive layer. The memory cell includes a first transistor and a second transistor. The semiconductor layer of the first transistor comprises a metal oxide. The first region includes a plurality of gaps. The first bit line and the second bit line extend in a first direction. The first word line and the second word line extend in a second direction. The gate of the first transistor is electrically connected to the first word line. One of the source and drain of the first transistor is electrically connected to the gate of the second transistor. The other of the source and drain of the first transistor is electrically connected to the first bit line. One of the source and drain of the second transistor is electrically connected to the second word line. The other of the source and drain of the second transistor is electrically connected to the second bit line. The first conductive layer includes a region overlapping the semiconductor layer of the first transistor and a region overlapping one of the source and drain of the first transistor. The first region includes a region extending in the first direction, and in the region extending in the first direction, the plurality of gaps are all included in a region extending in a direction intersecting the first direction.

[0029] The first conductive layer includes a region that serves as the back gate of the first transistor.

[0030] The semiconductor layer preferably contains at least one or both of In and Zn.

[0031] The first region may also include a region extending in the second direction. This region extending in the second direction includes multiple gaps. Preferably, all the multiple gaps are included in a region extending in a direction intersecting the second direction.

[0032] The area where the gate electrode of the second transistor overlaps with the semiconductor layer is preferably larger than the area where the gate electrode of the first transistor overlaps with the semiconductor layer. For example, the area where the gate electrode of the second transistor overlaps with the semiconductor layer is preferably more than 1 and less than 10 times the area where the gate electrode of the first transistor overlaps with the semiconductor layer.

[0033] Invention Effects

[0034] According to one aspect of the present invention, a semiconductor device with high integration density can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with high operating speed can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device capable of long-term data retention can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. Furthermore, according to one aspect of the present invention, a novel semiconductor device can be provided.

[0035] Note that the description of these effects does not preclude the existence of other effects. Furthermore, one embodiment of the invention does not necessarily require all of the aforementioned effects. Moreover, effects other than those described above are clearly present in the specification, drawings, and claims, and can be obtained from the description in the specification, drawings, and claims.

[0036] Brief description of the attached figures

[0037] Figure 1 This is a diagram illustrating an example of the structure of a semiconductor device.

[0038] Figures 2A to 2C This is a diagram illustrating an example of the structure of a cell array and a memory cell.

[0039] Figure 3 It is a timing diagram illustrating the operation of a storage unit.

[0040] Figure 4A and Figure 4B It is a diagram illustrating the electrical characteristics of a transistor.

[0041] Figures 5A to 5F This is a diagram illustrating an example of the structure of a storage unit.

[0042] Figure 6 This is a diagram illustrating an example of a cell array structure.

[0043] Figure 7 This is a diagram illustrating an example of a cell array structure.

[0044] Figure 8 This is a diagram illustrating an example of a cell array structure.

[0045] Figure 9 This is a diagram illustrating an example of a cell array structure.

[0046] Figure 10A and Figure 10B This is a diagram illustrating an example of the structure of a storage unit.

[0047] Figure 11 This is a cross-sectional diagram illustrating an example of the structure of a storage unit.

[0048] Figure 12 This is a diagram illustrating an example of the structure of a storage unit.

[0049] Figure 13 This is a cross-sectional diagram illustrating an example of the structure of a storage unit.

[0050] Figure 14 This is a diagram illustrating an example of the structure of a storage unit.

[0051] Figure 15 This is a diagram illustrating an example of the structure of a storage unit.

[0052] Figure 16 This is a diagram illustrating an example of the structure of a storage unit.

[0053] Figure 17A and Figure 17B This is a diagram illustrating a structural example in the region of low relative permittivity.

[0054] Figure 18A and Figure 18B This is a diagram illustrating a structural example in the region of low relative permittivity.

[0055] Figure 19A and Figure 19B This is a diagram illustrating a structural example in the region of low relative permittivity.

[0056] Figure 20A and Figure 20B This is a diagram illustrating a structural example in the region of low relative permittivity.

[0057] Figure 21A and Figure 21B This is a diagram illustrating a structural example in the region of low relative permittivity.

[0058] Figure 22A and Figure 22B This is a diagram illustrating an example of the manufacturing steps in the region of low relative permittivity.

[0059] Figures 23A to 23C This is a diagram illustrating an example of the manufacturing steps in the region of low relative permittivity.

[0060] Figure 24A and Figure 24B This is a diagram illustrating an example of the manufacturing steps in the region of low relative permittivity.

[0061] Figure 25This is a diagram illustrating an example of the structure of a storage unit.

[0062] Figure 26 This is a cross-sectional diagram illustrating an example of the structure of a storage unit.

[0063] Figure 27 This is a diagram illustrating an example of the structure of a storage unit.

[0064] Figure 28 This is a cross-sectional diagram illustrating an example of the structure of a storage unit.

[0065] Figures 29A to 29C This is a diagram illustrating an example of a transistor structure.

[0066] Figures 30A to 30C This is a diagram illustrating an example of a transistor structure.

[0067] Figure 31A and Figure 31B It is a diagram illustrating electronic components.

[0068] Figure 32 It is a diagram illustrating an electronic device.

[0069] Figures 33A to 33E It is a diagram illustrating an electronic device.

[0070] Figures 34A to 34C It is a diagram illustrating an electronic device.

[0071] Figures 35A to 35C It is a diagram illustrating an electronic device.

[0072] Figure 36 This is a diagram that shows various storage devices in a hierarchical manner.

[0073] Figure 37 It is a graph showing the data write time and write endurance of various storage devices.

[0074] Figure 38 It is a graph showing the data retention time and operating frequency of various storage devices.

[0075] Methods of implementing the invention

[0076] The embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments and examples shown below.

[0077] Note that in the inventive structure described below, the same symbols are used in different figures to represent the same parts or parts with the same function, and repeated descriptions are omitted. Furthermore, when representing parts with the same function, the same shading lines are sometimes used without additional symbols.

[0078] In the various figures of this specification, the size of the constituent elements, the thickness of the layers, and the area are sometimes exaggerated for ease of understanding. Therefore, the present invention is not limited to the dimensions shown in the figures.

[0079] In addition, in this specification, a high power supply potential is sometimes referred to as "H level" (also known as "VDD" or "H potential") and a low power supply potential is referred to as "L level" (also known as "VSS" or "L potential").

[0080] Note that voltage refers to the potential difference between two points, while potential refers to the electrostatic energy (potential energy) of a unit charge at a point in an electrostatic field. Generally, the potential difference between a point and a reference potential (e.g., ground potential) is simply referred to as potential or voltage; usually, potential and voltage are synonymous. Therefore, in this specification, unless specifically specified, "potential" may be referred to as "voltage," and "voltage" may be referred to as "potential."

[0081] Furthermore, the following embodiments and examples in this specification can be appropriately combined. Additionally, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0082] In this specification and the like, "metal oxide" refers to oxides of metals in a broad sense. Metal oxides are classified as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors. For example, when a metal oxide is used as the semiconductor layer of a transistor, it is sometimes referred to as an oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor containing either a metal oxide or an oxide semiconductor. In this specification and the like, nitrogen-containing metal oxides are sometimes collectively referred to as metal oxides.

[0083] Furthermore, unless otherwise stated, the transistors shown in this specification are enhancement-mode (normally off) n-channel field-effect transistors. Therefore, their threshold voltage (also referred to as "Vth") is greater than 0V.

[0084] (Implementation Method 1)

[0085] In this embodiment, a storage device according to one aspect of the present invention is described.

[0086] <Storage device>

[0087] Figure 1 This is a block diagram illustrating an example of the structure of a storage device. The storage device 100 includes peripheral circuitry 111 and a cell array 201. The peripheral circuitry 111 includes a row decoder 121, a word line driver circuit 122, a column decoder 131, a bit line driver circuit 130, an output circuit 140, and a control logic circuit 160. The cell array 201 includes storage cells 211, word lines WWL, RWL, bit lines WBL, and RBL.

[0088] The word line driver circuit 122 provides potential to the word line WWL and word line RWL. The bit line driver circuit 130 includes a pre-charge circuit 132, an amplifier circuit 133, and an input / output circuit 134. The pre-charge circuit 132 pre-charges the bit line RBL, etc. The amplifier circuit 133 amplifies the data signal read from the bit line RBL.

[0089] Word line WWL, word line RWL, bit line WBL, and bit line RBL are wiring connections to memory cell 211, which will be described in detail later. The amplified data signal is output as a digital data signal RDATA to the outside of memory device 100 via output circuit 140.

[0090] The storage device 100 is supplied with VDD and VSS as power supply potentials from an external source.

[0091] In addition, the storage device 100 receives external inputs such as clock signal CLK, chip enable signal CE, write enable signal WE, read enable signal RE, address signal ADDR, and data signal WDATA. The address signal ADDR is input to row decoder 121 and column decoder 131, and the data signal WDATA is input to input / output circuit 134.

[0092] The control logic circuit 160 processes the chip enable signal CE, the write enable signal WE, and the read enable signal RE to generate control signals for the row decoder 121 and the column decoder 131. For example, when the chip enable signal CE is high and the write enable signal WE is low, the row decoder 121 and the column decoder 131 perform read operations; when the chip enable signal CE is high and the write enable signal WE is high, the row decoder 121 and the column decoder 131 perform write operations; when the chip enable signal CE is low, regardless of whether the write enable signal WE is high or low, the row decoder 121 and the column decoder 131 simply standby.

[0093] Furthermore, the signals processed by the control logic circuit 160 are not limited to these. Other signals can also be input to the control logic circuit 160 as needed.

[0094] The above circuits or signals can be used or not used as needed.

[0095] OS transistors can be used as the transistors constituting the cell array 201. Furthermore, OS transistors can be used as the transistors constituting the peripheral circuit 111. By using OS transistors to form both the cell array 201 and the peripheral circuit 111, both can be manufactured using the same manufacturing process, thereby reducing manufacturing costs.

[0096] Furthermore, OS transistors can be used not only in storage devices but also in logic circuits such as central processing units (CPUs) and graphics processing units (GPUs). Integrated circuits using OS transistors are collectively referred to as "OS-LSI".

[0097] [Example of a cell array structure]

[0098] Figure 2A The details of cell array 201 are shown. Cell array 201 has m (m is an integer greater than or equal to 1) cells in one column and n (n is an integer greater than or equal to 1) cells in one row, for a total of m×n storage cells 211. The storage cells 211 are configured in a row-column structure.

[0099] Figure 2A The addresses of memory cells 211 are also shown. For example, [1,1] represents the memory cell 211 located in the first row and first column, and [i,j] (where i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n) represents the memory cell 211 located in the i-th row and j-th column. Furthermore, the number of wirings connecting the cell array 201 and the word line driver circuit 122 is determined by the structure of the memory cells 211 and the number of memory cells 211 in a column, etc. Similarly, the number of wirings connecting the cell array 201 and the bit line driver circuit 130 is determined by the structure of the memory cells 211 and the number of memory cells 211 in a row, etc.

[0100] In this embodiment, the cell array 201 includes n bit lines WBL (WBL[1] to WBL[n]), n bit lines RBL (RBL[1] to RBL[n]), m word lines WWL (WWL[1] to WWL[m]) and m word lines RWL (RWL[1] to RWL[m]).

[0101] Storage cell 211 is connected to bit line WBL, bit line RBL, word line WWL, and word line RWL. For example... Figure 2A As shown, the memory cell 211 with address [i,j] is electrically connected to the word line driver circuit 122 through word line WWL[i] and word line RWL[i], and electrically connected to the bit line driver circuit 130 through bit line WBL[j] and bit line RBL[j].

[0102] [Example of a storage unit structure]

[0103] Figure 2B , Figure 2C and Figures 5A to 5D An example of a circuit structure that can be applied to memory cell 211 is shown. Figure 2B An example circuit structure of a gain-cell type (also known as "2Tr1C type") memory cell 211A is shown, comprising two transistors and a capacitor. Memory cell 211A includes transistor M11, transistor M12, and capacitor Cs.

[0104] In memory cell 211A, one of the source and drain of transistor M11 is electrically connected to the first terminal of capacitor Cs and the gate of transistor M12; the other of the source and drain of transistor M11 is electrically connected to bit line WBL; and the gate of transistor M11 is electrically connected to word line WWL. One of the source and drain of transistor M12 is electrically connected to word line RWL, and the other of the source and drain of transistor M12 is electrically connected to bit line RBL. Furthermore, the second terminal of capacitor Cs is electrically connected to wiring CAL. Wiring CAL serves as wiring to apply a specified potential to the second terminal of capacitor Cs. The node where one of the source and drain of transistor M11, the first terminal of capacitor Cs, and the gate of transistor M12 are electrically connected is called node SN.

[0105] Bit line WBL is used as the write bit line, bit line RBL is used as the read bit line, word line WWL is used as the write word line, and word line RWL is used as the read word line. Transistor M11 is used as a switch to turn node SN on or off with bit line WBL.

[0106] Reference Figure 3 This section describes the data writing and data reading operations of storage unit 211A. Figure 3 This is a timing diagram used to illustrate the operation of memory cell 211A. To write data, during the data write period (Twrite), VDD is applied to the word line WWL, turning on transistor M11 (also called the "on state"), thus electrically connecting node SN to bit line WBL. At this time, the potential of word line RWL is set to VDD. Furthermore, it is preferable to also set the potential of bit line RBL to VDD.

[0107] Specifically, when transistor M11 is in the ON state, the potential (e.g., VDD) corresponding to the data being written (Vdata) is applied to the bit line WBL, thereby writing this potential to node SN through transistor M11. Then, VSS is applied to the word line WWL, causing transistor M11 to become non-ON (also known as "OFF"), thereby maintaining the potential of node SN.

[0108] The parasitic capacitance Cz is generated between the gate of transistor M11 and one of its source and drain terminals. The word line WWL and node SN are capacitively coupled through the parasitic capacitance Cz. Therefore, as the potential of word line WWL drops from VDD to VSS at the end of the write operation, the potential of node SN drops by a voltage ΔV1.

[0109] With the capacitance of node SN being Csn, the voltage ΔV1 depends on the ratio of the parasitic capacitance Cz to the capacitance Csn. The larger the capacitance Csn is than the parasitic capacitance Cz, the smaller the voltage ΔV1.

[0110] Furthermore, the capacitance Csn includes the parasitic capacitance Cx generated in node SN and the gate capacitance of transistor M12. The capacitance Csn can be increased by increasing the gate capacitance of transistor M12.

[0111] Furthermore, the parasitic capacitance Cz is proportional to the gate capacitance of transistor M11, and in particular, proportional to the channel width of transistor M11. Moreover, when the parasitic capacitance Cx is much smaller than the gate capacitance of transistor M12, the gate capacitance of transistor M12 dominates in the total capacitance Csn. In this case, by making the gate capacitance of transistor M12 larger than that of transistor M11, the voltage ΔV1 can be reduced.

[0112] In order to read data, during the data readout period (Tread), after applying a specified potential to the bit line RBL, the bit line RBL is made to float, and then a low-level potential is applied to the word line RWL. Hereinafter, "making the bit line RBL to float after applying a specified potential to the bit line RBL" is referred to as "pre-charging the bit line RBL".

[0113] For example, bit line RBL is pre-charged to VDD, and then word line RWL is applied with VSS. At this point, if the potential difference between node SN and word line RWL is above the threshold voltage of transistor M12, the potential of bit line RBL decreases at a rate corresponding to that potential difference. In other words, by knowing the potential change of bit line RBL, the potential held by node SN can be read.

[0114] Furthermore, the row containing memory cells 211A to be written to is selected by applying VDD to the word line WWL, and the row containing memory cells 211 to be read is selected by applying VSS to the word line RWL. Conversely, a non-selection state can be formed by applying VSS to the word line WWL in the row containing memory cells 211 to which data is not to be written, and applying a potential higher than that used to precharge the bit line RBL to the word line RWL in the row containing memory cells 211A to which data is not to be read.

[0115] Here, transistors M11 and M12 can be transistors containing metal oxide in the channel formation region (OS transistors). For example, a metal oxide containing any one of indium, element M (element M is selected from one or more of aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) and zinc can be used in the channel formation region of transistors M11 and M12. Metal oxides composed of indium, gallium, and zinc are particularly preferred.

[0116] The off-state current of the OS transistor is very small, so by using the OS transistor as transistor M11, the potential written to node SN can be maintained for a long time. In other words, the data written to memory cell 211A can be maintained for a long time.

[0117] There are no particular restrictions on the transistor used as transistor M12. OS transistors, Si transistors, or other transistors can also be used as transistor M12.

[0118] Furthermore, when using a Si transistor in transistor M12, the silicon used to form the semiconductor layer of the channel can be amorphous silicon, polycrystalline silicon, low-temperature polycrystalline silicon (LTPS), or monocrystalline silicon. Since the field-effect mobility of Si transistors is sometimes higher than that of OS transistors, the readout speed can be improved when using Si transistors as readout transistors.

[0119] When transistor M11 uses an OS transistor and transistor M12 uses a Si transistor, they can be placed in different layers. OS transistors can be manufactured using the same equipment and processes as Si transistors. Therefore, it is easy to mix and mount OS transistors and Si transistors (hybridization), and high integration can be easily achieved.

[0120] Furthermore, using an OS transistor in transistor M12 minimizes leakage current during non-selection, thereby improving readout accuracy. By using OS transistors for both transistors M11 and M12, the number of manufacturing steps in semiconductor devices can be reduced, increasing productivity. For example, semiconductor devices can be manufactured at process temperatures below 400°C.

[0121] In this specification, the memory device that uses OS transistors as transistor M11 to form 2Tr1C type memory cells is called NOSRAM (Non-volatile Oxide Semiconductor Random Access Memory).

[0122] As described above, memory cell 211A is a 2Tr1C type memory cell. Even when the capacitor Cs storing charge is small, memory cell 211A can function as a memory by amplifying the stored charge using transistor M12. Furthermore, the off-state current of the OS transistor is very small; therefore, by using the OS transistor as transistor M11, the capacitor Cs can be reduced or eliminated.

[0123] Figure 2C An example circuit structure of a DRAM (Dynamic Random Access Memory) type memory cell 211R, including a transistor and a capacitor, is shown. The memory cell 211R includes a transistor M11 and a capacitor Cs.

[0124] In memory cell 211R, one of the source and drain of transistor M11 is electrically connected to the first terminal of capacitor Cs, the other of the source and drain of transistor M11 is electrically connected to bit line BL, and the gate of transistor M11 is electrically connected to word line WL. Furthermore, the second terminal of capacitor Cs is electrically connected to wiring CAL. Wiring CAL serves as wiring to apply a specified potential to the second terminal of capacitor Cs. The node where one of the source and drain of transistor M11 is electrically connected to the first terminal of capacitor Cs is called node SN.

[0125] By using an OS transistor as transistor M11 in memory cell 211R, capacitor Cs can be reduced or eliminated. Furthermore, transistor M11 can be used to hold written data for extended periods, thereby reducing the refresh frequency of the DRAM-type memory cell, or even eliminating the need for DRAM-type memory cell refresh.

[0126] In this specification, a memory device that uses OS transistors as transistors M11 to form DRAM-type memory cells is referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory).

[0127] By using OS transistors, the footprint of memory cells can be reduced. Therefore, miniaturization or high integration of memory devices is easily achieved.

[0128] Here, the temperature dependence of the Id-Vg characteristic, one of the electrical characteristics of transistors, is explained. Figure 4A and Figure 4B This illustrates an example of the Id-Vg characteristic, one of the electrical characteristics of a transistor. The Id-Vg characteristic represents the change in drain current (Id) relative to a change in gate voltage (Vg). Figure 4A and Figure 4BThe horizontal axis represents Vg on a linear scale. Furthermore, Figure 4A and Figure 4B The vertical axis is shown on a logarithmic scale for Id.

[0129] Figure 4A The Id-Vg characteristics of the OS transistor are shown. Figure 4B The Id-Vg characteristics of a transistor (also known as a "Si transistor" or "Si-FET") in which silicon is used to form a semiconductor layer in which a channel is formed are shown. Figure 4A and Figure 4B Both are Id-Vg characteristics of n-channel transistors.

[0130] like Figure 4A As shown, even when operating at high temperatures, the off-state current of an OS transistor does not easily increase. OS transistors can achieve on / off ratios exceeding ten digits even at operating temperatures above 125°C and below 150°C. As the operating temperature of an OS transistor increases, Vth shifts negatively, and the on-state current increases. Therefore, the higher the operating temperature, the easier it is to improve the frequency characteristics. On the other hand, as... Figure 4B As shown, the off-state current of a Si transistor increases with rising temperature. Conversely, as the temperature rises, the Vth of the Si transistor shifts in the positive direction, and the on-state current decreases.

[0131] By using OS transistors as transistors M11 and M12, data can be retained for extended periods even at high temperatures. Furthermore, the power consumption of the storage device can be reduced even when operating at high temperatures.

[0132] By using OS transistors as transistors M11 and M12, for example, an operating frequency of over 200MHz can be achieved under conditions of a drive voltage of 2.5V and an operating temperature of -40°C to 85°C.

[0133] Figure 5A An example of the circuit structure of the storage cell 211 without capacitor Cs is shown. Figure 5A The illustrated memory cell 211B has a circuit structure that removes capacitor Cs from memory cell 211A. In memory cell 211B, the charge (potential) written to node SN is mainly held by the gate capacitance and parasitic capacitance Cx of transistor M12. Furthermore, the gate capacitance can also be considered as part of the parasitic capacitance Cx.

[0134] Alternatively, a transistor with a back gate can be used as one or both of transistors M11 and M12.

[0135] In actual transistors, the gate and back gate overlap each other through channel formation regions separated by semiconductor layers. Both the gate and back gate can be used as gates. Therefore, one is sometimes called the "back gate" and the other is called the "gate" or "front gate". In addition, one is sometimes called the "first gate" and the other is called the "second gate".

[0136] The potential of the back gate can be the same as the gate, or it can be ground or any other potential. Furthermore, by making the potential of the back gate change independently of the gate, the threshold voltage of the transistor can be altered.

[0137] By setting a back gate and making the potentials of the gate and back gate equal, the area through which charge carriers flow in the semiconductor layer is further expanded in the film thickness direction, thus increasing the amount of charge carrier migration. As a result, the on-state current of the transistor increases, and the field-effect mobility also increases.

[0138] Therefore, transistors with a large on-state current relative to their occupied area can be manufactured. That is, the transistor's occupied area relative to the required on-state current can be reduced. Therefore, highly integrated semiconductor devices can be realized.

[0139] Figures 5B to 5D The diagram shows an example of a circuit structure where transistors M11 and M12 use transistors with a back gate (4-terminal transistors, also known as "4-terminal elements"). Figure 5B The storage unit 211C shown Figure 5C The storage cell 211D shown and Figure 5D The storage cell 211E shown is a modified example of storage cell 211B.

[0140] exist Figure 5B In the memory cell 211C shown, the gate of transistor M11 is electrically connected to the back gate. Furthermore, the gate of transistor M12 is electrically connected to the back gate.

[0141] exist Figure 5C In the memory cell 211D shown, the back gates of transistor M11 and M12 are electrically connected to wiring BGL. Through wiring BGL, a specified potential can be applied to the back gates of transistors M11 and M12.

[0142] By utilizing the potential of the wiring BGL, the threshold voltages of transistors M11 and M12 can be changed. Specifically, by increasing the potential applied to the back gates of transistors M11 and M12, each threshold voltage drifts to a negative value. By drifting the threshold voltages to negative values, the on-state current of the transistors can be increased, and the operating speed of the memory cell 211D can be improved.

[0143] Furthermore, by reducing the potential applied to the back gates of transistors M11 and M12, each threshold voltage drifts to a positive value. By drifting the threshold voltages to a positive value, the off-state current of the transistors can be reduced, thereby allowing the data written to memory cell 211D to be retained for a longer period of time.

[0144] exist Figure 5D In the memory cell 211E shown, the back gate of transistor M11 is electrically connected to wiring WBGL, and the back gate of transistor M12 is electrically connected to wiring RBGL. By connecting the back gates of transistor M11 and transistor M12 to different wirings, the threshold voltage can be changed independently.

[0145] Furthermore, the storage device using storage cells 211B to 211E can also be referred to as NOSRAM.

[0146] also, Figures 5B to 5D The transistor shown is a 4-terminal device, which gives it the advantage of being able to easily and independently control input and output compared to 2-terminal devices such as MRAM (Magnetoresistive Random Access Memory), ReRAM (Resistive Random Access Memory), and Phase-change memory that utilize the characteristics of MTJ (Magnetic Tunnel Junction).

[0147] Furthermore, MRAM, ReRAM, and phase-change memories sometimes undergo atomic-level structural changes when rewriting information. On the other hand, a storage device according to one aspect of the present invention operates by charging or discharging charges through transistors when rewriting information, thus exhibiting good rewrite durability and minimal structural changes.

[0148] Without capacitor Cs in storage cell 211, node SN is susceptible to noise. Specifically, through capacitive coupling between node SN and adjacent storage cells, it is easily affected by potential fluctuations in adjacent storage cells. As a result, data retention time is shortened, read accuracy is reduced, and this leads to decreased reliability of the storage device.

[0149] The aforementioned noise can be reduced by decreasing the parasitic capacitance between adjacent memory cells. In one embodiment of the invention, to reduce the parasitic capacitance between adjacent memory cells, a low relative permittivity region (LDR) can be provided outside the memory cell. The relative permittivity of the LDR only needs to be less than the relative permittivity of the adjacent insulating layer.

[0150] For example, such as Figure 5E As shown, an LDR221 is provided on the outside of the storage unit 211E. Figure 6 The storage cells 211[i,j] to 211[i+1,j+2] are arranged in a matrix and Figure 5E The example configuration of LDR221 is shown. Furthermore, in Figure 6 In China, use Figure 5D The storage unit 211E shown is used as storage unit 211.

[0151] also, Figure 7 Show Figure 6 Examples of variations. For example... Figure 7 As shown, several LDR221s can also be connected. Figure 7 The LDR221 shown includes regions extending along word lines and regions extending along bit lines.

[0152] In addition, such as Figure 5F As shown, an entire storage cell 211E can also be formed by LDR221 surrounding a storage cell 211E. Figure 8 The storage cells 211[i,j] to 211[i+1,j+2] are arranged in a matrix and Figure 5F The example configuration of LDR221 is shown. Furthermore, in Figure 8 In this context, storage unit 211E is used as storage unit 211. Figure 8 The LDR221 shown also includes the region extending along the word line and the region extending along the bit line.

[0153] By setting up LDR, the impact of noise can be reduced and the reliability of the storage device can be improved.

[0154] This embodiment can be implemented by appropriately combining the structures shown in other embodiments, etc.

[0155] (Implementation Method 2)

[0156] In this embodiment, examples of the planar structure and cross-sectional structure of the storage unit 211 and LDR 221 are described with reference to the accompanying drawings.

[0157] Figure 9An example of a planar structure with storage cells 211[i,j] to 211[i+1,j+2] configured as a matrix is ​​shown. Furthermore, Figure 9 The example of the planar structure shown is equivalent to Figure 7 The circuit diagram.

[0158] exist Figure 9 In this configuration, adjacent storage cells 211 are arranged in a mirror-symmetric manner. For example, storage cells 211[i,j] and 211[i,j+1] are mirror-symmetric. Furthermore, storage cells 211[i,j] and 211[i+1,j] are also mirror-symmetric. By configuring the storage cells 211 in this way, contact plugs and other components can be shared between adjacent storage cells, allowing for efficient configuration of the storage cells 211. This improves the integration density of the storage cells 211.

[0159] <Example of a planar structure>

[0160] Figure 10A Show Figure 7 Example of a planar structure for storage unit 211[i+1,j].

[0161] One of the source and drain of transistor M11 is electrically connected to conductive layer 360 via electrode 341. Conductive layer 360 serves as the gate electrode of transistor M12. The region including electrode 341 and conductive layer 360 serves as node SN. The other of the source and drain of transistor M11 is electrically connected to conductive layer 339. Conductive layer 339 serves as bit line WBL.

[0162] One of the source and drain of transistor M12 is electrically connected to conductive layer 333 through conductive layer 312, and the other of the source and drain of transistor M12 is electrically connected to conductive layer 338. Conductive layer 333 is used as word line RWL, and conductive layer 338 is used as bit line RBL.

[0163] also, Figure 10A The conductive layer 305 is used for wiring RBGL, and the conductive layer 306 is used for wiring WBGL. Furthermore, conductive layer 261 is used for word line WWL, and conductive layer 333 is used for word line RWL. A portion of conductive layer 305 is used as the back gate electrode of transistor M12. A portion of conductive layer 306 is used as the back gate electrode of transistor M11.

[0164] exist Figures 9 to 10B In the middle, LDR221 has a region extending along bit line RBL (conductive layer 338) and a region extending along word line RWL.

[0165] Because the storage cell 211 in one embodiment of the present invention does not have a capacitor Cs, the area occupied by the storage cell 211 can be reduced. However, when the area is reduced, it is more susceptible to noise generated in adjacent storage cells, etc. By setting up LDR 221, the noise transmitted to node SN can be reduced.

[0166] However, reduced noise transmitted to node SN also means reduced parasitic capacitance generated in node SN. Therefore, the gate capacitance of transistor M12 dominates the holding capacitance of node SN. Thus, as Figure 10B As shown, the overlapping area of ​​the semiconductor layer 260 and the conductive layer 360 of transistor M12 can also be increased, thereby increasing the gate capacitance of transistor M12. Furthermore, increasing the gate capacitance of transistor M12 is effective in mitigating the potential drop at node SN that occurs at the end of the write operation.

[0167] Specifically, the area of ​​overlap between the semiconductor layer of transistor M12 and the gate electrode is preferably more than 1 and less than 5 times the area of ​​overlap between the semiconductor layer of transistor M11 and the gate electrode, more preferably more than 1 and less than 10 times, and even more preferably more than 1 and less than 50 times.

[0168] <Example of cross-sectional structure>

[0169] Figure 11 Show along Figure 10A Examples of cross-sectional structures for the dashed-dot lines, specifically sections A1-A2, B1-B2, and C1-C2.

[0170] exist Figure 11 In this embodiment, a transistor M12 is disposed on a substrate 301. Alternatively, a transistor M11 may have the same stacked structure as transistor M12. An insulating layer 309 and an insulating layer 326 are disposed on the substrate 301, and conductive layers 305 and 306 are embedded in the insulating layer 326. Furthermore, insulating layers 322 and 324 are disposed on the insulating layer 326, and a semiconductor layer 260 is disposed on the insulating layer 324.

[0171] Furthermore, insulating layers 354 and 380 are provided on insulating layer 324 and semiconductor layer 260. Additionally, conductive layers 360 and 261 are embedded in insulating layer 380. Insulating layer 374 is provided on insulating layer 380, conductive layer 360, and conductive layer 261, and insulating layer 381 is provided on insulating layer 374.

[0172] In addition, conductive layers 312, 313, and 314 are disposed on the insulating layer 381. Conductive layer 312 is electrically connected to one of the source and drain terminals of transistor M12. Conductive layer 313 is electrically connected to the other of the source and drain terminals of transistor M12.

[0173] In addition, insulating layers 311 and 315 are provided on insulating layer 381, conductive layer 312, conductive layer 313, and conductive layer 314. Conductive layers 332 and 333 are provided on insulating layer 315. Conductive layer 332 is electrically connected to conductive layer 313 via contact plug 317, and conductive layer 333 is electrically connected to conductive layer 314 via contact plug 318.

[0174] Insulating layers 331, 319, and 334 are disposed on insulating layers 315, 332, and 333, respectively. An LDR 221 is disposed on a portion of insulating layer 319. The LDR 221 includes multiple LDS 235s (Low Dielectric Constant Spaces). The LDR 221 and LDS 235 are described in detail later.

[0175] An insulating layer 334 is provided on insulating layer 319 and LDS235. Insulating layers 335 and 336 are provided on insulating layer 334. A conductive layer 338 is provided on insulating layer 336, and this conductive layer 338 is electrically connected to conductive layer 332 via a contact plug 337. Furthermore, an insulating layer 343 is provided on insulating layer 336 and conductive layer 338.

[0176] Variation Example 1

[0177] In addition, such as Figure 12 and Figure 13 As shown, by changing the shape of a portion of the conductive layer 306 to overlap the conductive layer 306 with the node SN, the parasitic capacitance Cx generated in the node SN can be increased. Figure 12 An example of a planar structure for storage cell 211[i+1,j] is shown. Figure 13 Show along Figure 12 Example of the cross-sectional structure of the dotted-dash section G1-G2 in the image.

[0178] exist Figure 12 and Figure 13 In this configuration, one of the source and drain terminals of transistor M11, conductive layer 341, and conductive layer 306 are arranged in a manner that maximizes overlap. This structure allows for the increase of the parasitic capacitance Cx of node SN even in the absence of capacitor Cs.

[0179] In addition, Figure 12 In order to clearly show the conductive layer 306, it is indicated by a shaded line. The conductive layer 306 can be formed simultaneously using the same material and method as the conductive layer 305, which is not indicated by a shaded line.

[0180] Variation Example 2

[0181] In addition, such as Figure 14As shown, by increasing the area of ​​the conductive layer 306, the area of ​​overlap between the conductive layer 306 and the memory cell 211[i+1,j] can be increased.

[0182] Variation Example 3

[0183] In addition, such as Figure 15 As shown, by increasing the area of ​​overlap between the conductive layer 305 and the node SN, the parasitic capacitance Cx of the node SN can be increased.

[0184] exist Figure 15 In this configuration, by altering a portion of the shape of the conductive layer 305, one of the source and drain terminals of transistor M11, the conductive layer 341, and the conductive layer 305 are arranged in a manner that maximizes overlap. This structure allows for the increase of the parasitic capacitance Cx of node SN even in the absence of a capacitor Cs.

[0185] In addition, Figure 15 In order to clearly show the conductive layer 305, it is indicated by a shaded line. The conductive layer 305 can be formed simultaneously using the same material and method as the conductive layer 306, which is not indicated by a shaded line.

[0186] Variation Example 4

[0187] In addition, such as Figure 16 As shown, by increasing the area of ​​the conductive layer 305, the area of ​​overlap between the conductive layer 305 and the memory cell 211[i+1,j] can be increased.

[0188] <Constructing Materials>

[0189] [Substrate]

[0190] There are few restrictions on the substrate material. For example, insulating substrates, semiconductor substrates, or conductive substrates can be used as substrates.

[0191] Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconium oxide substrates (yttrium oxide stabilized zirconium oxide substrates, etc.), and resin substrates.

[0192] Furthermore, examples of semiconductor substrates include those made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon-germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Additionally, examples of semiconductor substrates having insulating regions within the aforementioned semiconductor substrates include SOI (Silicon On Insulator) substrates.

[0193] Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides can be used. Furthermore, examples include insulating substrates with conductors or semiconductors, semiconductor substrates with conductors or insulators, and conductive substrates with semiconductors or insulators. Substrates on which components are disposed can also be used. Examples of components disposed on the substrate include capacitors, resistors, switching elements, light-emitting elements, and storage elements. Additionally, substrates on which semiconductor elements such as strain gauge transistors or Fin-type transistors are disposed can be used. In other words, the substrate can be not only a supporting substrate but also a substrate on which transistors or other devices are formed.

[0194] [Insulating layer]

[0195] Materials used for insulating layers include oxides, nitrides, oxynitrides, nitrogen oxides, metal oxides, metal oxynitrides, and metal nitrogen oxides, all of which possess insulating properties.

[0196] For example, when miniaturizing and highly integrating transistors, problems such as leakage current sometimes occur due to the thinning of the gate insulating layer. By using a high-k material as the insulating layer used as the gate insulating layer, it is possible to achieve low voltage during transistor operation while maintaining the physical thickness. On the other hand, by using a material with a low relative permittivity as the insulating layer used as the interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select materials according to the function of the insulating layer.

[0197] In addition, examples of insulators with relatively high permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0198] In addition, examples of insulating materials with relatively low permittivity include silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide or resin with pores, etc.

[0199] Furthermore, when using an OS transistor, the transistor's electrical characteristics can be stabilized by surrounding it with insulating layers (insulating layers 309, 322, 354, and 374, etc.) that suppress the permeation of impurities such as hydrogen and oxygen. As the insulator that suppresses the permeation of impurities such as hydrogen and oxygen, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used, either as a single layer or in a stack. Specifically, as the insulating layer that suppresses the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, as well as metal nitrides such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon oxynitride, or silicon nitride can be used.

[0200] Furthermore, the insulating layer used as the gate insulating layer is preferably an insulator having regions containing oxygen that has been removed by heating. For example, by employing a structure in which silicon oxide or silicon oxynitride having regions containing oxygen that has been removed by heating is contacted with the semiconductor layer 260, oxygen vacancies contained in the semiconductor layer 260 can be filled.

[0201] Note that in this specification, nitrogen oxides refer to compounds in which the nitrogen content is greater than the oxygen content. Furthermore, oxynitrides refer to compounds in which the oxygen content is greater than the nitrogen content. Additionally, the content of each element can be determined, for example, using Rutherford backscattering spectrometry (RBS).

[0202] Furthermore, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, it is preferable to reduce the hydrogen concentration in the insulating layer to prevent an increase in the hydrogen concentration in the semiconductor layer. Specifically, the hydrogen concentration in the insulating layer, as measured by secondary ion mass spectrometry (SIMS), is 2 × 10⁻⁶. 20 atoms / cm 3 The following is preferred: 5×10 19 atoms / cm 3 Hereinafter, 1×10 is more preferred. 19 atoms / cm 3 The following is a further preferred option: 5×10 18 atoms / cm 3 The following is particularly important. It is preferable to reduce the hydrogen concentration in the insulating layer that contacts the semiconductor layer.

[0203] Furthermore, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, it is preferable to reduce the nitrogen concentration in the insulating layer to prevent an increase in the nitrogen concentration in the semiconductor layer. Specifically, the nitrogen concentration in the insulating layer, as measured by SIMS, is 5 × 10⁻⁶. 19 atoms / cm 3 The following is preferred: 5×10 18 atoms / cm 3 Hereinafter, 1×10 is more preferred. 18 atoms / cm 3 The following is a further preferred option: 5×10 17 atoms / cm 3 the following.

[0204] Furthermore, the region in the insulating layer that is in contact with at least the semiconductor layer preferably has few defects, typically indicating a low level of signal observed by electron spin resonance (ESR). For example, the E' center observed at a g value of 2.001 can be cited as an example of such a signal. The E' center originates from dangling bonds in silicon. For example, when using a silicon oxide layer or a silicon oxynitride layer as the insulating layer, a spin density of 3 × 10⁻⁶ originating from the E' center can be used. 17 spins / cm 3 The following, preferably 5×10 16 spins / cm 3 The following silicon oxide layer or silicon oxynitride layer.

[0205] Sometimes, in addition to the signals mentioned above, signals originating from nitrogen dioxide (NO2) are observed. This signal splits into three signals due to the nuclear spin of N: a g value greater than or equal to 2.037 and less than 2.039 (first signal), a g value greater than or equal to 2.001 and less than 2.003 (second signal), and a g value greater than or equal to 1.964 and less than 1.966 (third signal).

[0206] For example, as an insulating layer, it is preferable to use a signal originating from nitrogen dioxide (NO2) with a spin density of 1×10⁻⁶. 17 spins / cm 3 Above and less than 1×10 18 spins / cm 3 The insulating layer.

[0207] Nitrogen dioxide (NO2) and nitrogen oxides (NO) x An energy level is formed in the insulating layer. This energy level is located in the bandgap of the oxide semiconductor layer. Therefore, when nitrogen oxides (NO...)... xWhen electrons diffuse to the interface between the insulating layer and the oxide semiconductor layer, this energy level sometimes traps electrons on the insulating layer side. As a result, the trapped electrons remain near the interface between the insulating layer and the oxide semiconductor layer, thereby causing the threshold voltage of the transistor to drift in the positive direction. Therefore, when a film with a low content of nitrogen oxides is used as the insulating layer, the drift of the transistor's threshold voltage can be reduced.

[0208] As nitrogen oxides (NO) x For insulating layers with low ammonia release, silicon oxynitride layers can be used, for example. These silicon oxynitride layers exhibit a lower ammonia release compared to nitrogen oxides (NOx) as measured by thermal desorption spectroscopy (TDS). x Membranes that release a large amount of ammonia, typically 1×10⁻⁶. 18 pcs / cm 3 Above and 5×10 19 pcs / cm 3 The following is a summary. Furthermore, the ammonia release mentioned above refers to the total amount released in TDS within a temperature range of 50°C to 650°C or 50°C to 550°C during heat treatment.

[0209] Because when heat treatment is performed, nitrogen oxides (NOx) x It reacts with ammonia and oxygen, so using an insulating layer with high ammonia release can reduce nitrogen oxides (NOx). x ).

[0210] At least one of the insulating layers in contact with the oxide semiconductor layer is preferably formed using an insulating layer that releases oxygen upon heating. Specifically, an insulating layer is preferably used where the amount of oxygen removed, converted to oxygen atoms, is 1.0 × 10⁻⁶ when performing TDS analysis (wherein a heat treatment is performed at a film surface temperature of 100°C or higher and 700°C or lower, preferably 100°C or higher and 500°C or lower). 18 atoms / cm 3 The preferred value is 1.0 × 10⁴. 19 atoms / cm 3 or above 1.0×10 20 atoms / cm 3 That's all. Furthermore, in this specification and other materials, the oxygen released by heating is referred to as "excess oxygen".

[0211] Furthermore, an insulating layer containing excess oxygen can be formed by adding oxygen to the insulating layer. As an oxygen addition treatment, heat treatment under an oxidizing atmosphere, plasma treatment, etc., can be used. Alternatively, oxygen addition can be performed using ion implantation, ion doping, plasma immersion ion implantation, etc. Examples of gases used in the oxygen addition treatment include... 16 O2 or18 Oxygen gases such as O2, nitrous oxide, or ozone are also oxygen-containing gases. Note that in this specification, the process of adding oxygen is sometimes referred to as "oxygen doping." Oxygen doping can also be performed while the substrate is heated.

[0212] As an insulating layer, heat-resistant organic materials such as polyimide, acrylic resins, benzocyclobutene resins, polyamides, and epoxy resins can be used. In addition to the above organic materials, low-dielectric-constant materials (low-k materials), siloxane resins, PSG (phosphosilicate glass), and BPSG (borophosphosilicate glass) can also be used. Furthermore, a planarized insulating layer can be formed by stacking multiple insulating films made of these materials.

[0213] Siloxane resins are resins containing Si-O-Si bonds formed from siloxane materials as starting materials. Siloxane resins may include organic groups (e.g., alkyl or aryl) or fluorine groups as substituents. Furthermore, the organic groups may also have fluorine groups.

[0214] There are no particular restrictions on the method for forming the insulating layer. Note that sometimes a baking process is required depending on the material used in the insulating layer. In this case, transistors can be manufactured efficiently by combining the baking process of the insulating layer with another heat treatment process.

[0215] There are no particular restrictions on the method for forming the insulating layer. Note that sometimes a baking process is required depending on the material used in the insulating layer. In this case, transistors can be manufactured efficiently by combining the baking process of the insulating layer with another heat treatment process.

[0216] [Conductor]

[0217] As the conductive layer, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above-mentioned metallic elements, or an alloy combining the above-mentioned metallic elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even after absorbing oxygen, and are therefore preferred. In addition, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicides can also be used.

[0218] Furthermore, multiple conductive layers formed from the aforementioned materials can be stacked. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Additionally, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0219] Furthermore, when an oxide semiconductor, which is a type of metal oxide, is used as the semiconductor layer, a stacked structure combining a material containing the aforementioned metal element and an oxygen-containing conductive material is preferably adopted as the conductive layer used as the gate electrode. In this case, it is preferable to provide the oxygen-containing conductive material on the channel formation region side. By providing the oxygen-containing conductive material on the channel formation region side, oxygen detached from the conductive material can be easily supplied to the channel formation region.

[0220] In particular, as the conductive layer used as the gate electrode, a conductive material containing a metal element and oxygen contained in the metal oxide in which the channel is formed is preferably used. Alternatively, a conductive material containing the aforementioned metal element and nitrogen can also be used. For example, nitrogen-containing conductive materials such as titanium nitride and tantalum nitride can be used. Furthermore, indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon can also be used. By using the above materials, hydrogen contained in the metal oxide forming the channel can sometimes be trapped. Or, hydrogen mixed in from external insulators or the like can sometimes be trapped.

[0221] Furthermore, highly embedded conductive materials such as tungsten or polycrystalline silicon can be used as conductive materials for the contact plug. Alternatively, a combination of highly embedded conductive materials with barrier layers (diffusion prevention layers) such as titanium layers, titanium nitride layers, or tantalum nitride layers can also be used.

[0222] [Semiconductor layer]

[0223] As the semiconductor layer, one or more of the following can be used: single-crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or amorphous semiconductor. As the semiconductor material, silicon or germanium can be used, for example. Furthermore, compound semiconductors or organic semiconductors such as silicon-germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used.

[0224] Furthermore, when using organic semiconductors as semiconductor layers, low-molecular-weight organic materials with aromatic rings or π-electron conjugated conductive polymers can be used. For example, red fluorene, tetraphenylene, pentaphenylene, perylene diimide, tetracyanoquinone dimethyl ether, polythiophene, polyacetylene, and poly(p-phenylene vinylidene) can be used.

[0225] Semiconductor layers can also be stacked. When semiconductor layers are stacked, semiconductors with different crystal states can be used, as can different semiconductor materials.

[0226] Furthermore, since oxide semiconductors, as a type of metal oxide, have a band gap of 2 eV or more, transistors with extremely low off-state currents can be realized when oxide semiconductors are used as the semiconductor layer. Specifically, the off-state current can be set to less than 1 × 10⁻⁶ eV for a source-drain voltage of 3.5 V and a channel width of 1 μm at room temperature (typically 25 °C). -20 A. Less than 1×10 -22 A or less than 1×10 -24 A. That is to say, the switching ratio can be 20 digits or more. Furthermore, in transistors using oxide semiconductors (OS transistors) as the semiconductor layer, the insulation withstand voltage between the source and drain is high. Therefore, transistors with high reliability can be provided. Furthermore, transistors with high output voltage and high withstand voltage can be provided. Furthermore, memory devices with high reliability can be provided, etc. Furthermore, memory devices with high output voltage and high withstand voltage can be provided.

[0227] Compared to OS transistors, crystalline Si transistors readily achieve higher mobility. However, crystalline Si transistors struggle to achieve the extremely low off-state currents of OS transistors. Therefore, it is important to appropriately select the semiconductor material used for the semiconductor layer based on its purpose and application. For example, depending on the purpose or application, a combination of OS transistors and crystalline Si transistors may be used.

[0228] When using an oxide semiconductor layer as the semiconductor layer, it is preferable to form the oxide semiconductor layer by sputtering. Oxide semiconductor layers formed by sputtering have a higher density, making it preferred. When forming the oxide semiconductor layer by sputtering, a rare gas (typically argon), oxygen, or a mixture of a rare gas and oxygen can be used as the sputtering gas. Furthermore, it is necessary to ensure the high purity of the sputtering gas. For example, a high-purity gas with a dew point of -60°C or below, preferably -100°C or below, is used as the oxygen or rare gas used as the sputtering gas. By using a high-purity sputtering gas to form a thin film, the incorporation of moisture and other contaminants into the oxide semiconductor layer can be minimized.

[0229] When forming an oxide semiconductor layer by sputtering, it is preferable to remove as much moisture as possible from the film-forming chamber of the sputtering apparatus. For example, it is preferable to use an adsorption vacuum pump, such as a cryogenic pump, to perform high-vacuum evacuation (evacuating to 5 × 10⁻⁶ m³ / s) of the film-forming chamber. -7 Pa to 1×10 -4(Approximately Pa). In particular, during the standby period of the sputtering apparatus, the partial pressure of gas molecules equivalent to H2O (equivalent to gas molecules with m / z = 18) in the film formation chamber is preferably 1 × 10⁻⁶ Pa. -4 Pa or less, more preferably 5×10 Pa -5 Below Pa.

[0230] [Metal Oxides]

[0231] By changing the composition of the elements contained in a metal oxide, conductors, semiconductors, and insulators can be formed, respectively. Sometimes, metal oxides with conductive properties are called "conductive oxides." Sometimes, metal oxides with semiconductor properties are called "oxide semiconductors." Sometimes, metal oxides with insulating properties are called "insulating oxides."

[0232] Oxide semiconductors, as one type of metal oxide, preferably contain at least indium or zinc. Indium and zinc are particularly preferred. Furthermore, aluminum, gallium, yttrium, or tin are also preferred. Alternatively, one or more of boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium may be included.

[0233] Here, we consider the case where the oxide semiconductor contains indium, element M, and zinc. Note that element M can be aluminum, gallium, yttrium, or tin, etc. Other elements that can be used as element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that multiple of the above elements can sometimes be combined as element M.

[0234] Furthermore, in this specification and other materials, nitrogen-containing metal oxides are sometimes referred to as metal oxides. Additionally, nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0235] [Structure of metal oxides]

[0236] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductor), a-like OS (amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0237] CAAC-OS exhibits c-axis orientation, with multiple nanocrystals linked along the ab-plane direction, resulting in a distorted crystal structure. Distortion refers to the change in the orientation of the lattice arrangement between regions with consistent lattice alignment and other regions with consistent lattice alignment within the linked nanocrystal region.

[0238] Nanocrystals are primarily hexagonal, but not limited to regular hexagons; sometimes they are non-regular hexagonal. Furthermore, nanocrystals sometimes exhibit pentagonal or heptagonal lattice arrangements during distortion. Moreover, in CAAC-OS, clear grain boundaries are difficult to observe even near the distortion. That is, it is known that lattice distortion can suppress grain boundary formation. This is because CAAC-OS can contain distortion due to the low density of oxygen atoms along the ab-plane or changes in interatomic bonding distance caused by the substitution of metal elements.

[0239] CAAC-OS tends to have a layered crystalline structure (also called a layered structure), in which layers containing indium and oxygen (hereinafter referred to as In layers) and layers containing elements M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. Furthermore, indium and element M can be substituted for each other; when element M in a (M, Zn) layer is replaced by indium, the layer can also be represented as an (In, M, Zn) layer. Similarly, when indium in an In layer is replaced by element M, the layer can also be represented as an (In, M) layer.

[0240] CAAC-OS is a highly crystalline metal oxide. Furthermore, distinct grain boundaries are not readily observed in CAAC-OS, thus reducing the likelihood of decreased electron mobility due to grain boundaries. Additionally, the crystallinity of metal oxides can sometimes decrease due to the incorporation of impurities or the formation of defects; therefore, CAAC-OS can be considered a metal oxide with few impurities or defects (such as oxygen vacancies). Consequently, metal oxides containing CAAC-OS exhibit stable physical properties. Therefore, metal oxides containing CAAC-OS possess excellent heat resistance and high reliability.

[0241] In nc-OS, the atomic arrangement in tiny regions (e.g., regions above 1 nm and below 10 nm, particularly above 1 nm and below 3 nm) exhibits periodicity. Furthermore, no regularity in crystal orientation is observed between different nanocrystals in nc-OS. Therefore, no orientation is observed throughout the film. Thus, sometimes nc-OS is indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods.

[0242] Furthermore, In-Ga-Zn oxide (hereinafter, IGZO), which is a metal oxide containing indium, gallium, and zinc, may have a stable structure when it is formed from the aforementioned nanocrystals. In particular, IGZO tends to not readily undergo crystal growth in the atmosphere, so it is sometimes structurally more stable when formed from small crystals (e.g., the aforementioned nanocrystals) compared to when it is formed from large crystals (here, crystals a few millimeters or a few centimeters).

[0243] a-like OS is a metal oxide with a structure intermediate between nc-OS and amorphous oxide semiconductors. a-like OS contains voids or low-density regions. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0244] Oxide semiconductors (metal oxides) have various structures and properties. One embodiment of the present invention may also include two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0245] [Transistors containing metal oxides]

[0246] Next, the use of the aforementioned metal oxide in the channel formation region of a transistor will be explained.

[0247] By using the aforementioned metal oxides in the channel formation region of a transistor, transistors with high field-effect mobility can be realized. Furthermore, transistors with high reliability can also be achieved.

[0248] Furthermore, it is preferable to use metal oxides with low carrier density in transistors. Reducing the carrier density of the metal oxide film lowers the impurity concentration and thus the defect state density. In this specification, the state of low impurity concentration and low defect state density is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". For example, the carrier density in the metal oxide can be lower than 8 × 10⁻⁶. 11 cm -3 Preferably less than 1×10 11 cm -3 More preferably, less than 1×10 10 cm -3 And it is 1×10 -9 cm -3 above.

[0249] Because high-purity intrinsic or substantially high-purity intrinsic metal oxide films have a low defect state density, they may have a low trap state density.

[0250] Furthermore, the charge trapped in the trap levels of metal oxides takes a long time to dissipate, sometimes acting like a fixed charge. Therefore, the electrical characteristics of transistors with channel formation regions in metal oxides with high trap state densities are sometimes unstable.

[0251] Therefore, reducing the impurity concentration in the metal oxide is effective in stabilizing the electrical characteristics of the transistor. To further reduce the impurity concentration in the metal oxide, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0252] [Impurities]

[0253] Here, we will explain the effects of various impurities in metal oxides.

[0254] Furthermore, when the metal oxide contains alkali metals or alkaline earth metals, defect energy levels can sometimes be formed, leading to the formation of charge carriers. Therefore, transistors using metal oxides containing alkali metals or alkaline earth metals as the channel formation region tend to exhibit always-on characteristics. Consequently, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the metal oxide. Specifically, the concentration of alkali metals or alkaline earth metals in the metal oxide, as measured by SIMS, should be 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferred: 2×10 16 atoms / cm 3 the following.

[0255] Hydrogen contained in metal oxides reacts with oxygen bonded to metal atoms to form water, thus sometimes creating oxygen vacancies. When the channel-forming region in a metal oxide contains oxygen vacancies, the transistor tends to have always-on characteristics. When hydrogen enters this oxygen vacancy, electrons are sometimes generated as charge carriers. Furthermore, sometimes electrons are generated as charge carriers due to partial bonding of hydrogen with oxygen bonded to metal atoms. Therefore, transistors using metal oxides containing hydrogen as the channel-forming region tend to have always-on characteristics.

[0256] Therefore, it is preferable to minimize the amount of hydrogen in metal oxides. Specifically, the hydrogen concentration in metal oxides, as measured by SIMS analysis, is set to be below 1 × 10⁻⁶. 20 atoms / cm 3 Preferably less than 1×10 19 atoms / cm 3 More preferably, less than 5×10 18 atoms / cm 3 Further optimization of less than 1×10 18 atoms / cm 3By using metal oxides with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0257] As a semiconductor used in transistors, a metal oxide film with high crystallinity is preferred. Using this film can improve the stability or reliability of the transistor. Examples of such films include, for instance, single-crystal metal oxide films or polycrystalline metal oxide films. However, forming single-crystal or polycrystalline metal oxide films on a substrate requires high-temperature or laser heating processes. Therefore, the manufacturing process becomes more expensive and throughput decreases.

[0258] Non-patent documents 1 and 2 report the discovery of In-Ga-Zn oxides (also known as CAAC-IGZO) with a CAAC structure in 2009. These documents report that CAAC-IGZO exhibits c-axis orientation, indistinct grain boundaries, and can be formed on substrates at low temperatures. Furthermore, transistors using CAAC-IGZO are reported to possess excellent electrical characteristics and reliability.

[0259] Furthermore, in 2013, an In-Ga-Zn oxide with an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Literature 3). It is reported here that the atomic arrangement of nc-IGZO in small regions (e.g., regions above 1 nm and below 3 nm) is periodic, and no regularity of crystal orientation is observed between different regions.

[0260] Non-Patent Documents 4 and 5 show the shift in average crystal size when the aforementioned CAAC-IGZO, nc-IGZO, and low-crystallinity IGZO films are irradiated with an electron beam, respectively. In the low-crystallinity IGZO film, approximately 1 nm of crystalline IGZO can be observed before electron beam irradiation. Therefore, Non-Patent Documents 4 and 5 report that the presence of a completely amorphous structure could not be confirmed in the IGZO. Furthermore, it is disclosed that CAAC-IGZO and nc-IGZO films exhibit higher stability relative to electron beam irradiation compared to the low-crystallinity IGZO film. Therefore, CAAC-IGZO or nc-IGZO films are preferably used as semiconductors for transistors.

[0261] Non-Patent Document 6 discloses a transistor using metal oxides with extremely low leakage current in the non-conducting state; specifically, the off-state current of the transistor is yA / μm per channel width of 1μm (10). -24(A / μm) level (order). For example, a low-power CPU that utilizes the characteristic of low leakage current of transistors using metal oxides has been disclosed (see Non-Patent Document 7).

[0262] Furthermore, there are reports of applying transistors using metal oxide transistors to display devices, taking advantage of their low leakage current (see Non-Patent Document 8). In display devices, the displayed image is switched dozens of times per second. The number of image switches per second is called the "refresh rate." The refresh rate is sometimes referred to as the "drive frequency." Such high-speed image switching, which is difficult for the human eye to perceive, is considered a cause of eye fatigue. Therefore, a technique has been proposed to reduce the refresh rate of the display device to decrease the number of image rewrites. A drive with a lower refresh rate can reduce the power consumption of the display device. This drive method is called "idle stop (IDS) drive."

[0263] The discovery of CAAC and nc structures has contributed to improving the electrical characteristics and reliability of metal-oxide transistors using CAAC or nc structures, reducing manufacturing costs, and increasing throughput. Furthermore, research has been conducted on utilizing the low leakage current of these transistors for application in display devices and LSIs.

[0264] [Film Formation Method]

[0265] Insulating materials used to form insulating layers, conductive materials used to form conductive layers, and semiconductor materials used to form semiconductor layers can be obtained through sputtering, spin coating, CVD (Chemical Vapor Deposition) methods (including thermal CVD, MOCVD (Metal Organic Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), High Density Plasma CVD, LPCVD (Low Pressure CVD), APCVD (Atmospheric Pressure CVD), ALD (Atomic Layer Deposition), MBE (Molecular Beam Epitaxy), and PLD (Pulsed Laser Deposition). Deposition can be achieved through methods such as pulsed laser deposition, dip coating, spraying, droplet jetting (inkjet printing, etc.), and printing (screen printing, offset printing, etc.).

[0266] High-quality films can be obtained at lower temperatures using plasma CVD. In film deposition methods that do not use plasma, such as MOCVD, ALD, or thermal CVD, damage is less likely to occur on the formed surface. For example, wiring, electrodes, and components (transistors, capacitors, etc.) included in storage devices can sometimes accumulate charge due to receiving charge from the plasma. This accumulated charge can sometimes damage these components. On the other hand, in film deposition methods that do not use plasma, this plasma damage does not occur, thus improving the yield of storage devices. Furthermore, the absence of plasma damage during film deposition results in films with fewer defects.

[0267] ALD (Alternating Layer Deposition) utilizes the self-regulating nature of atoms to deposit atoms in each layer, resulting in advantages such as the ability to form extremely thin films, films with high aspect ratios, films with few defects such as pinholes, films with excellent coverage, and films formed at low temperatures. Furthermore, ALD also includes PEALD (Plasma Enhanced ALD), which utilizes plasma. By using plasma, film deposition can be performed at even lower temperatures, making it sometimes preferred. Note that the precursors used in ALD sometimes contain impurities such as carbon. Therefore, films formed using ALD sometimes contain more impurities such as carbon compared to films formed using other deposition methods. Moreover, the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS).

[0268] Unlike film deposition methods that use particles released from a target material, CVD and ALD methods form films through reactions on the surface of the workpiece. Therefore, films formed by CVD and ALD are less affected by the shape of the workpiece and exhibit good step coverage. In particular, films formed by ALD have excellent step coverage and thickness uniformity, making ALD suitable for forming films covering surfaces with high aspect ratio openings. However, ALD has a relatively slow deposition rate, so it is sometimes preferred to combine it with other film deposition methods, such as CVD, which has a faster deposition rate.

[0269] The composition of the resulting membrane can be controlled by adjusting the flow rate ratio of the source gas in CVD or ALD methods. For example, when using CVD or ALD methods, membranes with arbitrary compositions can be formed by adjusting the flow rate ratio of the source gas. Furthermore, for example, when using CVD or ALD methods, membranes with continuously varying compositions can be formed by changing the flow rate ratio of the source gas while forming the membrane. When forming a membrane while changing the flow rate ratio of the source gas, the time required for conveying and adjusting the pressure can be eliminated, thus shortening the membrane formation time compared to using multiple membrane chambers. Therefore, the productivity of storage devices can sometimes be improved.

[0270] Low Dielectric Region (LDR)

[0271] [Structure Example]

[0272] The following is for reference Figures 17A to 19B This section illustrates the structure of the LDR221. Additionally, the accompanying diagram shows arrows indicating the X, Y, and Z directions. These directions are orthogonal to each other.

[0273] Figure 17A Is with Figure 10A A planar diagram of the same storage unit 211[i+1,j]. Figure 17B yes Figure 17A The diagram shows a three-dimensional representation of part 350. Figure 17B Only insulating layers 315, 331, 319 and LDR221 are shown.

[0274] As described above, LDR221 includes a plurality of LDS235s. LDS235s are provided by selectively removing a portion of the insulating layer 319. In this specification, the length of the opening of the LDS235 is referred to as "length GL", the width of the opening of the LDS235 is referred to as "width GW", and the height (depth) of the LDS235 is referred to as "height GH".

[0275] LDR221 includes a region extending in the Y direction and a region extending in the X direction. Figure 17B In the region where LDR221 extends in the Y direction, the direction of the length GL of LDS235 is aligned with the X direction. However, the direction of the length GL does not need to be exactly aligned with the X direction. It is sufficient that the direction of the length GL of LDS235 intersects the Y direction within the region where LDR221 extends in the Y direction.

[0276] In addition, Figure 17BIn the region where LDR221 extends in the X direction, the direction of the length GL of LDS235 is aligned with the Y direction. However, the direction of the length GL does not need to be exactly aligned with the Y direction. It is sufficient that the direction of the length GL of LDS235 intersects the X direction within the region where LDR221 extends in the X direction.

[0277] like Figure 18A and Figure 18B As shown, in the region where LDR221 extends in the Y direction, the direction of the length GL of LDS235 can also be consistent with or approximately consistent with the Y direction. Similarly, in the region where LDR221 extends in the X direction, the direction of the length GL of LDS235 can also be consistent with or approximately consistent with the X direction. Figure 18A It is a partial 350-degree 3D image. Figure 18B yes Figure 18A The top view of part 351 shown.

[0278] When the length GL is too long relative to the height GH and width GW of the LDS235, the mechanical strength of the LDR221 decreases, which leads to a reduction in the reliability of the memory cell 211. In other words, there is a concern about a decrease in the reliability of the memory device 100. Specifically, the insulating layer 319 between adjacent LDS235s is prone to breakage. The portion of the insulating layer sandwiched between adjacent LDS235s is also referred to as a "rib".

[0279] Therefore, as Figure 19A and Figure 19B As shown, the LDS235 is preferably configured with a certain length GL. Specifically, the length GL is preferably 50 times or less than the width GW, more preferably 30 times or less. Furthermore, the length GL is preferably 20 times or less than the height GH, more preferably 10 times or less. Figure 19A This is a partial 350-degree 3D view. In addition, Figure 19B yes Figure 19A The top view of part 352 shown.

[0280] In the insulation layer, the portion sandwiched between adjacent LDS235s is also referred to as a "rib arch". The height GH is preferably the width RW of the rib arch (refer to...). Figure 22B Less than 20 times, more preferably less than 10 times.

[0281] like Figure 20A and Figure 20B As shown, the direction of the length GL can also vary depending on each region. Figure 20A It is a partial 350-degree 3D diagram. In addition, Figure 20B yes Figure 20A The top view of part 353 is shown. Figure 20A and Figure 20BIn this process, the direction of length GL is rotated by 90 degrees at regular intervals, but the angle of rotation at regular intervals is not limited to 90 degrees.

[0282] Furthermore, when viewed from the Z-direction, the shape of the LDS235 does not necessarily need to be composed of straight lines. For example, the LDS235 can have... Figure 21A The bent portion shown can also have Figure 21B The curved portion is shown. In the region where LDR221 extends in the Y direction, LDS235 has a region extending in a direction intersecting the Y direction.

[0283] [Example of manufacturing process]

[0284] Next, refer to Figures 22A to 24B An example of the manufacturing process of LDR221 will be described. In this embodiment, the manufacturing process from the formation of insulating layer 331 to the formation of insulating layer 343 will be described. Figures 22A to 24B Equivalent to along Figure 10A The cross-sectional views of the dashed-dot lines A1-A2 and B1-B2. Note that... Figures 22A to 24B The cross section A1-A2 shown only shows the portion spanning the conductive layer 338.

[0285] After forming the insulating layer 331 in a manner that covers the conductive layer 332, the insulating layer 319 is formed (see reference). Figure 22A In this embodiment, an alumina layer is formed as the insulating layer 331 using the ALD method. The insulating layer 331 may also have a multilayer structure. For example, an alumina layer may be formed using the ALD method, and then an alumina layer may be formed on that alumina layer using a sputtering method. Alternatively, an alumina layer may be formed using a sputtering method, and then an alumina layer may be formed on that alumina layer using the ALD method.

[0286] Next, an insulating layer serving as insulating layer 319 is formed on insulating layer 331. In this embodiment, a silicon oxynitride layer is formed using CVD as the insulating layer serving as insulating layer 319. Alternatively, a heat treatment may be performed before forming the insulating layer serving as insulating layer 319. The heat treatment can be performed under reduced pressure to continuously form insulating layer 319 without exposure to the atmosphere. By performing this treatment, moisture and hydrogen adsorbed on the surface of insulating layer 331 can be removed, thereby reducing the moisture and hydrogen concentrations in insulating layer 331 and insulating layer 319.

[0287] The heat treatment is performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then, to replenish the removed oxygen, in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas.

[0288] Next, the insulating layer 319 is subjected to chemical mechanical polishing (CMP). This results in an insulating layer 319 with a flat top surface.

[0289] Next, a portion of the insulating layer 319 is selectively removed using photolithography to form LDS235 (see reference). Figure 22B ).

[0290] Note that in photolithography, the resist is first exposed through a mask. Next, a developer is used to remove or leave the exposed areas, forming a resist mask. Then, etching is performed through this resist mask to process conductors, semiconductors, or insulators into the desired shape. For example, the resist mask can be formed by exposing the resist to KrF stimulated excimer laser, ArF stimulated excimer laser, or EUV (Extreme Ultraviolet) light. Alternatively, immersion lithography can be used, where exposure is performed with liquid (e.g., water) filling the space between the substrate and the projection lens. Electron beams or ion beams can also be used instead of the aforementioned light. Note that when using electron beams or ion beams, a mask is not required. Furthermore, when removing the resist mask, dry etching (such as ashing) or wet etching can be performed, or wet etching can be performed after dry etching, or dry etching can be performed after wet etching.

[0291] Alternatively, a hard mask made of an insulator or conductor can be used instead of a photoresist mask. When using a hard mask, an insulating or conductive film that serves as the hard mask material can be formed on the insulating layer 319, and a photoresist mask can be formed on top of it. Then, the hard mask material can be etched to form a hard mask of the desired shape. The etching of the insulating layer 319 can be performed either after removing the photoresist mask or without removing it. In the latter case, the photoresist mask may sometimes disappear during etching. The hard mask can be removed by etching after etching the insulating layer 319. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessary to remove the hard mask.

[0292] After forming the resist mask and / or hard mask, an opening leading to the insulating layer 331 is formed in the insulating layer 319 using a dry etching method. This opening serves as LDS235. Although the opening can be formed by wet etching, it is more preferable to form it by dry etching for microfabrication. Furthermore, the insulating layer 331 is preferably made of a material that serves as an etch stop layer when etching the insulating layer 319 to form LDS235. For example, when silicon oxynitride is used as the insulating layer 319 for forming LDS235, silicon nitride, aluminum oxide, hafnium oxide, etc., are preferably used as the insulating layer 331.

[0293] As a dry etching apparatus for performing etching, a capacitively coupled plasma (CCP) etching apparatus including parallel planar electrodes can be used, for example. The CCP etching apparatus including parallel planar electrodes can also employ a structure that supplies a high-frequency voltage to one of the parallel planar electrodes. Alternatively, it can employ a structure that supplies multiple different high-frequency voltages to one of the parallel planar electrodes. Alternatively, it can employ a structure that supplies high-frequency voltages of the same frequency to each of the parallel planar electrodes. Alternatively, it can employ a structure that supplies high-frequency voltages of different frequencies to each of the parallel planar electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can also be used. For example, an inductively coupled plasma (ICP) etching apparatus can be used as a dry etching apparatus having a high-density plasma source.

[0294] The width GW of LDS235 is preferably 3 nm to 20 nm, more preferably 3 nm to 10 nm. When the width GW is too large, the subsequently formed insulating layer 334 can easily penetrate into LDS235. Therefore, an excessively large width GW may cause LDS235 to become smaller.

[0295] Furthermore, the width RW of the insulating layer 319, which corresponds to the aforementioned "rib arch" sandwiched between adjacent LDS235, is preferably 0.5 times to 5 times the width GW, more preferably 0.5 times to 3 times the width GW. A large width RW can improve the mechanical strength of LDR221, but if the width RW is too large, the parasitic capacitance reduction effect of LDR221 is weakened. A small width RW can improve the parasitic capacitance reduction effect of LDR221, but if the width RW is too small, the mechanical strength of LDR221 is excessively weakened.

[0296] Next, an insulating layer 334 is formed on the insulating layer 319 and LDS235. The insulating layer 334 is formed under conditions of low coverage using methods such as sputtering or CVD. In particular, sputtering is preferred because it facilitates film formation under low coverage conditions. In this embodiment, a silicon nitride layer (see reference 1) is formed as the insulating layer 334 using sputtering. Figure 23A ).

[0297] LDS235 is a void surrounded by insulating layers 331, 319, and 334. Therefore, the relative permittivity of LDS235 can be around 1. Furthermore, LDS235 sometimes contains a certain gas. Additionally, when insulating layer 334 is formed under reduced pressure, LDS235 may be in a reduced-pressure state. For example, when insulating layer 334 is formed using sputtering, if an oxygen-containing gas is used as the sputtering gas, LDS235 may contain oxygen. In this case, LDS235 can function as an oxygen storage device.

[0298] LDS235 can be either void or include structures whose dielectric constant is lower than that of insulating layer 319. For example, if insulating layer 319 is silicon oxide with a relative dielectric constant of 3.8, LDS235 can also be filled with polyethylene with a relative dielectric constant of 2.4, polypropylene with a relative dielectric constant of 2.1, etc. By incorporating structures within LDS235, the mechanical strength of LDR221 can be improved.

[0299] Next, insulating layers 335 and 336 are formed on insulating layer 334 (see reference). Figure 23B In this embodiment, a silicon oxynitride layer is formed using CVD as insulating layer 335. Furthermore, a silicon nitride layer is formed using CVD as insulating layer 336. CMP processing may also be performed after forming insulating layer 335 or insulating layer 336.

[0300] Next, by removing a portion of insulating layers 336, 335, 334, 319, and 331, an opening 342 is formed that reaches the conductive layer 332 (see reference). Figure 23C ).

[0301] Next, a conductive layer for forming the contact plug 337 is formed on the opening 342 and the insulating layer 336. This conductive layer can be formed using methods such as plating, sputtering, CVD, MBE, PLD, and ALD. In this embodiment, a tungsten layer is formed using sputtering as the conductive layer. Then, a portion of the conductive layer is removed by CMP treatment to expose the insulating layer 336. As a result, the conductive layer remains only in the opening 342, thereby forming the contact plug 337 (see reference). Figure 24A ).

[0302] Next, a conductive layer 338 is formed on the insulating layer 336, and an insulating layer 343 is formed on the conductive layer 338. Through the above process, LDR221 can be formed.

[0303] Variation Example 1

[0304] LDR221 can also be disposed in an insulating layer other than insulating layer 319. See below for reference. Figures 25 to 28 Other configuration examples for LDR221 are explained. Figure 25 This is a top view of storage unit 211[i+1,j]. Figure 26 It is along Figure 25 The cross-sectional view of the dashed-dot section C1-C2 and the section D1-D2.

[0305] Figure 25 and Figure 26 An example of LDR221 being provided not only in insulating layer 319 but also in insulating layer 315. Figure 25 and Figure 26 In the diagram, LDR221, which is disposed in insulating layer 315, is shown as LDR221a. Furthermore, LDS235, which is contained in LDR221a, is indicated as LDS235a. Additionally, insulating layer 344 and insulating layer 345 are disposed between insulating layer 315 and conductive layer 333.

[0306] Insulating layer 311 can be formed using the same materials and methods as insulating layer 331. Insulating layer 315 can be formed using the same materials and methods as insulating layer 319. Insulating layer 344 can be formed using the same materials and methods as insulating layer 334. Insulating layer 345 can be formed using the same materials and methods as insulating layer 335.

[0307] Therefore, LDS235a can be formed in the same way as LDS235. It includes not only LDR221 but also LDR221a, thereby further reducing the parasitic capacitance generated between adjacent memory cells.

[0308] Furthermore, by providing LDR221a between conductive layer 261 (word line WWL[i+1]) and conductive layer 333 (word line RWL[i+1]), the parasitic capacitance generated between them can be reduced. Providing LDR221a at the wiring intersection can reduce signal distortion and improve the reliability of the memory device. Additionally, it can reduce the power consumption of the memory device.

[0309] Variation Example 2

[0310] Figure 27 This is a top view of storage unit 211[i+1,j]. Figure 28 It is along Figure 27The cross-sectional view of the section E1-E2 marked with a dotted line.

[0311] like Figure 27 and Figure 28 As shown, the LDR221 can also be formed in a way that avoids the area where the contact plug is formed and covers the memory cell. Figure 28 An example is shown where LDR221 is disposed in the insulating layer 319 outside the contact plug 347. Furthermore, although in Figure 28 LDR221 is not provided on the conductive layer 346 that is electrically connected to the contact plug 347, but LDR221 can be provided on the conductive layer 346 within the range that does not affect the contact plug 347.

[0312] Furthermore, although not illustrated, it can also be compared with... Figure 27 and Figure 28 The LDR221 shown is also arranged to overlap with the memory cell, as is LDR221a. By expanding the arrangement range of LDR221 and LDR221a, the parasitic capacitance generated between adjacent memory cells can be further reduced. Furthermore, the parasitic capacitance generated between conductive layers can be further reduced, thereby reducing signal distortion and improving the reliability of the memory device. In addition, the power consumption of the memory device can be reduced.

[0313] This embodiment can be implemented by appropriately combining the structures shown in other embodiments, etc.

[0314] (Implementation Method 3)

[0315] In this embodiment, a structural example of a transistor that can be applied to transistors M11 and M12 is described with reference to the accompanying drawings.

[0316] <Example 1 of transistor structure>

[0317] Reference Figure 29A , Figure 29B and Figure 29C This section provides an example illustrating the structure of a transistor 200A. Figure 29A This is a top view of the transistor 200A. Figure 29B Is Figure 29A A cross-sectional view of the portion indicated by the dashed lines L1-L2. Figure 29C Is Figure 29A A cross-sectional view of the portion indicated by the dashed lines W1-W2. Figure 29A In the top view, for ease of understanding, some of the constituent elements are omitted and represented.

[0318] exist Figure 29A , Figure 29B and Figure 29CThe diagram shows a transistor 200A, and insulating layers 309, 316, 322, 324, 354, 380, 374, and 381 serving as interlayer films. It also shows conductive layers 340 (conductive layers 340a and 340b) that are electrically connected to the transistor 200A and serve as contact plugs. Furthermore, insulating layers 341 (insulating layers 341a and 341b) are provided that contact the sides of the conductive layers 340 serving as contact plugs.

[0319] As interlayer insulating layers, single layers or stacks of insulators such as silicon oxide, silicon oxynitride, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or barium strontium titanate ((Ba,Sr)TiO3) can be used. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide can be added to these insulators. Furthermore, these insulators can be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride can also be stacked on top of the aforementioned insulators.

[0320] The transistor 200A includes: a conductive layer 360 (conductive layer 360a and conductive layer 360b) serving as a first gate electrode; a conductive layer 305 serving as a second gate electrode; an insulating layer 349 serving as a first gate insulating film; insulating layers 322 and insulating layers 324 serving as a second gate insulating film; a semiconductor layer 260 (semiconductor layer 260a, semiconductor layer 260b and semiconductor layer 260c) including a region forming a channel; a conductive layer 342a serving as one of the source and drain electrodes; a conductive layer 342b serving as the other of the source and drain electrodes; and an insulating layer 354.

[0321] The conductive layer 305 is disposed in a manner that embeds the insulating layer 316, and the insulating layer 322 is disposed on the insulating layer 316 and the conductive layer 305. The insulating layer 324 is disposed on the insulating layer 322. Furthermore, semiconductor layers 260 (semiconductor layers 260a, 260b, and 260c) are disposed on the insulating layer 324. The insulating layer 349 is disposed on the semiconductor layer 260, and the conductive layers 360 (conductive layers 360a and 360b) are disposed on the insulating layer 349.

[0322] The conductive layers 342a and 342b are configured to contact a portion of the top surface of the semiconductor layer 260b, and the insulating layer 354 is configured to contact a portion of the top surface of the insulating layer 324, the side surface of the semiconductor layer 260a, the side surface of the semiconductor layer 260b, the side surface of the conductive layer 342a, the top surface of the conductive layer 342a, the side surface of the conductive layer 342b, and the top surface of the conductive layer 342b.

[0323] Furthermore, an insulating layer 341 is provided in contact with the sidewalls of openings formed in insulating layers 380, 374, and 381, and a first conductor of conductive layer 340 is provided in contact with its sidewalls, with a second conductor of conductive layer 340 disposed inside it. Here, the height of the top surface of conductive layer 340 can be approximately the same as the height of the top surface of insulating layer 381. Furthermore, in transistor 200A, the first conductor of conductive layer 340 and the second conductor of conductive layer 340 are stacked, but the present invention is not limited to this. For example, conductive layer 340 may also have a single-layer structure or a stacked structure of three or more layers. When the structure has a stacked structure, sometimes ordinal numbers are assigned according to the order of formation for differentiation.

[0324] Semiconductor layer 260 preferably includes semiconductor layer 260a disposed on insulating layer 324, semiconductor layer 260b disposed on semiconductor layer 260a, and semiconductor layer 260c disposed on semiconductor layer 260b, at least a portion of which contacts the top surface of semiconductor layer 260b. When semiconductor layer 260a is disposed below semiconductor layer 260b, impurities can be prevented from diffusing from the structure formed below semiconductor layer 260a to semiconductor layer 260b. When semiconductor layer 260c is disposed above semiconductor layer 260b, impurities can be prevented from diffusing from the structure formed above semiconductor layer 260c to semiconductor layer 260b.

[0325] The semiconductor layer 260 of transistor 200A is preferably an oxide semiconductor, which is one of the metal oxides.

[0326] Transistors using oxide semiconductors to form the channel semiconductor layer exhibit extremely low leakage current (off-state current) in the non-conducting state, thus enabling low-power semiconductor devices. Furthermore, since oxide semiconductors can be formed using methods such as sputtering, highly integrated semiconductor devices can be easily realized.

[0327] For example, In-M-Zn oxide (where element M is selected from one or more of gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) is preferably used as the semiconductor layer 260. In particular, gallium, yttrium, or tin is preferably used as element M. Furthermore, In-M oxide, In-Zn oxide, and M-Zn oxide can also be used as the semiconductor layer 260.

[0328] In transistor 200A, a conductive layer 360 serving as a first gate (also called a top gate) is formed in a self-aligned manner to fill an opening formed in an insulating layer 380, etc. By forming the conductive layer 360 in this way, the conductive layer 360 can be reliably disposed in the region between the conductive layers 342a and 342b without position alignment.

[0329] The conductive layer 360 preferably includes a conductive layer 360a and a conductive layer 360b on the conductive layer 360a. For example, the conductive layer 360a is preferably disposed in a manner that surrounds the bottom surface and side surfaces of the conductive layer 360b. Figure 29B As shown, the top surface of the conductive layer 360 is roughly the same as the top surface of the insulating layer 349 and the top surface of the oxide layer 330c.

[0330] Conductive layer 305 is sometimes used as a second gate (also called a bottom gate) electrode. In this case, the threshold voltage (V) of transistor 200A can be controlled by individually changing the potential applied to conductive layer 305 without linking it to the potential applied to conductive layer 360. th In particular, by applying a negative potential to the conductive layer 305, the V of the transistor 200A can be increased. th A voltage greater than 0V can reduce the off-state current. Therefore, applying a negative potential to the conductive layer 305 can reduce the leakage current of the conductive layer 360 when a potential of 0V is applied, compared to not applying a negative potential to the conductive layer 305.

[0331] Furthermore, for example, when the conductive layer 305 and the conductive layer 360 overlap across the channel formation region of the semiconductor layer 260, when a voltage is applied to the conductive layer 305 and the conductive layer 360, the electric field generated in the conductive layer 360 and the electric field generated in the conductive layer 305 can be connected to cover the channel formation region of the semiconductor layer 260.

[0332] In other words, a region can be formed around the channel by the electric field of the conductive layer 360 used as the first gate electrode and the electric field of the conductive layer 305 used as the second gate electrode. In this specification, the structure of a transistor in which the electric fields of the first gate electrode and the second gate electrode form a region around the channel is referred to as a surround channel (S-channel) structure.

[0333] Insulating layers 322 and 354 preferably have the function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). Furthermore, insulating layers 322 and 354 preferably have the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, compared to insulating layer 324, insulating layers 322 and 354 preferably have the function of suppressing the diffusion of one or both of hydrogen and oxygen. Compared to insulating layer 349, insulating layers 322 and 354 preferably have the function of suppressing the diffusion of one or both of hydrogen and oxygen. Compared to insulating layer 380, insulating layers 322 and 354 preferably have the function of suppressing the diffusion of one or both of hydrogen and oxygen.

[0334] Furthermore, in this specification and other materials, a membrane that has the function of inhibiting the diffusion of hydrogen or oxygen is sometimes referred to as a membrane that is not easily permeable to hydrogen or oxygen, a membrane with low permeability to hydrogen or oxygen, a membrane that blocks hydrogen or oxygen, or a barrier membrane for hydrogen or oxygen. Additionally, when the barrier membrane is conductive, it is sometimes referred to as a conductive barrier membrane.

[0335] In addition, such as Figure 29B As shown, the insulating layer 354 preferably contacts the top surfaces of conductive layers 342a and 342b, the sides of conductive layers 342a and 342b other than their opposing sides, the sides of semiconductor layers 260a and 260b, and a portion of the top surface of the insulating layer 324. Thus, the insulating layer 380 is separated from the insulating layer 324, semiconductor layers 260a and 260b by the insulating layer 354. Therefore, impurities such as hydrogen contained in the insulating layer 380 can be suppressed from intruding into the insulating layer 324, semiconductor layers 260a and 260b.

[0336] In addition, such as Figure 29B As shown, transistor 200A has a structure in which insulating layer 374 contacts the top surfaces of conductive layer 360, insulating layer 349, and semiconductor layer 260c. By employing this structure, impurities such as hydrogen from insulating layer 381 can be suppressed from entering insulating layer 349. This helps to prevent negative impacts on the electrical characteristics and reliability of the transistor.

[0337] By having the above structure, a transistor with a large on-state current can be provided. Furthermore, a transistor with a small off-state current can be provided. Moreover, a semiconductor device that achieves stable electrical characteristics while suppressing variations in electrical characteristics can be provided, thereby improving reliability.

[0338] <Example 2 of transistor structure>

[0339] Reference Figure 30A , Figure 30B and Figure 30C This section provides an example illustrating the structure of the transistor 200B. Figure 30A This is a top view of the transistor 200B. Figure 30B Is Figure 30A A cross-sectional view of the portion indicated by the dashed lines L1-L2. Figure 30C Is Figure 30A A cross-sectional view of the portion indicated by the dashed lines W1-W2. Figure 30A In the top view, for ease of understanding, some of the constituent elements are omitted and represented.

[0340] Transistor 200B is a variation of transistor 200A. Therefore, to avoid repetition, we will mainly explain its differences from transistor 200A.

[0341] The conductive layer 360 used as the first gate electrode includes a conductive layer 360a and a conductive layer 360b on the conductive layer 360a. The conductive layer 360a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms. Furthermore, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.).

[0342] When the conductive layer 360a has the function of inhibiting oxygen diffusion, the material selectivity of the conductive layer 360b can be improved. That is, by including the conductive layer 360a, the oxidation of the conductive layer 360b can be inhibited, thereby preventing a decrease in conductivity.

[0343] Furthermore, it is preferable that the insulating layer 354 is provided in a manner that covers the top and side surfaces of the conductive layer 360, the side surfaces of the insulating layer 349, and the side surfaces of the semiconductor layer 260c. The insulating layer 354 is preferably made of an insulating material that has the function of suppressing the diffusion of impurities such as water or hydrogen and oxygen. For example, aluminum oxide or hafnium oxide is preferred. In addition, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, as well as silicon oxynitride or silicon nitride, can be used.

[0344] By providing the insulating layer 354, oxidation of the conductive layer 360 can be suppressed. Furthermore, by including the insulating layer 354, the diffusion of impurities such as water and hydrogen contained in the insulating layer 580 into the transistor 200B can be suppressed.

[0345] Because a portion of conductive layer 342a and a portion of conductive layer 342b overlap with conductive layer 360 in transistor 200B, the parasitic capacitance of transistor 200B tends to be larger compared to transistor 200A. Therefore, it tends to have a lower operating frequency compared to transistor 200A. However, transistor 200B does not require the process of embedding conductive layer 360 or insulating layer 349 by creating openings in insulating layer 380, etc., thus it has higher productivity compared to transistor 200A.

[0346] This embodiment can be implemented by appropriately combining the structures shown in other embodiments, etc.

[0347] (Implementation Method 4)

[0348] In this embodiment, electronic components and electronic devices of a storage device or semiconductor device to which one aspect of the present invention can be applied are described.

[0349] The storage device or semiconductor device according to one aspect of the present invention can be installed in various electronic devices. In particular, the semiconductor device according to one aspect of the present invention can be used as a memory built into an electronic device. Examples of electronic devices include, in addition to electronic devices with large screens such as television sets, desktop or laptop personal computers, displays for computers, digital signage, and large game machines such as pinball machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices.

[0350] An electronic device according to one aspect of the present invention may also include an antenna. By receiving signals through the antenna, images or information can be displayed on a display unit. Furthermore, when the electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0351] An electronic device according to one aspect of the present invention may also include a sensor (the sensor having the function of measuring factors such as force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation).

[0352] An electronic device according to one aspect of the present invention can have various functions. For example, it can have the following functions: displaying various information (static images, animated images, text images, etc.) on a display unit; a touch panel; displaying a calendar, date, or time; executing various software (programs); performing wireless communication; reading programs or data stored in a storage medium; etc.

[0353] <Electronic Components>

[0354] First, refer to Figure 31A and Figure 31B An example of an electronic component assembled with storage device 100 will be described.

[0355] Figure 31A A perspective view of the electronic component 700 and the substrate (circuit board 704) on which the electronic component 700 is mounted is shown. Figure 31A The electronic component 700 shown is an IC semiconductor device, including leads and circuitry. The electronic component 700 is mounted, for example, on a printed circuit board 702. Circuit board 704 is completed by combining multiple such IC semiconductor devices and electrically connecting them respectively on the printed circuit board 702.

[0356] The storage device 100 shown in the above embodiment is provided as the circuit section of the electronic component 700. Although Figure 31AThe electronic component 700 is packaged using QFP (Quad Flat Package), but the packaging method is not limited to this.

[0357] Figure 31B A perspective view of electronic component 730 is shown. Electronic component 730 is an example of SiP (System in Package) or MCM (Multi-Chip Module). In electronic component 730, an interposer 731 is disposed on a package substrate 732 (printed circuit board), and semiconductor devices 735 and multiple memory devices 100 are disposed on the interposer 731.

[0358] Electronic component 730 illustrates an example of using storage device 100 as high-bandwidth memory (HBM). Furthermore, semiconductor device 735 may utilize integrated circuits (semiconductor devices) such as CPUs, GPUs, and FPGAs.

[0359] The packaging substrate 732 can be a ceramic substrate, a plastic substrate, or a glass epoxy substrate, etc. The through-hole board 731 can be a silicon through-hole board, a resin through-hole board, etc.

[0360] The through-hole board 731 has multiple wirings capable of electrically connecting to multiple integrated circuits with different terminal spacings. These wirings can be composed of a single layer or multiple layers. Furthermore, the through-hole board 731 has the function of electrically connecting integrated circuits disposed on the through-hole board 731 to electrodes disposed on the packaging substrate 732. Therefore, the through-hole board is sometimes referred to as a "rewiring substrate" or "intermediate substrate." Additionally, sometimes a through-electrode is provided in the through-hole board 731 to electrically connect the integrated circuit to the packaging substrate 732. Furthermore, in the case of using a silicon through-hole board, a TSV (Through Silicon Via) can also be used as the through-electrode.

[0361] Silicon interposers are preferred for the 731 interposer. Since silicon interposers do not require active components, they can be manufactured at a lower cost than integrated circuits. Wiring formation on silicon interposers can be performed during semiconductor processes, and resin interposers are easier to form with fine wiring.

[0362] In HBM, a large number of wirings are required to achieve wide memory bandwidth. Therefore, the mounting board for HBM needs to be able to form fine wirings at high density. Thus, silicon mounting boards are preferred as mounting boards for HBM.

[0363] Furthermore, in SiP or MCM applications using silicon interposers, reliability degradation due to differences in the coefficients of thermal expansion between the integrated circuit and the interposer is less likely to occur. Additionally, due to the high surface flatness of the silicon interposer, poor connection between the integrated circuit and the interposer is less likely to occur. Silicon interposers are particularly preferred for 2.5D packaging (2.5D mounting), where multiple integrated circuits are arranged and configured on the interposer.

[0364] Alternatively, a heat sink (heat plate) may be provided overlapping with the electronic component 730. When a heat sink is provided, it is preferable that the integrated circuits provided on the insert 731 are at the same height. For example, in the electronic component 730 shown in this embodiment, it is preferable that the storage device 100 and the semiconductor device 735 are at the same height.

[0365] In order to mount the electronic component 730 on another substrate, an electrode 733 can be provided on the bottom of the package substrate 732. Figure 31B An example of forming electrode 733 using solder balls is shown. BGA (Ball Grid Array) mounting can be achieved by arranging solder balls in a matrix on the bottom of the package substrate 732. Alternatively, electrode 733 can also be formed using conductive pins. PGA (Pin Grid Array) mounting can be achieved by arranging conductive pins in a matrix on the bottom of the package substrate 732.

[0366] Electronic component 730 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. For example, it can be mounted using SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package).

[0367] <Electronic Devices>

[0368] Next, refer to Figures 32 to 35C Examples of electronic devices equipped with the aforementioned electronic components will be described.

[0369] Figure 32The robot 7100 shown includes an illuminance sensor, microphone, camera, speaker, display, various sensors (infrared sensor, ultrasonic sensor, accelerometer, piezoelectric sensor, light sensor, gyroscope sensor, etc.) and a movement mechanism. The electronic component 730 includes a processor and has the function of controlling these peripheral devices. For example, the electronic component 700 has the function of storing data measured by the sensors.

[0370] The microphone detects audio signals such as the user's voice and ambient sounds. The speaker emits audio signals such as sounds and warning tones. Robot 7100 can analyze the audio signals input through the microphone and emit the necessary audio signals from the speaker. Robot 7100 can communicate with the user using both the microphone and speaker.

[0371] The camera has the function of capturing images of the surroundings of robot 7100. Furthermore, robot 7100 has the function of moving using a locomotion mechanism. Robot 7100 can analyze the images captured by the camera to determine the presence or absence of obstacles during movement.

[0372] The flying object 7120 includes a propeller, camera, and battery, and has autonomous flight capabilities. The electronic component 730 has the function of controlling the aforementioned peripheral equipment.

[0373] For example, image data captured by the camera is stored in electronic component 700. Electronic component 730 can analyze the image data to determine the presence or absence of obstacles during movement. Furthermore, electronic component 730 can use changes in battery capacity to estimate the remaining battery power.

[0374] The 7140 robotic vacuum cleaner includes a display on the top surface, multiple cameras on the sides, brushes, control buttons, and various sensors. Although not shown, the 7140 is equipped with tires and a suction inlet. The 7140 can move automatically, detect debris, and suck it up from the suction inlet on the bottom.

[0375] For example, the electronic component 730 can determine the presence or absence of obstacles such as walls, furniture, or steps by analyzing images captured by the camera. Furthermore, if image analysis detects objects such as wiring that might get tangled in the brush, the brush rotation can be stopped.

[0376] An example of a moving body is shown: a car 7160. The car 7160 includes an engine, tires, brakes, a steering system, a camera, etc. For example, electronic component 730 performs control to optimize the driving state of the car 7160 based on data such as navigation information, speed, engine status, gear selection status, and brake usage frequency. For example, image data captured by the camera is stored in electronic component 700.

[0377] While the automobile was used as an example of a mobile body in the above example, mobile bodies are not limited to automobiles. For example, trams, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles, airplanes, rockets) can also be cited as mobile bodies. The computer of one aspect of the present invention can be applied to these mobile bodies to provide a system utilizing artificial intelligence.

[0378] Electronic components 700 and / or 730 can be installed in television receiver (TV) devices 7200, smartphones 7210, PCs 7220 (personal computers), 7230, game consoles 7240, game consoles 7260, etc.

[0379] For example, the electronic component 730 installed in the TV device 7200 can be used as an image engine. For example, the electronic component 730 performs image processing such as noise removal and resolution up-conversion.

[0380] Smartphone 7210 is an example of a portable information terminal. Smartphone 7210 includes a microphone, camera, speaker, various sensors, and a display. Electronic components 730 control the aforementioned peripheral devices.

[0381] PC7220 and PC7230 are examples of a notebook PC and a desktop PC, respectively. The keyboard 7232 and the display device 7233 can be connected to PC7230 wirelessly or wiredly.

[0382] Game console 7240 is an example of a portable game console. Game console 7260 is an example of a home-based stationary game console. Game console 7260 connects to controller 7262 wirelessly or via wired connection. Electronic components 700 and / or 730 may be installed on controller 7262.

[0383] Game machines using a semiconductor device according to one aspect of the present invention are not limited thereto. Examples of game machines using a semiconductor device according to one aspect of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and ball-throwing machines installed in sports facilities.

[0384] The storage device or semiconductor device of one aspect of the present invention can be applied to various portable storage devices such as memory cards (e.g., SD cards), USB memory, SSDs (solid-state drives). Figures 33A to 33E Several structural examples of removable storage devices are schematically illustrated. A storage device or semiconductor device according to one aspect of the present invention can be used in various storage devices or removable memories.

[0385] Figure 33A This is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed within the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. A storage device or semiconductor device according to one aspect of the present invention can be assembled onto the memory chip 1105, etc., on the substrate 1104.

[0386] Figure 33B This is a schematic diagram of the SD card's appearance. Figure 33C This is a schematic diagram of the internal structure of an SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed within the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Furthermore, a wireless chip with wireless communication capabilities can also be provided on the substrate 1113. Thus, data can be read from and written to the memory chip 1114 via wireless communication between the host device and the SD card 1110. A storage device or semiconductor device according to one aspect of the present invention can be assembled onto the memory chip 1114, etc., on the substrate 1113.

[0387] Figure 33D This is a schematic diagram of the SSD's appearance. Figure 33E This is a schematic diagram of the internal structure of an SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed within the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 serves as the working memory for the controller chip 1156; for example, a DOSRAM chip can be used. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. A storage device or semiconductor device according to one aspect of the present invention can be assembled onto the memory chip 1154, etc., on the substrate 1153.

[0388] Figure 34AThe alarm device 8100 shown is a residential fire alarm device, including a detection unit and a semiconductor device 8101. By incorporating the aforementioned electronic components 700 and / or 730 into the semiconductor device 8101, the power consumption of the alarm device 8100 can be reduced. Furthermore, stable operation can be achieved even in high-temperature environments. Therefore, the reliability of the alarm device 8100 can be improved.

[0389] Figure 34A The air conditioner shown includes an indoor unit 8200 and an outdoor unit 8204. The indoor unit 8200 includes a casing 8201, an air vent 8202, and a semiconductor device 8203, etc. Although in Figure 34A The diagram shows a case where the semiconductor device 8203 is installed in the indoor unit 8200, but the semiconductor device 8203 can also be installed in the outdoor unit 8204. Alternatively, the semiconductor device 8203 can be installed in both the indoor unit 8200 and the outdoor unit 8204. By incorporating the aforementioned electronic components 700 and / or 730 into the semiconductor device 8203, the power consumption of the air conditioner can be reduced. Furthermore, stable operation can be achieved even in high-temperature environments. Therefore, the reliability of the air conditioner can be improved.

[0390] Figure 34A The electric refrigerator / freezer 8300 shown includes an outer casing 8301, a refrigerator door 8302, a freezer door 8303, a semiconductor device 8304, etc. Figure 34A In this design, a semiconductor device 8304 is disposed inside the housing 8301. By incorporating the aforementioned electronic components 700 and / or 730 into the semiconductor device 8304, the power consumption of the electric refrigerator / freezer 8300 can be reduced. Furthermore, stable operation can be achieved even in high-temperature environments. Therefore, the reliability of the electric refrigerator / freezer 8300 can be improved.

[0391] In this embodiment, an electric refrigerator / freezer and an air conditioner are described as examples of electrical products. The semiconductor device of one aspect of the present invention can also be applied to other electrical products. Examples of other electrical products include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cooking appliances, water dispensers, air conditioners (including air conditioners), washing machines, dryers, and audio-visual equipment.

[0392] Figure 34BAn example of an electric vehicle is shown. The electric vehicle 9700 is equipped with a secondary battery 9701. The power from the secondary battery 9701 is adjusted by a control circuit 9702 and supplied to the drive unit 9703. The control circuit 9702 is controlled by a processing unit 9704, which includes semiconductor devices (not shown). By using the aforementioned electronic components 700 and / or 730 in the control circuit 9702 or the processing unit 9704, the power consumption of the electric vehicle 9700 can be reduced. Furthermore, stable operation can be achieved even in high-temperature environments. Therefore, the reliability of the electric vehicle 9700 can be improved.

[0393] The drive unit 9703 utilizes a DC motor or an AC motor, or a combination of an electric motor and an internal combustion engine. The processing unit 9704 outputs control signals to the control circuit 9702 based on input information such as driver operation information (acceleration, deceleration, stopping, etc.) and driving information (climbing hills, descending hills, or load on the wheels during driving, etc.). The control circuit 9702 uses the control signals from the processing unit 9704 to adjust the output of the drive unit 9703 by controlling the electrical energy supplied from the secondary battery 9701. When an AC motor is installed, although not shown, an inverter that converts DC to AC is also installed.

[0394] Figure 35A The computer 5400 shown is an example of a mainframe computer. In computer 5400, multiple rack-mounted computers 5420 are housed in rack 5410.

[0395] Computer 5420, for example, can have Figure 35B The structure shown in the 3D diagram. In Figure 35B In the computer 5420, a motherboard 5430 is included, and the motherboard includes multiple slots 5431. A personal computer card 5421 is inserted into the slots 5431.

[0396] Personal computer card 5421, for example, can have Figure 35C The structure of the 3D diagram shown. Figure 35C The personal computer card 5421 shown is an example of a processing board including a CPU, GPU, storage device, etc. The personal computer card 5421 has a board 5422. Furthermore, the board 5422 includes connection terminals 5423, 5424, and 5425, semiconductor devices 5426, 5427, and 5428, and a connection terminal 5429. Note that... Figure 35C Semiconductor devices other than semiconductor devices 5426, 5427 and 5428 are shown. For a description of these semiconductor devices, please refer to the description of semiconductor devices 5426, 5427 and 5428 described below.

[0397] The connection terminal 5429 has a shape that allows it to be inserted into a slot 5431 of the motherboard 5430. The connection terminal 5429 is used as an interface for connecting the personal computer card 5421 to the motherboard 5430. Examples of specifications for the connection terminal 5429 include PCIe.

[0398] Connection terminals 5423, 5424, and 5425 can be used, for example, as interfaces for powering or inputting signals to the personal computer card 5421. Furthermore, they can be used, for example, as interfaces for outputting signals calculated by the personal computer card 5421. Examples of specifications for connection terminals 5423, 5424, and 5425 include, for example, USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when outputting video signals from connection terminals 5423, 5424, and 5425, examples of specifications include HDMI (registered trademark).

[0399] Semiconductor device 5426 includes terminals (not shown) for inputting and outputting signals. By inserting these terminals into a socket (not shown) included in board 5422, semiconductor device 5426 and board 5422 can be electrically connected.

[0400] Semiconductor device 5427 includes multiple terminals, which can be electrically connected to board 5422 by reflow soldering the terminals to wiring provided on board 5422. Examples of semiconductor devices 5427 include FPGAs, GPUs, and CPUs. Electronic component 730 can also be used as a semiconductor device 5427.

[0401] Semiconductor device 5428 includes multiple terminals, which can be electrically connected to board 5422 by reflow soldering the terminals to wiring provided on board 5422. Examples of semiconductor devices 5428 include memory devices. Electronic component 700 can also be used as a semiconductor device 5428.

[0402] The Computer 5400 can be used as a parallel computer. By using the Computer 5400 as a parallel computer, large-scale computations required for artificial intelligence learning and inference can be performed, for example.

[0403] By using the semiconductor device of one aspect of the present invention in the aforementioned various electronic devices, miniaturization, high speed, or low power consumption of the electronic devices can be achieved. Furthermore, the semiconductor device of one aspect of the present invention consumes little power, thereby reducing circuit heat generation. This reduces the negative impact of heat generation on the circuit itself, peripheral circuits, and modules. Moreover, stable operation can be achieved even in high-temperature environments. This improves the reliability of the electronic devices.

[0404] This embodiment can be implemented by appropriately combining the structures shown in other embodiments, etc.

[0405] (Implementation Method 5)

[0406] The OS-LSI described in the above embodiments can be applied to a wide variety of storage devices. In this embodiment, reference is made to... Figures 36 to 38 This indicates that the storage device can be replaced with an OS-LSI.

[0407] Generally speaking, storage devices are broadly divided into working memory and long-term storage.

[0408] Working memory is the storage device that is directly written to and read from during computational processing by the CPU and other computing devices. Therefore, working memory is required to have high operating speed and high write resistance. Working memory is classified into registers, cache, and main memory according to its purpose. In most cases, cache uses SRAM, and main memory uses DRAM.

[0409] Long-term storage (LSD) is also known as "external storage device" or "auxiliary storage device." LSD is connected to computing devices such as the CPU via an external bus. While LSD has a slower data transfer speed than working memory, it has a large storage capacity, making it suitable for long-term data storage. Types of LSD include NOR flash memory, NAND flash memory, HDDs, and magnetic tape.

[0410] Figure 36 The operating speed and write resistance of registers, cache, main memory, and long-term memory are shown in hierarchical order.

[0411] In addition, in recent years, research has been conducted on resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), phase-change memory (PCM), and other next-generation memory technologies.

[0412] For example, ReRAM is difficult to use in working memory due to its low write endurance. Although MRAM is being explored for application to SRAM, it is susceptible to external magnetic fields and has low heat resistance. In addition, PCM requires high voltage for writing data, which can easily increase power consumption.

[0413] Figure 37 This shows the data write time (time required to write data) and write resistance of various storage devices. Storage devices using OS-LSI have short data write times and high write resistance.

[0414] Figure 38 This shows the data retention time and operating frequency of various storage devices after a power outage. Storage devices using OS-LSI can retain data for more than a year even after a power outage. Furthermore, storage devices using OS-LSI operate at high frequencies, enabling high-speed operation.

[0415] The OS-LSI-based storage devices described in the above embodiments offer high operating speeds, long-term data retention, and low power consumption. Furthermore, they can retain data even at high temperatures. Therefore, OS-LSI-based storage devices can be used for both working memory and long-term storage. By using OS-LSI, general-purpose memory can be realized.

[0416] This embodiment can be implemented by appropriately combining the structures shown in other embodiments, etc.

[0417] [Symbol Explanation]

[0418] 100: Storage device; 111: Peripheral circuit; 121: Row decoder; 122: Word line driver circuit; 130: Bit line driver circuit; 131: Column decoder; 132: Precharge circuit; 133: Amplifier circuit; 134: Input / output circuit; 140: Output circuit; 160: Control logic circuit; 201: Cell array; 211: Storage cell

Claims

1. A storage device, comprising: A memory cell including a first transistor and a second transistor; Insulating layers on the first transistor and the second transistor; First character line, second character line; as well as First line, second line. The semiconductor layer of the first transistor comprises a metal oxide. The insulating layer includes multiple voids. The first bit line and the second bit line extend in a first direction. The first character line and the second character line extend in the second direction. The gate of the first transistor is electrically connected to the first word line. One of the source and drain terminals of the first transistor is electrically connected to the gate of the second transistor. The other of the source and drain of the first transistor is electrically connected to the first bit line. One of the source and drain of the second transistor is electrically connected to the second word line. The other of the source and drain of the second transistor is electrically connected to the second bit line. The plurality of gaps all comprise regions extending in directions intersecting the first direction. Furthermore, the first character line, the second character line, and the second bit line all include regions that overlap with the plurality of gaps.

2. A storage device, comprising: A memory cell including a first transistor and a second transistor; Insulating layers on the first transistor and the second transistor; First character line, second character line; First line, second line; as well as First conductive layer, The semiconductor layer of the first transistor comprises a metal oxide. The insulating layer includes multiple voids. The first bit line and the second bit line extend in a first direction. The first character line and the second character line extend in the second direction. The gate of the first transistor is electrically connected to the first word line. One of the source and drain terminals of the first transistor is electrically connected to the gate of the second transistor. The other of the source and drain of the first transistor is electrically connected to the first bit line. One of the source and drain of the second transistor is electrically connected to the second word line. The other of the source and drain of the second transistor is electrically connected to the second bit line. The first conductive layer includes a region that overlaps with the semiconductor layer of the first transistor and a region that overlaps with one of the source and drain electrodes of the first transistor. The plurality of gaps all comprise regions extending in directions intersecting the first direction. Furthermore, the first character line, the second character line, and the second bit line all include regions that overlap with the plurality of gaps.

3. The storage device according to claim 2, The first conductive layer includes a region that serves as the back gate of the first transistor.

4. The storage device according to any one of claims 1 to 3, The semiconductor layer contains at least one or both of In and Zn.

5. The storage device according to any one of claims 1 to 3, The plurality of gaps are all included in regions extending in directions intersecting the second direction.

6. The storage device according to any one of claims 1 to 3, The area where the gate electrode of the second transistor overlaps with the semiconductor layer is larger than the area where the gate electrode of the first transistor overlaps with the semiconductor layer.

7. The storage device according to any one of claims 1 to 3, The area where the gate electrode of the second transistor overlaps with the semiconductor layer is more than 1 and less than 10 times the area where the gate electrode of the first transistor overlaps with the semiconductor layer.

8. An electronic device, comprising: The storage device according to any one of claims 1 to 3; as well as Microphone, camera, speaker, antenna, or battery.

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