Performance Efficiency-Based Scheduling Method, Device, and Computer-Readable Storage Medium

Abstract

The scheduling method includes calculating the required performance of a given task, calculating the utilization performance and the actual performance of a candidate processor, calculating the power corresponding to the actual performance, calculating the expected energy consumption of the candidate processor based on the required performance, the utilization performance, the actual performance, and the calculated power, and calculating the performance efficiency of the candidate processor by considering the ratio of the expected energy consumption to the actual performance.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2019 - 0094799, filed on August 5, 2019 with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Background Art 1. Technical Field

[0004] The present disclosure relates to a performance - efficiency - based scheduling method and apparatus and a computer - readable storage medium. 2. Background Art

[0006] The best - effort scheduling (BES) method assigns a given task to a hardware resource (i.e., a processor) that can process the task according to the performance required by the task. The BES method is applicable to alternating - current (AC) powered devices such as servers and desktop computers, and this method is based on the assumption that the energy supply for resource use is unlimited. The BES method may not be applicable to mobile devices that receive energy from a battery. This is because battery time and performance are important factors.

[0007] On the other hand, the energy - aware scheduling (EAS) method assigns a task to a processor that consumes the lowest power among the processors that satisfy the performance required by the task. The purpose of the EAS method is to reduce (or alternatively, minimize) energy use without degrading performance. The EAS method is based on the premise that all processors that satisfy the performance required by the task provide the same performance. However, since processors are actually different in performance, the task assignment using the EAS method may not be completely efficient. Summary of the Invention

[0008] Exemplary embodiments of the present disclosure provide a performance - efficiency - based scheduling method.

[0009] Exemplary embodiments of the present disclosure also provide a performance - efficiency - based scheduling apparatus.

[0010] Exemplary embodiments of the present disclosure further provide a computer - readable storage medium storing a computer program product for performing scheduling based on performance efficiency.

[0011] However, the exemplary embodiments of the present disclosure are not limited to the exemplary embodiments set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the following detailed description of the present disclosure.

[0012] According to an exemplary embodiment of the present disclosure, a method for scheduling tasks is provided. The method includes calculating the required performance of a task; calculating the utilization performance and the actual performance of a corresponding candidate processor among a plurality of candidate processors; calculating the power corresponding to the actual performance; calculating the expected energy consumption of the corresponding candidate processor based on the required performance, the utilization performance, the actual performance, and the power corresponding to the actual performance; calculating the performance efficiency of the corresponding candidate processor based on the expected energy consumption and the actual performance; and scheduling the task to one of the plurality of candidate processors based on the performance efficiency.

[0013] According to another exemplary embodiment of the present disclosure, a method for scheduling a task to one of a first candidate processor to an nth candidate processor is provided, where n is a natural number of 2 or greater. The method includes calculating the first performance efficiency to the nth performance efficiency of the first candidate processor to the nth candidate processor capable of processing the task, respectively; and allocating the task to the kth candidate processor among the first candidate processor to the nth candidate processor based on the first performance efficiency to the nth performance efficiency, where k is a natural number satisfying 1≤k≤n.

[0014] According to other exemplary embodiments of the present disclosure, a scheduling device is provided, which includes a memory storing computer-readable instructions; and a processing circuit configured to execute the computer-readable instructions to calculate the required performance of a task, calculate the utilization performance and the actual performance of a corresponding candidate processor among a plurality of candidate processors, calculate the power corresponding to the actual performance, calculate the performance efficiency of the corresponding candidate processor based on the expected energy consumption and the actual performance, the expected energy consumption being based on the required performance, the utilization performance, the actual performance, and the power corresponding to the actual performance, and schedule the task to one of the plurality of candidate processors based on the performance efficiency.

[0015] According to other exemplary embodiments of the present disclosure, a non-transitory computer-readable storage medium is provided, which stores a computing program product that, when executed by a computing device, is configured to calculate the required performance of a task; calculate the utilization performance and the actual performance of a corresponding candidate processor among a plurality of candidate processors; calculate the power corresponding to the actual performance; calculate the performance efficiency of the corresponding candidate processor based on the expected energy consumption and the actual performance, the expected energy consumption being based on the required performance, the utilization performance, the actual performance, and the power corresponding to the actual performance; and schedule the task to one of the plurality of candidate processors based on the performance efficiency.

[0016] According to other exemplary embodiments of the present disclosure, at least one computer program product is provided, which is stored in at least one computer-readable storage medium and executed by a computing device. The at least one computer program product includes: instructions for calculating the required performance for a given task, instructions for calculating the usage performance and actual performance of a candidate processor, instructions for calculating the power corresponding to the actual performance, and instructions for calculating the performance efficiency of the candidate processor by considering the ratio of the expected energy usage to the actual performance, where the expected energy usage is a value calculated based on the required performance, usage performance, actual performance, and calculated power.

[0017] However, the exemplary embodiments of the inventive concept are not limited to the exemplary embodiments set forth herein. By referring to the detailed description of the inventive concept given below, the above and other exemplary embodiments of the inventive concept will become more apparent to those of ordinary skill in the art to which the inventive concept pertains. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] These and / or other aspects will become apparent and more readily understood from the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is a block diagram of a computing device in which a scheduling method according to an exemplary embodiment is applied;

[0020] Figure 2 is a flowchart showing a scheduling method according to an exemplary embodiment;

[0021] Figure 3 is a flowchart showing a scheduling method according to an exemplary embodiment;

[0022] Figure 4 is an example table summarizing the actual performance of a processor and the power corresponding to the actual performance;

[0023] Figure 5 is a diagram for illustrating a plurality of cluster processors;

[0024] Figure 6 is a diagram for illustrating a plurality of processors with clamped actual performance; and

[0025] Figure 7 shows a scheduling device according to an exemplary embodiment. DETAILED DESCRIPTION

[0026] In the following, various exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0027] Figure 1 is a block diagram of a computing device in which a scheduling method according to an exemplary embodiment is applied.

[0028] ReferenceFigure 1 , wherein the computing device to which the scheduling method according to the exemplary embodiment is applied includes a plurality of processors 110, 120, 122 and a memory 140, etc. In Figure 1 , the processors 110, 120, 122 and the memory 140, etc. are connected via a bus 115. However, the exemplary embodiment is not limited to this case. Known or dedicated techniques can also be used to connect the processors 110, 120, 122 within the system.

[0029] Each of the processors 110, 120, 122 may include an operating system (OS) 130. At least one of the processors 110, 120, and 122 may execute a scheduler 135 included in the OS to assign a given task to at least one of the processors 110, 120, 122. For example, the scheduler 135 selects one of the processors 110, 120, 122 for each task and starts routing each task to the selected processor. The scheduler 135 may be, but is not limited to, a software program operating in the environment of the OS 130, which, when executed, configures a corresponding one of the processors 110, 120, 122 as a dedicated computer. The scheduler 135 can be loaded and operated from the memory 140 connected to the processor 110 (each of the processors 110, 120, 122). In addition, the memory 140 may store information associated with the various processors 110, 120, 122 located in the system. The memory 140 may be implemented as a volatile memory, such as a dynamic random access memory (DRAM) or a static RAM (SRAM), or may be implemented as a non-volatile memory, such as a flash memory, a phase change RAM (PRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), or a magnetic RAM (MRAM).

[0030] The scheduler 135 is a module that, when loaded onto a corresponding one of the processors 110, 120, 122, configures the corresponding one of the processors 110, 120, and 122 to execute the scheduling method according to the exemplary embodiment. Thus, the reference to the scheduler 135 performing various functions hereinafter can be made by a corresponding one of the processors 110, 120, 122, and the processor executes the functions as a dedicated computer.

[0031] The scheduler 135 calculates the required performance of a given task, calculates the utilization performance and the actual performance of candidate processors, calculates the power corresponding to the actual performance, calculates the expected energy consumption of the candidate processors based on the required performance, utilization performance, actual performance, and the calculated power, and calculates the performance efficiency of the candidate processors by considering the ratio of the expected energy consumption to the actual performance. That is, the scheduler 135 calculates the performance efficiency of multiple candidate processors for a given task and assigns the task to any one of the candidate processors based on the calculated performance efficiency. Later, a detailed scheduling method will be described with reference to Figures 2 to 6 Describe the detailed scheduling method.

[0032] Figure 2 is a flowchart showing a scheduling method according to an exemplary embodiment. The scheduling method according to the embodiment is a performance efficiency scheduling (PES) method, which is a scheduling method based on performance efficiency. Figure 4 is an example table summarizing the actual performance of a processor and the power corresponding to the actual performance. Figure 5 is a diagram for explaining multiple cluster processors. Figure 6 is a diagram for explaining multiple processors with clamped actual performance.

[0033] First, with reference to Figure 2 , in operation S10, the scheduler 135 calculates the required performance of a given task. Specifically, the scheduler 135 may calculate the required performance of a given task using historical data as an average. For example, a historical average function provided by an operating system 130 such as LINUX may be used. For example, if the average performance required to execute a given task according to historical data is 30, the required performance of the given task is calculated as 30.

[0034] If the given task does not exist in the history, the scheduler 135 may refer to the history of similar tasks to calculate the required performance of the given task. For example, if the average performance required to execute a similar task according to historical data is 30, the required performance of the given task may be calculated as 30. Or, if the required performances of similar tasks are 20, 30, and 40, the required performance of the given task may be calculated as 30 (= (20 + 30 + 40) / 3).

[0035] In operation S20, the scheduler 135 may calculate the utilization performance and the actual performance of candidate processors.

[0036] Specifically, the scheduler 135 calculates the actual performance (true performance) of the candidate processors. Here, the actual performance can represent the performance set in the processor during scheduling. In other words, the actual performance represents the maximum performance of the processor when scheduling at the frequency set in the processor. Specifically, the actual performance of the processor can be determined by the frequency set in the processor. The higher the set frequency, the higher the actual performance of the processor. Conversely, the lower the set frequency, the lower the actual performance of the processor. By setting the frequency used by the processor, the actual performance of the processor can be determined.

[0037] In addition, the scheduler 135 calculates the usage performance of the candidate processors. Here, the usage performance represents the performance required for the processor to execute basic operations and / or the currently assigned tasks. The usage performance can also be referred to as the required performance of the processor.

[0038] For example, when the actual performance of a candidate processor is 100, the usage performance of the candidate processor is 100 or lower, because 100 represents the maximum performance at the set frequency.

[0039] The actual performance of the processor can be selected and set from several desired (or alternatively, preset) levels. For example, the actual performance can be selected from five desired (or alternatively, preset) levels of 50, 100, 150, 200, and 250 (see Figure 4 ). For example, when the required performance of the processor (e.g., the sum of the usage performance of the processor and the required performance of the given task) is 160, 200 can be selected as the actual performance instead of 160. This is because 160 is not included in the preset levels. For example, the dynamic voltage and frequency scaling (DVFS) method can be used to control the actual performance of the processor. Here, the DVFS levels can be non - continuous (discrete).

[0040] Here, referring to Figure 5 , the x - axis represents the processors, and the y - axis represents the performance. In Figure 5 , the usage performance (see the shaded part) of each of the multiple processors from P1 to P4 is shown. Processors P1 to P4 form a cluster. For example, the usage performance CU(1) of processor P1 is lower than the usage performance CU(2) of processor P2.

[0041] Figure 5Dashed lines are also shown, which show the actual performance RU(1) of processor P1 and the actual performance RU(2) of processor P2, which are equal to each other and greater than the usage performance CU(1) and CU(2). That is, considering the usage performance CU(1) of processor P1, the actual performance RU(1) of processor P1 does not need to be set so high. However, when multiple processors from P1 to P4 form a cluster, the actual performance can be controlled for the cluster (not for each individual processor). In the above DVFS method, the actual performance can also be controlled for each cluster. For example, the actual performance can be set based on the processor with the highest load in the cluster. That is, since processor P2 has the highest load (i.e., the highest usage performance CU(2)), the actual performance of all processors P1 to P4 belonging to the cluster is set based on processor P2. Therefore, the actual performance RU(1) of processor P1 is set to be equal to the actual performance RU(2) of processor P2. That is, when there is a serious load imbalance in the cluster, the gap between the actual performance RU(1) and the usage performance CU(1) of some processors (e.g., P1) may be large. In this case, even if the required performance TU of the task is increased to the usage performance CU(1), the actual performance RU(1) will not change.

[0042] In addition, referring to Figure 6 , the x-axis represents the processors, and the y-axis represents the performance. In Figure 6 , the usage performance of each of the multiple processors from P1 to P4 is shown (see the shaded part). For example, in order to improve the performance perceived by the user, each of the processors P1 to P4 can be clamped to an actual performance much higher than its usage performance. As shown in the figure, for example, the usage performance CU(1) of processor P1 is low, but the actual performance RU(1) is set to a high clamping level. In this case, since processor P1 runs at a higher frequency corresponding to the actual performance RU(1), the running speed of processor P1 is high (although processor P1 consumes more energy). Therefore, the performance perceived by the user is high. In this case, even if the required performance TU of the task is increased to the usage performance CU(1), the actual performance RU(1) will not change.

[0043] Next, referring again to Figure 2 , in operation S30, the scheduler 135 can calculate the power corresponding to the actual performance.

[0044] Specifically, the scheduler 135 can use a table showing the relationship between performance and power (see Figure 4) Calculate the power corresponding to the actual performance. The power can be calculated on average using previous history. Alternatively, an equation can be used to calculate the power, which reflects the set frequency and architecture of the processor (e.g., cache size, pipeline configuration, etc.). Alternatively, the power can be calculated to use a program (e.g., a benchmark program or Dhrystone), which uses the maximum performance of the processor.

[0045] As Figure 4 shown, when the performance is 50, 100, 150, 200, and 250, the power can be 400, 500, 700, 1000, and 1300 respectively. To calculate the power, methods other than using a table can also be used.

[0046] Next, in operation S40, the scheduler 135 can calculate the expected energy consumption of the candidate processors based on the required performance, used performance, actual performance, and calculated power.

[0047] Specifically, the expected energy consumption can be proportional to the required performance, used performance, and power, and can be inversely proportional to the actual performance.

[0048] When EE(1), CU(1), and RU(1) are the expected energy consumption, used performance, and actual performance of a candidate processor (e.g., P1) respectively, when RP(1) is the power corresponding to the actual performance RU(1) of the candidate processor P1, and when TU is the required performance of a given task, the expected energy consumption EE(1) can be calculated by Equation 1 below. Equation 1 is just an example, and the scope of the rights is not limited to this example.

[0049] EE(1) = (TU + CU(1)) x RP(1) / RU(1) … (1).

[0050] For example, when the used performance CU(1) of the candidate processor P1 is 160, the actual performance RU(1) is 200, the power corresponding to 200 (i.e., the actual performance RU(1)) is 1000, and the required performance TU of the given task is 30, then the scheduler 135 can calculate the expected energy consumption EE(1) as 950.

[0051] EE(1) = (30 + 160) x 1000 / 200 = 950

[0052] Next, in operation S50, the scheduler 135 can calculate the performance efficiency of the candidate processors by considering the ratio of the expected energy consumption to the actual performance.

[0053] Specifically, the performance efficiency of the candidate processor is a value obtained by dividing the actual performance by the expected energy usage, and represents the maximum performance that can be achieved for the consumed energy. That is, the performance efficiency represents the maximum performance that can be achieved per unit energy.

[0054] When PE(1), EE(1), and RU(1) are the performance efficiency, expected energy usage, and actual performance of a candidate processor (e.g., P1), the performance efficiency PE(1) can be calculated by the following equation 2. The performance efficiency PE(1) is proportional to the square of the actual performance RU(1) and inversely proportional to the used performance CU(1).

[0055] PE(1)=RU(1) / EE(1)

[0056] =RU(1) / {(TU+CU(1))x RP(1) / RU(1)}

[0057] =RU(1) 2 / {(TU+CU(1))x RP(1)}…(2).

[0058] For example, when the actual performance RU(1) of the candidate processor P1 is 200 and the expected energy usage EE(1) is 950, the scheduler 135 may calculate the performance efficiency PE(1) as approximately 0.210.

[0059] PE(1)=200 / 950=0.210

[0060] Next, in operation S60 , the scheduler 135 may allocate tasks based on the calculated performance efficiency.

[0061] Specifically, when there are n candidate processors, the scheduler 135 calculates the performance efficiency of each of the n candidate processors and allocates the task to the candidate processor with the highest performance efficiency.

[0062] In summary, the scheduler 135 calculates the first performance efficiency to the nth performance efficiency (where n is a natural number of 2 or greater) of the first candidate processor to the nth candidate processor that can process a given task. Here, the kth performance efficiency (where k is a natural number satisfying 1≤k≤n) represents the performance efficiency of the kth candidate processor. When PE(k), EE(k), CU(k), and RU(k) are the performance efficiency, expected energy usage, used performance, and actual performance of the kth candidate processor, respectively, when RP(k) is the power corresponding to the actual performance of the kth candidate processor, and when TU is the required performance of the given task, the expected energy usage EE(k) and performance efficiency PE(k) are determined by Equation 3.

[0063] EE(k) = (TU + CU(k)) x RP(k) / RU(k)

[0064] PE(k) = RU(k) / EE(k)

[0065] = RU(k) 2 / {(TU + CU(k)) x RP(k)}…(3).

[0066] The scheduler 135 assigns the task to the candidate processor corresponding to the highest performance efficiency among the calculated first to nth performance efficiencies.

[0067] Now, the performance efficiency scheduling method (PES method) according to the exemplary embodiment will be described in more detail using examples. The process of assigning a task to any one of the first candidate processor and the second candidate processor will be described.

[0068] Assume that the required performance TU of the task is 35, the utilization performance CU(1) of the first candidate processor is 100, and the utilization performance CU(2) of the second candidate processor is 110. However, the exemplary embodiment is not limited thereto.

[0069] Table 1 shows the relationship between the performance and power of the first candidate processor.

[0070] As described above, since the utilization performance CU(1) of the first candidate processor is 100, the scheduler 135 can select 140 as the actual performance RU(1) of the first candidate processor from the desired (or alternatively, preset) levels of 105 and 140 in Table 1. Thus, the scheduler 135 can determine based on Table 1 that the required power RP(1) corresponding to the performance 140 is 1000. In addition, since the utilization performance is 100 and the required performance TU of the task is 35, the scheduler 135 can calculate the sum (utilization performance + required performance) as 135.

[0071] [Table 1]

[0072] Performance Power 140 1000 105 700

[0073] Table 2 shows the relationship between the performance and power of the second candidate processor.

[0074] As described above, since the utilization performance CU(2) of the second candidate processor is 110, the scheduler 135 can select 160 as the actual performance RU(2) of the second candidate processor from the desired (or alternatively, preset) levels of 130 and 160 in Table 2. Thus, the scheduler 135 can determine based on Table 2 that the required power RP(2) corresponding to the performance 160 is 1100.

[0075] In addition, since the required performance TU of the task is 35, and the scheduler 135 can calculate the sum (utilization performance + required performance) as 145.

[0076] [Table 2]

[0077] Performance Power 160 1100 130 800

[0078] The scheduler 135 can calculate the expected energy usage EE(1) and performance efficiency PE(1) of the first candidate processor as follows.

[0079] EE(1) = (TU + CU(1)) x RP(1) / RU(1) = (35 + 100) x 1000 / 140 = 964.2857

[0080] PE(1) = RU(1) / EE(1) = 140 / 964.2857 = 0.145185

[0081] The scheduler 135 can calculate the expected energy usage EE(2) and performance efficiency PE(2) of the second candidate processor as follows.

[0082] EE(2) = (TU + CU(2)) x RP(2) / RU(2) = (35 + 110) x 1100 / 160 = 996.875

[0083] PE(2) = RU(2) / EE(2) = 160 / 996.875 = 0.160502

[0084] If the scheduler 135 allocates the task based on the minimum expected energy usage, the task will be allocated to the first candidate processor because the expected energy usage EE(1) = 964.2857 of the first candidate processor is less than the expected energy usage EE(2) = 996.875 of the second candidate processor.

[0085] However, if the scheduler 135 allocates the task based on the maximum performance efficiency, the task will be allocated to the second candidate processor because the performance efficiency PE(2) = 0.160502 of the second candidate processor is greater than the performance efficiency PE(1) = 0.145185 of the first candidate processor.

[0086] When allocating tasks in the following situations, the scheduling method according to the exemplary embodiment can exhibit a maximized effect. The following situations are those in which multiple candidate processors capable of handling the task do not provide the same performance. Since the scheduling method according to the exemplary embodiment calculates the performance efficiency by considering not only the utilization performance CU, but also the actual performance RU and the power RP corresponding to the actual performance, even in the following situations, more efficient and accurate task allocation is possible.

[0087] The first case is the one in which multiple processors operating at different non - consecutive DVFS levels form a system. As in the above example, this is the case in which the scheduler 135 controls the first candidate processor at the DVFS level of Table 1 and the second candidate processor at the DVFS level of Table 2. For example, even if the sum of the utilization performance of the first candidate processor and the required performance of the task (e.g., 140) is equal to the sum of the utilization performance of the second candidate processor and the required performance of the task, the scheduler 135 should control the DVFS level (actual performance) of the first candidate processor at 140, and control the DVFS level (actual performance) of the second candidate processor at 160.

[0088] The second case is the one in which multiple processors P1 to P4 form a cluster and there is a severe load imbalance in the cluster, as described using Figure 5 In this case, the scheduler 135 can set the actual performance of all processors P1 to P4 based on the processor with the highest load in the cluster. Since processor P2 has the highest load (i.e., the highest utilization performance CU(2)), the scheduler 135 sets the actual performance of all processors P1 to P4 belonging to the cluster based on processor P2. Therefore, the scheduler 135 sets the actual performance RU(1) of processor P1 to the actual performance RU(2) of processor P2. Therefore, the gap between the actual performance RU(1) and the utilization performance CU(1) of a processor (e.g., P1) may be large.

[0089] The third case is the one in which each of the processors P1 to P4 is clamped to an actual performance far higher than its utilization performance in order to improve the performance perceived by the user, as described using Figure 6 Although the utilization performance CU(1) of processor P1 is low, the scheduler 135 sets the actual performance RU(1) to a high clamping level.

[0090] The fourth case is the one in which multiple different - type (i.e., heterogeneous) processors form a system, or the one in which multiple processors with different architectural structures form a system, even if they are of the same type (i.e., homogeneous). Different architectures represent different cache sizes and pipeline configurations. For example, if a processor has a larger cache size or a more suitable pipeline configuration than other processors of the same type as that processor, it may exhibit substantially higher performance.

[0091] As described above, when there are differences in performance among multiple candidate processors capable of handling a task, the scheduler 135 can assign the task to the processor with the highest maximum performance per unit energy, as in the scheduling method according to the exemplary embodiment.

[0092] Figure 3is a flowchart showing a scheduling method according to an exemplary embodiment. For ease of description, the following will mainly describe the differences from the components and features described using Figure 1 and Figure 2 Description of components and features.

[0093] Referring to Figure 3 , in operation S52, the scheduler 135 may assign a weight to the performance efficiency calculated in operation S50, and operation S52 may occur between operation S50 and operation S60.

[0094] That is, when PE(k), w(k), and EE(k) are the performance efficiency, weight, and expected energy usage of the k-th candidate processor, respectively, the scheduler 135 may calculate the performance efficiency PE(k) based on Equation 4.

[0095] PE(k) = w(k) x RU(k) / EE(k)…(4).

[0096] The weight w(k) can be taken into account for the following reasons. A table (e.g., Figure 4 table) is used to calculate the actual performance and the power corresponding to the actual performance. However, the information provided in the table may not represent all real situations. A table of Figure 4 can be created based on a program (e.g., a benchmark program or Dhrystone) that uses the maximum performance of the processor as described above. However, in typical user scenarios (UX, games, etc.), the utilization rate of the processor is not 100%. Therefore, the table may not accurately reflect typical user scenarios. Therefore, in one or more exemplary embodiments, the reduction in accuracy can be compensated by using the weight w(k). In addition, user satisfaction can be intentionally improved by using different weights for performance / power consumption according to the scenario.

[0097] As described above, the k-th candidate processor may correspond to the following situations.

[0098] The k-th candidate processor and the first processor may form a cluster. The usage performance of the first processor may be set to be higher than that of the k-th candidate processor, and the actual performance of the first processor may be set to be higher than its usage performance. Here, the actual performance of the k-th candidate processor may be set to be equal to the actual performance of the first processor.

[0099] Alternatively, the k-th candidate processor may be clamped. Considering the usage performance of the k-th candidate processor, the first level of actual performance may be sufficient. However, the actual performance of the k-th candidate processor may be set to a second level higher than the first level. Here, the first level and the second level may be levels selected from preset levels.

[0100] Alternatively, the k-th candidate processor can be controlled at non - contiguous DVFS levels. That is, the actual performance of the k-th candidate processor can be selected and set from several preset levels.

[0101] Alternatively, the plurality of candidate processors can include the k-th candidate processor and the m-th candidate processor (where m is a natural number different from k and satisfies 1 ≤ m ≤ n), and the k-th candidate processor and the m-th candidate processor can be heterogeneous or can have different architectures, even if they are homogeneous.

[0102] Figure 7 A scheduling device according to an exemplary embodiment is shown. Figure 7 is a diagram showing Figure 1 an example configuration of the scheduler 135. For ease of description, the description of the elements and features described using Figures 1 to 6 will be omitted.

[0103] Referring to Figure 7 , a respective one of the processors 110, 120, 122 can execute software that configures the respective one of the processors 110, 120, 122 as a dedicated computer to perform the functions of a scheduling device including a task manager 210, a performance calculator 220, a performance efficiency calculator 230, and a selector 240.

[0104] Specifically, the task manager 210 calculates the required performance TU of a given task.

[0105] The performance calculator 220 calculates the usage performance CU(k) and the actual performance RU(k) of the candidate processor, and calculates the power RP(k) corresponding to the actual performance RU(k).

[0106] The performance efficiency calculator 230 calculates the performance efficiency PE(k) of each of the plurality of candidates. The performance efficiency calculator 230 calculates the performance efficiency PE(k) of each candidate processor among the candidate processors by considering the ratio of the expected energy usage EE(k) to the actual performance RU(k). Here, the expected energy usage EE(k) can be a value calculated based on the required performance TU, the usage performance CU(k), the actual performance RU(k), and the calculated power RP(k).

[0107] The expected energy usage EE(k) can be proportional to the required performance TU, the usage performance CU(k), and the power RP(k), and can be inversely proportional to the actual performance RU(k). The performance efficiency PE(k) can be proportional to the square of the actual performance RU(k) and inversely proportional to the usage performance CU(k). For example, the expected energy usage EE(k) and the performance efficiency PE(k) can be defined as in Equation 3. Additionally, the performance efficiency calculator 230 can assign a weight w(k) to the calculated performance efficiency PE(k).

[0108] The selector 240 assigns the task to the candidate processor with the highest performance efficiency, and thereafter, the candidate processor executes the assigned task.

[0109] The usage Figures 1 to 6 described scheduling method can be implemented as a non-transitory computer-readable storage medium that stores a computing program product executed by a computing device.

[0110] The computer program product can include instructions for calculating the required performance of a given task, instructions for calculating the usage performance and the actual performance of candidate processors, instructions for calculating the power corresponding to the actual performance, and instructions for calculating the performance efficiency of candidate processors by considering the ratio of the expected energy usage to the actual performance, where the expected energy usage is a value calculated based on the required performance, the usage performance, the actual performance, and the calculated power.

[0111] The computing device can include at least one of, for example, a desktop personal computer (PC), a laptop computer, a netbook computer, a workstation, a personal digital assistant (PDA), a portable multimedia player (PMP), a smartphone, a tablet computer, a mobile phone, a video phone, an e-book reader, an MP3 player, a medical device, a camera, and a wearable device. Here, the wearable device can include at least one of an accessory-type wearable device (e.g., a watch, a ring, a bracelet, an anklet, a necklace, glasses, contact lenses, and a head-mounted device (HMD)), a fabric / clothing integrated wearable device (e.g., electronic clothing), a body-attached wearable device (e.g., a skin pad and a tattoo), and a body-implanted circuit. In some embodiments, the computing device can include, for example, a television (TV), a digital video disc (DVD) player, an audio player, a refrigerator, an air conditioner, a vacuum cleaner, an oven, a microwave oven, a washing machine, an air purifier, a set-top box, a home automation control panel, a security control panel, a media box (e.g., Samsung HomeSync TM , Apple TV TM , or Google TV TM ), a game console (e.g., Xbox TM and PlayStation TM), at least one of an electronic dictionary, an electronic key, a camera, and an electronic photo frame.

[0112] In other example embodiments, the computing device may include at least one of the following: various medical devices (e.g., various portable medical measurement devices such as a blood glucose meter, a heart rate monitor, a blood pressure monitor, and a thermometer), magnetic resonance angiography (MRA) devices, magnetic resonance imaging (MRI) devices, computed tomography (CT) devices, scanners, and ultrasonic devices), navigation devices, global navigation satellite systems (GNSS), event data recorders (EDR), flight data recorders (FDR), vehicle infotainment devices, electronic devices for ships (e.g., ship navigation systems and gyrocompasses), avionics, safety devices, automotive head units, home or industrial robots, automated teller machines (ATMs) in financial institutions, point-of-sale (POS) devices in stores, and Internet of Things (IoT) devices (e.g., light bulbs, various sensors, sprinkler devices, fire alarms, thermostats, street lights, bread ovens, sports goods, hot water tanks, heaters, and boilers). According to an example embodiment, the electronic device may include at least one of a part of furniture or a building / structure or a vehicle, an electronic board, an electronic signature receiving device, a projector, and various measuring instruments (e.g., water meters, electricity meters, gas meters, and radio wave meters). In various example embodiments, the electronic device may be flexible, or may be a combination of two or more of the above devices.

[0113] The computer-readable storage medium may be a hard disk, a floppy disk, a magnetic medium (e.g., magnetic tape), an optical recording medium (e.g., a compact disc read-only memory (CD-ROM) or a digital versatile disc (DVD)), or a magneto-optical medium (e.g., an optical disk). In addition, the computer-readable storage medium may be a memory that includes volatile memory such as DRAM or SRAM and / or non-volatile memory such as flash memory, PRAM, RRAM, FRAM, or MRAM.

[0114] The above elements, such as the scheduler 135 and the modules therein (including the task manager 210, the performance calculator 220, the performance efficiency calculator 230, and the selector 240), may be implemented in a processing circuit, such as hardware including logic circuits; a hardware / software combination, such as a processor that executes software; or a combination of them and a memory. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. The processing circuit may be a dedicated processing circuit that more effectively and accurately allocates tasks not only based on the usage performance CU but also based on the actual performance RU and the power RP corresponding to the actual performance.

[0115] Upon concluding the detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the present invention concept. Therefore, the disclosed exemplary embodiments of the present invention concept are used only in a general and descriptive sense and not for the purpose of limitation.

[0116] Exemplary embodiments of the present invention concept have been described with reference to the accompanying drawings, but those of ordinary skill in the art can understand that the present invention concept can be implemented in other specific forms by those of ordinary skill in the art without changing the technical concept or basic features of the present invention concept. In addition, the above exemplary embodiments are merely examples and do not limit the scope of rights of the present invention concept.

Claims

1. A method for scheduling tasks, the method comprising: Calculating the required performance of the task; Calculating the usage performance and the actual performance of a corresponding candidate processor among a plurality of candidate processors; Calculating the power corresponding to the actual performance; Calculating the expected energy consumption of the corresponding candidate processor based on the required performance, the usage performance, the actual performance, and the power corresponding to the actual performance; Calculating the performance efficiency of the corresponding candidate processor based on the expected energy consumption and the actual performance; And Scheduling the task to one of the plurality of candidate processors based on the performance efficiency, wherein the usage performance represents the performance required for the corresponding candidate processor to execute the assigned task, wherein the actual performance represents the performance set at the time of scheduling in the corresponding candidate processor.

2. The method according to claim 1, further comprising: Applying a weight to the performance efficiency to generate a weighted performance efficiency, wherein Scheduling the task includes scheduling based on the weighted performance efficiency.

3. The method according to claim 1, wherein the scheduling includes assigning the task to one of the plurality of candidate processors having the highest performance efficiency.

4. The method according to claim 1, wherein calculating the expected energy consumption calculates the expected energy consumption such that: The expected energy consumption is proportional to the required performance, the usage performance, and the power corresponding to the actual performance, and The expected energy consumption is inversely proportional to the actual performance.

5. The method according to claim 1, wherein calculating the performance efficiency calculates the performance efficiency such that: The performance efficiency is proportional to the square of the actual performance, and The performance efficiency is inversely proportional to the usage performance.

6. The method according to claim 1, wherein the plurality of candidate processors includes a first candidate processor and a second candidate processor forming a cluster, and calculating the usage performance and the actual performance includes: Setting the usage performance of the first candidate processor to be higher than the usage performance of the second candidate processor; Setting the actual performance of the first candidate processor to be higher than the usage performance of the first candidate processor; And Setting the actual performance of the second candidate processor to be equal to the actual performance of the first candidate processor.

7. The method according to claim 1, wherein calculating the usage performance and the actual performance includes: Clamping the actual performance of the corresponding candidate processor to a second level of actual performance, the second level of actual performance being higher than the first level of actual performance, although the first level of actual performance is sufficient considering the usage performance of the corresponding candidate processor.

8. The method according to claim 1, wherein calculating the usage performance and the actual performance includes: Selecting the actual performance of the corresponding candidate processor from a plurality of preset levels.

9. The method according to claim 1, wherein the plurality of candidate processors includes a first candidate processor and a second candidate processor, and the first candidate processor and the second candidate processor are heterogeneous or have different architectures.

10. A method for scheduling a task to one of a first candidate processor to an nth candidate processor, where n is a natural number of 2 or greater, the method comprising: calculating a first performance efficiency to an nth performance efficiency of the first candidate processor to the nth candidate processor capable of processing the task, respectively, at least based on a usage performance of the corresponding candidate processor among the first candidate processor to the nth candidate processor, an actual performance of the corresponding candidate processor among the first candidate processor to the nth candidate processor, and a power corresponding to the actual performance; and assigning the task to a kth candidate processor among the first candidate processor to the nth candidate processor based on the first performance efficiency to the nth performance efficiency and a required performance of the task, where k is a natural number satisfying 1 ≤ k ≤ n, and wherein the kth candidate processor has the highest calculated performance efficiency among the first candidate processor to the nth candidate processor, wherein the usage performance represents the performance required for the corresponding candidate processor to execute the assigned task, wherein the actual performance represents the performance set at the time of scheduling in the corresponding candidate processor.

11. The method according to claim 10, wherein the calculation includes: calculating a kth performance efficiency for the kth candidate processor based on PE(k) = w(k) x RU(k) / EE(k), EE(k) = (TU + CU(k)) x RP(k) / RU(k), where, PE(k), w(k), EE(k), CU(k), and RU(k) are the performance efficiency, weight, expected energy usage, usage performance, and actual performance of the kth candidate processor, respectively, RP(k) is the power corresponding to the actual performance of the kth candidate processor, and TU is the required performance of the task.

12. The method according to claim 10, wherein the first candidate processor to the nth candidate processor form a cluster, and the method includes: setting the usage performance of the first candidate processor to be higher than the usage performance of the kth candidate processor; setting the actual performance of the first candidate processor to be higher than the usage performance of the first candidate processor; and setting the actual performance of the kth candidate processor to be equal to the actual performance of the first candidate processor.

13. The method according to claim 10, further comprising: clamping the actual performance of the kth candidate processor to a second level of actual performance, the second level of actual performance being higher than a first level of actual performance, although the first level of actual performance is sufficient considering the usage performance of the kth candidate processor.

14. The method according to claim 10, further comprising: selecting the actual performance of the kth candidate processor from a plurality of preset levels.

15. The method of claim 10, wherein the kth candidate processor and the mth candidate processor are provided, and the kth candidate processor and the mth candidate processor are heterogeneous, or even if the kth candidate processor and the mth candidate processor are homogeneous, they have different architectures, where m is a natural number different from k and satisfies 1≤m≤n.

16. A scheduling device comprising: a memory storing computer-readable instructions; and processing circuitry configured to execute the computer-readable instructions for: the required performance of the computational task, Calculating the usage performance and actual performance of corresponding candidate processors among the plurality of candidate processors, Calculate the power corresponding to the actual performance, calculating a performance efficiency of the corresponding candidate processor based on an expected energy usage and the actual performance, the expected energy usage being based on the required performance, the used performance, the actual performance, and the power corresponding to the actual performance, and scheduling the task to one of the plurality of candidate processors based on the performance efficiency, The usage performance represents the performance required by the corresponding candidate processor to execute the assigned task. The actual performance refers to the performance set during scheduling in the corresponding candidate processor.

17. The scheduling device of claim 16, wherein the processing circuit is configured to apply a weight to the performance efficiency to generate a weighted performance efficiency.

18. The scheduling device of claim 16, wherein the processing circuit is configured to schedule the task by allocating the task to one of the plurality of candidate processors having the highest performance efficiency.

19. The scheduling device of claim 16, wherein the processing circuit is configured to calculate the expected energy usage such that: The expected energy usage is proportional to the required performance, the used performance, and the power corresponding to the actual performance, and The expected energy usage is inversely proportional to the actual performance.

20. The scheduling device of claim 16, wherein the processing circuit is configured to calculate the performance efficiency such that: The performance efficiency is proportional to the square of the actual performance, and The performance efficiency is inversely proportional to the usage performance.

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