A source follower type equalization circuit

Abstract

A source follower form of equalization circuit, which adopts a symmetrical common-source circuit structure and is divided into a left circuit and a right circuit. The left circuit is as follows: A resistor R1 is connected from the first power supply and then connected to the D pole of the NMOS transistor NM1. The G pole of the NMOS transistor NM1 is connected to the S pole of the NMOS transistor NM1 through a capacitor C1. The S pole of the NMOS transistor NM1 is grounded through a capacitor C2, and the S pole of the NMOS transistor NM1 is grounded later. Through the zero point formed by the gm of the NMOS transistor and C1, the pole point formed by R1, C1 and the gm of the NMOS transistor, and the differences between Av|high and Av|low, this scheme achieves the equalization effect, and at the same time takes into account the requirements of common-mode level conversion while realizing equalization. The circuit is simple and small in area, and is especially suitable for DC coupling circuits with not too large attenuation.

Description

Technical Field

[0001] The present invention relates to the field of equalization circuits, and particularly to an equalization circuit in the form of a source follower. Background Art

[0002] Existing equalization circuits mostly adopt two structural forms. One is a passive structure, and the other is a common-source structure. The circuit of the passive structure is as Figure 1 , it can be seen that the passive structure cannot provide gain, and the effect is not good for signals with relatively small amplitudes; the circuit of the common-source structure is as Figure 2 , it can be seen that the circuit of the common-source structure is relatively complex, and moreover, the circuit of the common-source structure has certain requirements for the input common-mode level, such as Figure 3 is the waveform diagram of the existing common-source structure circuit, and from which we can obtain according to the formula: And due to Therefore, it can be obtained that Therefore, we can know that the prior art achieves the equalization effect by selecting different R S , C S , and the gm of the nmos transistor, and has certain requirements for the input common-mode level. Summary of the Invention

[0003] The purpose of the present invention is to provide an equalization circuit in the form of a source follower, which designs a special circuit by using the characteristics of NMOS transistors or PMOS transistors to solve the above problems.

[0004] The technical solution adopted by the present invention is as follows:

[0005] Solution 1: An equalization circuit in the form of a source follower adopts a symmetric common-source circuit structure, which is divided into a left circuit and a right circuit. The left circuit is: connected from the first power supply to the D pole of the NMOS transistor NM1, the G pole of the NMOS transistor NM1 is connected to the S pole of the NMOS transistor NM1 through the capacitor C1, the S pole of the NMOS transistor NM1 is grounded through the capacitor C2, and the S pole of the NMOS transistor NM1 is also grounded through a resistor R1;

[0006] The right circuit: connected from the second power supply to the D pole of the NMOS transistor NM2, the G pole of the NMOS transistor NM2 is connected to the S pole of the NMOS transistor NM2 through the capacitor C3, the S pole of the NMOS transistor NM2 is grounded through the capacitor C4, and the S pole of the NMOS transistor NM2 is also grounded through a resistor R2; the PN of the NMOS transistor NM1 and the NMOS transistor NM2 are connected and then grounded;

[0007] The capacitor C1 and the capacitor C3 are the same, the capacitor C2 and the capacitor C4 are the same, the resistor R1 and the resistor R2 are the same, and the NMOS transistor NM1 and the NMOS transistor NM2 are the same; the G pole of the NMOS transistor NM1 is used as the high-level input Vin+, and the S pole of the NMOS transistor NM1 is used as the high-level output Vo+; the G pole of the NMOS transistor NM2 is used as the low-level input Vin-, and the S pole of the NMOS transistor NM2 is used as the low-level output Vo-.

[0008] Solution 2: A source-follower type equalization circuit, which adopts a symmetric common-source circuit structure and is divided into a left circuit and a right circuit. The left circuit is as follows: A resistor R1 is connected from the first power supply and then connected to the D pole of the PMOS transistor PM1. The G pole of the PMOS transistor PM1 is connected to the D pole of the PMOS transistor PM1 through a capacitor C1. The S pole of the PMOS transistor PM1 is grounded, and the D pole of the PMOS transistor PM1 is also grounded through a capacitor C2;

[0009] The right circuit is as follows: A resistor R2 is connected from the second power supply and then connected to the D pole of the PMOS transistor PM2. The G pole of the PMOS transistor PM2 is connected to the D pole of the PMOS transistor PM1 through a capacitor C3. The S pole of the PMOS transistor PM1 is grounded, and the D pole of the PMOS transistor PM1 is also grounded through a capacitor C4; The PN of the PMOS transistor PM1 and the PMOS transistor PM2 are connected and then connected to the third power supply;

[0010] The capacitor C1 and the capacitor C3 are the same, the capacitor C2 and the capacitor C4 are the same, the resistor R1 and the resistor R2 are the same, and the PMOS transistor PM1 and the PMOS transistor PM2 are the same; the G pole of the PMOS transistor PM1 is used as the high-level input Vin+, and the D pole of the PMOS transistor PM1 is used as the high-level output Vo+; the G pole of the PMOS transistor PM2 is used as the low-level input Vin-, and the D pole of the PMOS transistor PM2 is used as the low-level output Vo-.

[0011] In fact, the two solutions are different variants of the same idea, and the difference between Solution 1 and Solution 2 lies in the different circuits when using NMOS transistors and PMOS transistors. Here, we take Solution 1 as an example. In Solution 1, while and therefore Through the zero point formed by the gm of the NMOS transistor and C1, the pole point formed by R1, C1 and the gm of the NMOS transistor, and the differences between Av|high and Av|low, the equalization effect is achieved in this technology, and the requirement of common-mode level conversion is taken into account while realizing equalization. The circuit is simple and small in area, and is especially suitable for DC coupling circuits with not too large attenuation.

[0012] In summary, due to the adoption of the above technical solutions, the beneficial effects of the present invention are:

[0013] 1. An equalization circuit in the form of a source follower according to the present invention utilizes the characteristics of NMOS or PMOS transistors to design a special circuit, realizing the equalization technology in the form of a source follower and reducing the requirement of the input stage for the common-mode level;

[0014] 2. An equalization circuit in the form of a source follower according to the present invention utilizes the characteristics of NMOS or PMOS transistors to design a special circuit, which realizes a certain degree of equalization while achieving level conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solution of the present invention, the accompanying drawings required for use in the embodiments will be briefly introduced below. It should be understood that for those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings, where:

[0016] Figure 1 is the circuit diagram of the passive structure in the prior art of the present invention;

[0017] Figure 2 is the circuit diagram of the common-source structure in the prior art of the present invention;

[0018] Figure 3 is the waveform diagram of the common-source structure circuit in the prior art of the present invention;

[0019] Figure 4 is the circuit diagram of the first solution of the present invention;

[0020] Figure 5 is the circuit diagram of the second solution of the present invention;

[0021] Figure 6 is the output AC response curve of the solution of the present invention;

[0022] Figure 7 is the waveform diagram of the output current of the solution of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] In order to more clearly illustrate the technical solution of the embodiments of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. It should be understood that the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments, and should not be regarded as a limitation of the protection scope. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0024] In the description of the present invention, it should be noted that unless otherwise clearly specified and defined, the terms "arranged", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can also be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0025] The following will Figures 1 to 7 describe the present invention in detail.

[0026] Embodiment 1

[0027] Solution 1: As shown in Figure 4 , a source-follower type equalization circuit adopts a symmetric common-source circuit structure and is divided into a left circuit and a right circuit. The left circuit is: connected from the first power supply to the D pole of NMOS transistor NM1, the G pole of NMOS transistor NM1 is connected to the S pole of NMOS transistor NM1 through capacitor C1, the S pole of the NMOS transistor NM1 is grounded through capacitor C2, and the S pole of the NMOS transistor NM1 is also grounded through a resistor R1;

[0028] The right circuit: connected from the second power supply to the D pole of NMOS transistor NM2, the G pole of NMOS transistor NM2 is connected to the S pole of NMOS transistor NM2 through capacitor C3, the S pole of the NMOS transistor NM2 is grounded through capacitor C4, and the S pole of the NMOS transistor NM2 is also grounded through a resistor R2; the PN connections of the NMOS transistor NM1 and the NMOS transistor NM2 are grounded;

[0029] The capacitor C1 and the capacitor C3 are the same, the capacitor C2 and the capacitor C4 are the same, the resistor R1 and the resistor R2 are the same, and the NMOS transistor NM1 and the NMOS transistor NM2 are the same; the G pole of the NMOS transistor NM1 is the high-level input Vin+, and the S pole of the NMOS transistor NM1 is the high-level output Vo+; the G pole of the NMOS transistor NM2 is the low-level input Vin-, and the S pole of the NMOS transistor NM2 is the low-level output Vo-.

[0030] Working principle: As shown in Figure 6 is the output AC response curve of the solution described in this embodiment; Figure 7 is the waveform diagram of the current output by the solution described in this embodiment. In Solution 1, while and therefore Through the zero point formed by the gm of the NMOS transistor and C1, the pole formed by R1, C1 and the gm of the NMOS transistor, and the differences between Av|high and Av|low, the present technology achieves a balanced effect, taking into account the requirements of common-mode level conversion while achieving balance. The circuit is simple and small in area, and is particularly suitable for DC coupling circuits with not too large attenuation.

[0031] Embodiment 2

[0032] Solution 2: As Figure 5 , a source-follower type equalization circuit, adopting a symmetric common-source circuit structure, divided into a left circuit and a right circuit. The left circuit is: connected from the first power supply to the D pole connection of PMOS transistor PM1. The G pole of PMOS transistor PM1 is connected to the D pole of PMOS transistor PM1 through capacitor C1. The S pole of the PMOS transistor PM1 is grounded through resistor R1, and the D pole of the PMOS transistor PM1 is also grounded through a capacitor C2.

[0033] The right circuit is: connected from the second power supply to the D pole connection of PMOS transistor PM2. The G pole of PMOS transistor PM2 is connected to the D pole of PMOS transistor PM1 through capacitor C3. The S pole of the PMOS transistor PM1 is grounded through resistor R2, and the D pole of the PMOS transistor PM1 is also grounded through a capacitor C4. The PN connections of the PMOS transistor PM1 and the PMOS transistor PM2 are connected to the third power supply.

[0034] The capacitor C1 and the capacitor C3 are the same, the capacitor C2 and the capacitor C4 are the same, the resistor R1 and the resistor R2 are the same, and the PMOS transistor PM1 and the PMOS transistor PM2 are the same. Taking the G pole of the PMOS transistor PM1 as the high-level input Vin+, and the D pole of the PMOS transistor PM1 as the high-level output Vo+. Taking the G pole of the PMOS transistor PM2 as the low-level input Vin-, and the D pole of the PMOS transistor PM2 as the low-level output Vo-.

[0035] Other parts and principles of this embodiment are the same as those of the above Embodiment 1, so they will not be elaborated here.

[0036] In fact, the two solutions are different variants of the same idea. The difference between Solution 1 and Solution 2 lies in the different circuits when using NMOS transistors and PMOS transistors, realizing the source-follower type equalization technology and reducing the requirements of the input stage for the common-mode level. While achieving level conversion, a certain degree of equalization is also realized, taking into account the requirements of common-mode level conversion while achieving equalization. The circuit is simple and small in area, and is particularly suitable for DC coupling circuits with not too large attenuation.

[0037] The above are only the preferred embodiments of the present invention, and do not impose any formal limitations on the present invention. Any simple modifications and equivalent changes made to the above embodiments based on the technical essence of the present invention all fall within the protection scope of the present invention.

Claims

1. A source follower type equalization circuit, characterized in that: A symmetric common-source circuit structure is adopted, which is divided into a left circuit and a right circuit. The left circuit is as follows: It is connected from the first power supply to the D pole of NMOS transistor NM1. The G pole of NMOS transistor NM1 is connected to the S pole of NMOS transistor NM1 through capacitor C1. The S pole of the NMOS transistor NM1 is grounded through capacitor C2, and the S pole of the NMOS transistor NM1 is also grounded through a resistor R1. The right circuit: It is connected from the second power supply to the D pole of NMOS transistor NM2. The G pole of NMOS transistor NM2 is connected to the S pole of NMOS transistor NM2 through capacitor C3. The S pole of the NMOS transistor NM2 is grounded through capacitor C4, and the S pole of the NMOS transistor NM2 is also grounded through a resistor R2. The PN connection of the NMOS transistor NM1 and the NMOS transistor NM2 is grounded. The capacitor C1 and the capacitor C3 are the same, the capacitor C2 and the capacitor C4 are the same, the resistor R1 and the resistor R2 are the same, and the NMOS transistor NM1 and the NMOS transistor NM2 are the same. The G pole of the NMOS transistor NM1 is used as the high-level input Vin+, and the S pole of the NMOS transistor NM1 is used as the high-level output Vo+. The G pole of the NMOS transistor NM2 is used as the low-level input Vin-, and the S pole of the NMOS transistor NM2 is used as the low-level output Vo-. Among them, , , , ; The zero formed by the gm of NMOS transistor NM1 and capacitor C1 , and the pole formed by resistor R1, capacitor C1 and the gm of NMOS transistor NM1 , and due to the differences between the high-frequency gain Av|high and the low-frequency gain Av|low, an equalization effect is achieved, while meeting the requirements of common-mode level conversion while achieving equalization.

2. A source follower type equalization circuit, characterized in that: A symmetric common-source circuit structure is adopted, which is divided into a left circuit and a right circuit. The left circuit is as follows: A resistor R1 is connected from the first power supply and then connected to the D pole of PMOS transistor PM1. The G pole of PMOS transistor PM1 is connected to the D pole of PMOS transistor PM1 through capacitor C1. The S pole of the PMOS transistor PM1 is grounded, and the D pole of the PMOS transistor PM1 is also grounded through a capacitor C2. The right circuit is as follows: A resistor R2 is connected from the second power supply and then connected to the D pole of PMOS transistor PM2. The G pole of PMOS transistor PM2 is connected to the D pole of PMOS transistor PM1 through capacitor C3. The S pole of the PMOS transistor PM1 is grounded, and the D pole of the PMOS transistor PM1 is also grounded through a capacitor C4. The PN connection of the PMOS transistor PM1 and the PMOS transistor PM2 is connected to the third power supply. The capacitor C1 and the capacitor C3 are the same, the capacitor C2 and the capacitor C4 are the same, the resistor R1 and the resistor R2 are the same, and the PMOS transistor PM1 and the PMOS transistor PM2 are the same. The G pole of the PMOS transistor PM1 is used as the high-level input Vin+, and the D pole of the PMOS transistor PM1 is used as the high-level output Vo+. The G pole of the PMOS transistor PM2 is used as the low-level input Vin-, and the D pole of the PMOS transistor PM2 is used as the low-level output Vo-. Through the zero point formed by the gm of the PMOS transistor PM1 and the capacitor C1, the pole point formed by the resistor R1, the capacitor C1 and the gm of the PMOS transistor PM1, and the differences between Av|high and Av|low, an equalization effect is achieved, and while achieving equalization, the requirements of common-mode level conversion are also taken into account.

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