On-chip reliability monitor and method

Abstract

Disclosed is a chip-borne reliability monitor and method. The monitor includes a test circuit having a test device, a reference circuit having a reference device, and a comparator circuit. The monitor periodically switches from stress mode operation to test mode operation, and back again. During each stress mode, the test device is subjected to stress conditions that simulate the operating conditions of the chip-borne functional device, while the reference device remains substantially unstressed. During each test mode, the comparator circuit compares the parameters of the test device with the same parameters of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches value, it is an indicator that the functional device has been subjected to a predetermined number of power-on hours. Alternatively, multiple monitors can be connected in series to more accurately monitor stress-induced changes over time.

Description

[0001] This application is a divisional application of the Chinese patent application with application number 201910063350.5, application date January 23, 2019, and invention name “Crystal-borne reliability monitor and method”. Technical Field

[0002] The present invention relates to device reliability, and more particularly to on-chip reliability monitors and methods. Background Art

[0003] Various mechanisms associated with different classes of devices incorporated into integrated circuit (IC) chips (e.g., hot carrier injection, time-dependent dielectric breakdown, negative-bias temperature instability (NBTI), positive-bias temperature instability (PBTI), etc.) cause chip performance to degrade over time due to stress conditions (e.g., high temperature and / or high voltage). Generally, to predict how IC chips in a given semiconductor technology will perform over time and in response to high stress conditions, all devices available in the given semiconductor technology are subjected to accelerated voltage and / or temperature stress tests at the wafer level or module level in a laboratory environment, and / or in a test system environment. Then, based on the results of the accelerated stress tests, performance degradation models and end of life (EOL) predictions are generated. Generally, to monitor the reliability of IC chips, power-on hours (POH) monitors are used to track the amount of time the chip is powered on, and the POH number is compared to the end of life prediction. Unfortunately, the environmental assumptions associated with the selected product sample used to apply the performance degradation model and end-of-life prediction may be different from the actual environmental conditions in other products. For example, the operating temperature, operating voltage, power-on hours (POH), etc. of the IC chip may vary from product to product. Therefore, the resulting performance degradation model and EOL prediction may not be applicable to all products. In this case, tracking POH alone may cause the chip to fail before the predicted EOL (measured in POH), or alternatively, may cause the chip to be scrapped too early. Summary of the invention

[0004] In view of the foregoing, a chip-borne reliability monitor and a reliability monitoring method are disclosed herein. The reliability monitor may include a test circuit having a test device, a reference circuit having a reference device, and a comparator circuit connected to the test circuit and the reference circuit. The reliability monitor may operate alternately in stress and test modes, and specifically, may periodically switch from operating in stress mode to operating in test mode and back again. During each stress mode, the test device may be subjected to a stress condition that simulates the operating conditions of the chip-borne functional device, while the reference device remains substantially unstressed. During each test mode, the stress condition may be removed from the test device, and the comparator circuit may compare the parameters of the test device with the same parameters of the reference device, and may output a status signal based on the difference between the parameters. Specifically, when the difference between the parameters reaches a predetermined threshold amount, the comparator circuit may switch the status signal from one value to another, and may ensure that the status signal remains constant once switched. It should be noted that when the parameter in question is known to change at a higher rate in response to applied stresses at the beginning of life and to change at a lower rate in response to applied stresses toward the end of life, and when small differences in the parameter are difficult to detect, multiple reliability monitors can be connected in series to more accurately monitor stress-induced changes near the end of life, as described in more detail below.

[0005] More particularly, disclosed herein is a specific embodiment of an integrated circuit (IC) chip that includes a substrate and a reliability monitor located on the substrate. The reliability monitor may include a test circuit having a test device, and a reference circuit having a reference device. Both the test device and the reference device may be substantially equivalent to a die-borne functional device. The reliability monitor may further include a comparator circuit connected to the test circuit and the reference circuit. When the IC chip is powered on, the reliability monitor may operate alternately in stress and test modes (e.g., may periodically switch from operating in a stress mode to operating in a test mode and back again). During each stress mode, the test device may be subjected to a stress condition that simulates the operating conditions of the die-borne functional device, while the reference device remains substantially unstressed. During each test mode, the stress condition may be removed from the test device, and the comparator circuit may compare a specific parameter of the test device (referred to as a test parameter) with the same parameter of the reference device (referred to as a reference parameter), and may output a status signal based on the difference between the test parameter and the reference parameter. Specifically, when the difference between the test parameter and the reference parameter reaches a predetermined threshold amount, the comparator circuit may switch the state signal from one value to another value (e.g., from low to high, from logic value "0" to "1"), and may further ensure that the state signal remains constant once switched. This switching of the state signal value will indicate that the power of the on-chip functional device is turned on for a predetermined number of hours (e.g., X power-on hours (POH)).

[0006] Another embodiment of an integrated circuit (IC) chip is also disclosed herein, which includes a substrate and a plurality of serially connected reliability monitors located on the substrate. In particular, it is often known that the parameter in question changes at a higher rate in response to applied stress at the beginning of life, and changes at a lower rate in response to applied stress toward the end of life. Furthermore, small differences in the parameter may be difficult to detect. In such cases, a plurality of substantially identical reliability monitors may be serially connected together to more accurately monitor stress-induced changes, particularly near the end of life.

[0007] Each reliability monitor may include a test circuit having a test device, and a reference circuit having a reference device. Both the test device and the reference device may be substantially equivalent to the on-chip functional device. Each reliability monitor may further include a comparator circuit connected to the test circuit and the reference circuit. Each reliability monitor may operate alternately in stress and test modes when the IC chip power is turned on and the particular reliability monitor is enabled. Specifically, once enabled, the reliability monitor may periodically switch from operating in stress mode to operating in test mode and back again. During each stress mode, the test device may be subjected to stress conditions that simulate the operating conditions of the on-chip functional device, while the reference device remains substantially unstressed. During each test mode, the stress condition may be removed from the test device, and the comparator circuit may compare a specific parameter of the test device (referred to as a test parameter) with the same parameter of the reference device (referred to as a reference parameter), and may output a status signal based on the difference between the test parameter and the reference parameter. Specifically, when the difference between the test parameter and the reference parameter reaches a predetermined threshold amount, the comparator circuit can switch the state signal from one value to another (for example, from low to high, from logical value "0" to "1"), and can further ensure that the state signal remains constant once switched.

[0008] The plurality of serially connected reliability monitors may include at least a first reliability monitor enabled by an enable signal, and a second reliability monitor coupled to the first reliability monitor and enabled only when a status signal output from the first reliability monitor switches a value.

[0009] A reliability monitoring method is also disclosed herein for a functional device on an integrated circuit (IC) chip, and thus for the IC chip. The method may include providing an IC chip, which includes a functional device on a substrate, and one or more reliability monitors for the functional device, as described above with respect to the structural embodiment.

[0010] The method may further include powering on the IC chip, and after powering on the IC chip, enabling the reliability monitor so that the reliability monitor operates alternately in stress and test modes (e.g., so that when the IC chip is powered on, the reliability monitor periodically switches from operating in stress mode to operating in test mode and back again). Operating the reliability monitor in stress mode includes subjecting the test device to a stress condition that simulates the operating conditions of the on-chip functional device, and leaving the reference device unstressed. Operating the reliability monitor in test mode includes removing the stress condition from the test device, comparing a test parameter of the test device with a reference parameter of the reference device, and outputting a status signal based on a difference between the test parameter and the reference parameter. Specifically, when the difference between the test parameter and the reference parameter reaches a predetermined threshold amount, the value of the status signal may be switched (e.g., from low to high, from a logical value "0" to "1"). The method may further include ensuring that the status signal remains constant once switched. This switching of the status signal value will indicate that the on-chip functional device is powered on for a predetermined number of hours (e.g., X power-on hours (POH)).

[0011] Alternatively, the IC chip may include not only a single reliability monitor but also a plurality of substantially equivalent serially connected reliability monitors (e.g., at least a first reliability monitor and a second reliability monitor coupled to the first reliability monitor). In this case, the method may include using an enable signal to enable the first reliability monitor so that the first reliability monitor operates alternately in stress and test modes. Then, when the status signal output from the first reliability monitor switches value, the status signal from the first reliability monitor is used to enable the second reliability monitor so that the second reliability monitor operates alternately in stress and test modes. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present invention will be more clearly understood through the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale, in which:

[0013] Figure 1 is a block diagram illustrating one embodiment of an integrated circuit (IC) chip having (a plurality of) on-chip reliability monitors;

[0014] Figure 2 is a graph showing the threshold voltage shift over time for two different field effect transistors (FETs) having different gate oxide thicknesses;

[0015] Figure 3A is a schematic diagram illustrating an exemplary reliability monitor and includes a sub-diagram of an exemplary test circuit, an exemplary reference circuit, and an exemplary comparator circuit that may be incorporated into the reliability monitor;

[0016] Figure 3B To illustrate a sub-diagram of an exemplary state latch in detail, the exemplary state latch may be incorporated into Figure 3A The comparator circuit of

[0017] Figure 4 for FIG. 3A to FIG. 3B A timing diagram of the reliability monitor shown;

[0018] Figure 5 To illustrate an alternative test circuit, the alternative test circuit may be incorporated into Figure 3A Reliability monitor;

[0019] Figure 6 A schematic diagram illustrating a plurality of serially connected reliability monitors;

[0020] Figure 7 is a graph having dispersion curves illustrating exemplary threshold voltage shifts exhibited by test devices in each of a plurality of cascaded reliability monitors; and

[0021] Figure 8 The figure is a flow chart showing a reliability monitoring method.

[0022] Description of Reference Numerals

[0023] 100 IC chips

[0024] 101 Substrate

[0025] 110 Functional Circuit

[0026] 111 Functional device, on-chip functional device

[0027] 1111~111 n Functional device

[0028] 120,120' test circuit

[0029] 121,121' Test device

[0030] 130 Reference Circuit

[0031] 131 Reference Devices

[0032] 140 Comparator Circuit

[0033] 141 Current Mirror

[0034] 142 Voltage Latch

[0035] 143 Status Latch

[0036] 144 Internal signal generator, signal generator

[0037] 150,1501~150 n Reliability Monitor

[0038] 151 Initial enable signal

[0039] 152,1521~152 n Status signal

[0040] 160 Sequential Circuits

[0041] 161 Clock signal, CLKP clock signal

[0042] 162 Clock signal, STRESSN clock signal

[0043] 163 Clock signal, SETP clock signal

[0044] 164 clock signal, STRESSP clock signal

[0045] 165 Clock signal, channel gate signal

[0046] 166 Clock signal, channel gate signal

[0047] 167,168 Latch signal

[0048] 301 P-type field effect transistor, first PFET

[0049] 302 P-type field effect transistor, second PFET

[0050] 303 P-type field effect transistor, third PFET

[0051] 304 P-type field effect transistor, fourth PFET

[0052] 305 Analog voltage multiplexer, multiplexer

[0053] 306,371~374,401,402 Inverter

[0054] 307 test nodes

[0055] 311,312,354,356,359,361,362,363,364,367 PFET

[0056] 313,314,347,350,353,355,357,358 NFET

[0057] 315,349,352,366,502 P-type channel gate FET

[0058] 316,348,351,365,501 N-type channel gate FET

[0059] 317 Reference Node

[0060] 341 First Branch Road

[0061] 342 Second Branch Road

[0062] 343,345 first node, node

[0063] 344,346 Second Node, Node

[0064] 411~415 Channel Gate FET

[0065] 421 Anti-and Gate

[0066] 802~826 Program

[0067] A, B sensing nodes

[0068] Q,QN output node. DETAILED DESCRIPTION

[0069] As described above, various mechanisms associated with different classes of devices incorporated into integrated circuit (IC) chips (e.g., hot carrier injection, time-dependent dielectric breakdown, negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), etc.) can cause chip performance to degrade over time due to stress conditions (e.g., high temperature and / or high voltage). Generally, to predict how IC chips in a given semiconductor technology will perform over time and in response to high stress conditions, all devices available in the given semiconductor technology are subjected to accelerated voltage and / or temperature stress tests at the wafer level or module level in a laboratory environment, and / or in a test system environment. Then, based on the results of the accelerated stress tests, performance degradation models and end-of-life (EOL) predictions are generated. Generally, to monitor the reliability of IC chips, power-on hours (POH) monitors are used to track the amount of time the chip is powered on, and the POH number is compared to the end-of-life prediction. Unfortunately, the environmental assumptions associated with the selected product samples used to apply the performance degradation models and end-of-life predictions may be different from the actual environmental conditions in other products. For example, the operating temperature, operating voltage, power-on hours (POH), etc. of an IC chip may vary from product to product. Therefore, the resulting performance degradation model and EOL prediction may not be applicable to all products. In this case, tracking POH alone may cause the chip to fail before the predicted EOL (measured in POH), or alternatively, may cause the chip to be scrapped too early.

[0070] In view of the foregoing, a chip-borne reliability monitor and a reliability monitoring method are disclosed herein. The reliability monitor may include a test circuit having a test device, a reference circuit having a reference device, and a comparator circuit connected to the test circuit and the reference circuit. The reliability monitor may operate alternately in stress and test modes, and specifically, may periodically switch from operating in stress mode to operating in test mode and back again. During each stress mode, the test device may be subjected to a stress condition that simulates the operating conditions of the chip-borne functional device, while the reference device remains substantially unstressed. During each test mode, the stress condition may be removed from the test device, and the comparator circuit may compare the parameters of the test device with the same parameters of the reference device, and may output a status signal based on the difference between the parameters. Specifically, when the difference between the parameters reaches a predetermined threshold amount, the comparator circuit may switch the status signal from one value to another, and may ensure that the status signal remains constant once switched. It should be noted that when the parameter in question is known to change at a higher rate in response to applied stresses at the beginning of life and to change at a lower rate in response to applied stresses toward the end of life, and when small differences in the parameter are difficult to detect, multiple reliability monitors can be connected in series to more accurately monitor stress-induced changes near the end of life, as described in more detail below.

[0071] Figure 1 1 is a block diagram illustrating a specific embodiment of an integrated circuit (IC) chip 100. The IC chip 100 may include a substrate 101 and a functional circuit 110 located on the substrate 101. The functional circuit 110 may be, for example, a circuit required for operating a product (e.g., a memory circuit, a processing circuit, etc.). In any case, the functional circuit 110 may include, for example, at least one functional device 111, and may optionally include more than one functional device (e.g., see the functional device 111). 1-n ). Functional device 111 1-n It may be an active device such as a field effect transistor (FET) or any other type of active semiconductor device.

[0072] The IC chip 100 may further include at least one reliability monitor 150 on the same substrate 101, and may optionally include more than one reliability monitor (eg, see reliability monitor 150). 1-n) for a given on-die functional device 111, and thereby for the functional circuit 110 itself. Such a reliability monitor 150 may include a test circuit 120 having a test device 121, a reference circuit 130 having a reference device 131, and a comparator circuit 140 coupled to the test circuit 120 and the reference circuit 130. The reliability monitor 150 may be further configured to impart stress on the test device 121 such that the test device 121 and the given on-die functional device 111 are subjected to substantially the same stress conditions (e.g., temperature and / or voltage bias conditions) in parallel over time, and thus such that the test device 121 and the given on-die functional device 111 are susceptible to the same failure mechanisms (e.g., hot electron injection, time-dependent dielectric breakdown, etc.). The reliability monitor 150 may also be configured to output a status signal 152 (eg, a flag) to indicate whether a performance parameter (eg, saturated drain current, threshold voltage, etc.) of the test device 121 has degraded by a predetermined threshold amount due to a failure mechanism.

[0073] For example, the reliability monitor 150 may be configured to output a status signal 152 that indicates when the saturation drain current of the test device 121 decreases by a predetermined threshold amount and / or when the threshold voltage of the test device 121 increases by a predetermined threshold voltage amount. As will be appreciated by those skilled in the art, the threshold voltage and the saturation drain current are inversely related. That is, as the threshold voltage increases, the saturation drain current generally decreases.

[0074] Specifically, the reliability monitor 150 may be configured to alternately operate in stress and test modes when the IC chip 100 is powered on and the reliability monitor 150 is enabled by an enable signal, and in particular, to periodically switch from operating in the stress mode to operating in the test mode and back again. During each stress mode, the test device 121 may be subjected to a particular stress condition that simulates the operating conditions of the on-chip functional device 111, thereby making the test device 121 susceptible to the same failure mechanism(s) as the on-chip functional device 111. During this stress mode, the reference device 131 remains substantially unstressed. During each test mode, the stress condition may be removed from the test device 121, and the comparator circuit 140 may compare a particular performance parameter of the test device 121 (referred to as a test parameter, such as a saturated drain current or a threshold voltage) with the same performance parameter of the reference device 131 (referred to as a reference parameter), and may output a status signal 152 based on the difference between the test parameter and the reference parameter. That is, when the difference between the test parameter and the reference parameter reaches a predetermined threshold amount, the comparator circuit 140 may switch the state signal 152 from one value to another value (e.g., from low to high, from logic value "0" to "1"). The comparator circuit 140 may be further configured to ensure that the state signal 152 remains constant once switched, and to ensure that when the IC chip 100 is powered off and then powered on again, the state signal 152 will automatically reset to its last maintained value. Therefore, when the IC chip 100 is powered off and then powered on again, the state signal 152 of the reliability monitor 150 will be reset to low (i.e., reset to logic value "0") if it is low when the IC chip 100 is powered off, and will be reset to high (i.e., reset to logic value "1") if it is high when the IC chip 100 is powered off.

[0075] IC chip 100 also includes timing circuit 160 that receives main clock signal 161 (CLKP) and outputs a plurality of additional clock signals (e.g., clock signal 162 (STRESSN) and clock signal 163 (SETP)). Clock signals 161-163 are received by reliability monitor 150 and, in conjunction with a plurality of internally generated signals (e.g., clock signal 164 (STRESSP), clock signal 165 (SENSEP), clock signal 166 (SENSEN), latch signal 167 (SENSEP_D), and latch signal 168 (LATCHP_D)), control the timing of various components of reliability monitor 150, as discussed in more detail below, to cause the reliability to periodically switch to a test mode, with the duration of the test mode being sufficient to allow the state of test device 121 to be captured (i.e., to compare a particular performance parameter of test device 121 to reference device 131), and to cause the reliability monitor to otherwise operate in a stress mode.

[0076] Additionally, it should be noted that the predetermined threshold attenuation amount may be a threshold amount known or expected to occur over a given number of power-on hours (POH) from the beginning of device life (BOL) based on empirical data and / or simulation data. Thus, such a value switch in the status signal 152 will indicate that the on-chip functional device is powered on for the given number of hours (e.g., X power-on hours (POH)).

[0077] For example, the predetermined threshold degradation amount may be the amount of degradation that is expected to be exhibited by the on-chip functional device 111 upon reaching a POH number specified in an end-of-life (EOL) prediction, which triggers the value of the status signal 152 to switch from low to high. In this case, only a single reliability monitor 150 is required on the IC chip 100, and the status signal 152 (i.e., flag) will indicate whether the predicted EOL has been reached, and therefore whether the functional circuit 110 should be considered reliable.

[0078] However, the performance parameter in question (e.g., saturated drain current, threshold voltage, etc.) will often change at a higher rate in response to an applied stress at BOL, but will change at a lower rate in response to the same stress applied toward EOL. Furthermore, small differences in performance parameters toward EOL can be difficult to detect. For example, FIG. 2 is a graph showing threshold voltage shift over time for two different field effect transistors (FETs), one FET having a first gate oxide thickness (e.g., 16 nm) and the other FET having a second gate oxide thickness (e.g., 200 nm), the two FETs being subjected to identical operating conditions (e.g., 100° C. and 0.95 Vgs) from BOL to EOL. As shown, the two FETs exhibit a substantial increase in threshold voltage within the first 20,000 POHs due to a failure mechanism (e.g., due to negative bias temperature instability (NBTI)), but the rate of change decreases significantly over time. One of ordinary skill in the art will recognize that threshold voltage shift and saturated drain current shift are generally inversely related.

[0079] In this case (ie, when the EOL parameter shift is small and difficult to detect), multiple substantially identical reliability monitors 150 1-nThe cascaded reliability monitors may be connected together to more accurately monitor stress-induced changes, especially those near EOL. For example, the cascaded reliability monitors may include a first reliability monitor 1501 that is enabled by the initial enable signal 151 and monitors a given die-borne functional device 111 during the initial X POHs of the IC chip 100, and a second reliability monitor 1502 that is enabled by the status signal 1521 only after the initial X POHs have been reached and monitors the given die-borne functional device 111 within the next X POHs of the IC chip 100, and so on. With this configuration, the cascaded reliability monitor 1501 may be connected together to more accurately monitor stress-induced changes, especially those near EOL. For example, the cascaded reliability monitors may include a first reliability monitor 1501 that is enabled by the initial enable signal 151 and monitors a given die-borne functional device 111 during the initial X POHs of the IC chip 100, and a second reliability monitor 1502 that is enabled by the status signal 1521 only after the initial X POHs have been reached and monitors the given die-borne functional device 111 within the next X POHs of the IC chip 100, and so on. With this configuration, when the performance parameters of the die-borne functional device 111 are about to change significantly, the cascaded reliability monitor 150 1-n The first reliability monitor 1501 in the IC chip 100 will monitor the performance parameters of the corresponding test device during the initial X POH period; and when the performance parameters of the on-chip functional device 111 will only show a small change, the serial reliability monitor 150 1-n The last reliability monitor 150 n Another test device will monitor the performance parameters within the last X POH of IC chip 100. However, since the last reliability monitor 150 n The test device 121 in FIG. 1 is subjected to stress conditions only during the last X POHs of the IC chip 100, so it will exhibit larger performance parameter variations. n Such a large performance parameter change of the test device 121 can be easily detected and will occur in parallel with the smaller performance parameter change of the on-chip functional device 111 near its EOL. 1-n The last reliability monitor 150 n Status signal 152 n When the PWM signal (ie, flag) switches value (eg, from low to high, from logic value "0" to "1"), the functional circuit 110 is considered no longer reliable and the IC chip 100 is considered to have reached EOL.

[0080] Figure 3A FIG. 1 is a schematic diagram illustrating an exemplary reliability monitor 150 , and includes a sub-diagram of an exemplary test circuit 120 , an exemplary reference circuit 130 , and an exemplary comparator circuit 140 that may be incorporated into the reliability monitor 150 . Figure 3B To illustrate the exemplary state latch 143 in detail, the exemplary state latch 143 may be incorporated into Figure 3A The comparator circuit 140 is provided. Figure 3A and Figure 3B It also refers to the recognition of various signals used to control the test circuit 120, the reference circuit 130 and the comparator circuit 140.

[0081] For illustration, a given on-chip functional device 111 to be monitored by the reliability monitor 150 may be an N-type field effect transistor (NFET) (e.g., a current source). During operation of the IC chip, the NFET may be subjected to certain stress conditions (e.g., certain temperature and / or voltage bias conditions), and these certain stress conditions may make the functional device susceptible to certain failure mechanisms, namely, hot electron injection induced saturated drain current decay.

[0082] The exemplary test circuit 120 includes a test device 121 that is a NFET that is substantially identical to the functional device to be monitored. Furthermore, the exemplary test circuit 120 may be configured to impart specific stress conditions on the test device 121 over time, and, more specifically, when the reliability monitor 150 is enabled and operating in a stress mode. These stress conditions may be substantially the same as those encountered in parallel by the functional device 111, such that the test device 121 is similarly susceptible to hot electron injection induced saturated drain current decay. The test circuit 120 may be further configured to remove the stress conditions when the reliability monitor 150 periodically switches operation to a test mode to allow the test device 121 to be tested. More specifically, the exemplary test circuit 120 may further include a plurality of P-type field effect transistors (PFETs) 301 to 304; an analog voltage multiplexer 305; and an inverter 306. The source of the test device 121 may be electrically connected to ground, and the drain of the test device 121 may be electrically connected to the drains of the first PFET 301 and the second PFET 302 (also referred to herein as a pass-gate device). In addition, the source of the second PFET 302 may be electrically connected to the drain of the third PFET 303 (also referred to herein as a precharge device), and to the drain of the fourth PFET 304. The sources of the first PFET 301, the third PFET 303, and the fourth PFET 304 may be electrically connected to a first supply voltage (e.g., VDD). The gate of the test device 121 may be selectively connected to a second supply voltage (stress voltage (VSTRESS)) or a third supply voltage (read voltage (VREAD)) through a multiplexer 305. It should be noted that VSTRESS may be high enough to put the test device 121 in a high stress or overdrive condition (e.g., up to 0.55V) during the stress mode, while VREAD may be lower than VSTRESS so that the high stress condition is removed from the test device 121 during the test mode. The gates of the first PFET 301 and the third PFET 303 may be controlled by the STRESSN clock signal 162 output from the timing circuit 160. The inverter 306 may receive and invert the STRESSN clock signal 162, and output an inverted clock signal 164 (STRESSP) that controls the gate of the second PFET 302.

[0083] The timing circuit 160 may be configured to cause the STRESSN clock signal 162 to generally have a low value that causes the reliability monitor 150 to operate in the stress mode, and further cause it to periodically (i.e., at some desired interval) switch to a high value and remain high only for some short duration sufficient to allow the state of the test device 121 to be captured (i.e., sufficient to compare a particular performance parameter of the test device 121 with the reference device 131). Since the STRESSP clock signal 164 is inverted compared to the STRESSN clock signal 162, during the stress mode, the STRESSP clock signal 164 will be high and the STRESSN clock signal 162 will be low; and during the test mode, the STRESSP clock signal 164 will be low and the STRESSN clock signal 162 will be high.

[0084] Within the test circuit 120, the timing of the multiplexer 305 and the third PFET 303 (pre-charge device) may be such that during the stress mode, the test node 307 (DUTI) of the test circuit 120 at the drains of the third PFET 303 and the fourth PFET 304, and at the source of the second PFET 302 may be maintained at the first supply voltage (VDD), and the test device 121 may be biased at VSTRESS (e.g., 0.55V) on its gate and at about 0.8V at the drain to source to emulate the biasing conditions of the on-chip functional device 111. During the test mode, the aforementioned high stress condition may be turned off, specifically, the third PFET 303 (i.e., pre-charge device) may be turned off, VREAD may be applied to the gate of the test device 121, and the current at the drain of the test device 121 may be coupled to the test node 307 (DUTI) of the test circuit 120 through the second PFET 302 (pass-gate device).

[0085] like Figure 3AAs shown, the reference device 131 of the reference circuit 130 is also an NFET, which is substantially equivalent to the functional device 111 in question, and is therefore also substantially equivalent to the test device 121. The reference circuit 130 may be further configured to make the reference device 131 less susceptible to hot electron injection induced saturated drain current decay. For example, in addition to the reference device 131, the reference circuit 130 may further include a PFET 311 (also referred to herein as a precharge device), another PFET 312 (also referred to herein as a pass gate device), and an NFET 313 electrically connected in series between a first supply voltage (VDD) and ground. The reference circuit 130 may also include a reference node 317 (REFI) at the interface between the PFET 311 and the PFET 312. The gate of the PFET 311 may be controlled by the STRESSN clock signal 162, and the gates of the PFET 312 and the NFET 313 may be controlled by the STRESSP clock signal 164. The source of the reference device 131 may be electrically connected to ground, and the drain of the reference device 131 may be electrically connected to the node at the drains of the PFET 312 and the NFET 313. The reference circuit 130 may further include a multiplexer and another NFET 314. The gate of the reference device 131 may be electrically connected to the drain of the NFET 314. The source of the NFET 314 may be electrically connected to ground, and the gate of the NFET 314 may be controlled by the STRESSP clock signal 164. The gate of the reference device 131 may be further selectively connected to a fourth supply voltage (VREAD+ΔV) through the multiplexer, which includes coupled P-type and N-type pass-gate FETs 315-316 controlled by the STRESSN clock signal 162 and the STRESSP clock signal 164, respectively. The fourth supply voltage may be equal to the third supply voltage (VREAD) plus a voltage increase factor. The voltage increase factor may correspond to a change in current (ΔI) known or expected to occur at the drain of test device 121 when the saturated drain current decays by a predetermined threshold amount, thereby indicating that a given number of power-on hours (POH) has elapsed.

[0086] During the test mode, control of the gate of test device 121 at a third supply voltage (VREAD) and of reference device 131 at a fourth supply voltage equal to the third supply voltage plus a voltage increase factor (VREAD+ΔV) ensures that status signal 152 will stay low until the device in test device 121 decays sufficiently to reduce its drain current below the drain current of reference device 131. When the drain current of test device 121 becomes less than the drain current of reference device 131, status signal 152 will switch high to indicate that a given number of power-on hours (POH) has elapsed.

[0087] As described above, during the stress mode, the STRESSP clock signal 164 will be high and the STRESSN clock signal 162 will be low, while during the test mode, the STRESSP clock signal 164 will be low and the STRESSN clock signal 162 will be high. Therefore, during the stress mode, the reference node 317 (REFI) of the reference circuit 130 will be precharged to the first supply voltage (VDD) through the PFET 311 (precharge device), and the reference device 131 will have a 0 volt bias on the gate and, therefore, will not be stressed. As a result, the reference device 131 will maintain its inherent strength throughout the life of the IC chip 100. During the test mode, VREAD+ΔV will be applied to the gate of the reference device 131 through the adjacent multiplexer, and the current at the drain of the reference device 131 will be coupled to the reference node 317 of the reference circuit 130 through the PFET 312 (pass gate device).

[0088] The comparator circuit 140 may include: a current mirror with hysteresis 141 (also referred to herein as current sensing with hysteresis); a voltage latch 142 ; a state latch 143 ; and an internal signal generator 144 .

[0089] Specifically, the current mirror 141 may be a series-connected mirror circuit, which includes a first branch 341 and a second branch 342, each of which is connected to the ground at one end and connected to the first supply voltage (VDD) at the opposite end through an N-type field effect transistor (NFET) 358 (i.e., a pin device). The first branch 341 may include two p-type field effect transistors (PFETs) 361 to 362 and an NFET 347 (also referred to as a current source herein) connected in series between the first supply voltage (VDD) and the NFET 358. The second branch 342 may similarly include two PFETs 363 to 364 and an NFET 350 (also referred to as a current source herein) connected in series between the first supply voltage (VDD) and the NFET 358. The gates of the NFETs 347 and 350 (i.e., the gates of the current sources at the bottom of each branch) may be electrically connected to a fifth supply voltage (bias gate voltage (VBIAS)). The first branch 341 may include a pair of first nodes 343 and 345. 361-362 and can be coupled to the test node 307 of the test circuit 120. Another first node 345 (MIRROR) can be located at a junction between the PFET 362 and the NFET 347 and, as discussed in more detail below, can be coupled to the voltage latch 142. The second branch 342 can have a pair of second nodes 344 and 346. One second node 344 can be located at a junction between the PFETs 363-364 and can be coupled to the reference circuit 130 at the reference node 317 of the reference circuit 130. Another second node 346 (OUT) can be located at a junction between the PFET 364 and the NFET 350 and, as discussed in more detail below, can be coupled to the voltage latch 142. The gates of PFETs 361-364 and the first node 345 (MIRROR) of the first branch 341 can all be biased in the same manner during different modes by a current source (e.g., PFET 367), which is coupled to the gates of PFETs 361-364 and coupled to the output node 345 through an adjacent multiplexer (e.g., through coupled N-type and P-type channel gate FETs 365-366).

[0090] The voltage latch 142 may be a voltage sense amplifier including a pair of cross-coupled inverters. The cross-coupled inverters may include a first inverter (PFET 354 connected in series with NFET 353) and a second inverter (PFET 356 connected in series with NFET 355). Each inverter may be electrically connected to a first supply voltage (VDD) at one end through PFET 359 and to ground at an opposite end through NFET 357. A sense node A at the interface between PFET 354 and NFET 353 of the first inverter may control the gates of PFET 356 and NFET 355 in the second inverter, and may be further electrically connected to a first node 345 (MIRROR) of a first branch 341 of the current mirror 141 through an adjacent multiplexer (e.g., through coupled N-type and P-type pass-gate FETs 348 to 349). Another sensing node B at the interface between the PFET 356 and the NFET 355 of the second inverter can control the gates of the PFET 354 and the NFET 353 of the first inverter, and can be electrically connected to the second node 346 (OUT) of the second branch 342 of the current mirror 141 through an adjacent multiplexer (for example, through coupled N-type and P-type channel gate FETs 351 to 352).

[0091] The state latch 143 may be a sample-and-hold latch coupled to the sensing node A and the sensing node B of the voltage latch 142 . Figure 3B To illustrate an exemplary state latch 143, the exemplary state latch 143 may be incorporated into the comparator circuit 140. As shown, the state latch 143 includes a tri-state inverter, which is a latch formed by inverters 401 and 402 and pass-gate FETs 411-415.

[0092] As described above, during the stress mode, the STRESSP clock signal 164 will be high and the STRESSN clock signal 162 will be low; and during the test mode, the STRESSP clock signal 164 will be low and the STRESSN clock signal 162 will be high.

[0093] Thus, during stress conditions, NFET 358 (leg device) of current mirror 141 may be cut off so that the internal node floats to VDD or slightly below VDD. However, during test mode, NFETs 347 and 350 (current sources) at the bottom of the first branch 341 and the second branch 342 of current mirror 141 will be biased at a biased gate voltage (VBIAS) respectively to provide a small current through PFETs 361-362 in the first branch 341 of current mirror 141 and through PFETs 363-364 in the second branch 342 of current mirror 141. As a result, a test current will flow through PFET 361 of the first branch 341 and node 343 and into test circuit 120 to the drain of test device 121. The first branch 341 of current mirror 141 will sense this test current and will output an analog test voltage at node 345 (MIRROR). Additionally, the reference current will flow through PFET 363 of second branch 342 and node 344, and into reference circuit 130 to the drain of reference device 131. Second branch 342 of current mirror 141 will sense the reference current and output an analog reference voltage at node 346 (OUT).

[0094] During the test mode, the voltage latch 142 senses the analog test voltage at the node 345 (MIRROR) and the analog reference voltage at the node 346 (OUT), and further converts the analog test voltage into a digital test voltage at the sensing node A, and converts the analog reference voltage into a digital reference voltage at the sensing node B. More specifically, the SETP clock signal 163 (which is outputted by the timing circuit 160 like the STRESSN clock signal 162) can control the NFET 357, and can further be provided as an input to the signal generator 144, which includes a plurality of inverters 371 to 374 connected in series for internally generating the following signals: a channel gate signal 165 (SENSEP), a channel gate signal 166 (SENSEN), a latch signal 167 (SENSEP_D), and a latch signal 168 (LATCHP_D), in sequence. The timing circuit 160 may be further configured to ensure that the SETP clock signal 163 will go high within a short interval after the STRESSN clock signal 162 goes high, and thus after the reliability monitor has entered the test mode. This causes the analog test voltage on the node 345 (MIRROR) of the first branch 341 of the current mirror 141 and the analog reference voltage on the node 346 (OUT) of the second branch 342 of the current mirror 141 to be respectively transmitted to the sensing nodes A and B of the voltage latch 142. Upon issuing the latch signals SENSEP_D and LATCHP_D 167-168, the voltage latch 142 latches the voltage difference between A and B to low or high (i.e., logic value "0" or "1").

[0095] In addition, during the test mode, the states of the sensing nodes A and B of the voltage latch 142 are transferred to the state latch 143. The state latch 143 senses the digital test voltage and the digital reference voltage on the sensing nodes A and B, respectively, and outputs a state signal based on the difference between these voltages. Figure 3B , the enable signal (ENABLEP) initializes the latch so that the output node Q is low, and thus the state signal 152 is low (i.e., at a logic value of "0") shortly after power is turned on and before a full cycle of the CLKP clock signal 161 occurs. When the CLKP clock signal 161 goes low, the voltage levels on the sense nodes A and B are latched. The state latch 143 is further configured with a clock suppression logic so that once the test device 121 is weakened to the point where the state latch 143 detects a low at the sense node B and a high at the sense node A, further clock signals are isolated to maintain the latched state in which the output node Q goes high (i.e., becomes a logic value of "1") and the state signal 152 (flag) also switches from low to high (i.e., switches from a logic value of "0" to a logic value of "1"), thereby indicating that the test device 121 has been subjected to stress long enough to show attenuation. In addition, when the output node Q goes high, the output node QN will go low. This latches the NAND gate 421 so that its output is low (ie, logic value "0") and keeps the clock signal CLKP low (ie, at logic value "0") to prevent further changes in the state latch state.

[0096] Furthermore, when the output node Q goes high, the hysteresis function of the current mirror 141 is enabled. Specifically, once the output node Q switches from low to high, and thus when the status signal 152 has also switched value from low to high, the hysteresis is activated. The hysteresis changes the balance within the current mirror 141 to facilitate sensing of the difference in saturated drain current between the test device 121 and the reference device 131 being above a predetermined threshold amount. In this way, noise is prevented from causing the analog test voltage and the analog reference voltage at nodes 345 and 346 of the current mirror 141 to chatter and short-term pulse waveform interference at the beginning of the test mode, respectively. The hysteresis continues to provide such noise immunity to ensure that the status signal 152 (flag) remains high as long as the IC chip 100 is powered on. Furthermore, the state of the status signal 152 will be maintained even if the power is cycled (that is, even if the supply VDD is removed from the circuit system and then restored). That is, when the IC chip is powered off and then powered on again, the state of the state signal 152 (flag) output by the state latch 143 will be reset to its last held state.

[0097] Figure 4 As an exemplary timing diagram, it depicts the timing of some signals, as described above, these signals control FIG. 3A to FIG. 3B The operation of the reliability monitor 150 is shown.

[0098] When IC chip 100 is powered on, initial enable signal 151 may be automatically set high (i.e., at a logic value of "1"). This enable signal ENABLEP enables the comparator circuit system and, in particular, allows reliability monitor 150 to periodically switch from operating in a stress mode to operating in a test mode and back again.

[0099] As described above, the timing circuit 160 may receive the CLKP clock signal 161 and, based on the CLKP clock signal 161, may output the STRESSN clock signal 162 and the SETP clock signal 163. These three clock signals 161 to 163 may be received by the reliability monitor 150 and, in conjunction with a number of internally generated signals (e.g., signals 164 to 168), control the timing of the various components 120, 130, and 140 of the reliability monitor 150 so that the operation is periodically switched to a test mode, with the duration of the test mode being sufficient to allow the state of the test device 121 to be captured (i.e., to compare a specific performance parameter of the test device 121 with that of the reference device 131), and to cause the reliability monitor 150 to operate in a stress mode in another manner.

[0100] The CLKP clock signal 161 may be a spontaneous clock signal oscillating at a desired frequency. The timing circuit 160 may include an N-bit counter and control logic. The N-bit counter may be set to shift the frequency of the CLKP clock signal 161 to a desired interval to be used for periodically testing the test device 121 (i.e., periodically switching the operation of the reliability monitor 150 from the stress mode to the test mode and back again). For example, for a 1 GHz clock (i.e., a 1 ns clock period), it may be desirable to test the test device 121 once every 1 us. In this case, the N-bit counter may be set to 1000 so that the reliability monitor switches from the stress mode to the test mode each time the counter decrements to 0 after 1000 clock pulses (1000*1 ns=1 us). When the counter reaches 0 (i.e., when COUNTER=0), the control logic will cause the STRESSN clock signal 162 to go high. This in turn will cause the STRESSP clock signal 164 to go low (i.e., to a logic value of "0"), and thereby cause the reliability monitor 150 to enter a test mode during which the high stress condition is removed from the test device 121 and a parameter comparison of the test device 121 with the reference device 131 is initiated. The control logic may further cause the SETP clock signal 163 to go high for a short interval after the STRESSN clock signal 162 goes high, and to go low again before the STRESSN clock signal 162 goes back low. The high SETP clock signal will cause the comparator circuit 140 to latch the differential current between the test device 121 and the reference device 131, and output a status signal 152 (flag). If the difference in the parameter in question (e.g., saturated drain current) between the test device 121 and the reference device 131 is below a predetermined threshold amount, the status signal 152 will remain low (see the left side of the timing diagram); however, when the difference becomes greater than the predetermined threshold amount, the status signal will switch from low to high (see the right side of the timing diagram).

[0101] It should be noted that the above FIG. 3A to FIG. 3B The exemplary circuit system shown is not intended to be limiting. For example, the reliability monitor 150 can be configured to have different test circuits 120', such as Figure 5 As shown, in order to monitor different on-chip functional devices (e.g., different NFETs) that are subjected to different stress conditions that make the functional devices susceptible to different failure mechanisms such as forward bias temperature instability (PBTI) hot electron injection induced saturated drain current decay. In this case, the exemplary test circuit 120' will replace Figure 3A1 . The test circuit 120' includes a test device 121', which is a NFET substantially identical to the functional device to be monitored. As with the test circuit 120 described above, the exemplary test circuit 120' may be configured to impart specific stress conditions on the test device 121' over time, and, in particular, when the reliability monitor 150 is enabled and operating in a stress mode. These stress conditions may be substantially the same as those encountered in parallel by the functional device 111, such that the test device 121' is similarly susceptible to PBTI. In particular, during the stress mode, the test device 121' may be reverse biased and susceptible to PBTI. A multiplexer, and in particular coupled N-type and P-type pass-gate FETs 501-502, respectively controlled by clock signals STRESSN and STRESSP, may be connected to the gate of the test device 121. During the test mode, the multiplexer may apply a gate voltage VREAD to the gate of the test device 121 ′, thereby biasing the device 121 ′ in the saturation region for testing, and in particular, for comparison with the reference device 131 .

[0102] As mentioned above, and as Figure 1 As shown, a single reliability monitor 150 may be used on the IC chip 100, with a status signal 152 (ie, a flag) indicating whether the predicted EOL has been reached. Alternatively, however, when the EOL parameter shift is small and difficult to detect, multiple substantially identical reliability monitors 150 may be used. 1-n Can be connected in series to more accurately monitor stress-induced changes, especially near the EOL.

[0103] Figure 6 To illustrate three such serially connected reliability monitors 150 in more detail 1-3 As shown in the figure, the serial reliability monitor 150 1-3 The first reliability monitor 1501 is enabled by the initial enable signal 151ENABLEP when the ENABLEP signal goes high. When the first reliability monitor 1501 is enabled, the CLKP, STRESSN and SETP signals cause the first reliability monitor 1501 to periodically switch between stress and test modes and output a status signal 1521, which eventually switches from low to high, indicating that the initial X POH (e.g., 10,000 POH) has been reached. 1-3Further included is a second reliability monitor 1502 that receives a status signal 1521 from the first reliability monitor 1501 and is enabled only when the status signal 1521 has gone high. In other words, the status signal 1521 acts as an enable signal ENABLEP for the second reliability monitor 1502. When the second reliability monitor 1502 is enabled, the CLKP, STRESSN, and SETP signals cause the second reliability monitor 1502 to periodically switch between stress and test modes and output a status signal 1522 that eventually switches from low to high, indicating that 2X POH (e.g., 20,000 POH) has been reached. The serial reliability monitor 150 1-3 Further included is a third reliability monitor 1503 that receives a status signal 1522 from the second reliability monitor 1502 and is enabled only when the status signal 1522 has gone high. In other words, the status signal 1523 acts as an enable signal ENABLEP for the third reliability monitor 1503. When the third reliability monitor 1503 is enabled, the CLKP, STRESSN and SETP signals cause the third reliability monitor 1503 to periodically switch operation between the stress mode and the test mode and output the status signal 1523, which eventually switches from low to high, indicating that 3X POH (e.g., 30,000 POH) of the IC chip 100 has been reached and the EOL is predicted. See also Figure 4 and the above detailed discussion of the various signal values ​​required to cause the reliability monitor operation to switch from stress mode to test mode and back again.

[0104] Figure 7 is a graph having discrete curves, which depict the series-connected reliability monitor 150 1-3 The threshold voltage shift exhibited by the test device in each. These curves show that the threshold voltage shift does not occur after a given reliability monitor is enabled, and show that the threshold voltage shift is initially large in each case, but the rate of change drops sharply after about 20,000 POH. Figure 6 In the configuration shown, since the test device in the third reliability monitor 1503 is subjected to stress conditions only during the last X POHs of the IC chip 100, it will exhibit large performance parameter changes. Such large changes can be easily detected and will occur in parallel with smaller performance parameter changes of the on-chip functional device in question near its EOL. Therefore, only when the status signal 1523 switches value (e.g., from low to high, from logic value "0" to "1"), the functional circuit is considered no longer reliable and the IC chip 100 is considered to have reached EOL.

[0105] This article also discloses a reliability monitoring method for a functional device on an integrated circuit (IC) chip and thus for the IC chip. Figures 1 to 7 See also Figure 8 The method may include providing an IC chip 100, which includes a functional device 111 on a substrate 101, one or more reliability monitors 150 for the functional device 111, and 1-3 , and for reliability monitor 150 1-3 The timing circuit 160 controls the timing of each component, as discussed in detail above with respect to the specific embodiment of the structure.

[0106] The method may further include powering on the IC chip 100 (see procedure 802), and after powering on the IC chip 100, enabling the reliability monitor 150 and using a clock signal to control the reliability monitor 150 so that the reliability monitor operates alternately in stress and test modes (i.e., so that when the IC chip is powered on, the reliability monitor 150 periodically switches from operating in the stress mode to operating in the test mode and back again) (see procedure 804). Operating the reliability monitor 150 in the stress mode (see procedure 808) includes subjecting the test device 121 of the test circuit 120 of the reliability monitor 150 to stress conditions that simulate the operating conditions of a given on-chip functional device 111. For example, in one embodiment, the functional device 111, and the test device 121 of the exemplary test circuit 120 (see Figure 3A ) can be substantially equivalent to an NFET, the functional device 111 can be susceptible to hot electron injection induced saturation drain current decay, and during the stress mode, the stress condition biases the test device 121 so that it is similarly susceptible to hot electron injection induced saturation drain current decay. In another embodiment, the functional device 111 and the test device 121 'of the exemplary test circuit 120 ' (see Figure 5 ) may also be substantially identical NFETs; however, in this case, functional device 111 may be susceptible to forward bias temperature instability (PBTI), and the stress condition reverse biases test device 121' so that the test device is similarly susceptible to PBTI. It should be noted that during the stress mode, reference device 131 of reference circuit 130 of reliability monitor 150 remains unstressed. In any case, reliability monitor 150 may continue to operate in stress mode for some regular interval, which is set by timing circuit 160, and in particular, is set by decrementing a counter based on a clock cycle (see procedure 810). As long as the counter is still counting down (i.e., has not reached 0), the reliability monitor may continue to operate in stress mode (see procedure 812).

[0107] Once the counter counts down to zero, it can be reset (see process 814), and the operation of the reliability monitor can be switched to a test mode (see process 816). Operating the reliability monitor in the test mode at process 816 includes removing the stress condition from the test device 121, comparing the test parameters of the test device 121 with the reference parameters of the reference device 131 (see process 818), and outputting the status signal 152 based on the difference between the test parameters and the reference parameters. The process 818 of comparing the test parameters of the test device 121 with the reference parameters of the reference device 131 may include, for example: generating an analog test voltage based on the test current flowing to the test device 121, and generating an analog reference voltage based on the reference current flowing to the reference device 131; converting the analog test voltage into a digital test voltage, and converting the analog reference voltage into a digital reference voltage; and maintaining the value of the status signal 152 low when the digital test voltage is the same as the digital reference voltage, or switching the value of the status signal 152 high when the digital test voltage is different from the digital reference voltage. Specifically, a finding at step 818 that the digital test voltage is the same as the digital reference voltage indicates that the difference between the test parameter and the reference parameter is less than a predetermined threshold amount. Therefore, the value of the status signal 152 will remain low, and operation of the reliability monitor 150 in the stress mode may be restarted at step 808. However, a finding at step 818 that the digital test voltage is different from the digital reference voltage indicates that the difference between the test parameter and the reference parameter is greater than a predetermined threshold amount at step 818. Therefore, the value of the status signal 152 is switched (e.g., from low to high), thereby setting a flag for the reliability monitor 150 (see step 820). At step 820, the method may further include ensuring that this status signal 152 remains constant once it is switched high. This switching of the value of the status signal 152 will indicate that the power on the chip functional device 111 is turned on for a predetermined number of hours (e.g., X power-on hours (POH)).

[0108] If this is the only reliability monitor on IC chip 100, then the IC chip can be determined to be at EOL (see procedures 822 and 826). Figure 1 and 6 As shown, the IC chip 100 includes a plurality of serially connected reliability monitors 150 1-3 (eg, at least the first reliability monitor 1501, the second reliability monitor 1502 coupled to the first reliability monitor 1501, and so on), and if all flags of all reliability monitors are not set, the serial reliability monitor 150 may be initiated. 1-3822 and 824). In this case, the method may include using the initial enable signal 151 to enable the first reliability monitor 1501 so that the first reliability monitor 1501 operates alternately in the stress and test modes. The method may further include using the status signal 1521 output by the first reliability monitor 1501 to enable the second reliability monitor 1502. That is, the method may include: when the status signal 1521 output from the first reliability monitor 1501 switches its value, automatically enabling the second reliability monitor 1502 so that the second reliability monitor 1502 operates alternately in the stress and test modes. In this case, the switching of the value of the status signal 1521 output by the first reliability monitor 1501 (e.g., switching from low to high, from 0 to 1) will indicate that the power of the on-chip functional device is turned on for a predetermined number of hours (e.g., X power-on hours (POH)). A subsequent switch in the value of the status signal 1522 output by the second reliability monitor 1502 (e.g., from low to high, from 0 to 1) will indicate that the on-chip functional device is powered on for another X power-on hours (POH) (i.e., 2X power-on hours). Alternatively, the method may further include using the status signal 1522 output by the second reliability monitor 1502 to enable the third reliability monitor 1503. That is, the method may further include: automatically enabling the third reliability monitor 1503 when the status signal 1522 output from the second reliability monitor 1502 switches value, so that the third reliability monitor 1503 operates alternately in the stress and test modes. A subsequent switch in the value of the status signal 1523 output by the third reliability monitor 1503 (e.g., from low to high, from 0 to 1) will indicate that the on-chip functional device is powered on for another X power-on hours (POH) (i.e., 3X power-on hours). In this case, the determination that the IC chip is at EOL is made at process 826 only if process 822 determines that all flags of all reliability monitors in the reliability monitor cascade have been set.

[0109] It should be understood that the terms used herein are for the purpose of illustrating the disclosed structures and methods, and are not intended to be limiting. For example, the singular "a" (and its variations) and "the" when used herein are intended to include the plural form as well, unless the content clearly indicates otherwise. In addition, when the words "include" and / or "include" (and its variations) are used herein, they indicate the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. Furthermore, terms such as "right", "left", "vertical", "horizontal", "top", "bottom", "up", "down", "below", "below", "lower layer", "above", "upper layer", "parallel", "vertical" and the like are intended to illustrate the relative positions of these terms when they are oriented and depicted in the drawings (unless otherwise indicated), and terms such as "touching", "directly in contact", "adjacent", "directly adjacent to", "closely adjacent to" and the like are intended to indicate that at least one element physically contacts another element (these elements are not separated by other elements). As the elements are oriented and illustrated in the drawings, the term "laterally" is used herein to describe the relative position of elements, and more particularly, to indicate that an element is placed to the side of another element, as opposed to above or below the other element. For example, an element disposed laterally adjacent to another element will be located next to the other element, an element disposed laterally immediately adjacent to another element will be located directly next to the other element, and an element laterally surrounding another element will be adjacent to and bordering the outer sidewall of the other element. All means or steps in the claims below plus corresponding structures, materials, actions, and equivalents of functional elements are intended to include any structure, material, or action used to perform the function in conjunction with other claimed elements as specifically claimed.

[0110] The various embodiments of the present invention have been described for purposes of illustration, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, their practical applications, or technical improvements over existing technologies in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. An integrated circuit (IC), comprising: an electronic circuit including a plurality of electronic components; as well as reliability monitoring circuitry configured to evaluate, during operation of the integrated circuit in a host system, one or more parameters indicative of reliability of one or more on-chip functional devices selected from the plurality of electronic components that are affected by temperature and voltage induced stresses during operation of the integrated circuit, and to provide an output indicative of the reliability, wherein the integrated circuit further comprises a test device and a reference device configured to emulate functional devices of the one or more on-chip functional devices, and wherein the reliability monitoring circuit is coupled to the test device and the reference device and configured to evaluate one or more parameters on the test device and the reference device, And wherein, the reliability monitoring circuit is configured as follows: subjecting the test device to a stress condition that emulates a stress condition of the functional device without subjecting the reference device to the stress condition; comparing a first parameter of the one or more parameters evaluated on the test device with a second parameter of the one or more parameters evaluated on the reference device; and The output is provided based on the comparison.

2. The integrated circuit according to claim 1, wherein: At least one of the die-borne functional devices includes a field effect transistor (FET), and wherein the reliability monitoring circuit is configured to evaluate one or both of the following for the field effect transistor: (i) a drain side saturation current and (ii) a threshold voltage.

3. The integrated circuit according to claim 1, wherein: The reliability monitoring circuit assembly is configured to generate an alarm in response to the reliability violating a predetermined condition.

4. The integrated circuit according to claim 1, wherein: The one or more die-borne functional devices include active semiconductor devices.

5. The integrated circuit according to claim 1, wherein: The output indicates the power-on hours of the one or more on-chip functional devices.

6. The integrated circuit of claim 1, wherein: The output indicates end of life of the one or more on-die functional devices.

7. The integrated circuit according to claim 1, wherein: The reliability monitoring circuit is composed of: evaluating a first parameter of the one or more parameters on the test device during a first hour of operation of the one or more on-die functional devices; evaluating a second parameter of the one or more parameters on the reference device during a second hour of operation of the one or more on-chip functional devices after the first hour; as well as A second output is provided based on the first parameter and the second parameter, the second output indicating end of life of the one or more on-die functional devices.

8. The integrated circuit of claim 1, wherein: A plurality of the test devices and reference devices emulating the same on-chip functional device are connected in series, and wherein the reliability monitoring circuit assembly is configured to evaluate the one or more parameters of the same on-chip functional device based on corresponding parameters evaluated on the plurality of the test devices and reference devices.

9. A method for reliability monitoring in an integrated circuit (IC) comprising a plurality of electronic components, the method comprising: evaluating, using a reliability monitoring circuit in the integrated circuit, one or more parameters during operation of the integrated circuit in a host system, the one or more parameters indicative of reliability of one or more on-chip functional devices selected from the plurality of electronic components that are affected by temperature and voltage induced stresses during operation of the integrated circuit; providing an output indicative of the reliability, wherein evaluating the one or more parameters comprises evaluating the one or more parameters on a test device and a reference device in the integrated circuit, the test device and the reference device being configured to emulate functional devices of the one or more on-die functional devices; subjecting the test device to a stress condition that emulates a stress condition of the functional device without subjecting the reference device to the stress condition; comparing a first parameter of the one or more parameters evaluated on the test device with a second parameter of the one or more parameters evaluated on the reference device; and The output is provided based on the comparison.

10. The method of claim 9, further comprising issuing an alarm in response to the reliability violating a predetermined condition.

11. The method according to claim 9, wherein: The one or more die-borne functional devices include active semiconductor devices.

12. The method according to claim 9, wherein: The output indicates at least one of power-on hours and end of life of the one or more on-chip functional devices.

13. The method according to claim 9, further comprising: evaluating a first parameter of the one or more parameters on the test device during a first hour of operation of the one or more on-die functional devices; evaluating a second parameter of the one or more parameters on the reference device during a second hour of operation of the one or more on-chip functional devices after the first hour; as well as A second output is provided based on the first parameter and the second parameter, the second output indicating end of life of the one or more on-die functional devices.

14. The method according to claim 9, further comprising: Connecting in series a plurality of the test devices and reference devices emulating the same on-chip functional device; as well as The one or more parameters of the same on-die functional device are evaluated based on corresponding parameters evaluated on the plurality of the test devices and the reference device.

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