Composite device with back field plate

Abstract

A semiconductor device with a back side field plate includes a buffer layer including a first compound semiconductor material, wherein the buffer layer is epitaxially extended to a crystalline substrate. The semiconductor device also includes a field plate layer disposed on a surface of the buffer layer. The semiconductor device also includes a first channel layer disposed on the field plate layer, wherein the first channel layer includes a first compound semiconductor material. The semiconductor device also includes a region including a two-dimensional electron gas, wherein the two-dimensional electron gas is formed at an interface between the first channel layer and the second channel layer. The semiconductor device also includes a back side field plate formed by a region of the field plate layer and electrically isolated from other regions of the field plate layer.

Description

[0001] priority

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 62 / 694,717, filed on July 6, 2018, entitled “SITE MANAGED III-V GROUP FIELD EFFECT DEVICE WITH EPITAXIAL BACK FIELD PLATE,” and naming James Fiorenza et al. as inventors, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This document relates generally, but not exclusively, to semiconductor devices and, more particularly, to techniques for constructing gallium nitride devices with back surface field plates. Background Art

[0004] Electronic devices constructed from gallium nitride-based compound semiconductors can operate at higher frequencies and higher powers than similar silicon-based devices. The advantages of these gallium nitride-based devices stem at least in part from the higher critical breakdown field of gallium nitride compared to silicon (e.g., for example, the critical breakdown field of gallium nitride is 3 MV / cm, while the critical breakdown field of Si is 0.3 MV / cm). The performance of these gallium nitride-based devices can be improved by adjusting the electric field generated in these devices, such as by minimizing the electric field peak using a source field plate, thereby enabling these devices to be safely driven by higher voltages. For example, U.S. Patent No. 9,112,009 B2 to Charles et al. (hereinafter the '009 patent) describes a III-nitride device having a back conduit and a field plate for improving transconductance. The III-nitride device includes a field plate deposited in a trench that is etched on the back side of the silicon nitride from which the III-nitride device is grown. However, the device described in the '009 patent can be difficult and expensive to manufacture. Additionally, the field plates described in the '009 patent are not epitaxial to the Group III nitride material, which can limit the performance improvements that can be obtained from the field plates. Summary of the invention

[0005] According to one aspect of the present disclosure, a semiconductor device with a back surface field plate is provided, the semiconductor device comprising: a buffer layer comprising a first compound semiconductor material, the buffer layer being epitaxially extended to a crystalline substrate; a field plate layer disposed on a surface of the buffer layer; a first channel layer disposed on the field plate layer, the first channel layer comprising a first compound semiconductor material; a region comprising a two-dimensional electron gas, the two-dimensional electron gas being formed at an interface between the first channel layer and a second channel layer, the second channel layer comprising a second compound semiconductor material in physical contact with the first channel layer; and a first back surface field plate, which is formed by a region of the field plate layer and is electrically isolated from other regions of the field plate layer.

[0006] In some embodiments, the semiconductor device further includes: a gate electrically coupled to the first back surface field plate; a source including a source contact coupled to the two-dimensional electron gas; and a back surface field plate contact coupling the source to the first back surface field plate.

[0007] In some embodiments, the first back field plate contact and the source contact are located at approximately the same distance from the gate.

[0008] In some embodiments, the field plate layer is epitaxially extended to the buffer layer.

[0009] In some embodiments, the semiconductor device further includes: a second back side field plate of the field plate layer electrically isolated from other regions of the field plate layer, and a depth of the second epitaxial region in the field plate layer is different from a depth in the first back side field plate.

[0010] In some embodiments, the first back surface field plate and the second back surface field plate at least partially overlap along a dimension parallel to the two-dimensional electron gas.

[0011] In some embodiments, the field plate layer includes a deactivated p-type compound semiconductor material, and the first back surface field plate includes an activated p-type compound semiconductor material.

[0012] In some embodiments, the field plate layer includes an unintentionally doped compound semiconductor material, and the first back field plate includes an activated p-type compound semiconductor material, the activated p-type compound semiconductor material is disposed in a groove of the unintentionally doped compound semiconductor material, the groove having an opening in the direction of the two-dimensional electron gas.

[0013] In some embodiments, the first compound semiconductor is gallium nitride and the second compound semiconductor is aluminum gallium nitride.

[0014] In some embodiments, the field plate layer includes an aluminum nitride material or an aluminum gallium nitride material, and the first back surface field plate is formed by a two-dimensional electron gas formed at an interface between the buffer layer and the aluminum nitride material or the aluminum gallium nitride material.

[0015] According to one aspect of the present disclosure, a method for manufacturing a semiconductor device with a back surface field plate is provided, the method comprising: forming a buffer layer on a substrate, the buffer layer comprising a first compound semiconductor material; forming a field plate layer on the buffer layer; forming a first channel layer on the field plate layer, the first channel layer comprising the first compound semiconductor material; forming a two-dimensional electron gas by forming a second channel layer on the first channel layer, the second channel layer comprising a second compound semiconductor material; and forming a back surface field plate by patterning the field plate layer.

[0016] In some embodiments, the field plate layer includes a conductive layer of n-type material and a field plate barrier layer, and forming a back surface field plate by patterning the field plate layer includes: forming a mask on the second channel layer, the mask defining the geometry of the back surface field plate; and isolating the back surface field plate from other areas of the field plate layer by selectively destroying areas of the n-type material exposed by the mask using an ion implantation process.

[0017] In some embodiments, the mask includes a gate, a source, or a drain of a semiconductor device.

[0018] In some embodiments, the field plate layer includes a conductive layer of n-type material and a field plate barrier layer, and forming a back surface field plate by patterning the field plate layer includes: forming a mask on the field plate barrier layer, the mask determining the geometry of the back surface field plate; and isolating the back surface field plate from other areas of the field plate layer by selectively destroying areas of the n-type material exposed by the mask using an ion implantation process before forming the second channel layer.

[0019] In some embodiments, the method further includes growing the second channel layer at a temperature lower than an annealing or activation temperature of the n-type material.

[0020] In some embodiments, the field plate layer includes a region of the buffer layer, and forming a back field plate by patterning the field plate layer includes: etching a groove in the buffer layer before forming a first channel layer; forming a conductive layer of p-type material in the groove and above a surface of the buffer layer; and removing the conductive layer of p-type material from the surface of the buffer layer.

[0021] In some embodiments, removing the conductive layer of p-type material includes etching the p-type material from the surface of the buffer layer using a chemical mechanical planarization process.

[0022] In some embodiments, the field plate layer includes a region of the buffer layer, and forming a back field plate by patterning the field plate layer includes: etching a groove in the buffer layer before forming a first channel layer; forming a conductive layer of n-type material in the groove and above a surface of the buffer layer; forming a protective layer of material on the conductive layer of n-type material in the groove; and etching the conductive layer of n-type material from the surface of the buffer layer.

[0023] In some embodiments, the field plate layer includes a conductive layer of p-type material, and forming a back field plate by patterning the field plate layer includes: after forming a second channel layer, deactivating the p-type material by diffusing a deactivating material into the p-type material using an annealing process; forming a mask including a material selected to absorb light having at least a threshold energy level, the mask covering an area above the p-type material corresponding to the geometry of the back field plate; and selectively activating the area above the p-type material by heating the semiconductor device in the presence of an activating material using a heat source disposed above the mask, the heat source being selected to radiate light having at least a threshold energy level.

[0024] In some embodiments, the p-type material is magnesium-doped gallium nitride or carbon-doped gallium nitride.

[0025] In some embodiments, the deactivating material is ammonia or hydrogen, and the activating material is nitrogen.

[0026] In some embodiments, the mask is polysilicon or a refractory metal.

[0027] In some embodiments, the field plate layer includes a conductive layer of p-type material, and forming a back field plate by patterning the field plate layer includes: after forming a second channel layer, forming a mask that covers an area of ​​the second channel layer above the p-type material corresponding to the geometry of the back field plate; and deactivating the area of ​​the p-type material exposed by the mask by diffusing a deactivating material into the p-type material using an annealing process.

[0028] In some embodiments, the mask is a metal and the deactivating material is hydrogen.

[0029] In some embodiments, the mask comprises a material selected to reflect light.

[0030] In some embodiments, the field plate layer includes a conductive layer of a p-type material, and forming a back field plate by patterning the field plate layer includes: after forming a second channel layer, forming a mask that covers an area of ​​the second channel layer above the p-type material corresponding to the geometry of the back field plate; and deactivating an area of ​​the p-type material exposed by the mask by injecting a deactivating material into the p-type material.

[0031] In some embodiments, the field plate layer includes a buffer layer and a field plate barrier layer, and forming a back field plate by patterning the field plate layer includes: selectively implanting an n-type dopant material in a region of the buffer layer corresponding to the back field plate after forming a second channel layer and before forming a device contact; and selectively activating a region of the buffer layer by annealing the semiconductor device in the presence of an activating material.

[0032] In some embodiments, the field plate layer includes a buffer layer and a field plate barrier layer, and forming a back field plate by patterning the field plate layer includes: before forming a first channel layer, selectively implanting an n-type dopant material in a region of the buffer layer corresponding to the back field plate; and before forming the first channel layer, selectively activating the region implanted with the n-type dopant material.

[0033] According to another aspect of the present disclosure, a transistor with a back surface field plate is provided, the transistor comprising: a channel layer including a first two-dimensional electron gas; and a back surface field plate disposed between the channel layer and a crystalline substrate, the back surface field plate including a second two-dimensional electron gas, wherein the second two-dimensional electron gas is disposed on an area smaller than the first two-dimensional electron gas.

[0034] In some embodiments, the two-dimensional electron gas is formed at an interface between the gallium nitride layer and the patterned layer of aluminum nitride material or aluminum gallium nitride material.

[0035] In some embodiments, the transistor further comprises a gate, a source contact, and a field plate contact, wherein the source contact is disposed along a first dimension of the gate and the field plate contact is disposed along a second dimension of the gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A flowchart illustrating an example of a process for fabricating a semiconductor device according to various embodiments is shown.

[0037] Figure 2A Cross-sections of various layers of a semiconductor device that can be fabricated using the techniques described in this disclosure are shown according to various embodiments.

[0038] Figure 2B A perspective view is shown of an example of a semiconductor device that can be manufactured using the techniques described in this disclosure according to various embodiments.

[0039] Figure 3 A flow chart illustrating an example of an ion implantation process for forming a back surface field plate after forming a two-dimensional electron gas during fabrication of a semiconductor device according to various embodiments.

[0040] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E A cross section of layers of a semiconductor device having a back surface field plate formed using an ion implantation process after forming a two-dimensional electron gas according to various embodiments is illustrated.

[0041] Figure 5A flow chart illustrating an example of an ion implantation process for forming a back surface field plate before forming a two-dimensional electron gas during fabrication of a semiconductor device according to various embodiments.

[0042] Fig. 6A , 6B , 6C, 6D, and 6E illustrate cross sections of layers of a semiconductor device having a back surface field plate formed using an ion implantation process before forming a two-dimensional electron gas according to various embodiments.

[0043] Figure 7 A flow chart illustrating an example of a trench and regrowth process for forming a p-type back surface field plate during fabrication of a semiconductor device according to various embodiments.

[0044] Fig. 8A , 8B , 8C, 8D, and 8E illustrate cross-sections of various layers of a semiconductor device having a p-type back surface field plate formed using a trench and regrowth process according to various embodiments.

[0045] Fig. 9 A flow chart illustrating an example of a trench and regrowth process for forming an n-type back surface field plate during fabrication of a semiconductor device according to various embodiments.

[0046] Fig. 10A , 10B , 10C, 10D, 10E, and 10F illustrate cross sections of various layers of a semiconductor device having an n-type back surface field plate formed using a trench and regrowth process according to various embodiments.

[0047] Fig.11 A flow chart illustrating an example of a process of forming a back surface field plate from a deactivated p-type material during the fabrication of a semiconductor device according to various embodiments.

[0048] Fig. 12A , 12B , 12C, 12D, 12E, and 12F illustrate cross-sections of various layers of a semiconductor device having a back surface field plate formed of a passivated p-type material according to various embodiments.

[0049] Fig.13 A flow chart illustrating an example of a local implantation process for forming a back surface field plate during formation of a semiconductor device according to various embodiments.

[0050] Fig.14A , 14B 14C, 14D, 14E, and 14F illustrate cross sections of various layers of a semiconductor device having a back surface field plate formed using a local implantation process according to various embodiments.

[0051] Fig.15A flow chart illustrating an example of an aluminum-based process for forming a back surface field plate using a two-dimensional electron gas during fabrication of a semiconductor device according to various embodiments.

[0052] Fig.16A , 16B , 16C, and 16D illustrate cross-sections of layers of a semiconductor device having a back surface field plate formed using an aluminum-based process and a two-dimensional electron gas according to various embodiments.

[0053] In the accompanying drawings, which are not necessarily drawn to scale, like numbers may describe similar components in different views. Like numbers with different letter suffixes may represent different instances of similar components. The accompanying drawings generally illustrate various embodiments discussed in this document by way of example and not limitation. DETAILED DESCRIPTION

[0054] The present disclosure describes, among other things, semiconductor devices, such as high electron mobility transistors, formed from compound semiconductors, such as gallium nitride (GaN) compounds, and having a back surface field plate that can be epitaxially extended to the compound semiconductor. The back surface field plate can help deplete channel electrons and can help distribute the electric field in the GaN device, for example, to enable the device to operate at a higher voltage than other GaN or semiconductor devices, for example, to enable the construction of faster or more powerful electronic circuits.

[0055] Exemplary embodiments include semiconductor devices that can be used at high power density and high frequency, and methods of making such devices. In this case, high power density can be a power density greater than 5 watts / millimeter (W / mm), and high frequency can be a frequency greater than 5 gigahertz (GHz). A back surface field plate can be formed by epitaxially forming, for example, by growth and patterning, on a compound semiconductor during formation of the semiconductor device so that the back surface field plate exhibits the crystal structure of the compound semiconductor. The back surface field plate can be used to shape the electric field within the semiconductor device, for example to minimize electric field peaks that can cause charge trapping, device breakdown, and other reliability and performance issues.

[0056] Compound semiconductors used to form semiconductor devices described herein may include compounds of elements from different groups in the periodic table. Such compounds may include a pairing of elements from the 13th group (i.e., a group including boron (B), aluminum (Al), gallium (Ga), indium (In) and thium (Tl)) with elements from the 15th group (i.e., a group including nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi)). The 13th group of the periodic table may also be referred to as the III group, and the 15th group may also be referred to as the V group. Without limitation, semiconductor devices may be made of gallium nitride (GaN) and aluminum indium gallium nitride (AlInGaN). In addition, semiconductor devices may be made using aluminum nitride (AlN) / GaN / AlN heterostructures, aluminum indium nitride (InAlN) / GaN, GaN / aluminum nitride GaN (AlGaN) or other combinations of elements from the 13th and 15th groups. These heterostructures can form a two-dimensional electron gas (2DEG) at the interface of the compound semiconductors forming the heterostructure, such as the interface of GaN and AlGaN. The 2DEG can form a conductive channel for electrons, which can be controllably depleted, for example, by an electric field formed by a gate terminal arranged above the channel to control the current through the semiconductor device. In an example, the semiconductor device can be a field effect transistor, such as a high electron mobility transistor (HEMT), having a source terminal and a drain terminal electrically coupled to the channel formed by the 2DEG, and a gate terminal arranged above the channel. The voltage on the gate terminal determined relative to the voltage on the drain terminal can induce an electric field into the channel to control the concentration of free electrons in the 2DEG, thereby controlling the current flowing through the transistor.

[0057] As used herein, the term epitaxy refers to forming (e.g., depositing or growing) a crystalline layer or film on the surface of a crystalline substrate, the layer thus formed having the crystal structure and lattice properties of the substrate. Epitaxy can be used in semiconductor device manufacturing to form single crystal thin films. Epitaxy can be performed in the gas phase, liquid phase, or solid phase. In some embodiments, molecular beam epitaxy ("MBE") can be used to grow semiconductor crystals from elements in Groups 13 and 15, but it should be understood that other forms of epitaxy can be used with the techniques described herein.

[0058] Figure 1A flow chart of an example of a process 100 for manufacturing a semiconductor device according to various embodiments is shown. Process 100 may be initiated by receiving a substrate having a basic crystal structure. Such a substrate may be received from a previous manufacturing process, or may be produced according to one or more substrate growth and processing techniques. Such a substrate may be a wafer, such as sapphire (α-Al2O3), gallium nitride (GaN), gallium arsenide (GaAs), silicon (Si), any polymorph of silicon carbide (SiC) (including wurtzite), aluminum nitride (AlN), indium phosphide (InP), or a similar substrate material used to manufacture semiconductor devices. In some embodiments, the substrate may include one or more layers of epitaxially grown material, such as a sacrificial layer for separating one or more layers of a semiconductor device from another layer, or a nucleation or transition layer to assist in the epitaxial growth of one or more other layers of semiconductor material.

[0059] At 105, a buffer layer (buffer layer) of a first compound semiconductor material such as GaN may be epitaxially grown on the substrate to form a heteroepitaxial thin film. The quality of the GaN heteroepitaxial thin film may depend on one or more properties of the substrate. Such properties may include lattice constants, thermal expansion coefficients, and process-induced properties such as surface roughness, step height, and platform width; among others. See, for example, L. Liu et al., "Gallium Nitride Epitaxial Substrates," Materials Science and Engineering: R: Reports, Vol. 37, No. 3, April 30, 2002, pp. 61-127. Therefore, these properties should be carefully controlled. Proper control of these properties may enable the formation of a GaN layer with extremely high purity or consistency. The buffer layer may be formed by epitaxial growth or by using another thin film formation technique such as chemical vapor deposition (CVD) to have a depth of approximately 400-500 nanometers (nm) thick. However, in some embodiments, the buffer layer may include a field plate layer, as described herein. In such an embodiment, the buffer layer may be approximately 500-600 nm thick.

[0060] At 110, a field plate layer may be formed on the buffer layer. Such a field plate layer may include approximately 100 nm of compound semiconductor material epitaxially grown on the buffer layer. Such a field plate layer may include a portion or region of the buffer layer (e.g., a volume determined by a particular depth), such as a 100 nm thick region. Such a field plate layer may include a conductive p-type layer, for example, a dopant formed by depositing a p-type dopant in a crystal structure of a compound semiconductor material in the buffer layer (e.g., by using ion implantation or CVD techniques). In one example, a p-type field plate layer may be formed by annealing a semiconductor device having a GaN buffer layer in a chamber with an ambient nitrogen (N2) gas at an ambient annealing temperature varying between 1000-1100 degrees Celsius (C). Such a field plate layer may alternatively include a conductive n-type layer, for example, a layer formed by depositing an n-type dopant in a crystal structure of a compound semiconductor material in the buffer layer and forming a field plate barrier layer on top of the doped buffer layer. In one example, an n-type field plate layer may be formed by annealing a semiconductor device having a GaN buffer layer in an ambient silane (SiH4) gas chamber at an ambient annealing temperature varying between 1000-1100° C., followed by deposition of an AlN field plate barrier layer. Such a doped field plate layer may have a crystal structure substantially similar to or formed from the crystal structure of the buffer layer.

[0061] In some embodiments, forming the field plate layer can include removing a partially formed semiconductor device from an annealing chamber and performing one or more semiconductor fabrication steps, such as etching, planarization, or ion implantation steps.

[0062] At 115, a first channel layer (GaN channel layer) of a compound semiconductor material for forming a buffer layer may be formed on the field plate layer. The first channel layer may be formed in the same manner as the buffer layer, such as by epitaxial growth, or using another thin film formation technique. In some embodiments, the first channel layer may be formed by continuing a GaN growth process in an annealing chamber. In other embodiments, such a GaN layer may be formed by returning a partially completed semiconductor device to an annealing chamber and initiating a GaN regrowth process. Such a GaN growth or regrowth process may be continued until a GaN layer of approximately 100 nm is grown.

[0063] At 120, a 2DEG may be formed, for example, by epitaxially growing a second channel layer of a second compound semiconductor material such as AlGaN (e.g., an AlGaN channel layer) on a surface of the first channel layer to form a heterojunction. The second channel layer may be formed in the same manner as the first channel layer, for example, by epitaxial growth or using another thin film formation technique. The first compound semiconductor material and the second compound semiconductor material may be selected to have different band gaps so as to form a heterojunction at an interface between a surface of the first compound semiconductor material and a surface of the second compound semiconductor material. Such a selection may allow a two-dimensional electron gas (2DEG) to form at the heterojunction.

[0064] At 125, a back field plate may be formed by patterning the field plate layer formed at step 110. Figure 3 , 5 , 7, 9, 11, or 13. In some embodiments, the back surface field plate can be epitaxially extended to the buffer layer.

[0065] Process 100 may be completed by forming one or more device components and electrically coupling the one or more device components to the heterojunction. In one example, a source, a drain, and a gate of a HEMT may be formed and electrically coupled to the heterojunction. A back field plate contact may also be formed in the semiconductor device to physically and electrically couple the back field plate to ground.

[0066] Figure 2A A cross section of the layers of a semiconductor device 200 that can be manufactured according to any process described in the present disclosure (such as process 100) is shown. Such a semiconductor device may include a high electron mobility transistor. Such a HEMT may include a field effect transistor (FET) that includes at least two semiconductor materials with different band gaps (e.g., a heterostructure) so as to form a charge transfer channel (e.g., a heterojunction) at an interface between the two semiconductor materials. The semiconductor device 200 may include a crystalline substrate 225, a buffer layer 220 (e.g., a first layer of a first compound semiconductor material), a field plate layer 215, a first channel layer 210 (e.g., a second layer of a first semiconductor material), a region 240 forming a 2DEG, and a second channel layer 205 (e.g., a barrier layer of a second compound semiconductor material). The semiconductor device 200 may also include an epitaxial back field plate 230 and one or more device layers 270. The one or more device layers 270 may include one or more device elements, such as a drain 245, a source 250, a gate 255, and a source field plate 260.

[0067] In some embodiments, source 250 can include a source contact (not shown) disposed between the source and gate 255. Source 250 can also include a back surface field plate contact 235 that faces away from the gate further than the source contact. Such an arrangement of back surface field plate contacts can require that back surface field plate 230 extend laterally beyond gate 255 to be aligned with or below source 250 so that the back surface field plate contact physically and electrically couples the back surface field plate to the source.

[0068] Figure 2B A perspective view is shown of an example of a semiconductor device that can be manufactured using the techniques described in this disclosure according to various embodiments. Figure 2B The semiconductor device of FIG. 200 includes a device layer 290 , which may correspond to layers 205 , 210 , 215 , 220 , and 225 of semiconductor device 200 . Figure 2B The semiconductor device further includes a device layer 285, which may correspond to the device layer 270, such as Figure 2A shown. Figure 2B The specific device elements shown include epitaxial back surface field plate 265 , source 270 , source contact 272 , drain 275 , drain contact 277 , gate 280 , and back surface field plate contact 282 .

[0069] Figure 2B Alternative configurations for arranging source contact 272 and back field plate contact 282 are included. Figure 2B As shown, the width of the gate 280 enables the back surface field plate contact to be formed along the back dimension of the gate, while the source contact is formed along the lateral dimension of the gate. Such a configuration can improve the efficiency of the semiconductor device, for example, by eliminating the need to extend the back surface field plate 265 under the source 270. Such a configuration can also improve the performance of the semiconductor device by allowing the back surface field plate 265 to be formed completely under the gate 280.

[0070] Figure 3 A flow chart illustrating an example of an ion implantation process 300 for forming a back surface field plate after forming a 2DEG during fabrication of a semiconductor device is shown. FIG. 4A to FIG. 4E A cross section of the layers of the semiconductor device at each step in process 300 is shown. Process 300 may be any embodiment of process 100, wherein processes 110 and 125 are expanded to include specific steps for forming a field plate layer and a back field plate, respectively. Process 300 may begin with a partially formed semiconductor device, such as a semiconductor device formed according to step 105 of process 100, and having a crystalline substrate layer 225 and an epitaxial buffer layer 220, such as Figure 4A shown.

[0071] At 305, a conductive layer of n-type material 410 may be formed on buffer layer 220. As described herein, such a conductive layer may be formed by depositing an n-type dopant material (eg, SiH4) using an annealing process.

[0072] At 310, a field plate barrier layer 405 may be deposited on the conductive layer of n-type material 410. Such a field plate barrier layer may include an amount of material having a thickness less than 5 nm and selected to inhibit current flow between the conductive layer of n-type material 410 and a subsequently deposited conductive or semiconductive layer. The field plate barrier layer material may include a p-type material, such as p-type GaN, or an insulator, such as AlN.

[0073] At 315, a semiconductor device may be fabricated at least by forming a 2DEG. Such fabrication may include epitaxially forming a first channel layer 210 and forming a 2DEG by epitaxially forming a second channel layer barrier layer 205, such as Figure 4B In some embodiments, such fabrication may include fabricating one or more device components, such as drain, gate, and source terminals of a semiconductor device.

[0074] At 320, a field plate mask 415 may be formed to define the geometry and location of the back side field plate of the semiconductor device. Figure 4C As shown, such a field plate mask 415 may be formed on the second channel layer 205 using a mask material selected to block or prevent ions implanted to deactivate regions of the n-type conductive layer 410 to form a back surface field plate of the semiconductor device. Subsequent manufacturing steps of a semiconductor device having a field plate patterned from a field plate mask formed on the second channel layer 205 may include steps or device layout considerations to ensure that one or more device elements (e.g., a gate or drain) are aligned with the position and geometry of the back surface field plate. In some embodiments, the field plate mask 415 may be formed on or comprised of one or more device elements of the semiconductor device 200. In these embodiments, the back surface field plate produced in subsequent semiconductor device manufacturing steps may be self-aligned with the one or more device elements, thereby avoiding the need for further alignment considerations.

[0075] At 325, the back field plate may be isolated from the n-type conductive layer 410, for example by implanting a deactivating material such as nitrogen into the n-type conductive layer using ion implantation to damage the area exposed by the field plate mask 415, such as Figure 4D The resulting damaged regions 425 and 425 may have increased resistance compared to the region of the field plate layer below the field plate mask, thereby forming a Figure 4EThe electrically isolated back field plate 430 is shown. Consideration may be given to ensuring that the implanted ions have sufficient energy to damage the field plate layer 410 while limiting damage to other layers of the semiconductor device, such as, for example, to limit damage to the 2DEG to preserve electron transport properties or reduce defects that may cause charge trapping and drain / body leakage. In some embodiments, such damage and defects may be at least partially cured by annealing the semiconductor device after the ion implantation process. In certain embodiments, as described herein, process 300 may be completed by forming one or more device components (e.g., a source electrode, a gate electrode, and a drain electrode) and electrically coupling the one or more device components to the 2DEG or a heterojunction forming the 2DEG.

[0076] Figure 5 A flowchart illustrating an example of an ion implantation process 500 for forming a back surface field plate before forming a two-dimensional electron gas during fabrication of a semiconductor device is shown. FIG. 6A to FIG. 6E A cross section of the layers of the semiconductor device at each step in process 500 is shown. The semiconductor device may be a HEMT device, such as semiconductor device 200. Process 500 may be an embodiment of process 100, wherein steps 110 and 125 are expanded to include specific steps for forming a field plate layer such as field plate layer 215 and a back surface field plate such as back surface field plate 230, respectively. Process 500 may start with a partially formed semiconductor device, such as the semiconductor device formed according to step 105 of process 100, and having a crystalline substrate layer 225 and an epitaxial buffer layer 220, such as Fig. 6A shown.

[0077] At 505, a conductive layer of n-type material 610 may be formed on buffer layer 220. As described herein, such a conductive layer may be formed by depositing an n-type dopant material using an annealing process.

[0078] At 510, if Fig. 6A As shown, the field plate barrier layer 605 can be deposited on the conductive layer of n-type material 610. Figures 4A-4E As shown, such a field plate barrier layer may be substantially similar to field plate barrier layer 405 .

[0079] At 515, a field plate mask 615 may be formed to define the geometry and location of the back side field plate of the semiconductor device. Figure 6BAs shown, such a field plate mask 615 may be formed on the field plate barrier layer 605, for example, to form or pattern a back surface field plate of a semiconductor device, using a mask material selected to block or prevent implanted ions from deactivating regions of the n-type conductive layer 610. Subsequent fabrication steps of a semiconductor device including a field plate patterned from the field plate mask formed on the field plate barrier layer 605 may include one or more steps or device layout considerations to ensure that one or more device elements, such as a gate or drain, are aligned with the location and geometry of the back surface field plate.

[0080] At 520, the back field plate may be isolated from the n-type conductive layer 610, for example, by using ion implantation of a deactivating material 620, such as nitrogen ions, into the n-type conductive layer to damage the area exposed by the field plate mask 615, as shown in FIG. Figure 6C The resulting damaged regions 615 and 625 may have increased resistance compared to the region of the field plate layer below the field plate mask, thereby forming a Fig.6D An electrically isolated back surface field plate 630 is shown.

[0081] At 525, a semiconductor device may be fabricated at least by forming a 2DEG. Such fabrication may include epitaxially growing a second layer of the first semiconductor material 210, and forming a 2DEG by epitaxially growing a barrier layer of a second compound semiconductor material 205, such as Fig. 6E As shown. Process 500 can form a back surface field plate using an ion implantation process while limiting the possibility of damage to other layers of the semiconductor device, such as the 2DEG. This can enable the use of higher ion implantation energies, such as enabling the formation of a thicker back surface field plate or a back surface field plate formed at a greater distance from the 2DEG or gate of the semiconductor device.

[0082] In certain embodiments, process 500 may be performed by forming one or more device components (eg, source electrode, gate electrode, and drain electrode) and electrically coupling the one or more device components to the 2DEG or forming a heterojunction of the 2DEG.

[0083] In some embodiments, process 500 can be combined with process 200 to fabricate a semiconductor device having two or more back surface field plates. In an example, a first back surface field plate can be formed at a first depth in field plate layer 610 according to process 500. A second back surface field plate can then be formed at a second shallow depth in the field plate layer using process 300. Careful selection of each back surface field plate depth can allow two or more back surface field plates to at least partially overlap while maintaining electrical isolation.

[0084] Figure 7 A flow chart showing an example of a trench and regrowth process for forming a p-type back surface field plate during fabrication of a semiconductor device, and Figures 8A-8EA cross section of the layers of the semiconductor device is shown at each step in process 700. The semiconductor device may be a HEMT device, such as semiconductor device 200. Process 700 may be an embodiment of process 100, where step 125 is expanded to include specific steps for forming a back surface field plate, such as back surface field plate 230 (FIG. 2).

[0085] At 705, a semiconductor device may be fabricated by forming a field plate layer 215 (eg, an epitaxial field plate layer), such as Fig. 8A Such fabrication may include steps substantially similar to steps 105 and 110 of process 100, for example, to form a partially developed semiconductor device having a crystalline substrate layer 225, an epitaxial buffer layer 220, and a field plate layer 215. In some embodiments, the field plate layer 215 (e.g., an insulator layer) may be a portion of the buffer layer 220, such as a 100 nm thick region of the buffer layer.

[0086] At 710, if Figure 8B As shown, trenches 805 can be etched in the field plate layer 215, for example, by using a dry GaN etching technique such as an inductively coupled plasma or reactive ion etching process. The trenches 805 can be etched to a depth of about 100 nm or another predetermined depth corresponding to a desired height or desired distance of the back surface field plate to position the back surface field plate away from device elements of the semiconductor device.

[0087] At 715, a conductive layer of p-type material may be formed in trench 805 and over the top surface of field plate layer 215. Such a conductive layer of p-type material may be epitaxially grown onto field plate layer 215, for example, by growing a compound semiconductor such as GaN in trench 805 and over field plate layer 215, and then using an annealing process to deposit a p-type dopant such as magnesium (Mg). Figure 8C A partially completed semiconductor device is shown having a conductive layer of p-type material 810 as it is epitaxially formed in trench 805 and over the top surface of field plate layer 215 .

[0088] At 720, the p-type material 810 may be removed from the top surface of the field plate layer 215, such as by using a GaN dry etch process, to form an isolated p-type field plate 815 in the trench 805, as shown in FIG. Fig.8D shown.

[0089] At 725, fabrication of the semiconductor device may continue by at least forming a 2DEG, as described herein and Fig. 8E shown.

[0090] Fig. 9 A flow chart illustrating an example of a trench and regrowth process 900 for forming an n-type back surface field plate during fabrication of a semiconductor device is shown. FIG. 10A to FIG. 10E A cross section of layers of a semiconductor device is shown at each step in process 900. The semiconductor device may be a HEMT device, such as semiconductor device 200. Process 900 may be an embodiment of process 100, wherein step 125 is expanded to include specific steps for forming a back surface field plate, such as back surface field plate 230 (FIG. 2).

[0091] At 905, a semiconductor device may be developed by forming a field plate layer 215, such as Fig. 10A Such processing may include steps substantially similar to steps 105 and 110 of process 100, for example to form a partially developed semiconductor device having a crystalline substrate layer 225, an epitaxial buffer layer 220, and a field plate layer 215. In an embodiment, the field plate layer 215 may be a portion of the buffer layer 220, for example a 100 nm thick region of the buffer layer.

[0092] At 910, trenches 1005 may be etched in the field plate layer 215, for example, by using a dry GaN etching technique, such as Fig. 10B Such a cavity may be etched to a depth of about 100 nm or another predetermined depth corresponding to a desired height of a back surface field plate or a desired distance from a device element (eg, a gate) of a semiconductor device.

[0093] At 915, a conductive layer of n-type material may be formed in trench 1005 and over the top surface of field plate layer 215. This conductive layer of n-type material may be epitaxially grown onto field plate layer 215, for example, by growing a compound semiconductor such as GaN in trench 1005 and over field plate layer 215, and then using an annealing process to deposit an n-type dopant such as SiH4 gas. Fig. 10C A partially completed semiconductor device is shown having a conductive layer 1010 of n-type material as it is epitaxially formed in trench 1005 and over the top surface of field plate layer 215 .

[0094] At 920, a protective material layer 1015 may be deposited in or over the trench 1005 to form a mask over the trench to prevent etching of the n-type material formed in the trench during subsequent processing of the semiconductor device, such as Fig. 10D Such a protective material may include silicon nitride or any other material that may be used as a mask for this purpose.

[0095] At 925, the n-type material 1010 may be removed from the top surface of the field plate layer 215, such as by using an etching process, to form an isolated n-type field plate 1020 in the trench 1005, as shown in FIG. Fig. 10E shown.

[0096] At 930, a field plate barrier layer 1025 may be formed over the field plate layer 215 and over the n-type field plate 1020 and as described herein and Fig.10F As shown, the fabrication of the semiconductor device can be continued at least by forming a 2DEG.

[0097] Fig.11 A flow chart illustrating an example of a process 1100 for forming a back surface field from a deactivated p-type material during fabrication of a semiconductor device is shown, and FIG. 12A to FIG. 12F A cross section of the layers of the semiconductor device at each step in process 1100 is shown. The semiconductor device may be a HEMT device, such as semiconductor device 200. Process 1100 may be an embodiment of process 100 in which steps 110 and 125 are expanded to include specific steps for forming a field plate layer and a back surface field plate, respectively. Process 1100 may begin with a partially formed semiconductor device, such as a semiconductor device formed according to step 105 of process 100 and having a crystalline substrate layer 225 and an epitaxial buffer layer 220, such as Fig. 12A shown.

[0098] At 1105, a conductive layer 1205 of a p-type material may be formed on the buffer layer 220. Fig. 12A Such a conductive layer is shown to be formed by depositing a p-type dopant material, such as magnesium (Mg), using an annealing process specifically configured to exclude hydrogen.

[0099] At 1110 , a semiconductor device can be fabricated at least through formation of a 2DEG as described herein. Fig. 12B A partially completed semiconductor device is shown having a 2DEG formed at the interface of an epitaxial layer of a first compound semiconductor and an epitaxial buffer layer of a second component semiconductor, as described herein.

[0100] In 1115, Fig. 12C As shown, the p-type material 1205 can be deactivated, for example, by annealing the semiconductor device in the presence of a deactivating material 1210 such as ammonia (NH4) or hydrogen. In some embodiments, the deactivation can be performed after forming a conductive layer of p-type material and before fabricating subsequent layers of the semiconductor device.

[0101] At 1120, a mask 1215 may be formed over the region of p-type material to define the geometry and location of the back surface field plate of the semiconductor device, such as Fig.12DAs shown. Such a mask may include a material selected to absorb wavelengths of light that would otherwise pass through the semiconductor material used to fabricate the semiconductor device. In one example, when the semiconductor device is composed of GaN, such a mask may include a material selected to absorb light having an energy less than the band gap of GaN (e.g., 3.3 electron volts). Such a mask may typically include refractory metals such as tungsten, tantalum, and rhenium.

[0102] In 1125, Fig.12E As shown, the p-type material 1205 located below the mask 1215 can be selectively activated by heating the semiconductor device from the top of the device in the presence of an activating material 1220 such as N2 or magnesium. Such heating can include emitting radiant energy using a light source that is selected to emit light having an energy lower than the band gap energy of the semiconductor material used to manufacture the semiconductor device. Such heating can cause the radiant energy emitted by the selected light source to pass through the areas of the semiconductor device exposed by the mask 1215 without heating these exposed areas. Such heating can also cause the radiant energy emitted by the selected light source to be absorbed by the mask 1215, thereby causing localized heating of the semiconductor device area located below the mask, thereby enabling the activating material to diffuse into the heated p-type material. The p-type material activated according to this process can form an isolated back surface field plate 1225, as shown in FIG. Fig.12F shown.

[0103] In some embodiments, step 1115 can be omitted and a mask 1215 can be formed over the conductive layer of p-type material 1205 to expose regions of the p-type material that define the geometry and location of the back surface field plate of the semiconductor device. In these embodiments, the back surface field plate can be formed by annealing the semiconductor device using a selected light source in the presence of a deactivating material, thereby deactivating the regions of the p-type material under the mask 1215 while keeping the regions exposed by the tanning activated.

[0104] In some embodiments, step 1115 may be omitted and mask 1215 may include a material selected to inhibit diffusion of deactivating materials. Such a mask may be formed over a region of p-type material 1205 to define the geometry and location of a back surface field plate of a semiconductor device, such as Fig.12D In these embodiments, the back surface field plate can be formed by annealing the semiconductor device in the presence of the deactivation material using a semiconductor material selected to emit radiant energy, the radiated energy being absorbed by the semiconductor material used to manufacture the semiconductor device, thereby causing the deactivation material to diffuse into the p-type material region exposed by the mask 1215 and deactivate it.

[0105] In some embodiments, step 1115 may be omitted and mask 1215 may include a material selected to inhibit the passage of ions having energy levels below a threshold energy level. Such a mask may be formed over a region of p-type material 1205 to define the geometry and location of a back surface field plate of a semiconductor device, such as Fig.12D In these embodiments, the back field plate can be formed by implanting ions of a deactivating material into the regions of the p-type material exposed by the mask 1215, so that the deactivating material deactivates the exposed regions while keeping the masked regions of the p-type material in an activated state.

[0106] Fig.13 A flow chart of an example of a local implantation process 1300 for forming a back surface field plate during fabrication of a semiconductor device according to various embodiments is shown. Process 1300 may be an embodiment of process 100 in which steps 110 and 125 are expanded to include specific steps for forming a field plate layer and a back surface field plate, respectively. Although the process is discussed with reference to using n-type materials, a substantially similar process may be implemented using p-type materials. Process 1300 may begin with a partially formed semiconductor device, such as a semiconductor device formed according to step 105 of process 100, and having a crystalline substrate layer 225 and an epitaxial buffer layer 220, as shown in FIG. 2 .

[0107] At 1305, a field plate barrier layer can be formed on the buffer layer, as described herein. At 1310, n-type dopants can be selectively implanted into the field plate region of the buffer layer to form a region of inactive n-type material.

[0108] At 1315, the passivated n-type material can be selectively activated, for example, by patterning a mask to expose the passivated n-type material on the semiconductor device and implanting an activating material into the passivated n-type material using an ion implantation process. At 1320, fabrication of the semiconductor device can then continue by at least forming a 2DEG.

[0109] In some embodiments, such as Fig.14A As shown, a semiconductor device may be manufactured by forming a 2DEG before step 1310. In these embodiments, before step 1310, the semiconductor device may include a substrate 225, a buffer layer 220, a field plate layer 215, a first channel layer 210, and a second channel layer 205. The field plate layer 215 may include a region 1415 of the buffer layer 220 and a field plate barrier layer 1410. The semiconductor device may further include a field plate mask 1405. Figure 4A As shown, n-type dopants 1420 may be implanted through the field plate layer 215, the first channel layer 210, and the second channel layer 205. The implantation may form a field plate region 430A, which may be activated according to step 1315, such as Fig. 14BAs shown. However, such implantation may damage one or more layers of the semiconductor device. Such damage may be repaired by annealing the semiconductor device. The annealing temperature, however, should be selected to avoid deactivating the field plate region 430.

[0110] In some embodiments, such as Fig. 14C As shown, the semiconductor device can be manufactured by forming a field plate barrier layer 1410 before step 1310. In these embodiments, as Fig. 14C and 14D As shown, n-type dopants 1420 may be implanted and activated before forming subsequent semiconductor device layers, such as forming conductive field plate region 430B. After activating the field plate region, the fabrication of the semiconductor device may continue according to process 1300, such as by performing a regeneration process to continue fabrication of the device at least by forming a 2DEG. This regeneration technique may eliminate the need for a carefully controlled annealing process to repair damage that may be caused by the implantation process.

[0111] In some embodiments, such as Fig.14E As shown, the semiconductor device can be manufactured by forming the first compound semiconductor layer 210 before step 1310. In these embodiments, as Fig.14E and 14F As shown, n-type dopants 1420 may be implanted and activated before forming subsequent semiconductor device layers, such as forming a conductive field plate region 430C. After activating the field plate region, the fabrication of the semiconductor device may continue according to process 1300, such as by performing a regeneration process to continue fabrication of the device at least by forming a 2DEG. This regeneration technique may eliminate the need for a carefully controlled annealing process to repair damage that may be caused by the implantation process.

[0112] Fig.15 A flow chart illustrating an example of an aluminum-based process 1500 for forming a back surface field plate using a two-dimensional electron gas during fabrication of a semiconductor device is shown, and Figures 16A-16D A cross-sectional view of various layers of a semiconductor device in process 1500 is shown. The semiconductor device may be a HEMT device, such as semiconductor device 200. Process 1500 may be an embodiment of process 100, wherein steps 110 and 125 are expanded to include specific steps for forming a field plate layer and a back field plate. Process 1500 may begin with a partially formed semiconductor device, such as a semiconductor device, which may be formed according to step 105 of process 100 and has a crystalline substrate layer 225 and an epitaxial buffer layer 220 (e.g., a GaN buffer layer), such as Fig.16A shown.

[0113] At 1505, a conductive layer 1605 of AlN or AlGaN material may be formed on the buffer layer 220. At 1510, an insulator layer 1610 such as a silicon nitride (SiN) layer may be formed on the conductive layer 1605. Fig.16A At 1515, the insulator layer 1610 can be patterned, for example, to define features (e.g., geometry or location) of the back field plate. At 1520, the patterned insulator layer can be etched, such as to form a field plate mask 1620, such as Fig. 16B At 1525, a back field plate 1630 may be formed using a field plate mask by, for example, selectively etching the conductive layer 1605 to remove areas not protected by the mask or by using an ion implantation process to inactivate such unprotected areas. Fig. 16C As shown, an isolated back surface field plate is formed by 2DEG at the interface between the buffer layer 220 and the remaining AlN or AlGaN material 1625 .

[0114] At 1530, a semiconductor device may be fabricated by at least forming a second 2DEG, for example, to serve as a conductive path of the semiconductor device. Such fabrication may include epitaxially growing a second layer of the first semiconductor material 210 and forming the second 2DEG by epitaxially growing a barrier layer of a second compound semiconductor material 205, such as Fig.16D shown.

[0115] In certain embodiments, process 1500 may be completed by forming one or more device components (eg, source electrode, gate electrode, and drain electrode) and electrically coupling the one or more device components to a 2DEG or a heterojunction forming a 2DEG.

[0116] Although the above discussion discloses various exemplary embodiments, it will be apparent that various modifications can be made by those skilled in the art which will achieve certain advantages of the invention without departing from the true scope of the invention.

[0117] Each non-limiting aspect or example described herein may stand alone or may be combined with one or more of the other examples in various permutations or combinations.

[0118] The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The accompanying drawings show specific embodiments in which the present invention can be practiced by way of illustration. These embodiments are also referred to as "examples" in this article. In addition to the elements shown or described, such examples may include elements. However, the inventors also contemplate examples that only provide those elements shown or described. In addition, the inventors also contemplate examples of any combination or arrangement of those elements (or one or more aspects thereof) shown or described, about the specific examples (or one or more aspects thereof) shown or described herein, or other examples (or one or more aspects thereof).

[0119] In the event of an inconsistency in usage between this document and any document incorporated by reference, the usage in this document controls.

[0120] In this document, the terms "a" or "an" are used in patent documents to include one or more, independent of any other instances or uses of "at least one" or "one or more". In this document, unless otherwise stated, the term "or" is used to indicate non-exclusivity or "A or B" includes "A but not B", "B but not A", and "A and B". In this document, the terms "including" and "wherein" are used as ordinary equivalents of the corresponding terms "comprising" and "wherein". Similarly, in the following aspects, the terms "including" and "comprising" are open-ended, that is, systems, devices, articles, compositions, preparations, or processes that include other elements in addition to the elements listed after the term in an aspect are still considered to be within the scope of that aspect. In addition, in the following aspects, the terms "first", "second", and "third", etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0121] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. After reviewing the above description, other embodiments may be used, for example, by a person of ordinary skill in the art. An abstract is provided to allow the reader to quickly determine the nature of the technical disclosure. It should be understood when submitting this document that it will not be used to explain or limit the scope or meaning of the aspects. In addition, in the above detailed description, various features may be grouped together to simplify the disclosure. This should not be interpreted as intending to mean that undeclared public features are essential to any aspect. Instead, the subject matter of the invention may be less than all the features of a specific disclosed embodiment. Therefore, the following aspects are incorporated into the detailed description as examples or embodiments herein, each of which exists independently as an independent embodiment, and it is expected that these embodiments may be combined with each other in various combinations or arrangements. The scope of the present invention should be determined with reference to the attached aspects and the full range of equivalent forms that these aspects should have.

Claims

1. A semiconductor device having a back surface field plate, the semiconductor device comprising: A buffer layer comprising a first compound semiconductor material epitaxially grown to a crystalline substrate; a field plate layer disposed on a surface of the buffer layer; A first channel layer disposed on the field plate layer, wherein the first channel layer comprises a first compound semiconductor material; a region including a two-dimensional electron gas, the two-dimensional electron gas being formed at an interface between the first channel layer and a second channel layer, the second channel layer including a second compound semiconductor material in physical contact with the first channel layer; a back field plate formed by a region of the field plate layer and electrically isolated from other regions of the field plate layer; as well as a gate, a source contact, and a field plate contact, the field plate contact being coupled to the back field plate, The source contact is arranged along a first dimension of the gate, and the field plate contact is arranged along a second dimension of the gate.

2. The semiconductor device according to claim 1, further comprising: a source including a source contact coupled to the two-dimensional electron gas, wherein the field plate contact couples the source with the back field plate. 3 . The semiconductor device of claim 1 , wherein the field plate layer comprises a deactivated p-type compound semiconductor material, and the back side field plate comprises an activated p-type compound semiconductor material.

4. The semiconductor device according to claim 1, wherein the field plate layer comprises an inactivated compound semiconductor material, and the back field plate comprises an activated p-type compound semiconductor material, the activated p-type compound semiconductor material is arranged in a groove in the inactivated compound semiconductor material, and the groove has an opening in the direction of the two-dimensional electron gas. 5 . The semiconductor device according to claim 1 , wherein the first compound semiconductor material is gallium nitride, and the second compound semiconductor material is aluminum gallium nitride. 6 . The semiconductor device according to claim 1 , wherein the field plate layer comprises an aluminum nitride material or an aluminum gallium nitride material, and the back field plate is formed by a two-dimensional electron gas formed at an interface between the buffer layer and the aluminum nitride material or the aluminum gallium nitride material.

7. A method for manufacturing a semiconductor device having a back surface field plate, the method comprising: forming a buffer layer on a substrate, wherein the buffer layer comprises a first compound semiconductor material; forming a field plate layer on the buffer layer; forming a first channel layer on the field plate layer, wherein the first channel layer comprises the first compound semiconductor material; forming a two-dimensional electron gas by forming a second channel layer on the first channel layer, wherein the second channel layer includes a second compound semiconductor material; forming a back field plate by patterning the field plate layer; as well as A gate, a source contact, and a field plate contact are formed, the field plate contact being coupled to the back field plate, wherein the source contact is disposed along a first dimension of the gate and the field plate contact is disposed along a second dimension of the gate.

8. The method according to claim 7, wherein the field plate layer comprises a conductive layer of an n-type material and a field plate barrier layer, and forming a back side field plate by patterning the field plate layer comprises: forming a mask on the second channel layer, the mask determining the geometry of the back surface field plate; and The back surface field plate is isolated from other areas of the field plate layer by selectively destroying areas of the n-type material exposed by the mask using an ion implantation process. 9 . The method according to claim 8 , wherein the mask comprises a gate, a source or a drain of a semiconductor device.

10. The method according to claim 7, wherein the field plate layer comprises a conductive layer of an n-type material and a field plate barrier layer, and forming a back side field plate by patterning the field plate layer comprises: forming a mask on the field plate barrier layer, the mask determining the geometry of the back field plate; and Before forming the second channel layer, the back surface field plate is isolated from other regions of the field plate layer by selectively destroying regions of the n-type material exposed by the mask using an ion implantation process.

11. The method according to claim 10, further comprising: The second channel layer is grown at a temperature lower than an annealing or activation temperature of the n-type material.

12. The method of claim 7, wherein the field plate layer includes a region of the buffer layer, and forming a back field plate by patterning the field plate layer comprises: before forming the first channel layer, etching a trench in the buffer layer; forming a conductive layer of p-type material in the trench and over a surface of the buffer layer; and The conductive layer of the p-type material is removed from the surface of the buffer layer. 13 . The method of claim 12 , wherein removing the conductive layer of p-type material comprises etching the p-type material from the surface of the buffer layer using a chemical mechanical planarization process.

14. The method of claim 7, wherein the field plate layer includes a region of the buffer layer, and forming a back field plate by patterning the field plate layer comprises: before forming the first channel layer, etching a trench in the buffer layer; forming a conductive layer of n-type material in the trench and over a surface of the buffer layer; forming a protective layer of material on the conductive layer of n-type material in the trench; and The conductive layer of n-type material is etched from the surface of the buffer layer.

15. The method of claim 7, wherein the field plate layer comprises a conductive layer of a p-type material, and forming a back field plate by patterning the field plate layer comprises: After forming the second channel layer, diffusing a deactivating material into the p-type material using an annealing process to deactivate the p-type material; forming a mask including a material selected to absorb light having at least a threshold energy level, the mask covering an area over the p-type material corresponding to the geometry of the back surface field plate; and Regions above the p-type material are selectively activated by heating the semiconductor device in the presence of the activating material using a heat source disposed above the mask, the heat source being selected to radiate light having at least a threshold energy level.

16. The method of claim 15, wherein the p-type material is magnesium-doped gallium nitride or carbon-doped gallium nitride.

17. The method of claim 15, wherein the deactivating material is ammonia or hydrogen, and the activating material is nitrogen.

18. The method of claim 15, wherein the mask is polysilicon or a refractory metal.

19. The method according to claim 7, wherein the field plate layer comprises a conductive layer of a p-type material, and forming a back field plate by patterning the field plate layer comprises: After forming the second channel layer, forming a mask that covers a region of the second channel layer above the p-type material that corresponds to a geometry of the back surface field plate; and Regions of the p-type material exposed by the mask are deactivated by diffusing a deactivating material into the p-type material using an annealing process.

20. The method of claim 19, wherein the mask is a metal and the deactivating material is hydrogen.

21. The method of claim 19, wherein the mask comprises a material selected to reflect light.

22. The method according to claim 7, wherein the field plate layer comprises a conductive layer of a p-type material, and forming a back field plate by patterning the field plate layer comprises: After forming the second channel layer, forming a mask that covers a region of the second channel layer above the p-type material that corresponds to a geometry of the back surface field plate; and Regions of the p-type material exposed by the mask are deactivated by implanting a deactivating material into the p-type material.

23. The method of claim 7, wherein the field plate layer comprises a buffer layer and a field plate barrier layer, and forming a back side field plate by patterning the field plate layer comprises: After forming the second channel layer and before forming the device contacts, selectively implanting an n-type dopant material in a region of the buffer layer corresponding to the back surface field plate; and The region of the buffer layer is selectively activated by annealing the semiconductor device in the presence of an activating material.

24. The method of claim 7, wherein the field plate layer comprises a buffer layer and a field plate barrier layer, and forming a back field plate by patterning the field plate layer comprises: Before forming the first channel layer, selectively implanting an n-type dopant material in a region of the buffer layer corresponding to the back surface field plate; and Before forming the first channel layer, the region implanted with the n-type dopant material is selectively activated.

25. The method according to claim 7, wherein the field plate layer comprises an aluminum nitride material or an aluminum gallium nitride material, and Forming a back side field plate by patterning the field plate layer includes: A region of the field plate layer is etched or inactivated to form a field plate region, the back field plate being formed by a two-dimensional electron gas formed at an interface between the buffer layer and the field plate region.

26. A transistor having a back surface field plate, the transistor comprising: a channel layer including a first two-dimensional electron gas; a back surface field plate disposed between the channel layer and the crystalline substrate, the back surface field plate comprising a second two-dimensional electron gas, the second two-dimensional electron gas being disposed on a smaller area than the first two-dimensional electron gas; as well as A gate, a source contact, and a field plate contact, the field plate contact being coupled to the back field plate, the source contact being disposed along a first dimension of the gate, and the field plate contact being disposed along a second dimension of the gate. 27 . The transistor of claim 26 , wherein the second two-dimensional electron gas is formed at an interface between a gallium nitride layer and a patterned layer of an aluminum nitride material or an aluminum gallium nitride material.

28. The transistor of claim 26, further comprising: A buffer layer comprising a first compound semiconductor material epitaxially grown to a crystalline substrate; as well as A field plate layer is provided on the surface of the buffer layer, wherein: The back field plate also includes a field plate region of the field plate layer that is electrically isolated from other regions of the field plate layer; The channel layer includes: A first channel layer disposed on the field plate layer, the first channel layer comprising a first compound semiconductor material; and The second channel layer includes a second compound semiconductor material in physical contact with the first channel layer.

29. The transistor of claim 28, wherein the field plate layer is epitaxial to the buffer layer.

30. The transistor of claim 28, wherein the field plate layer comprises a deactivated compound semiconductor material and the field plate region comprises an activated compound semiconductor material.

31. The transistor of claim 28, wherein the first compound semiconductor material is gallium nitride and the second compound semiconductor material is aluminum gallium nitride.

Images