Chip and mainboard

Abstract

The application provides a chip and a mainboard, the chip comprising a packaging substrate with opposite first and second surfaces, and at least one memory die arranged on the first surface of the packaging substrate. The first surface of the packaging substrate is provided with a central processing unit die, and the central processing unit die is electrically connected with each of the at least one memory die to write data into each memory die or read data from each memory die. The second surface of the packaging substrate is provided with pins for electrical connection with a printed circuit board, and the central processing unit die is also electrically connected with the pins of the second surface. By packaging the central processing unit die and the at least one memory die on one packaging substrate and electrically connecting each memory die with the central processing unit die, the central processing unit die and the memory die on the packaging substrate can work, the integration of the chip and the mainboard is improved, the area of the printed circuit board of the mainboard can be reduced, the system design is simplified, and the system reliability is improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more particularly to a chip and a motherboard. Background Technology

[0002] With the development of computers, component integration has gradually become a trend. In current technology, the connection between the central processing unit (CPU) and memory modules on a motherboard is as follows: the CPU and multiple memory connectors are located on a printed circuit board (PCB), with one memory module inserted into each connector. In other words, all the motherboard's memory is supplied by the memory modules on the PCB. Because memory modules are relatively large, and the memory connectors occupy a significant amount of PCB space, this reduces the space available for other components, resulting in a lower level of motherboard integration. Summary of the Invention

[0003] This invention provides a chip and a motherboard to improve the integration of the chip and the motherboard and reduce the area of ​​the printed circuit board of the motherboard.

[0004] In a first aspect, the present invention provides a chip comprising a packaging substrate having opposing first and second sides, and at least one memory die disposed on the first side of the packaging substrate. A central processing unit (CPU) die is also disposed on the first side of the packaging substrate, and the CPU die is electrically connected to each of the at least one memory die for writing data to or reading data from each memory die. Pins for electrical connection to a printed circuit board are also disposed on the second side of the packaging substrate, and the CPU die is also electrically connected to the pins on the second side.

[0005] In the above-described solution, by encapsulating a central processing unit (CPU) die and at least one memory die on a single packaging substrate, with each memory die electrically connected to the CPU die, operation is achieved solely through the CPU and memory dies on the packaging substrate. This improves the integration of the chip and motherboard, reducing the area of ​​the motherboard's printed circuit board. When the required memory capacity is small, there is no need to place memory connectors and memory modules on the motherboard; storage can be achieved simply through the memory dies housed within the packaging substrate. Existing technologies involve separately mounting the CPU chip and memory modules on the motherboard's printed circuit board, with the CPU chip and memory modules electrically connected via traces and vias within the printed circuit board. Compared to existing technologies, the solution in this application connects the CPU die and memory dies electrically via traces and vias within the packaging substrate. Since the area of ​​the packaging substrate is smaller than that of the motherboard's printed circuit board, the linewidth and length of the traces and vias within the packaging substrate can be smaller, resulting in higher integration. This improves the data transfer speed between the CPU die and memory dies, simplifies system design, and enhances system reliability.

[0006] In one specific implementation, the memory die is a DDR memory die to improve the chip's memory capacity and data transfer speed.

[0007] In one specific implementation, the central processing unit die and at least one memory die are flip-chip connected to the package substrate to simplify the structure and electrical connection.

[0008] In one specific implementation, a memory controller is integrated into the central processing unit die. The memory controller is electrically connected to the address and data signal bumps in each memory die to improve integration and increase the data transfer speed between the central processing unit die and the memory die.

[0009] In one specific embodiment, the packaging substrate includes stacked and insulated metal layers: a first metal layer, a second metal layer, a third metal layer, and a tenth metal layer. A central processing unit (CPU) die and at least one memory die are disposed on the first metal layer of the packaging substrate. The memory controller and address and data signal bumps in each memory die are electrically connected vias connecting the first and second metal layers and traces in the second metal layer. Pins are disposed on the tenth metal layer, and the memory controller and the pins are electrically connected vias between the first and second metal layers, traces in the second metal layer, and vias between the second and tenth metal layers. This simplifies the structure of the packaging substrate. Using fewer metal layers, the CPU die and memory die can be packaged together at a lower cost.

[0010] In one specific embodiment, a plurality of first decoupling capacitors are disposed on the first surface of the packaging substrate, each first decoupling capacitor being electrically connected to the central processing unit die and / or memory die to remove noise in the chip.

[0011] In one specific embodiment, a plurality of second decoupling capacitors are further disposed on the second surface of the packaging substrate. Each second decoupling capacitor is connected to the central processing unit die and / or memory die circuit, and the height of the second decoupling capacitor is not higher than the height of the pin. This is to better remove noise in the chip and improve chip integration.

[0012] Secondly, the present invention also provides a motherboard, which includes a printed circuit board and any of the above-mentioned chips disposed on the printed circuit board, with pins electrically connected to the printed circuit board.

[0013] In the above-described solution, by encapsulating a central processing unit (CPU) die and at least one memory die on a single packaging substrate, with each memory die electrically connected to the CPU die, operation is achieved solely through the CPU and memory dies on the packaging substrate. This improves the integration of the chip and motherboard, reducing the area of ​​the motherboard's printed circuit board. When the required memory capacity is small, there is no need to place memory connectors and memory modules on the motherboard; storage can be achieved simply through the memory dies housed within the packaging substrate. Existing technologies involve separately mounting the CPU chip and memory modules on the motherboard's printed circuit board, with the CPU chip and memory modules electrically connected via traces and vias within the printed circuit board. Compared to existing technologies, the solution in this application connects the CPU die and memory dies electrically via traces and vias within the packaging substrate. Since the area of ​​the packaging substrate is smaller than that of the motherboard's printed circuit board, the linewidth and length of the traces and vias within the packaging substrate can be smaller, resulting in higher integration. This improves the data transfer speed between the CPU die and memory dies, simplifies system design, and enhances system reliability.

[0014] In one specific implementation, the printed circuit board (PCB) also includes at least one memory connector and at least one memory module plugged into the at least one memory connector, with each memory connector electrically connected to the central processing unit (CPU) die. The PCB also includes a BIOS chip, which is electrically connected to both the CPU die and each memory connector to drive at least one memory die and at least one memory module. In applications requiring large-capacity memory, by designing memory connectors on the PCB and configuring them via the BIOS chip, the memory dies within the packaging substrate and the memory modules on the PCB can work together, solving the wiring problem of one-to-two or one-to-many connections on the packaging substrate and motherboard, and resolving the compatibility issue between the memory dies on the packaging substrate and the memory modules on the motherboard. Attached Figure Description

[0015] Figure 1 This is a cross-sectional structural diagram of a chip provided in an embodiment of the present invention;

[0016] Figure 2 for Figure 1 The diagram shown is a top view of the structure of a chip;

[0017] Figure 3 for Figure 1 The diagram shown is a top-view structural schematic of a chip;

[0018] Figure 4 This is a cross-sectional structural diagram of a packaging structure provided in an embodiment of the present invention;

[0019] Figure 5This is a cross-sectional structural diagram of a motherboard provided in an embodiment of the present invention.

[0020] Figure label:

[0021] 10-Packaging substrate; 11-First side; 12-Second side; 13-Pin.

[0022] 14-Bump 15-Trace 16-Via 20-CPU Die

[0023] 21-Memory controller; 30-Memory die; 41-First decoupling capacitor

[0024] 42-Second decoupling capacitor; 50-Printed circuit board; 51-Memory connector

[0025] 52-Memory module 53-BIOS chip Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] To facilitate understanding of the chip provided in the embodiments of the present invention, the application scenarios of the chip provided in the embodiments of the present invention will be described first. This chip is used in computer equipment such as servers. The chip will then be described in detail below with reference to the accompanying drawings.

[0028] refer to Figure 1 , Figure 2 and Figure 3 The chip provided in this embodiment of the invention includes a packaging substrate 10 having opposing first surfaces 11 and second surfaces 12, and at least one memory die 30 disposed on the first surface 11 of the packaging substrate 10. A central processing unit (CPU) die 20 is also disposed on the first surface 11 of the packaging substrate 10, and the CPU die 20 is electrically connected to each of the at least one memory die 30 to write data to or read data from each memory die 30. Pins 13 for electrical connection to a printed circuit board 50 are also disposed on the second surface 12 of the packaging substrate 10, and the CPU die 20 is also electrically connected to the pins 13 on the second surface 12.

[0029] In the above-described solution, by encapsulating the CPU die 20 and at least one memory die 30 on a single packaging substrate 10, with each memory die 30 electrically connected to the CPU die 20, operation is achieved solely through the CPU die 20 and memory die 30 on the packaging substrate 10. This improves the integration of the chip and motherboard, reducing the area of ​​the motherboard's printed circuit board 50. When the required memory capacity is small, there is no need to install memory connectors and memory modules on the motherboard; storage can be achieved simply through the memory dies 30 located within the packaging substrate 10. Existing technology involves separately mounting the CPU chip and memory modules on the motherboard's printed circuit board 50, with the CPU chip and memory modules electrically connected via traces 15 and vias 16 within the printed circuit board 50. Compared with the prior art, the solution of this application electrically connects the central processing unit die 20 and the memory die 30 through traces 15 and vias 16 within the packaging substrate 10. Since the area of ​​the packaging substrate 10 is smaller than that of the printed circuit board 50 of the motherboard, the line width and length of the traces 15 and vias 16 within the packaging substrate 10 can be smaller, resulting in higher integration. This improves the data transfer speed between the central processing unit die 20 and the memory die 30, simplifies system design, and enhances system reliability. The arrangement of the above components will be described in detail below with reference to the accompanying drawings.

[0030] refer to Figure 1 The packaging substrate 10 has opposing first surfaces 11 and second surfaces 12, wherein Figure 1 The first surface 11 shown is the upper surface of the packaging substrate 10, and the second surface 12 is the lower surface of the packaging substrate 10. Pins 13 are provided on the second surface 12 of the packaging substrate 10. After packaging, the pins 13 are exposed outside the packaging layer and are used to connect to the printed circuit board 50 of the motherboard. When setting the pins 13, the pins 13 can be as follows: Figure 1 The ball pin 13 shown in the BGA package can also be the pin pin 13 in the LGA package.

[0031] refer to Figure 1 and Figure 2 A CPU die 20 is disposed on the first surface 11 of the packaging substrate 10, and the CPU die 20 is also electrically connected to pins 13 on the second surface 12 of the packaging substrate 10. During installation, the CPU die 20 can be flip-chip connected to the first surface 11 of the packaging substrate 10. Specifically, on the lower surface of the CPU die 20 (as shown in the image), a CPU die 20 is disposed on the first surface 11 of the packaging substrate 10. Figure 1(The structure shown is for reference only) Bumps 14 are provided, and pads for electrical connection with the CPU die 20 are provided on the first surface 11 of the package substrate 10. This allows the CPU die 20 to be directly flip-mounted onto the corresponding pads on the first surface 11 of the package substrate 10, eliminating the need for wire bonding and simplifying the structure and electrical connection method. Figure 1 As shown, the bumps 14 on the central processing unit die 20 are electrically connected to the pins 13 on the second side 12 of the packaging substrate 10 through the traces 15 and vias 16 in the packaging substrate 10.

[0032] Continue to refer to Figure 1 and Figure 2 At least one memory die 30 is disposed on the first surface 11 of the packaging substrate 10, and each memory die 30 is electrically connected to the central processing unit die 20. Specifically, the number of memory dies 30 can be any value of at least one, such as 1, 2, 3, 4, 6, or 8. When there are multiple memory dies 30, refer to... Figure 2 Multiple memory dies 30 can be arranged side-by-side on both sides of the central processing unit die 20 to facilitate electrical connection between the central processing unit die 20 and each memory die 30. When determining the type of each memory die 30, it can be a DDR memory die 30 to improve the chip's memory capacity and data transfer speed. Specifically, the memory die 30 can be a relatively mature DDR3, DDR4, or DDR5 memory die 30. Of course, the memory die 30 can also be a DDR6 or DDR7 memory die 30 currently under development. That is, as long as the central processing unit die 20 and the memory dies 30 are of the same type, enabling the central processing unit die 20 to write data to or read data from the memory dies 30, it falls within the scope of protection of this invention.

[0033] When each memory die 30 is attached to the first surface 11 of the package substrate 10, each memory die 30 can be attached to the package substrate 10 in a flip-chip manner to simplify the structure and electrical connection method. Specifically, on the lower surface of each memory die 30 (with... Figure 1 (The structure shown is for reference only) is provided with bumps 14, and pads for electrical connection with the corresponding memory die 30 are provided on the first surface 11 of the packaging substrate 10. The memory die 30 can be directly flip-mounted onto the corresponding pads on the first surface 11 of the packaging substrate 10, thereby eliminating the need for bonding wire connection, simplifying the structure and facilitating connection.

[0034] When implementing the electrical connection between the central processing unit die 20 and each memory die 30, such as Figure 1As shown, the central processing unit die 20 and each memory die 30 are electrically connected via traces 15 and vias 16 in the package substrate 10. For example, see Reference Figure 1 A memory controller 21 can be integrated into the central processing unit (CPU) die 20. Each memory die 30 has address signal bumps 14 and data signal bumps 14. The memory controller 21 is electrically connected to the address and data signal bumps 14 in each memory die 30. By integrating the memory controller 21 into the CPU die 20, the integration density is improved. Compared with the prior art, which places the memory controller 21 on the motherboard or integrates it into the CPU chip, the solution of this application can improve the data transfer speed between the CPU die 20 and the memory die 30.

[0035] When specifically implementing the routing of trace 15 within the packaging substrate 10, refer to Figure 4 The packaging substrate 10 includes stacked and insulated metal layers: a first metal layer, a second metal layer, a third metal layer, and a tenth metal layer. The first metal layer is a power plane layer. The second metal layer is a wiring layer. The third metal layer is a ground layer. The fourth metal layer is a wiring layer. The fifth and sixth metal layers are core layers, respectively providing power and ground. The seventh metal layer is a wiring layer. The eighth metal layer is a ground layer, the ninth metal layer is a power layer, and the tenth metal layer is a ground layer. A central processing unit die 20 and at least one memory die 30 can be disposed on the first metal layer of the packaging substrate 10; that is, pads electrically connected to the central processing unit die 20 and pads electrically connected to at least one memory die 30 are provided on the first metal layer. (Reference) Figure 1The memory controller 21 is electrically connected to the address and data signal bumps 14 in each memory die 30 via vias 16 connecting the first and second metal layers and traces 15 in the second metal layer. Specifically, the bumps 14 on the memory controller 21 are first electrically connected to the corresponding pads on the first metal layer. Then, the signal lines of the memory controller 21 are connected to the second metal layer via vias 16 between the first and second metal layers. Next, the signal lines of the memory controller 21 are guided to the position directly below each memory die 30 via traces 15 in the second metal layer. Finally, they are connected to the pads electrically connected to the data and address signal bumps 14 on the memory die 30 via vias 16 between the first and second metal layers, thus achieving the electrical connection between the memory controller 21 and each memory die 30. Pins 13 are located on the tenth metal layer. The memory controller 21 and pins 13 are electrically connected via vias 16 between the first and second metal layers, traces 15 in the second metal layer, and vias 16 between the second and tenth metal layers. Specifically, the bump 14 on the memory controller 21 is first electrically connected to the corresponding pad on the first metal layer. Then, the signal line of the memory controller 21 is connected to the second metal layer through the via 16 between the first and second metal layers. Next, the signal line of the memory controller 21 is guided to the position directly above the corresponding pin 13 through the trace 15 in the second metal layer, and then electrically connected through the via 16 between the second and tenth metal layers. This simplifies the structure of the packaging substrate 10 and allows for the low-cost, integrated packaging of the central processing unit die 20 and the memory die 30 using fewer metal layers.

[0036] refer to Figure 1 and Figure 2 A plurality of first decoupling capacitors 41 may also be disposed on the first surface 11 of the packaging substrate 10, each first decoupling capacitor 41 being electrically connected to the central processing unit die 20 and / or the memory die 30 to remove noise in the chip. The number of first decoupling capacitors 41 can be any value, such as 2, 3, 4, or 5. (Reference) Figure 2 Multiple first decoupling capacitors 41 can be arranged on both sides of multiple memory dies 30 and central processing unit die 20 to facilitate electrical connection. Each first decoupling capacitor 41 is disposed on a first metal layer. Each first decoupling capacitor 41 can be electrically connected only to the central processing unit die 20 and not to the memory die 30; it can also be electrically connected only to the memory die 30 and not to the central processing unit die 20; or it can be electrically connected to both the central processing unit and the memory die 30. In specific connection, each first decoupling capacitor 41 is electrically connected to the central processing unit die 20 and / or the memory die 30 through the traces 15 and vias 16 in the package substrate 10.

[0037] refer to Figure 1 and Figure 3 Multiple second decoupling capacitors 42 can be disposed on the second surface 12 of the packaging substrate 10. Each second decoupling capacitor 42 is connected to the central processing unit die 20 and / or the memory die 30 circuit, and the height of the second decoupling capacitor 42 is not higher than the height of the pin 13. This is to better remove noise in the chip and improve chip integration. Specifically, the number of second decoupling capacitors 42 can be any value, such as 2, 3, 4, or 5. (Reference) Figure 3 Multiple second decoupling capacitors 42 can be arranged on both sides of pin 13 for easy setup and electrical connection. Each second decoupling capacitor 42 can be electrically connected only to the CPU die 20 and not to the memory die 30; it can also be electrically connected only to the memory die 30 and not to the CPU die 20; or it can be electrically connected to both the CPU and the memory die 30. In specific connection, each second decoupling capacitor 42 can be disposed on the tenth metal layer, and each second decoupling capacitor 42 is electrically connected to the CPU die 20 and / or the memory die 30 through the traces 15 and vias 16 in the package substrate 10. In addition, in order to prevent the second decoupling capacitors 42 from interfering with the connection between the pin 13 on the package substrate 10 and the printed circuit board 50 of the motherboard, the height of the second decoupling capacitors 42 should not be higher than the height of the pin 13 when necessary. Specifically, the height of the second decoupling capacitors 42 can be equal to or lower than the height of the pin 13. For example, when the height of pin 13 is 0.5mm, the height of the second decoupling capacitor 42 can be no greater than 0.5mm.

[0038] By encapsulating the CPU die 20 and at least one memory die 30 on a single packaging substrate 10, with each memory die 30 electrically connected to the CPU die 20, operation is achieved solely through the CPU die 20 and memory die 30 on the packaging substrate 10. This improves the integration of the chip and motherboard, reducing the area of ​​the motherboard's printed circuit board 50. When the required memory capacity is small, there is no need to place memory connectors and memory modules on the motherboard; storage can be achieved simply through the memory dies 30 located within the packaging substrate 10. Existing technology involves separately mounting the CPU chip and memory modules on the motherboard's printed circuit board 50, with the CPU chip and memory modules electrically connected via traces 15 and vias 16 in the printed circuit board 50. Compared with the prior art, the solution of this application connects the central processing unit die 20 and the memory die 30 through the traces 15 and vias 16 in the packaging substrate 10. Since the area of ​​the packaging substrate 10 is smaller than that of the printed circuit board 50 of the motherboard, the line width and length of the traces 15 and vias 16 in the packaging substrate 10 can be smaller, and the integration is higher. This improves the data transmission speed between the central processing unit die 20 and the memory die 30, simplifies the system design, and improves the reliability of the system.

[0039] In addition, embodiments of the present invention also provide a motherboard, see reference. Figure 5 The motherboard includes a printed circuit board 50 and any of the aforementioned chips disposed on the printed circuit board 50, with pins 13 electrically connected to the printed circuit board 50. By encapsulating the central processing unit die 20 and at least one memory die 30 on a packaging substrate 10, and with each memory die 30 electrically connected to the central processing unit die 20, operation can be achieved through the central processing unit die 20 and memory die 30 on the packaging substrate 10, thereby improving the integration of the chip and the motherboard and reducing the area of ​​the printed circuit board 50 of the motherboard. When the required memory capacity is small, there is no need to set the memory connector 51 and memory module 52 on the motherboard; storage can be achieved simply through the memory die 30 disposed within the packaging substrate 10. The prior art involves separately setting the central processing unit chip and memory module 52 on the printed circuit board 50 of the motherboard, with the central processing unit chip and memory module 52 electrically connected through traces 15 and vias 16 in the printed circuit board 50. Compared with the prior art, the solution of this application connects the central processing unit die 20 and the memory die 30 through the traces 15 and vias 16 in the packaging substrate 10. Since the area of ​​the packaging substrate 10 is smaller than that of the printed circuit board 50 of the motherboard, the line width and length of the traces 15 and vias 16 in the packaging substrate 10 can be smaller, and the integration is higher. This improves the data transmission speed between the central processing unit die 20 and the memory die 30, simplifies the system design, and improves the reliability of the system.

[0040] Continue to refer to Figure 5 The printed circuit board 50 may also include at least one memory connector 51 and at least one memory module 52 plugged into the memory connector 51. Each memory connector 51 is electrically connected to the central processing unit die 20 to expand the motherboard's memory capacity. The memory module 52 can be a DIMM memory module 52. One memory module 52 is plugged into each memory connector 51. The memory connector 51 can be soldered onto the printed circuit board 50. The number of memory modules 52 and memory connectors 51 can be any value, such as 1, 2, 3, or 4. The number of memory modules 52 is mainly related to the required memory capacity. More memory modules 52 can be used when a larger memory capacity is required, and fewer memory modules 52 can be used when a smaller memory capacity is required. In fact, if the memory die 30 in the chip can meet the memory capacity requirements, memory modules 52 and memory connectors 51 may not be necessary. Each memory connector 51 can be electrically connected to the pin 13 on the chip that is electrically connected to the CPU die 20 via the trace 15 and via 16 in the printed circuit board 50, and then electrically connected to the CPU die 20 via the corresponding pin 13.

[0041] Continue to refer to Figure 5 A BIOS chip 53 is also provided on the printed circuit board 50. The BIOS chip 53 is electrically connected to both the central processing unit die 20 and each memory connector 51 to drive at least one memory die 30 and at least one memory module 52 to work. In applications requiring large-capacity memory, by designing memory connectors 51 on the printed circuit board 50 and configuring them through the BIOS chip 53, the memory dies 30 in the packaging substrate 10 and the memory modules 52 on the printed circuit board 50 can work together. At the same time, signal reflection from the memory dies 30 on the packaging substrate 10 is reduced, solving the wiring problem of one-to-two or one-to-many on the packaging substrate 10 and the motherboard, and solving the compatibility problem between the memory dies 30 on the packaging substrate 10 and the memory modules 52 on the motherboard. Specifically, when the BIOS chip 53 is electrically connected to the CPU die 20, the BIOS chip 53 is electrically connected to its pins 13 via traces 15 and vias 16 within the printed circuit board 50. These pins 13 are electrically connected to both the CPU die 20 and the memory die 30, enabling the BIOS chip 53 to drive the memory die 30 within the chip. When the BIOS chip 53 is connected to the memory connector 51, the BIOS chip 53 can also be electrically connected via traces 15 and vias 16 within the printed circuit board 50.

[0042] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A chip, characterized in that, include: A packaging substrate having opposing first and second sides, the packaging substrate comprising a first metal layer, a second metal layer, a third metal layer, and a fourth to tenth metal layers stacked and insulated from each other, wherein the first metal layer is a power plane layer, the second metal layer is a wiring layer, the third metal layer is a ground layer, the fourth metal layer is a wiring layer, the fifth and sixth metal layers are core layers, respectively providing power and ground, the seventh metal layer is a wiring layer, the eighth metal layer is a ground layer, the ninth metal layer is a power layer, and the tenth metal layer is a ground layer, wherein the first metal layer is close to the first side, and the tenth metal layer is close to the second side; At least one memory die is disposed on the first surface of the packaging substrate, and the lower surface of each memory die is provided with address and data signal bumps. Central processing unit die disposed on the first side of the packaging substrate; The central processing unit die integrates a memory controller. The memory controller is electrically connected to the address and data signal bumps in each of the at least one memory die through vias connecting the first metal layer and the second metal layer, and through traces in the second metal layer, so as to write data to each memory die or read data from each memory die. The second surface of the packaging substrate has pins for electrical connection with a printed circuit board, and the memory controller is also electrically connected to the pins on the second surface.

2. The chip as described in claim 1, characterized in that, The memory die is a DDR memory die.

3. The chip as described in claim 1, characterized in that, The central processing unit die and at least one memory die are connected to the packaging substrate in a flip-chip manner.

4. The chip as described in claim 1, characterized in that, The pin is disposed on the tenth metal layer, and the memory controller is electrically connected to the pin through a via between the first metal layer and the second metal layer, a trace in the second metal layer, and a via between the second metal layer and the tenth metal layer.

5. The chip as described in claim 1, characterized in that, A plurality of first decoupling capacitors are disposed on the first surface of the packaging substrate, and each first decoupling capacitor is electrically connected to the central processing unit die and / or the memory die.

6. The chip as described in claim 5, characterized in that, A plurality of second decoupling capacitors are also provided on the second side of the packaging substrate, and each second decoupling capacitor is connected to the central processing unit die and / or the memory die circuit. Furthermore, the height of the second decoupling capacitor is not higher than the height of the pin.

7. A motherboard, characterized in that, include: Printed circuit boards; The chip as described in any one of claims 1 to 6 is disposed on the printed circuit board, wherein the pins are electrically connected to the printed circuit board.

8. The motherboard as described in claim 7, characterized in that, The printed circuit board is also provided with at least one memory connector and at least one memory module plugged into the at least one memory connector, and each memory connector is electrically connected to the central processing unit die; The printed circuit board is also provided with a BIOS chip; the BIOS chip is electrically connected to both the central processing unit die and each memory connector to drive the at least one memory die and the at least one memory module to work.

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