An epitaxial wafer for Micro-LED and a preparation method thereof

Abstract

The present invention relates to the field of semiconductor technology, and in particular to an epitaxial wafer for Micro-LED and a preparation method thereof, which is different in that it includes the following steps: Step 1: Select a substrate; Step 2: Sequentially grow a buffer layer, a stress and warpage control layer, an N-type semiconductor layer, an active layer, an electron blocking layer and a P-type semiconductor layer on the substrate; Step 3: Growing a contact layer on the P-type semiconductor layer; Step 4: After the above epitaxial growth is completed, anneal the epitaxial wafer, and then reduce the temperature of the epitaxial wafer to room temperature to complete the preparation. The present invention can effectively control the warpage performance and stress during the bottom epitaxy, and effectively improve the consistency of the edge and center yields.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an epitaxial wafer applied to Micro-LED and a preparation method thereof. Background Art

[0002] Light Emitting Diode (LED) is a semiconductor electronic component that can emit light. Gallium nitride (GaN) has good thermal conductivity, high temperature resistance, acid and alkali resistance, high hardness and other excellent properties, making GaN-based LEDs receive more and more attention and research.

[0003] Epitaxial wafers are the primary finished products in the LED manufacturing process. Existing LED epitaxial wafers include a substrate, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer, which are stacked on the substrate in sequence. The substrate is used to provide a growth surface for the epitaxial material, the N-type semiconductor layer is used to provide electrons for compound luminescence, the P-type semiconductor layer is used to provide holes for compound luminescence, and the active layer is used for radiation compound luminescence of electrons and holes.

[0004] The number of electrons provided by the N-type semiconductor is much greater than the number of holes in the P-type semiconductor layer. In addition, the volume of electrons is much smaller than the volume of holes, resulting in the number of electrons injected into the active layer being much greater than the number of holes. At the same time, due to the difference in lattice constants between the substrate (silicon carbide, sapphire, silicon wafer, etc.) and gallium nitride, stress and defects will accumulate during the epitaxy process. These stresses and defects will reduce the quality of epitaxial growth and element doping, thereby affecting the quantum efficiency of the light-emitting diode; in addition, gallium nitride epitaxy requires a higher growth temperature. As the size of the epitaxial wafer increases, the difference between the edge and the center will be severely amplified, limiting the promotion and application of Micro-LED.

[0005] In order to avoid the difference between edge yield and center, a low-temperature AlGaN layer is usually set on the substrate to alleviate warping and stress accumulation, improve the excessive warping during high-temperature growth of the bottom layer, and adjust the warping of the epitaxial wafer during MQW growth.

[0006] In the process of implementing the present invention, the inventors found that the prior art has at least the following problems:

[0007] The low-temperature AlGaN layer improves the lattice mismatch and stress between the substrate and the GaN, but has limited effect on the adjustment of the thick growth warp of the GaN bottom layer. In addition, defects and stress will be further introduced during the epitaxial growth of the bottom GaN, gradually accumulating to affect the stress and indium incorporation in the quantum well region, and has limited effect on the edge yield and well region stress control.

[0008] In view of this, in order to overcome the above-mentioned technical defects, providing an epitaxial wafer applied to Micro-LED and a preparation method thereof has become an urgent problem to be solved in the art. Summary of the invention

[0009] The purpose of the present invention is to overcome the shortcomings of the prior art and provide an epitaxial wafer and a preparation method thereof for Micro-LED, which can effectively control the warping performance and stress of the bottom layer during epitaxy and effectively improve the consistency of edge and center yield.

[0010] In order to solve the above technical problems, the technical solution of the present invention is: a method for preparing an epitaxial wafer applied to Micro-LED, which is different in that it includes the following steps:

[0011] Step 1: Select a substrate;

[0012] Step 2: sequentially growing a buffer layer, a stress and warpage control layer, an N-type semiconductor layer, an active layer, an electron blocking layer and a P-type semiconductor layer on the substrate;

[0013] Step 3: growing a contact layer on the P-type semiconductor layer;

[0014] Step 4: After the above-mentioned epitaxial growth is completed, the epitaxial wafer is annealed, and then the temperature of the epitaxial wafer is lowered to room temperature to complete the preparation.

[0015] According to the above technical solution, in step 1, the temperature is controlled to be 1000-1200° C., the substrate is annealed for 6-10 minutes in a hydrogen atmosphere, and the substrate is nitrided.

[0016] According to the above technical solution, step 2 includes the following sub-steps:

[0017] Step 21: Control the temperature to 450-600°C and the pressure to 200-500 torr to grow a GaN nucleation layer, and then increase the temperature to 950-1200°C to grow GaN three-dimensional and two-dimensional coating layers. The nucleation layer, GaN three-dimensional and two-dimensional coating layers are collectively referred to as a GaN buffer layer.

[0018] Step 22: controlling the temperature to 950-1100° C. and the pressure to 70-200 torr, growing a stress and warpage control layer on the gallium nitride buffer layer, the overall stress and warpage control layer thickness is 20-60 nm, the growth atmosphere of the stress and warpage control layer is mainly nitrogen, the gas volume ratio of nitrogen to hydrogen is in the range of 1:1-10:1, and the ammonia gas accounts for 0.25-0.40 in the entire carrier gas system;

[0019] Step 23: growing an N-type semiconductor layer on the stress and warpage control layer at a temperature of 950-1200° C. and a pressure range of 200-500 torr;

[0020] Step 24: growing an active layer on the N-type semiconductor layer; the growth temperature of the quantum well is 720-829° C., and the growth pressure of the quantum well is 100-500 torr; the growth temperature of the quantum barrier is 850-959° C., and the growth pressure of the quantum barrier is 100-500 torr;

[0021] Step 25: controlling the temperature to 850-1080° C. and the pressure to 200-500 torr, and growing an electron blocking layer on the active layer;

[0022] Step 26: Control the temperature to 850-1080° C. and the pressure to 100-300 torr to grow a P-type semiconductor layer on the electron blocking layer.

[0023] According to the above technical solution, the stress and warpage control layer is composed of a lower AlN layer and an upper Al x Ga 1-x N layers are stacked, wherein 0≤x<0.4, the AlN layer and Al x Ga 1-x The N layer thickness ratio range is 1:10~1:2.

[0024] According to the above technical solution, in step 3, the temperature is controlled to be 850-1050° C. and the pressure is controlled to be 100-300 torr, and a contact layer is grown on the P-type semiconductor layer.

[0025] According to the above technical solution, in step 4, the temperature is first lowered to 650-850° C., the epitaxial wafer is annealed for 5-15 minutes in a nitrogen atmosphere, and then the temperature of the epitaxial wafer is lowered to room temperature.

[0026] An epitaxial wafer for Micro-LED prepared according to the method described in the above technical solution is different in that it includes a substrate, and a buffer layer, a stress and warpage control layer, an N-type semiconductor layer, an active layer, an electron blocking layer, a P-type semiconductor layer and a contact layer grown from bottom to top on the substrate.

[0027] According to the above technical solution, the stress and warpage control layer is composed of a lower AlN layer and an upper Al x Ga 1-x N layers are stacked, wherein 0≤x<0.4, the AlN layer and Al x Ga 1-x The N layer thickness ratio ranges from 1:10 to 1:2, and the overall stress and warpage control layer thickness is 20 to 60 nm.

[0028] According to the above technical solution, a plurality of InGaN insertion layers are inserted into the stress and warpage control layer.

[0029] According to the above technical solution, the InGaN insertion layer has an In molar content of 5% to 20% and a thickness of 3 to 10 nm. The insertion position is at 1 / 5, 1 / 3, and 3 / 4 of the overall area of ​​the stress and warpage control layer. The In content gradually increases and the thickness also tends to increase.

[0030] Based on the above scheme, the present invention discloses an epitaxial wafer and a preparation method thereof for Micro-LED, which realizes the reduction of the bottom layer growth warping and the release of the bottom layer stress through reasonable thickness ratio and Al component optimization. At the same time, the InGaN insertion layer reasonably optimizes the accumulation of bottom layer polarization and stress, and adjusts the warping difference when growing quantum wells after the bottom layer warping is cooled, so that the growth warping of the well area approaches the plane, improves the edge wavelength yield, and thus increases the effective output. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the overall structure of an epitaxial wafer according to an embodiment of the present invention;

[0032] Wherein: 10-substrate; 20-buffer layer; 30-stress and warpage control layer (301-AlN layer, 302-Al x Ga 1-x N layer); 40- N-type semiconductor layer; 50- active layer; 60- electron blocking layer; 70- P-type semiconductor layer. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0034] Hereinafter, many aspects of the present invention will be better understood with reference to the accompanying drawings. The components in the accompanying drawings are not necessarily drawn to scale. Instead, emphasis is placed on clearly illustrating the components of the present invention. In addition, in several views of the accompanying drawings, the same reference numerals indicate corresponding parts.

[0035] As used herein, the words "exemplary" or "illustrative" mean used as an example, instance, or illustration. Any implementation described herein as "exemplary" or "illustrative" is not necessarily to be construed as preferred or advantageous over other implementations. All of the implementations described below are exemplary implementations, which are provided to enable those skilled in the art to make and use embodiments of the present disclosure and are not intended to limit the scope of the disclosure, which is defined by the claims. In other implementations, well-known features and methods are described in detail so as not to obscure the present invention. For the purposes of the description herein, the terms "upper," "lower," "left," "right," "front," "rear," "vertical," "horizontal," and their derivatives will be used interchangeably. Figure 1 The invention is directed to the invention of the present invention. Moreover, there is no intention to be bound by any express or implied theory given in the preceding technical field, background technology, summary of the invention or the detailed description below. It should also be understood that the specific devices and processes shown in the drawings and described in the following description are simple exemplary embodiments of the inventive concepts defined in the appended claims. Therefore, specific dimensions and other physical characteristics related to the embodiments disclosed herein should not be understood as limiting unless the claims explicitly state otherwise.

[0036] Please refer to Figure 1 The present invention provides a method for preparing an epitaxial wafer for Micro-LED, which is different in that it comprises the following steps:

[0037] Step 1: Select a substrate 10;

[0038] Step 2: sequentially growing a buffer layer 20 , a stress and warpage control layer 30 , an N-type semiconductor layer 40 , an active layer 50 , an electron blocking layer 60 and a P-type semiconductor layer 70 on the substrate 10 ;

[0039] Step 3: growing a contact layer on the P-type semiconductor layer 70;

[0040] Step 4: After the above-mentioned epitaxial growth is completed, the epitaxial wafer is annealed, and then the temperature of the epitaxial wafer is lowered to room temperature to complete the preparation.

[0041] Specifically, in step 1, the temperature is controlled to be 1000-1200° C. (preferably 1100° C.), the substrate 10 is annealed for 6-10 minutes (preferably 8 minutes) in a hydrogen atmosphere, and the substrate 10 is nitrided.

[0042] The above steps clean the surface of the substrate and prevent impurities from being incorporated into the epitaxial wafer, which is beneficial to improving the growth quality of the epitaxial wafer.

[0043] Specifically, step 2 includes the following sub-steps:

[0044] Step 21: Control the temperature to 450-600°C and the pressure to 200-500 torr to grow a gallium nitride nucleation layer, and then increase the temperature to 950-1200°C to grow gallium nitride three-dimensional and two-dimensional coating layers. The nucleation layer, gallium nitride three-dimensional and two-dimensional coating layers are collectively referred to as a gallium nitride buffer layer 20; the buffer layer 20 is arranged between the substrate 10 and the stress and warpage control layer 30 to relieve the stress and defects caused by the lattice mismatch between the substrate material and gallium nitride, and provide a nucleation center for the epitaxial growth of gallium nitride material.

[0045] In the specific implementation, the buffer layer is a thin layer of gallium nitride that is first grown at low temperature on a patterned substrate, so it is also called a low-temperature buffer layer. Gallium nitride is then grown vertically in the low-temperature buffer layer to form multiple independent three-dimensional island structures, called a three-dimensional nucleation layer; then gallium nitride is grown laterally on all three-dimensional island structures and between each three-dimensional island structure to form a two-dimensional planar structure, called a two-dimensional recovery layer; finally, a thicker layer of gallium nitride is grown at high temperature on the two-dimensional growth layer, called an intrinsic gallium nitride layer. In this embodiment, the three-dimensional nucleation layer, the two-dimensional recovery layer and the intrinsic gallium nitride layer are collectively referred to as a gallium nitride buffer layer. The thickness of the gallium nitride buffer layer 20 can be 1μm~5μm, preferably 3μm.

[0046] Step 22: controlling the temperature to 950-1100° C. and the pressure to 70-200 torr, growing a stress and warpage control layer 30 on the gallium nitride buffer layer 20, the overall stress and warpage control layer 30 having a thickness of 20-60 nm, and the growth atmosphere of the stress and warpage control layer 30 being mainly nitrogen, the gas volume ratio of nitrogen to hydrogen being in the range of 1:1-10:1, and the ammonia gas in the entire carrier gas system being in the range of 0.25-0.40;

[0047] Step 23: growing an N-type semiconductor layer 40 on the stress and warpage control layer 30 at a temperature of 950-1200° C. and a pressure range of 200-500 torr;

[0048] Step 24: growing an active layer 50 on the N-type semiconductor layer 40; the growth temperature of the quantum well is 720-829° C. (preferably 760° C.), and the growth pressure of the quantum well is 100-500 torr (preferably 300 torr); the growth temperature of the quantum barrier is 850-959° C. (preferably 900° C.), and the growth pressure of the quantum barrier is 100-500 torr (preferably 300 torr);

[0049] Step 25: controlling the temperature to 850-1080° C. (preferably 960° C.) and the pressure to 200-500 torr (preferably 350 torr), and growing an electron blocking layer 60 on the active layer 50;

[0050] Step 26 : Control the temperature to 850-1080° C. (preferably 960° C.) and the pressure to 100-300 torr (preferably 200 torr) to grow a P-type semiconductor layer 70 on the electron blocking layer 60 .

[0051] Specifically, the stress and warpage control layer 30 is composed of a lower AlN layer 301 and an upper Al x Ga 1-x N layer 302 is stacked, wherein 0≤x<0.4, the AlN layer 301 and Al x Ga 1-x The thickness ratio of the N layer 302 is in the range of 1:10 to 1:2. The AlN layer 301 has a significant effect on stress and can adjust the effective doping of indium in the well region. The optimized combination of 301 and 302 can control the bottom layer warpage while improving the stress in the well region. On the one hand, it can effectively improve the yield performance of the edge chip, and on the other hand, it can improve the quantum efficiency of the entire light-emitting diode.

[0052] Specifically, in step 3, the temperature is controlled to be 850-1050° C. (preferably 950° C.) and the pressure is controlled to be 100-300 torr (preferably 200 torr), and a contact layer is grown on the P-type semiconductor layer 70 .

[0053] Specifically, in step 4, the temperature is first lowered to 650-850° C. (preferably 750° C.), the epitaxial wafer is annealed in a nitrogen atmosphere for 5-15 minutes (preferably 10 minutes), and then the temperature of the epitaxial wafer is lowered to room temperature.

[0054] An epitaxial wafer for Micro-LED prepared according to the method described in the above technical solution is different in that it includes a substrate 10, and a buffer layer 20, a stress and warpage control layer 30, an N-type semiconductor layer 40, an active layer 50, an electron blocking layer 60, a P-type semiconductor layer 70 and a contact layer grown from bottom to top on the substrate 10. The gallium nitride buffer layer 20, the stress and warpage control layer 30, the N-type semiconductor layer 40, the active layer 50, the electron blocking layer 60 and the P-type semiconductor layer 70 are stacked on the substrate 10 in sequence.

[0055] Specifically, the stress and warpage control layer 30 is composed of a lower AlN layer 301 and an upper Al x Ga 1-x N layer 302 is stacked, wherein 0≤x<0.4, the AlN layer 301 and Al x Ga 1-x The thickness ratio of the N layer 302 is in the range of 1:10 to 1:2, and the thickness of the overall stress and warpage control layer 30 is in the range of 20 to 60 nm.

[0056] Specifically, a plurality of InGaN insertion layers are inserted into the stress and warpage control layer 30 .

[0057] Specifically, the InGaN insertion layer has an In molar content of 5% to 20% and a thickness of 3 to 10 nm. The insertion positions are at 1 / 5, 1 / 3, and 3 / 4 of the entire area of ​​the stress and warpage control layer 30. The In content gradually increases and the thickness also tends to increase.

[0058] Specifically, the substrate 10 may be made of sapphire or silicon wafer, and the main material of sapphire is aluminum oxide, such as sapphire with a crystal orientation of

[0001] . The gallium nitride buffer layer 20 is a low-temperature gallium nitride layer, and the material of the N-type semiconductor layer 40 may be gallium nitride doped with N-type (such as silicon or germanium). The active layer 50 may include a plurality of quantum wells and a plurality of quantum barriers, and the plurality of quantum wells and the plurality of quantum barriers are alternately stacked; the material of the quantum well may be indium gallium nitride (InGaN), such as InGaN. x Ga 1-x N, 0<x<1, the material of the quantum barrier can be gallium nitride. The electron blocking layer 60 is made of Al-doped GaN, and the material of the P-type semiconductor layer 70 can be P-type doped (such as magnesium) gallium nitride.

[0059] Furthermore, the thickness of the N-type semiconductor layer 40 may be 1 μm to 5 μm, preferably 3 μm; the doping concentration of the N-type dopant in the N-type semiconductor layer 40 may be 10 18 / cm 3 ~10 20 / cm 3 , preferably 10 19 / cm 3 The thickness of the quantum well can be 3nm~4nm, preferably 3.5nm; the thickness of the quantum barrier can be 8nm~15nm, preferably 10nm; the number of quantum wells is the same as the number of quantum barriers, and the number of quantum barriers can be 5~11, preferably 8. The thickness of the electron blocking layer 60 is 20-100nm, and the Al molar doping concentration is 0-0.25. The thickness of the P-type semiconductor layer 70 can be 10nm~100nm, preferably 50nm; the doping concentration of the P-type dopant in the P-type semiconductor layer 70 can be 10 18 / cm 3 ~ 10 20 / cm 3 , preferably 10 19 / cm 3 .

[0060] Controlling temperature and pressure refers to controlling the temperature and pressure in the reaction chamber for growing epitaxial wafers, specifically the reaction chamber of the metal-organic chemical vapor deposition (MOCVD) equipment. In implementation, trimethylgallium or triethylgallium is used as the gallium source, high-purity ammonia is used as the nitrogen source, trimethylindium is used as the indium source, trimethylaluminum is used as the aluminum source, silane is used as the silicon source, tetramethylgermanium is used as the germanium source, and bismuthocene magnesium is used as the magnesium source.

[0061] The above contents are further detailed descriptions of the present invention in combination with specific implementation methods, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for preparing an epitaxial wafer for Micro-LED, characterized in that: The following steps are involved: Step 1: Select a substrate; Step 2: sequentially growing a buffer layer, a stress and warpage control layer, an N-type semiconductor layer, an active layer, an electron blocking layer and a P-type semiconductor layer on the substrate; Step 3: growing a contact layer on the P-type semiconductor layer; Step 4: After the epitaxial growth is completed, the epitaxial wafer is annealed, and then the temperature of the epitaxial wafer is lowered to room temperature to complete the preparation; The step 2 includes the following sub-steps: Step 21: controlling the temperature to 450-600° C. and the pressure to 200-500 torr to grow a GaN nucleation layer, and then raising the temperature to 950-1200° C. to grow GaN three-dimensional and two-dimensional coating layers. The nucleation layer, GaN three-dimensional and two-dimensional coating layers are collectively referred to as a GaN buffer layer. Specific implementation: First, a layer of gallium nitride is grown at low temperature on a patterned substrate, which is called a low-temperature buffer layer; then gallium nitride is grown vertically on the low-temperature buffer layer to form multiple independent three-dimensional island structures, which are called three-dimensional nucleation layers; Then, gallium nitride is grown laterally on all three-dimensional island structures and between each three-dimensional island structure to form a two-dimensional planar structure, which is called a two-dimensional recovery layer; finally, a layer of gallium nitride is grown on the two-dimensional recovery layer at a high temperature, which is called an intrinsic gallium nitride layer; the thickness of the intrinsic gallium nitride layer is greater than that of the low-temperature buffer layer; the three-dimensional nucleation layer, the two-dimensional recovery layer and the intrinsic gallium nitride layer are collectively referred to as a gallium nitride buffer layer; Step 22: controlling the temperature to 950-1100° C. and the pressure to 70-200 torr, growing a stress and warpage control layer on the gallium nitride buffer layer, the overall stress and warpage control layer thickness is 20-60 nm, the growth atmosphere of the stress and warpage control layer is mainly nitrogen, the gas volume ratio of nitrogen to hydrogen is in the range of 1:1-10:1, and the proportion of ammonia in the entire carrier gas system is in the range of 0.25-0.40; Step 23: growing an N-type semiconductor layer on the stress and warpage control layer at a temperature of 950-1200° C. and a pressure range of 200-500 torr; Step 24: growing an active layer on the N-type semiconductor layer; the growth temperature of the quantum well is 720-829° C., and the growth pressure of the quantum well is 100-500 torr; the growth temperature of the quantum barrier is 850-959° C., and the growth pressure of the quantum barrier is 100-500 torr; Step 25: controlling the temperature to 850-1080° C. and the pressure to 200-500 torr, and growing an electron blocking layer on the active layer; Step 26: Control the temperature to 850-1080° C. and the pressure to 100-300 torr to grow a P-type semiconductor layer on the electron blocking layer.

2. The method for preparing an epitaxial wafer for Micro-LED according to claim 1, characterized in that: In the step 1, the temperature is controlled to be 1000-1200° C., the substrate is annealed for 6-10 minutes in a hydrogen atmosphere, and the substrate is nitrided.

3. The method for preparing an epitaxial wafer for Micro-LED according to claim 1, characterized in that: The stress and warpage control layer is composed of a lower AlN layer and an upper Al x Ga 1-x N layers are stacked, wherein 0≤x<0.4, the AlN layer and Al x Ga 1-x The N layer thickness ratio range is 1:10 to 1:

2.

4. The method for preparing an epitaxial wafer for Micro-LED according to claim 1, characterized in that: In the step 3, the temperature is controlled to be 850-1050° C. and the pressure is controlled to be 100-300 torr, and a contact layer is grown on the P-type semiconductor layer.

5. The method for preparing an epitaxial wafer for Micro-LED according to claim 1, characterized in that: In the step 4, the temperature is first lowered to 650-850° C., the epitaxial wafer is annealed for 5-15 minutes in a nitrogen atmosphere, and then the temperature of the epitaxial wafer is lowered to room temperature.

6. An epitaxial wafer for Micro-LED prepared by the method according to any one of claims 1 to 5, characterized in that: The invention comprises a substrate, and a buffer layer, a stress and warpage control layer, an N-type semiconductor layer, an active layer, an electron blocking layer, a P-type semiconductor layer and a contact layer which are grown on the substrate from bottom to top.

7. The epitaxial wafer for Micro-LED according to claim 6, characterized in that: The stress and warpage control layer is composed of a lower AlN layer and an upper Al x Ga 1-x N layers are stacked, wherein 0≤x<0.4, the AlN layer and Al x Ga 1-x The N layer thickness ratio ranges from 1:10 to 1:2, and the overall stress and warpage control layer thickness is 20 to 60 nm.

8. The epitaxial wafer for Micro-LED according to claim 7, characterized in that: A plurality of InGaN insertion layers are inserted into the stress and warpage control layer.

9. The epitaxial wafer for Micro-LED according to claim 8, characterized in that: The InGaN insertion layer has an In molar content of 5% to 20% and a thickness of 3 to 10 nm. The insertion positions are at 1 / 5, 1 / 3, and 3 / 4 of the entire area of ​​the stress and warpage control layer. The In content gradually increases and the thickness also tends to increase.

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