A DFB laser chip and its preparation method

Abstract

The present invention relates to the field of semiconductor technology, and in particular to a DFB laser chip and a preparation method thereof, which differs in that the chip comprises the following steps: step 1: selecting an n-type InP substrate; step 2: sequentially epitaxially growing a buffer layer, a lower waveguide layer, a quantum well active region, an upper waveguide layer, a lower isolation layer, an etched cutoff layer, an upper isolation layer and a grating layer on the substrate; step 3: making a refractive index coupling type grating in the grating layer to form a double grating structure; step 4: secondary epitaxial grating cover layer, an upper cladding layer and a contact layer; step 5: etching a laser waveguide structure in the contact layer and the upper cladding layer and growing an insulating layer; step 6: etching the insulating layer to form a current injection window; step 7: depositing metal on the p-type surface to form a p-side electrode, and depositing metal on the n-side substrate after thinning to form an n-side electrode, thereby completing the preparation. The present invention improves the yield rate of DFB devices.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a DFB laser chip and a preparation method thereof. Background Art

[0002] Distributed feedback (DFB) lasers have good single-mode characteristics and are widely used in many fields such as communications and sensing. They are a very important laser light source. The side mode suppression ratio that characterizes the single-mode characteristics of the laser is related to multiple physical parameters, among which its relationship with the grating coupling factor is particularly direct. If the grating coupling factor is small, the side mode suppression ratio will be very low and the single-mode characteristics will be poor. If the grating coupling factor is large, the probability of dual-mode lasing will increase significantly, and the single-mode characteristics will also be poor. In addition, it will bring about a serious spatial hole burning effect, further reducing the side mode suppression ratio. Therefore, it is particularly critical to control a reasonable grating coupling factor.

[0003] The grating coupling factor is determined by the design and process of making DFB lasers. After the appropriate grating coupling factor is designed according to theory, the actual grating coupling factor will be different from the design value and inconsistent on the whole piece due to the influence of various factors such as the difficulty in etching to make the grating sidewall completely steep, the grating duty cycle on the whole piece, and the etching depth completely consistent. This leads to a lower yield of the DFB laser produced due to the difference in grating coupling factor.

[0004] In view of this, in order to overcome the above technical defects, providing a DFB laser chip and a preparation method thereof has become an urgent problem to be solved in the art. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art, provide a DFB laser chip and a preparation method thereof, and improve the yield rate of DFB devices.

[0006] In order to solve the above technical problems, the technical solution of the present invention is: a method for preparing a DFB laser chip, which is different in that it includes the following steps:

[0007] Step 1: Select an n-type InP substrate;

[0008] Step 2: epitaxially growing a buffer layer, a lower waveguide layer, a quantum well active region, an upper waveguide layer, a lower isolation layer, an etching stop layer, an upper isolation layer and a grating layer on the substrate in sequence;

[0009] Step 3: manufacturing two refractive index coupling type gratings with different duty ratios in the grating layer to form a double grating structure;

[0010] Step 4: secondary epitaxial grating cover layer, upper cladding layer and contact layer;

[0011] Step 5: etching a laser waveguide structure in the contact layer and the upper cladding layer and growing an insulating layer, wherein there are two laser waveguide structures;

[0012] Step 6: etching the insulating layer to form a current injection window;

[0013] Step 7: Deposit metal on the p-type surface to form a p-side electrode, and deposit metal on the n-side substrate after thinning to form an n-side electrode to complete the preparation.

[0014] According to the above technical solution, the materials of the buffer layer and the upper cladding layer are InP.

[0015] According to the above technical solution, the material of the lower waveguide layer and the upper waveguide layer is AlGaInAs, and the thickness is 100nm-500nm.

[0016] According to the above technical solution, the quantum well active region is a multiple quantum well structure, the quantum well is a compressively strained well, and the well thickness is 6nm-10nm.

[0017] According to the above technical solution, the quantum barrier is a compressive strain barrier with a thickness of 15nm-20nm and a wavelength of the photoluminescence spectrum of 1300-1500nm.

[0018] According to the above technical solution, the material of the lower isolation layer and the upper isolation layer is InP.

[0019] According to the above technical solution, the material of the grating layer is InGaAsP, the thickness is 15nm-35nm, and the wavelength of the photoluminescence spectrum is 1200-1500nm.

[0020] According to the above technical solution, the duty cycles selected when the two gratings are exposed are different, and the obtained grating coupling coefficients are different.

[0021] According to the above technical solution, the grating etching is performed by dry etching, and the duty cycle controlled during exposure is transferred to the grating layer.

[0022] A DFB laser chip prepared according to the above preparation method, the difference of which lies in that: it includes, from bottom to top, an n-type InP substrate, a buffer layer, a lower waveguide layer, a quantum well active region, an upper waveguide layer, a lower isolation layer, an etching cutoff layer, an upper isolation layer, a grating layer, a grating cover layer, an upper cladding layer and a contact layer, and also includes an n-side electrode located below the n-type InP substrate and a p-side electrode located above the contact layer, and the grating layer includes two gratings with different duty ratios.

[0023] Based on the above scheme, the present invention discloses a DFB laser chip and a method for preparing the same, specifically, using metal organic chemical vapor deposition to epitaxially grow an active region and a waveguide structure, combining electron beam lithography and dry etching to produce a periodic grating to form a laser epitaxial wafer, and using conventional lithography and etching processes to produce a DFB laser chip. Two lasers are produced on the same chip, and the grating duty cycles of the two devices are different, so the obtained grating coupling factors are also different. Using this method, a device with a more suitable grating coupling factor can be obtained on a chip with a higher probability, thereby increasing the yield of DFB devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of the base structure of a DFB laser chip according to an embodiment of the present invention;

[0025] Figure 2 Schematic diagram of a grating according to an embodiment of the present invention Figure 1 ;

[0026] Figure 3 Schematic diagram of a grating according to an embodiment of the present invention Figure 2 ;

[0027] Figure 4 A schematic diagram of secondary epitaxy according to an embodiment of the present invention;

[0028] Figure 5 A schematic diagram of the overall structure of a DFB laser chip according to an embodiment of the present invention;

[0029] Figure 6 Schematic diagram of different grating duty ratios of a DFB laser chip according to an embodiment of the present invention;

[0030] Among them: 1-n-type InP substrate; 2-buffer layer; 3-lower waveguide layer; 4-quantum well active region; 5-upper waveguide layer; 61-lower isolation layer; 62-upper isolation layer; 7-etching cutoff layer; 8-grating layer; 9-grating; 10-grating cover layer; 11-upper cladding layer; 12-contact layer; 13-p-side electrode; 14-n-side electrode. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0032] Hereinafter, many aspects of the present invention will be better understood with reference to the accompanying drawings. The components in the accompanying drawings are not necessarily drawn to scale. Instead, emphasis is placed on clearly illustrating the components of the present invention. In addition, in several views of the accompanying drawings, the same reference numerals indicate corresponding parts.

[0033] As used herein, the words "exemplary" or "illustrative" mean used as an example, instance, or illustration. Any implementation described herein as "exemplary" or "illustrative" is not necessarily to be construed as preferred or advantageous over other implementations. All of the implementations described below are exemplary implementations, which are provided to enable those skilled in the art to make and use embodiments of the present disclosure and are not intended to limit the scope of the disclosure, which is defined by the claims. In other implementations, well-known features and methods are described in detail so as not to obscure the present invention. For the purposes of the description herein, the terms "upper," "lower," "left," "right," "front," "rear," "vertical," "horizontal," and their derivatives will be used interchangeably. Figure 1 The invention is directed to the invention of the present invention. Moreover, there is no intention to be bound by any express or implied theory given in the preceding technical field, background technology, summary of the invention or the detailed description below. It should also be understood that the specific devices and processes shown in the drawings and described in the following description are simple exemplary embodiments of the inventive concepts defined in the appended claims. Therefore, specific dimensions and other physical characteristics related to the embodiments disclosed herein should not be understood as limiting unless the claims explicitly state otherwise.

[0034] Please refer to Figures 1 to 6 The present invention provides a method for preparing a DFB laser chip, which is different in that it comprises the following steps:

[0035] Step 1: Select an n-type InP substrate 1;

[0036] Step 2: epitaxially growing an InP buffer layer 2, an AlGaInAs lower waveguide layer 3, a quantum well active region 4, an AlGaInAs upper waveguide layer 5, an InP lower isolation layer 61, an InGaAsP etching stop layer 7, an InP upper isolation layer 62 and an InGaAsP grating layer 8 in sequence on the substrate;

[0037] Step 3: In the grating layer 8, a refractive index coupling type grating 9 with different duty ratios is manufactured by holographic exposure and wet etching, and gratings 9 are manufactured in two waveguide ranges of the chip to form a double grating structure;

[0038] Step 4: secondary epitaxial InP grating cover layer 10, InP upper cladding layer 11 and InGaAs contact layer 12;

[0039] Step 5: etching a laser waveguide structure in the InGaAs contact layer 12 and the upper cladding layer 11 and growing a silicon dioxide insulating layer, wherein there are two laser waveguide structures;

[0040] Step 6: etching the insulating layer to form a current injection window;

[0041] Step 7: Deposit metal on the p-type surface to form a p-side electrode 13, and deposit metal on the n-side substrate after thinning to form an n-side electrode 14, and the preparation is completed.

[0042] The silicon dioxide insulating layer is etched away during the manufacturing process and is therefore not shown in the drawings.

[0043] Preferably, the material of the buffer layer 2 and the upper cladding layer 11 is InP.

[0044] Preferably, the material of the lower waveguide layer 3 and the upper waveguide layer 5 is AlGaInAs, and the thickness is 100nm-500nm.

[0045] Preferably, the quantum well active region 4 is a multiple quantum well structure, the quantum well is a compressively strained well, and the well thickness is 6nm-10nm.

[0046] According to the above technical solution, the quantum barrier is a compressive strain barrier with a thickness of 15nm-20nm and a wavelength of the photoluminescence spectrum of 1300-1500nm.

[0047] Preferably, the material of the lower isolation layer 61 and the upper isolation layer 62 is InP.

[0048] Preferably, the material of the grating layer 8 is InGaAsP, the thickness is 15nm-35nm, and the wavelength of the photoluminescence spectrum is 1200-1500nm.

[0049] Specifically, the duty cycles selected during the exposure of the two gratings are different, and the resulting grating coupling coefficients are different.

[0050] Preferably, the grating etching is performed by dry etching to transfer the duty cycle controlled during exposure to the grating layer.

[0051] A DFB laser chip prepared according to the above preparation method, the difference of which is that: it includes, from bottom to top, an n-type InP substrate 1, a buffer layer 2, a lower waveguide layer 3, a quantum well active region 4, an upper waveguide layer 5, a lower isolation layer 61, an etching stop layer 7, an upper isolation layer 62, a grating layer 8, a grating cover layer 10, an upper cladding layer 11 and a contact layer 12, and also includes an n-side electrode 14 located below the n-type InP substrate and a p-side electrode 13 located above the contact layer, and the grating layer 8 includes two gratings with different duty ratios.

[0052] In the embodiment of the present invention, two laser waveguide structures are etched simultaneously within the area of ​​a laser chip, that is, there are two DFB lasers in one chip, and the duty cycles of their gratings are different, and the corresponding grating coupling coefficients are different. The refractive index coupling type grating is made in the grating layer by electron beam exposure and dry etching methods. Two gratings with different coupling coefficients are used to further adjust the matching problem of the grating coupling factor, thereby improving the single-mode yield of the DFB chip.

[0053] The above contents are further detailed descriptions of the present invention in combination with specific implementation methods, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A method for preparing a DFB laser chip, characterized in that: The following steps are involved: Step 1: Select an n-type InP substrate; Step 2: epitaxially growing a buffer layer, a lower waveguide layer, a quantum well active region, an upper waveguide layer, a lower isolation layer, an etching stop layer, an upper isolation layer and a grating layer on the substrate in sequence; the quantum well active region is a plurality of quantum well structures, the quantum well is a compressively strained well, and the quantum barrier therein is a compressively strained barrier; the material of the etching stop layer is InGaAsP; Step 3: manufacturing two refractive index coupling type gratings with different duty ratios in the grating layer to form a double grating structure; different duty ratios are selected when the two gratings are exposed, and different grating coupling coefficients are obtained; the grating etching is performed by dry etching to transfer the duty ratio controlled during exposure to the grating layer; Step 4: secondary epitaxial grating cover layer, upper cladding layer and contact layer; Step 5: etching a laser waveguide structure in the contact layer and the upper cladding layer and growing a silicon dioxide insulating layer, wherein there are two laser waveguide structures; Step 6: etching the silicon dioxide insulating layer to form a current injection window, wherein the silicon dioxide insulating layer is etched away during the preparation process; Step 7: Deposit metal on the p-type surface to form a p-side electrode, and deposit metal on the n-side substrate after thinning to form an n-side electrode to complete the preparation.

2. The method for preparing a DFB laser chip according to claim 1, characterized in that: The materials of the buffer layer and the upper cladding layer are InP.

3. The method for preparing a DFB laser chip according to claim 1, characterized in that: The material of the lower waveguide layer and the upper waveguide layer is AlGaInAs, and the thickness is 100nm-500nm.

4. The method for preparing a DFB laser chip according to claim 1, characterized in that: The quantum well has a thickness of 6nm-10nm.

5. The method for preparing a DFB laser chip according to claim 4, characterized in that: The thickness of the quantum barrier is 15nm-20nm, and the wavelength of the photoluminescence spectrum is 1300-1500nm.

6. The method for preparing a DFB laser chip according to claim 1, characterized in that: The material of the lower isolation layer and the upper isolation layer is InP.

7. The method for preparing a DFB laser chip according to claim 1, characterized in that: The material of the grating layer is InGaAsP, the thickness is 15nm-35nm, and the wavelength of the photoluminescence spectrum is 1200-1500nm.

8. A DFB laser chip prepared according to the method according to any one of claims 1 to 7, characterized in that: It includes, from bottom to top, an n-type InP substrate, a buffer layer, a lower waveguide layer, a quantum well active region, an upper waveguide layer, a lower isolation layer, an etching cutoff layer, an upper isolation layer, a grating layer, a grating cover layer, an upper cladding layer and a contact layer, and also includes an n-side electrode located below the n-type InP substrate and a p-side electrode located above the contact layer. The grating layer includes two gratings with different duty ratios.

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