Method of manufacturing a semiconductor device

Abstract

A method of manufacturing a semiconductor device can be provided, the method including preparing a substrate including a wafer inner region and a wafer edge region, the wafer inner region including a chip region and a scribe groove region; sequentially stacking a mold layer and a support layer on the substrate; forming a first mask layer on the support layer, the first mask layer including a first step region on the wafer edge region; forming a step difference compensation pattern on the first step region; forming a second mask pattern including an opening on the first mask layer and the step difference compensation pattern; and sequentially etching the first mask layer, the support layer, and the mold layer using the second mask pattern as an etching mask to form a plurality of holes in at least the mold layer.

Description

Technical Field

[0001] This disclosure relates to methods for manufacturing semiconductor devices. Background Technology

[0002] Due to their small size, multifunctionality, and / or low cost, semiconductor devices are considered essential components in the electronics industry. With the development of the electronics industry, the demand for semiconductor devices with higher integration density continues to grow. To increase the integration density of semiconductor devices, it is desirable to reduce the linewidth of the patterns that constitute the semiconductor devices. However, reducing the linewidth of patterns requires new and expensive exposure techniques, making it difficult to increase the integration density of semiconductor devices. Therefore, various researches are actively underway on new technologies to increase the integration density of semiconductor devices. Summary of the Invention

[0003] Some exemplary embodiments of the present invention provide methods for improving productivity in the process of manufacturing semiconductor devices.

[0004] According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device includes: preparing a substrate including an internal wafer region and a wafer edge region, the internal wafer region including a chip region and a dicing region; sequentially stacking a molding layer and a support layer on the substrate; forming a first mask layer on the support layer, the first mask layer including a first step region on the wafer edge region; forming a step difference compensation pattern on the first step region; forming a second mask pattern including an opening on the first mask layer and the step difference compensation pattern; and sequentially etching the first mask layer, the support layer, and the molding layer using the second mask pattern as an etching mask to form a plurality of holes in at least the molding layer.

[0005] According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device includes: preparing a substrate including an interior region of a wafer and an edge region of a wafer; sequentially stacking a molding layer and a support layer on the substrate; forming a first mask layer on the support layer, the first mask layer including a first step region on the edge region of the wafer; forming a step difference compensation pattern to fill the first step region of the first mask layer and expose the top surface of the first mask layer on the interior region of the wafer; forming a second mask pattern on the first mask layer and on the step difference compensation pattern, the second mask pattern including an opening; and using the second mask pattern as an etching mask to sequentially etch the first mask layer, the support layer and the molding layer to form a plurality of holes in at least the molding layer.

[0006] According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device includes: preparing a substrate comprising an internal wafer region and a wafer edge region, the internal wafer region including a chip region and a dicing region; sequentially stacking a molding layer, a support layer, and a first mask layer on the substrate; removing a portion of the first mask layer on the wafer edge region to form a first step region in the first mask layer; forming a planarization mask layer on the first mask layer, the planarization mask layer filling the first step region, the top surface of the planarization mask layer having the same height in the internal wafer region and the wafer edge region; forming a second mask pattern having an opening on the planarization mask layer; and sequentially etching the planarization mask layer, the first mask layer, the support layer, and the molding layer using the second mask pattern as an etching mask to form a hole in at least the molding layer. Attached Figure Description

[0007] From the following brief description taken in conjunction with the accompanying drawings, exemplary embodiments will be more clearly understood. The drawings illustrate non-limiting exemplary embodiments as described herein.

[0008] Figure 1 This is a plan view of a wafer according to an example embodiment of the concept of the present invention.

[0009] Figure 2A , Figures 3 to 10 , Figure 11A , Figure 12 , Figure 13 , Figure 14A and Figures 15 to 18 Is with Figure 1 The cross-sectional views corresponding to lines IIA-IIA' are shown in sequence to illustrate the process of manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention.

[0010] Figure 2B yes Figure 2A An enlarged sectional view of part "IIB".

[0011] Figure 11B yes Figure 11A An enlarged sectional view of part of "XIB".

[0012] Figure 14B It is shown Figure 14A A plan view of the chip area. Figure 14A The chip area shown also corresponds to along Figure 14B The vertical cross section taken by the line XIVA-XIVA'.

[0013] Figures 19 to 21 Is with Figure 1 The cross-sectional views corresponding to lines IIA-IIA' sequentially illustrate a method for manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention.

[0014] Figures 22 to 24 Is with Figure 1 The cross-sectional views corresponding to lines IIA-IIA' sequentially illustrate a method for manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention.

[0015] It should be noted that these figures are intended to illustrate the general characteristics of the methods, structures, and / or materials used in some exemplary embodiments and to supplement the written description provided below. However, these figures are not to scale and may not accurately reflect the precise structural or performance characteristics of any given exemplary embodiment, and should not be construed as limiting or restricting the range of values ​​or properties covered by the exemplary embodiments. For example, the relative thickness and positioning of molecules, layers, regions, and / or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various figures is intended to indicate the presence of similar or identical elements or features. Detailed Implementation

[0016] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments are illustrated.

[0017] As used herein, the term “and / or” includes any and all combinations of one or more of the related listed items. When following a list of elements, expressions such as “one of…” or “at least one of…” modify the entire list of elements, not individual elements in the list. Thus, for example, “at least one of A, B, or C” and “at least one of A, B, and C” both mean A, B, C, or any combination thereof.

[0018] Although the terms “identical” or “the same” are used in the description of the example implementations, it should be understood that some imprecision may exist. Therefore, when an element or value is referred to as being identical to another element or value, it should be understood that the element or value is identical to the other element or value within the expected range of manufacturing or operating tolerances (e.g., ±10%).

[0019] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended that the relevant numerical values ​​include manufacturing or operational tolerances (e.g., ±10%) near said numerical values. Furthermore, when the words “usually” and “substantially” are used in conjunction with geometry, it is intended that precision of the geometry is not required, but the range of the shape is within the scope of this disclosure. Moreover, regardless of whether numerical values ​​or shapes are modified to “about” or “substantially”, it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) near said numerical values ​​or shapes.

[0020] Figure 1 This is a plan view of a wafer according to an example embodiment of the concept of the present invention.

[0021] Reference Figure 1 A wafer W, according to an example embodiment of the present invention, may include a plurality of chip regions CR and a dicing region SR providing between them. The wafer W may include a wafer edge region ER and an inner wafer region IR. A height difference may exist between the wafer edge region ER and the top surface of the chuck on which the wafer W is mounted, and such a height difference may cause defocusing problems on the wafer edge region ER during exposure processes. Therefore, it may be difficult to accurately form the desired pattern on the chip regions CR located in the wafer edge region ER. Therefore, when a chip dicing process is performed to divide the wafer W into semiconductor chips, the wafer edge region ER is discarded, and only the chip regions CR in the inner wafer region IR can be used as semiconductor chips. If a faulty pattern is formed in the wafer edge region ER, this faulty pattern may serve as a source of particles in subsequent semiconductor manufacturing processes. Therefore, it is desirable to perform processes to suppress pattern formation on the wafer edge region ER.

[0022] Figure 2A , Figures 3 to 10 , Figure 11A , Figure 12 , Figure 13 , Figure 14A and Figures 15 to 18 These are cross-sectional views showing a process for manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention. Figure 2A , Figures 3 to 10 , Figure 11A , Figure 12 , Figure 13 , Figure 14A and Figures 15 to 18 Each of the above shows the relationship with Figure 1 The vertical section corresponding to line IIA-IIA'. Figure 2B yes Figure 2A An enlarged sectional view of part "IIB". Figure 11B yes Figure 11A An enlarged sectional view of part of "XIB". Figure 14B It is shown Figure 14A A plan view of the chip area. Figure 14A The chip area shown corresponds to along Figure 14B The vertical cross section taken by the line XIVA-XIVA'.

[0023] Reference Figure 2A and Figure 2BA semiconductor substrate 1 may be provided. The semiconductor substrate 1 may correspond to a portion of a wafer W. The semiconductor substrate 1 may include a wafer edge region ER and a wafer interior region IR. A chip region CR and a scribe line region SR may be provided in the wafer interior region IR. The semiconductor substrate 1 may be, for example, a single-crystal silicon wafer. An interlayer insulating layer 3 may be disposed on the semiconductor substrate 1. The interlayer insulating layer 3 may be formed of, for example, silicon oxide. A plurality of lower electrode contacts 5 may be disposed on the chip region CR to penetrate the interlayer insulating layer 3 and be electrically connected to the semiconductor substrate 1. The lower electrode contacts 5 may be formed of, for example, at least one of doped polysilicon patterns, titanium nitride, or tungsten, or may include, for example, at least one of doped polysilicon patterns, titanium nitride, or tungsten. A test conductive pattern 5t may be disposed on the scribe line region SR of the semiconductor substrate 1. The test conductive pattern 5t may be formed of or include the same material as the lower electrode contacts 5.

[0024] Although not shown, a device isolation layer can be disposed in the chip region CR of the semiconductor substrate 1 to define the active region. Word lines can be buried in the semiconductor substrate 1. Word lines can be electrically separated from the semiconductor substrate 1 by a gate insulating layer and a cover pattern. Impurity implantation regions serving as source / drain regions can be disposed in portions of the semiconductor substrate 1 on both sides of the word lines. Impurity implantation regions located on one side of the word lines can be electrically connected to the bit lines. Lower electrode contacts 5 can be electrically connected to impurity implantation regions located on the opposite side of the word lines.

[0025] A first etch stop layer 7 can be formed on the interlayer insulating layer 3. The first etch stop layer 7 can be formed of a material (e.g., silicon nitride) that has etch selectivity relative to the interlayer insulating layer 3. A first molding layer 9, a first support layer 11, a second molding layer 13, a first bending suppression layer 15, a second bending suppression layer 17, a second support layer 19, a second etch stop layer 21, a first mask layer 23, and a second mask layer 25 can be sequentially stacked on the first etch stop layer 7. The first molding layer 9 and the second molding layer 13 can be formed of a material that has etch selectivity relative to the first support layer 11 and the second support layer 19. The first molding layer 9 and the second molding layer 13 can be formed of, for example, silicon oxide or include, for example, silicon oxide. The first support layer 11 and the second support layer 19 can be formed of, for example, silicon carbon nitride or include, for example, silicon carbon nitride. The second etch stop layer 21 can be formed of, for example, silicon nitride or include, for example, silicon nitride.

[0026] The first bending suppression layer 15 may include alternately stacked first sub-bending suppression layers 15a and second sub-bending suppression layers 15b. The first sub-bending suppression layer 15a may be formed of the same material as the second etch stop layer 21 (e.g., silicon nitride), or may include the same material as the second etch stop layer 21 (e.g., silicon nitride). The second sub-bending suppression layer 15b may be formed of the same material as the first molding layer 9 and the second molding layer 13 (e.g., silicon oxide), or may include the same material as the first molding layer 9 and the second molding layer 13 (e.g., silicon oxide). Each second sub-bending suppression layer 15b may be thicker than each first sub-bending suppression layer 15a. In some example embodiments, the second bending suppression layer 17 may be formed of or include a material that is etch-selective relative to the second support layer 19 and all of the first molding layer 9 and the second molding layer 13. The second bending suppression layer 17 may include, for example, a boron-doped silicon nitride layer.

[0027] The first mask layer 23 may be formed of, or include, a material having etch selectivity relative to the first molding layer 9, the first support layer 11, the second molding layer 13, the first bending suppression layer 15, the second bending suppression layer 17, the second support layer 19, and the second etch stop layer 21. The first mask layer 23 may be formed of, for example, polysilicon or include polysilicon. The second mask layer 25 may be formed of, or include, a material having etch selectivity relative to the first mask layer 23. The second mask layer 25 may be formed of, for example, silicon oxide or silicon nitride, or include, for example, silicon oxide or silicon nitride.

[0028] In the chip region CR, a first photoresist pattern 27 can be formed on the second mask layer 25. The first photoresist pattern 27 can be provided to expose the top surface of the second mask layer 25 in the wafer edge region ER and the adjacent dicing region SR. The first photoresist pattern 27 can be formed by a photolithography process.

[0029] Reference Figure 2A and Figure 3 The second mask pattern 25p can be formed by etching the second mask layer 25 using the first photoresist pattern 27 as an etching mask. In the wafer edge region ER and the adjacent dicing region SR, the second mask pattern 25p can expose the top surface of the first mask layer 23.

[0030] Reference Figure 3 and Figure 4 The first recessed region R1 can be formed by etching the upper part of the first mask layer 23 using the second mask pattern 25p as an etching mask. Therefore, the first mask layer 23 can be thinner in the wafer edge region ER and the adjacent dicing region SR than in the chip region CR. The thickness of the second mask pattern 25p can also be reduced by the etching process.

[0031] Reference Figure 4 and Figure 5 The second mask pattern 25p can be removed, and then the third mask layer 29, polishing stop layer 31, and fourth mask layer 33 can be sequentially and conformally formed by performing deposition processes (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD) processes). The fourth mask layer 33 may be referred to as a step difference compensation layer. The third mask layer 29 and the fourth mask layer 33 may be formed of or comprise the same material (e.g., silicon oxide). The polishing stop layer 31 may be formed of a material that has polishing selectivity or etching selectivity relative to the third mask layer 29 and the fourth mask layer 33. The polishing stop layer 31 may be formed of or comprise a material different from the third mask layer 29 and the fourth mask layer 33 (e.g., silicon nitride). The third mask layer 29 may fill the first recessed region R1. Since the third mask layer 29 is conformally formed, its top surface can have a second recessed region R2 in the wafer edge region ER and the adjacent dicing region SR. This second recessed region R2 is formed by transcription of the first recessed region R1 of the first mask layer 23. The fourth mask layer 33 can fill the second recessed region R2.

[0032] Reference Figure 5 and Figure 6 Chemical mechanical polishing (CMP) can remove the fourth mask layer 33 from the chip region CR and expose the polishing stop layer 31 on the chip region CR. Therefore, a portion of the fourth mask layer 33 can be removed from the wafer edge region ER and the adjacent dicing region SR, such that the fourth mask pattern 33p is formed to fill the second recessed region R2. Due to the presence of the fourth mask pattern 33p, the height difference between the wafer edge region ER and the chip region CR can be reduced or eliminated. For this reason, the fourth mask pattern 33p can also be referred to as a step difference compensation pattern.

[0033] Reference Figure 6 and Figure 7 The polishing stop layer 31 can be removed from the exposed portion not covered by the fourth mask pattern 33p to expose the top surface of the third mask layer 29 on the chip region CR. In this case, the polishing stop pattern 31p can remain between the third mask layer 29 and the fourth mask pattern 33p on the wafer edge region ER and the adjacent dicing region SR. In one example embodiment, an isotropic etching process can remove the polishing stop layer 31 from the chip region CR. The first recessed region R1 can have a first depth D1, and the fourth mask pattern 33p can have a first thickness T1. In one example embodiment, the first depth D1 can be the same as or substantially similar to the first thickness T1.

[0034] Reference Figure 7 and Figure 8 A planarization auxiliary layer 35 can be formed on the third mask layer 29 and the fourth mask pattern 33p. The planarization auxiliary layer 35 can be formed by, for example, spin coating and can be formed from at least one of spin-coated hard mask (SOH) or spin-coated carbon (SOC) materials. The third mask layer 29, the polishing stop pattern 31p, the fourth mask pattern 33p, and the planarization auxiliary layer 35 can collectively constitute a planarization mask layer 34. The height of the top surface of the planarization mask layer 34 can be the same or substantially constant, regardless of its position on the substrate 1. Due to the fourth mask pattern 33p and the polishing stop pattern 31p, the planarization mask layer 34 can be thicker in the wafer edge region ER than in the chip region CR.

[0035] A fifth mask layer 37 can be formed on the planarization mask layer 34. The fifth mask layer 37 can be formed of or include a material that has etch selectivity relative to the planarization auxiliary layer 35. For example, the fifth mask layer 37 may include a silicon nitride layer, a silicon oxide nitride layer, or a silicon oxide layer. The fifth mask layer 37 can serve as an anti-reflection layer. A second photoresist pattern 39 can be formed on the fifth mask layer 37. The second photoresist pattern 39 can be formed by a photolithography process. The second photoresist pattern 39 may include a first opening 41, which will be used to define or define a lower electrode hole. The first opening 41 may be formed not only in the chip region CR of the wafer interior region IR but also in the wafer edge region ER.

[0036] Reference Figure 8 and Figure 9 An anisotropic etching process using the second photoresist pattern 39 as an etching mask can sequentially etch the fifth mask layer 37 and the planarization mask layer 34 to form a planarization mask pattern 34p including a first hole 41h. The first hole 41h can be formed to expose the top surface of the first mask layer 23 in the chip region CR. When the first hole 41h is formed, a first edge hole 41he can also be formed on the wafer edge region ER. The first edge hole 41he may not expose the first mask layer 23. The planarization mask pattern 34p can include a third mask pattern 29p and a planarization auxiliary pattern 35p. The planarization mask pattern 34p can also include a polishing stop pattern 31p and a fourth mask pattern 33p, which are disposed between the third mask pattern 29p and the planarization auxiliary pattern 35p and on the wafer edge region ER and the adjacent dicing region SR. Since the polishing stop pattern 31p is used as an etching stop layer during the etching process, the depth of the first edge hole 41he can be less than the depth of the first hole 41h.

[0037] Reference Figure 9 and Figure 10 An anisotropic etching process using a planarization mask pattern 34p as an etching mask can etch the first mask layer 23 to form a first mask pattern 23p including a second aperture 42h. The second aperture 42h formed through transcription of the first aperture 41h can expose the second etch stop layer 21. During the etching process, the planarization mask pattern 34p can be etched and thinned. Therefore, only a portion of the third mask pattern 29p can remain on the first mask pattern 23p. A second edge aperture 42he can be formed in the third mask pattern 29p. The second edge aperture 42he formed through transcription of the first edge aperture 41he can not expose the first mask pattern 23p.

[0038] Reference Figure 10 , Figure 11A and Figure 11B An anisotropic etching process using the first mask pattern 23p as the etching mask can sequentially etch the second etch stop layer 21, the second support layer 19, the second bending suppression layer 17, the first bending suppression layer 15, the second molding layer 13, the first support layer 11, and the first molding layer 9, thereby forming a lower electrode hole 44 on the chip region CR to expose the first etch stop layer 7. When the lower electrode hole 44 is formed, the upper part of the second molding layer 13 may be exposed to the etchant for a long time. Therefore, a bending phenomenon of enlargement of the upper part of the second lower electrode hole 44 may occur. If the bending phenomenon deepens, bridging problems may occur (e.g., connecting the lower electrodes 43 subsequently formed by filling the lower electrode hole 44 to each other), or it may become difficult to form the dielectric layer and the upper electrode layer in subsequent processes.

[0039] However, in one exemplary embodiment of the present invention, the second bending suppression layer 17 may be formed of a different material than the second molding layer 13 (e.g., a boron-doped silicon nitride layer), as shown in the reference. Figure 2A and 2B For example, the second bending suppression layer 17 can have etch selectivity relative to the second molding layer 13. Therefore, when the lower electrode hole 44 is formed, bending may not occur in the second bending suppression layer 17. Furthermore, the height of the bending region BW can be reduced by decreasing the thickness of the second bending suppression layer 17.

[0040] Furthermore, since the first bending suppression layer 15 is composed of alternately stacked first sub-bending suppression layers 15a and second sub-bending suppression layers 15b, the etchant can be dispersed or the concentration of the etchant in the upper part of the second molding layer 13 can be suppressed. Therefore, the formation of the bending region BW in the upper part of the second molding layer 13 can be suppressed.

[0041] Reference Figure 10 and Figure 11ABecause of the third mask pattern 29p on the wafer edge region ER and the adjacent scribe groove region SR, the etching of the first mask pattern 23p can be delayed when the lower electrode hole 44 is formed in the molding layer (e.g., the first molding layer 9 and the second molding layer 13) on the chip region CR of the wafer W. Therefore, a considerable portion of the first mask pattern 23p can be retained on the wafer edge region ER and the adjacent scribe groove region SR to cover the second etch stop layer 21. The lower electrode hole 44 may not be formed on the wafer edge region ER and the adjacent scribe groove region SR.

[0042] Reference Figure 11A and Figure 12 An isotropic etching process can remove the first mask pattern 23p, and in this case, the second etch stop layer 21 can be exposed without damage. The first etch stop layer 7 exposed through the lower electrode hole 44 can be removed to expose the lower electrode contact 5. Since the second etch stop layer 21 is formed of the same material as the first etch stop layer 7, the second etch stop layer 21 can also be removed when the first etch stop layer 7 is removed, thus exposing the top surface of the second support layer 19.

[0043] Reference Figure 13 A conductive layer can be formed on the semiconductor substrate 1, and then a CMP or etch-back process can be performed to form a lower electrode 43 in the lower electrode hole 44 and expose the top surface of the second support layer 19. The lower electrode 43 can be formed of at least one of doped polysilicon, metal nitride (e.g., titanium nitride), or metal (e.g., tungsten), or include at least one of doped polysilicon, metal nitride (e.g., titanium nitride), or metal (e.g., tungsten). The lower electrode 43 can be referred to as a conductive pillar. The lower electrode 43 can have, for example, a plug shape, a hollow cylindrical shape, or a cup shape.

[0044] Reference Figure 13 , Figure 14A and Figure 14B A sixth mask pattern 45 can be formed on the second support layer 19. The sixth mask pattern 45 may include a photoresist pattern, a spin-on hard mask (SOH) material, a spin-on carbon (SOC) material, or an amorphous carbon layer (ACL). On the chip region CR, the sixth mask pattern 45 may have a second opening 45h that partially exposes the lower electrode 43. When viewed in a plan view, the second opening 45h may have a circular shape and may expose three adjacent lower electrodes in the lower electrode 43 and the second support layer 19 between them.

[0045] The second openings 45h can be identical in shape and spacing. All side surfaces of the lower electrodes 43 can be partially exposed through the second openings 45h. In some example embodiments, the exposed side surfaces of the lower electrodes 43 can have the same area. Therefore, the first molding layer 9 and the second molding layer 13, or the dielectric layer 47 and the upper electrode layer 49 (see...) can be removed. Figure 17 In subsequent processes, the loading effect can be reduced or suppressed, and spatial variations in process states or conditions can be minimized. Therefore, excessive damage to portions of the lower electrode 43 can be mitigated or prevented during the removal of the first molding layer 9 and the second molding layer 13. Furthermore, each of the dielectric layer 47 and the upper electrode layer 49 can be formed in subsequent processes to have a constant thickness throughout the semiconductor substrate 1.

[0046] The sixth mask pattern 45 may not be formed on the dicing region SR. Therefore, the second support layer 19 can be exposed on the dicing region SR. On the wafer edge region ER, the top surface of the second support layer 19 can be covered by the sixth mask pattern 45.

[0047] Reference Figure 14A and Figure 15 An anisotropic etching process using the sixth mask pattern 45 as the etching mask can sequentially etch the second support layer 19, the second bending suppression layer 17, the first bending suppression layer 15, the second molding layer 13, and the first support layer 11 (which are located on the chip region CR and between three adjacent lower electrodes in the lower electrode 43) to form a support hole 19h exposing the first molding layer 9. Here, the second support layer 19, the second bending suppression layer 17, the first bending suppression layer 15, the second molding layer 13, and the first support layer 11 can be removed from the dicing region SR, so the first molding layer 9 can be exposed on the dicing region SR.

[0048] Reference Figure 15 and Figure 16 The isotropic etching process removes the first molding layer 9 and the second molding layer 13, as well as the first bending suppression layer 15 and the second bending suppression layer 17, from the wafer interior region IR through the support hole 19h, exposing the surfaces of the first etch stop layer 7, the first support layer 11 and the second support layer 19, and the lower electrode 43. Here, the first remaining molding layer 9r and the second remaining molding layer 13r, as well as the first remaining bending suppression layer 15r and the second remaining bending suppression layer 17r, can remain on the wafer edge region ER. Since the first molding layer 9 and the second molding layer 13 are removed by the isotropic etching process, the first etch stop layer 7 on the dicing region SR is not damaged, and therefore the test conductive pattern 5t can be covered by the first etch stop layer 7 and is not exposed.

[0049] Reference Figure 17and Figure 18 A dielectric layer 47 can be conformally formed on the semiconductor substrate 1. An upper electrode layer 49 can then be formed on the dielectric layer 47. The dielectric layer 47 can be formed of a metal oxide material (e.g., aluminum oxide) having a dielectric constant higher than that of the silicon oxide layer. The upper electrode layer 49 can be formed of at least one of a titanium nitride layer, a tungsten layer, a doped polysilicon layer, or a doped silicon-germanium layer, or includes at least one of these. An upper interlayer insulating layer 51 can be formed on the upper electrode layer 49. Subsequently, a chip dicing process can remove the dicing region SR and the wafer edge region ER, and the remaining chip region CR can be used as a semiconductor chip. In one example embodiment, a chip testing process can be additionally performed using the test conductive pattern 5t of the dicing region SR before the chip dicing process.

[0050] In a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention, the step difference compensation pattern 33p can be formed from a material capable of being planarized by a CMP process (e.g., silicon nitride or silicon oxide), such as... Figure 6 As shown. When the step difference compensation pattern is formed by a photoresist pattern, the photoresist pattern may cause a height difference between the wafer edge region ER and the wafer interior region IR, thus leading to defocusing problems. Furthermore, performing CMP processes on materials such as photoresist patterns or SOH formed by spin coating processes can be difficult. Therefore, it may be difficult to planarize such materials using CMP processes. However, according to an exemplary embodiment of the present invention, a CMP process can be performed, and this can reduce or eliminate the height difference between the wafer edge region ER and the wafer interior region IR. Therefore, the defocusing problem between the wafer edge region ER and the wafer interior region IR can be solved.

[0051] In a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention, when such... Figure 11A When forming the lower electrode hole 44, the second etch stop layer 21 and the second support layer 19 on the dicing region SR or the wafer edge region ER do not need to be etched. Therefore, in Figure 16 In this step, the first etch stop layer 7 can be left undamaged to prevent the test conductive pattern 5t from being exposed. If the test conductive pattern 5t is exposed, peeling failures may occur in the subsequent cleaning process. For example, in the subsequent cleaning process, material in the test conductive pattern 5t (e.g., tungsten) may dissolve in the cleaning solution and then deposit on another area. However, according to an exemplary embodiment of the present invention, such peeling failures can be prevented.

[0052] Furthermore, in a manufacturing method according to an exemplary embodiment of the present invention, the entire manufacturing process can be simplified by not forming additional blank photoresist patterns covering the wafer edge region ER. Therefore, process defects can be reduced and productivity can be improved.

[0053] Figures 19 to 21 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention.

[0054] Reference Figure 19 In the manufacturing method according to this example embodiment, with Figure 2A Unlike previous example implementations, the first photoresist pattern 27 can be formed directly on the first mask layer 23. The first mask layer 23 can be etched using the first photoresist pattern 27 to form a first recessed region R1 on the wafer edge region ER and the adjacent dicing region SR. The first mask layer 23 can be formed of, for example, polysilicon or include, for example, polysilicon.

[0055] Reference Figure 19 and Figure 20 The first photoresist pattern 27 can be removed, and then a step difference compensation layer can be formed on the semiconductor substrate 1 to fill the first recessed region R1. Subsequently, a CMP process can form a step difference compensation pattern 330p on the first recessed region R1. The step difference compensation layer can be formed of or include a material having etch selectivity or polishing selectivity relative to the first mask layer 23 (e.g., silicon oxide or silicon nitride). The step difference compensation layer can be formed by a deposition process (e.g., CVD, ALD, and PVD processes) rather than by a spin coating process. During the CMP process, the first mask layer 23 can be used as a polishing stop layer. Therefore, the top surface of the first mask layer 23 in the chip region CR can become coplanar with the top surface of the step difference compensation pattern 330p. A second photoresist pattern 39 can be formed on the first mask layer 23 and the step difference compensation pattern 330p. The second photoresist pattern 39 may include a first opening 41. The first recessed region R1 may have a first depth D1, and the step difference compensation pattern 330p may have a first thickness T1. In one example implementation, the first depth D1 may be substantially equal to the first thickness T1.

[0056] Reference Figure 20 and Figure 21An anisotropic etching process using a second photoresist pattern 39 as an etching mask can etch the first mask layer 23 to form a first mask pattern 23p with a second aperture 42h. The second aperture 42h can be formed to expose a second etch stop layer 21 in the chip region CR. Furthermore, a step difference compensation pattern 330p can hinder the etching process in the wafer edge region ER and the adjacent scribe groove region SR, thus the top surface of the first mask pattern 23p can remain unexposed. Subsequent processes can be performed in accordance with the previously referenced... Figures 11A to 18 The process described is carried out in the same or similar manner.

[0057] Figures 22 to 24 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an exemplary embodiment of the concept of the present invention.

[0058] Reference Figure 22 When Figure 4 As shown, when a first recessed region R1 is formed in the first mask layer 23, the first recessed region R1 can be formed to have a first depth D1. In other words, the first recessed region R1 can be formed such that the height difference between the top surface of the first mask layer 23 outside the first recessed region R1 and the bottom surface of the first recessed region R1 on the chip region CR of the wafer interior region IR becomes the first depth D1. After forming the first recessed region R1, a third mask layer 29 can be formed on the first mask layer 23. The third mask layer 29 can be formed by a deposition process (e.g., CVD, ALD, and PVD processes). The third mask layer 29 can be formed of a material (e.g., silicon oxide, silicon nitride, or silicon nitride) that has etch selectivity relative to the first mask layer 23, or include such a material. A planarization auxiliary layer 61 can be formed on the third mask layer 29. The planarization auxiliary layer 61 can be formed by a spin coating process and can be formed of at least one of SOH or SOC materials. The flattening auxiliary layer 61 can help reduce the height difference caused by the first recessed region R1, but the flattening auxiliary layer 61 can still have a third recessed region R3 formed by transcription of the first recessed region R1.

[0059] An auxiliary mask layer 63 can be formed on the planarization auxiliary layer 61. The auxiliary mask layer 63 can serve as an anti-reflection layer. The auxiliary mask layer 63 may include a silicon nitride layer or an amorphous silicon layer. The auxiliary mask layer 63 may have a relatively small thickness, so the third recessed region R3 may not be completely filled by the auxiliary mask layer 63. A step difference compensation pattern 65 can be formed on the auxiliary mask layer 63 on the wafer edge region ER and the dicing region SR. The step difference compensation pattern 65 can fill the third recessed region R3. Here, the step difference compensation pattern 65 may be a photoresist pattern formed by a photolithography process. The step difference compensation pattern 65 may have a first thickness T1. In an example embodiment, the first thickness T1 may be equal to or substantially the same as the first depth D1.

[0060] Reference Figure 23 A fourth mask pattern 67 with a first opening 71 can be formed on the semiconductor substrate 1. The fourth mask pattern 67 can be a photoresist pattern formed by a photolithography process. The first opening 71 can define the position of the lower electrode hole. The first opening 71 can be formed not only on the chip region CR in the wafer interior region IR but also on the wafer edge region ER.

[0061] Reference Figure 23 and Figure 24 An anisotropic etching process using the fourth mask pattern 67 as the etching mask can etch the underlying structure. Therefore, the third mask layer 29 on the chip region CR of the wafer interior region IR can be etched to form a third mask pattern 29p with a first aperture 29h. Here, due to the presence of the step difference compensation pattern 65, the third mask layer 29 on the wafer edge region ER can be left unetched. Therefore, the first aperture 29h of the third mask pattern 29p can be left unformed on the wafer edge region ER. Subsequent processes can be performed in accordance with the previously referenced... Figures 10 to 18 The process described is performed in the same or similar manner.

[0062] According to an exemplary embodiment of the present invention, in a method for manufacturing a semiconductor device, a step difference compensation pattern can be formed from a material that can be polished by a chemical mechanical polishing (CMP) process, thus solving the defocusing problem. Furthermore, damage to the etch stop layer used to protect the underlying conductive pattern can be prevented in the edge region of the wafer or in the adjacent dicing groove region, thereby preventing peeling failure of the underlying conductive pattern. This can improve productivity.

[0063] Although some exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0064] This patent application claims priority to Korean Patent Application No. 10-2019-0100435, filed on August 16, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A method for manufacturing a semiconductor device, comprising: Prepare a substrate comprising an internal wafer region and a wafer edge region, wherein the internal wafer region includes a chip region and a dicing groove region; A molding layer and a support layer are sequentially stacked on the substrate; A first mask layer is formed on the support layer, the first mask layer including a first step region on the wafer edge region; A step difference compensation pattern is formed on the first step region, the step difference compensation pattern exposing the top surface of the first mask layer on the internal region of the wafer; A second mask pattern including an opening is formed on the first mask layer and on the step difference compensation pattern; as well as Using the second mask pattern as an etching mask, the first mask layer, the support layer, and the molding layer are etched sequentially to form a plurality of holes in at least the molding layer.

2. The method according to claim 1, further comprising, before forming the step difference compensation pattern: A third mask layer is conformally formed on the first mask layer, such that the top surface of the third mask layer has a second step region, which is located on the wafer edge region by transcription of the first step region; as well as A polishing stop pattern is formed to cover the second step area of ​​the third mask layer. The step difference compensation pattern fills the second step area.

3. The method according to claim 2, wherein The third mask layer and the step difference compensation pattern comprise the same material, and The polishing stop pattern includes a material that has polishing selectivity relative to the step difference compensation pattern.

4. The method according to claim 2, further comprising: Before forming the second mask pattern, a planarization auxiliary layer is formed to cover the third mask layer and the step difference compensation pattern. The planarization auxiliary layer is formed by spin coating. The planarization auxiliary layer is formed of a material different from that of the third mask layer and the step difference compensation pattern.

5. The method of claim 2, wherein forming the polishing stop pattern and forming the step difference compensation pattern comprises: A polishing stop layer and a step difference compensation layer are sequentially stacked on the third mask layer, wherein the step difference compensation layer fills the second step region of the third mask layer; A polishing process is performed on the step difference compensation layer to expose the polishing stop layer on the inner region of the wafer and to form the step difference compensation pattern on the edge region of the wafer. as well as The polishing stop layer is removed from the chip region to form the polishing stop pattern that exposes the top surface of the third mask layer on the chip region.

6. The method according to claim 1, wherein the step difference compensation pattern comprises a silicon oxide layer, a silicon nitride layer, or a photoresist pattern.

7. The method according to claim 1, wherein the depth of the first step region is equal to the thickness of the step difference compensation pattern.

8. The method of claim 1, wherein forming the first mask layer comprises: An auxiliary mask layer is formed to cover the entire top surface of the first mask layer; A photoresist pattern is formed on the auxiliary mask layer; The auxiliary mask layer is etched using the photoresist pattern to form the auxiliary mask pattern; as well as The first mask layer is etched using the auxiliary mask pattern to form the first step region. The photoresist pattern is formed to cover the auxiliary mask layer on the inner region of the wafer and expose the auxiliary mask layer on the edge region of the wafer.

9. The method according to claim 1, further comprising, before forming the step difference compensation pattern: A third mask layer is formed on the first mask layer; as well as A planarization auxiliary layer is formed on the third mask layer, wherein The step difference compensation pattern is formed on the planarization auxiliary layer. The third mask layer is formed by a deposition process, and The planarization auxiliary layer is formed by spin coating.

10. The method according to claim 1, further comprising: A bending suppression layer is formed between the molding layer and the support layer. The bending suppression layer comprises a material that is etch-selective relative to both the molding layer and the support layer.

11. The method according to claim 1, further comprising: A bending-inhibiting layer is formed between the molding layer and the support layer, wherein The bending suppression layer comprises alternately stacked first sub-bending suppression layers and second sub-bending suppression layers, and The second sub-bending suppression layer comprises the same material as the molding layer.

12. The method of claim 11, wherein each of the second sub-bending suppression layers is thicker than each of the first sub-bending suppression layers.

13. The method according to claim 1, further comprising: Remove the second mask pattern and the first mask layer; Lower electrodes are formed in the holes respectively; The support layer is patterned to form support holes; The molding layer is removed through the support hole; A dielectric layer is formed to cover the lower electrode and the support layer; as well as An upper electrode layer is formed to cover the dielectric layer.

14. The method according to claim 1, further comprising: Before the molding layer and the support layer are sequentially stacked on the substrate, a lower molding layer and a lower support layer are formed on the substrate. The hole is formed to penetrate the lower molding layer and the lower support layer.

15. A method for manufacturing a semiconductor device, comprising: Prepare a substrate that includes the internal region of the wafer and the edge region of the wafer; A molding layer and a support layer are sequentially stacked on the substrate; A first mask layer is formed on the support layer, the first mask layer including a first step region on the wafer edge region; A step difference compensation pattern is formed to fill the first step region of the first mask layer and expose the top surface of the first mask layer on the wafer interior region; A second mask pattern is formed on the first mask layer and on the step difference compensation pattern, the second mask pattern including an opening; and Using the second mask pattern as an etching mask, the first mask layer, the support layer, and the molding layer are etched sequentially to form a plurality of holes in at least the molding layer.

16. The method of claim 15, wherein the step difference compensation pattern comprises a material polishable by a chemical mechanical polishing (CMP) process.

17. The method of claim 15, wherein forming the first mask layer comprises: A first sub-mask layer is formed on the support layer; Remove a portion of the first sub-mask layer at the wafer edge region to form a second step region; A second sub-mask layer is formed on the first sub-mask layer; as well as A planarization auxiliary layer is formed on the second sub-mask layer, wherein The first sub-mask layer, the second sub-mask layer, and the planarization auxiliary layer constitute the first mask layer, and The first step region is formed on the planarization auxiliary layer.

18. The method of claim 17, wherein the step difference compensation pattern is formed by a photoresist pattern.

19. A method for manufacturing a semiconductor device, comprising: Prepare a substrate comprising an internal wafer region and a wafer edge region, wherein the internal wafer region includes a chip region and a dicing groove region; A molding layer, a support layer, and a first mask layer are sequentially stacked on the substrate. A portion of the first mask layer on the wafer edge region is removed to form a first step region in the first mask layer; A planarization mask layer is formed on the first mask layer, the planarization mask layer fills the first step region, and the top surface of the planarization mask layer has the same height in the wafer interior region and the wafer edge region; A second mask pattern with openings is formed on the planarized mask layer; as well as Using the second mask pattern as an etching mask, the planarization mask layer, the first mask layer, the support layer, and the molding layer are etched sequentially to form holes in at least the molding layer. The planarization mask layer includes a step difference compensation pattern located on the edge region of the wafer and not present on the chip region inside the wafer.

Images