Semiconductor Package

Abstract

A semiconductor package is disclosed, comprising: a first semiconductor chip; a second semiconductor chip located on a first surface of the first semiconductor chip; and a plurality of conductive pillars located on the first surface of the first semiconductor chip and adjacent to at least one side of the second semiconductor chip. The first semiconductor chip comprises a first circuit layer adjacent to the first surface of the first semiconductor chip. The second semiconductor chip and the plurality of conductive pillars are connected to the first surface of the first semiconductor chip.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2019-0100400 filed on August 16, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to semiconductor packages, and more particularly, to stacked semiconductor packages. Background Art

[0003] Semiconductor packages implement integrated circuit chips suitable for use in electronic products. Typically, in a semiconductor package, a semiconductor chip is mounted on a printed circuit board (PCB), and bonding wires or bumps are used to electrically connect the semiconductor chip to the printed circuit board. With the development of the electronics industry, the demand for compactness, lightness, and versatility of electronic products has led to many studies on stacked semiconductor packages, in which multiple semiconductor chips are stacked on a single semiconductor package. Summary of the invention

[0004] Some example embodiments of the inventive concepts provide a semiconductor package that can easily stack a plurality of semiconductor chips and has excellent reliability.

[0005] According to some example embodiments of the present inventive concept, a semiconductor package may include: a first semiconductor chip; a second semiconductor chip located on a first surface of the first semiconductor chip; and a plurality of conductive pillars located on the first surface of the first semiconductor chip and adjacent to at least one side of the second semiconductor chip. The first semiconductor chip may include a first circuit layer adjacent to the first surface of the first semiconductor chip. The second semiconductor chip and the plurality of conductive pillars may be connected to the first surface of the first semiconductor chip.

[0006] According to some example embodiments of the inventive concept, a semiconductor package may include: a first semiconductor chip; a plurality of second semiconductor chips located on a first surface of the first semiconductor chip and horizontally spaced apart from each other; and a plurality of conductive pillars located on the first surface of the first semiconductor chip and between the plurality of second semiconductor chips. The plurality of second semiconductor chips and the plurality of conductive pillars may be connected to the first surface of the first semiconductor chip.

[0007] According to some example embodiments of the present inventive concept, a semiconductor package may include: a lower structure; a first semiconductor chip located on the lower structure; a second semiconductor chip located between the lower structure and the first semiconductor chip; and a plurality of conductive pillars located between the lower structure and the first semiconductor chip. The plurality of conductive pillars may be adjacent to at least one side of the second semiconductor chip. The second semiconductor chip and the plurality of conductive pillars may be connected to a first surface of the first semiconductor chip. The first surface of the first semiconductor chip faces the lower structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Plan views illustrating semiconductor packages according to some example embodiments of the inventive concepts are illustrated.

[0009] Figure 2 Shown along Figure 1 A cross-sectional view taken along line II'.

[0010] Figures 3 to 7 Shown along Figure 1 1 is a cross-sectional view taken along line II′ of FIG. 1 , which illustrates a semiconductor package according to some example embodiments of the inventive concept.

[0011] Figures 8 to 10 Cross-sectional views illustrating a method of manufacturing a semiconductor package according to some example embodiments of the inventive concepts are illustrated.

[0012] Fig.11 and Fig.12 Cross-sectional views illustrating a method of manufacturing a semiconductor package according to some example embodiments of the inventive concepts are illustrated.

[0013] Figures 13 to 16 Shown along Figure 1 1 is a cross-sectional view taken along line II′ of FIG. 1 , which illustrates a semiconductor package according to some example embodiments of the inventive concept.

[0014] Fig.17 Cross-sectional views illustrating a method of manufacturing a semiconductor package according to some example embodiments of the inventive concepts are illustrated.

[0015] Fig.18 Cross-sectional views illustrating a method of manufacturing a semiconductor package according to some example embodiments of the inventive concepts are illustrated.

[0016] Fig.19 Cross-sectional views illustrating semiconductor packages according to some example embodiments of the inventive concepts are illustrated.

[0017] Fig. 20 Cross-sectional views illustrating semiconductor packages according to some example embodiments of the inventive concepts are illustrated.

[0018] Fig.21 Cross-sectional views illustrating semiconductor packages according to some example embodiments of the inventive concepts are illustrated. DETAILED DESCRIPTION

[0019] Some example embodiments of the inventive concept will now be described in detail below with reference to the accompanying drawings.

[0020] Figure 1 A plan view illustrating a semiconductor package 1000 according to some example embodiments of the inventive concepts is shown. Figure 2 Shown along Figure 1 A cross-sectional view taken along line II'.

[0021] Reference Figure 1 and Figure 2 , the first semiconductor chip 400 may be disposed on the substrate 100. The first semiconductor chip 400 may have a first surface 400S1 and a second surface 400S2 facing away from each other, and may include a first circuit layer 420 adjacent to the first surface 400S1. The first circuit layer 420 may include an integrated circuit. The first semiconductor chip 400 may be arranged so that the first surface 400S1 faces the top surface 100U of the substrate 100. The first semiconductor chip 400 may include a first chip pad (or "pad") 410 disposed on the first surface 400S1. The first chip pad 410 may include a conductive material. The first semiconductor chip 400 may be a logic chip or a memory chip.

[0022] The substrate 100 may be, for example, a printed circuit board (PCB). The substrate 100 may include a substrate pad 110, and the substrate pad 110 may be disposed on a top surface 100U of the substrate 100. The substrate pad 110 may include a conductive material. External terminals (not shown) may be disposed on a bottom surface 100L of the substrate 100, and the substrate pad 110 may be electrically connected to the external terminals through an internal wiring line in the substrate 100.

[0023] The second semiconductor chip 200 may be disposed between the substrate 100 and the first semiconductor chip 400. The second semiconductor chip 200 may be disposed on the first surface 400S1 of the first semiconductor chip 400 and connected to the first surface 400S1 of the first semiconductor chip 400. In some example embodiments, a plurality of second semiconductor chips 200 may be placed between the substrate 100 and the first semiconductor chip 400. The plurality of second semiconductor chips 200 may be disposed on the first surface 400S1 of the first semiconductor chip 400 and may be horizontally spaced apart from each other along the first direction D1. Each of the plurality of second semiconductor chips 200 may be connected to the first surface 400S1 of the first semiconductor chip 400.

[0024] The second semiconductor chip 200 may have a third surface 200S3 and a fourth surface 200S4 facing each other, and may include a second circuit layer 220 adjacent to the third surface 200S3. The second circuit layer 220 may include an integrated circuit. The second semiconductor chip 200 may be arranged so that the third surface 200S3 faces the first surface 400S1 of the first semiconductor chip 400. The second semiconductor chip 200 may include a second chip pad 210 disposed on the third surface 200S3. The second chip pad 210 may include a conductive material.

[0025] The connector 310 may be disposed between the first semiconductor chip 400 and the second semiconductor chip 200, and may be connected to the corresponding second chip pad 210. The connector 310 may be bonded to the corresponding first chip pad 410 in the first chip pad 410 of the first semiconductor chip 400. The connector 310 may include a conductive material, and may have one or more shapes in a solder ball shape, a bump shape, and a column shape. The second semiconductor chip 200 may be electrically connected to the first semiconductor chip 400 through the second chip pad 210, the connector 310, and the corresponding first chip pad 410. The fourth surface 200S4 of the second semiconductor chip 200 may face the top surface 100U of the substrate 100, and may be spaced apart from the top surface 100U of the substrate 100.

[0026] The second semiconductor chip 200 may be a logic chip or a memory chip. For example, the first semiconductor chip 400 may be a logic chip, and the second semiconductor chip 200 may be a memory chip. In some example embodiments, at least one of the plurality of second semiconductor chips 200 may be replaced by a passive device (e.g., a capacitor).

[0027] Each of the first semiconductor chip 400 and the second semiconductor chip 200 may have a width along the first direction D1. The first semiconductor chip 400 may have a width 400W greater than a width 200W of the second semiconductor chip 200. In some example embodiments, the width 400W of the first semiconductor chip 400 may be greater than the sum of the widths 200W of the plurality of second semiconductor chips 200.

[0028] A plurality of conductive pillars 300 may be disposed between the substrate 100 and the first semiconductor chip 400. On the first surface 400S1 of the first semiconductor chip 400, the conductive pillars 300 may be placed adjacent to at least one side of the second semiconductor chip 200. In some example embodiments, the conductive pillars 300 may be disposed between the plurality of second semiconductor chips 200. The conductive pillars 300 may be horizontally spaced apart from each other along the first direction D1 on the first surface 400S1 of the first semiconductor chip 400. Each of the conductive pillars 300 may be connected to the first surface 400S1 of the first semiconductor chip 400. For example, the conductive pillars 300 may be connected to a corresponding first chip pad 410 in the first chip pads 410 of the first semiconductor chip 400. The conductive pillars 300 may include a metal (e.g., copper).

[0029] The second semiconductor chip 200 and each of the conductive pillars 300 may have their heights along the second direction D2 perpendicular to the first surface 400S1 of the first semiconductor chip 400. In some example embodiments, each of the conductive pillars 300 may have a height 300H greater than a height 200H of the second semiconductor chip 200. Each of the conductive pillars 300 may have a surface 300S facing the top surface 100U of the substrate 100 and spaced apart from the top surface 100U of the substrate 100. The surface 300S of each of the conductive pillars 300 may be positioned at a level substantially the same as that of the first surface 400S1 of the first semiconductor chip 400 and the fourth surface 200S4 of the second semiconductor chip 200.

[0030] The mold layer 350 may be disposed between the substrate 100 and the first semiconductor chip 400, and may cover the lateral surface of the second semiconductor chip 200 and the lateral surface of the conductive pillar 300, thereby separating the second semiconductor chip 200 and the conductive pillar 300. The mold layer 350 may extend between the first semiconductor chip 400 and the second semiconductor chip 200, thereby covering the connector 310. In some example embodiments, the mold layer 350 may be spaced apart from the top surface 100U of the substrate 100, and may have a surface 350S that is substantially coplanar with the fourth surface 200S4 of the second semiconductor chip 200 and the surface 300S of each of the conductive pillars 300. The mold layer 350 may not cover but expose the fourth surface 200S4 of the second semiconductor chip 200 and the surface 300S of each of the conductive pillars 300. The mold layer 350 may include a dielectric material (e.g., an epoxy-based molding compound).

[0031] A plurality of bumps 320 may be disposed between the substrate 100 and the conductive pillars 300 and may be connected to the conductive pillars 300. Each of the conductive pillars 300 may penetrate the mold layer 350 and may have a connection with a corresponding one of the bumps 320. The bumps 320 may be connected to the substrate pad 110. Each of the conductive pillars 300 may be connected to the substrate 100 through the corresponding bump 320. The bumps 320 may include a conductive material.

[0032] The first semiconductor chip 400 may be electrically connected to the substrate 100 through the conductive pillars 300. In some example embodiments, the second semiconductor chip 200 may be spaced apart from the substrate 100. In this case, the second semiconductor chip 200 may be connected to the corresponding conductive pillars 300 through internal wiring lines in the first semiconductor chip 400, and may be electrically connected to the substrate 100 through the corresponding conductive pillars 300.

[0033] According to some example embodiments, a semiconductor package 1000 may include a first semiconductor chip 400 and a second semiconductor chip 200 stacked on a substrate 100. The semiconductor package 1000 may be provided with a first semiconductor chip 400 in an upper portion thereof, and a width 400W of the first semiconductor chip 400 is larger than a width 200W of the second semiconductor chip 200. Therefore, heat can be easily discharged outward from the first semiconductor chip 400. In addition, the semiconductor package 1000 may include a conductive column 300 for electrical connection between the first semiconductor chip 400 and the substrate 100. Because the first semiconductor chip 400 is electrically connected to the substrate 100 through the conductive column 300, the first semiconductor chip 400 may not require a through electrode therein. As a result, a semiconductor package can be provided that can easily stack a plurality of semiconductor chips and has excellent reliability.

[0034] Figure 3 Shown along Figure 1 A cross-sectional view taken along line II' of FIG. 1 shows an example of a semiconductor package 1000 according to some example embodiments of the inventive concept. For the sake of brevity of description, the following will focus on the semiconductor package 1000 described above. Figure 1 and Figure 2 The differences of the semiconductor package 1000 are discussed.

[0035] Reference Figure 1 and Figure 3, the bottom filling layer 370 may be disposed between the first semiconductor chip 400 and the second semiconductor chip 200, and may cover the connectors 310. The bottom filling layer 370 may cover the third surface 200S3 of the second semiconductor chip 200, and may fill the gap between the connectors 310. The bottom filling layer 370 may be partially disposed on the third surface 200S3 of the second semiconductor chip 200, and may contact the molding layer 350. The bottom filling layer 370 may include a dielectric polymer material such as an epoxy resin.

[0036] Figure 4 Shown along Figure 1 A cross-sectional view taken along line II' of FIG. 1 shows an example of a semiconductor package 1000 according to some example embodiments of the present inventive concept. For the sake of brevity of description, the following will focus on the above reference Figure 1 and Figure 2 The differences of the semiconductor package 1000 are discussed.

[0037] Reference Figure 1 and Figure 4 , the second semiconductor chip 200 may be disposed so that the third surface 200S3 faces the first surface 400S1 of the first semiconductor chip 400, and may be connected to the first surface 400S1 of the first semiconductor chip 400. The fourth surface 200S4 of the second semiconductor chip 200 may face the top surface 100U of the substrate 100, and be spaced apart from the top surface 100U of the substrate 100. The surface 300S of each of the conductive pillars 300 may face the top surface 100U of the substrate 100, and may be spaced apart from the top surface 100U of the substrate 100. In some example embodiments, the surface 300S of each of the conductive pillars 300 may be positioned farther from the first surface 400S1 of the first semiconductor chip 400 than from the fourth surface 200S4 of the second semiconductor chip 200.

[0038] In some example embodiments, the mold layer 350 may cover the lateral surfaces of the second semiconductor chip 200 and the lateral surfaces of the conductive pillars 300, and may also cover the fourth surface 200S4 of the second semiconductor chip 200. The mold layer 350 may encapsulate the second semiconductor chip 200. The mold layer 350 may be spaced apart from the top surface 100U of the substrate 100, and a surface 350S of the mold layer 350 may be substantially coplanar with a surface 300S of each of the conductive pillars 300.

[0039] Figure 5 Shown along Figure 1 A cross-sectional view taken along line II' of FIG. 1 shows an example of a semiconductor package 1000 according to some example embodiments of the inventive concept. For the sake of brevity of description, the following will focus on the semiconductor package 1000 described above. Figure 1 and Figure 2 The differences of the semiconductor package 1000 are discussed.

[0040] Reference Figure 1 and Figure 5 , the second semiconductor chip 200 may be disposed to be connected to the first surface 400S1 of the first semiconductor chip 400. The third surface 200S3 of the second semiconductor chip 200 may face the first surface 400S1 of the first semiconductor chip 400, and the fourth surface 200S4 of the second semiconductor chip 200 may face the top surface 100U of the substrate 10. In some example embodiments, the second circuit layer (see Figure 2 The substrate 220 ) may be adjacent to the third surface 200S3 or the fourth surface 200S4 of the second semiconductor chip 200 .

[0041] The through-electrodes 230 may be disposed in the second semiconductor chip 200, and the conductive pads 240 may be disposed on the fourth surface 200S4 of the second semiconductor chip 200. Each of the through-electrodes 230 may penetrate the second semiconductor chip 200, and may have a connection with a corresponding one of the second chip pads 210 and a corresponding one of the conductive pads 240. The through-electrodes 230 and the conductive pads 240 may include a conductive material.

[0042] Each of the conductive pads 240 may have a surface 240S facing the top surface 100U of the substrate 100 and spaced apart from the top surface 100U of the substrate 100. A surface 300S of each of the conductive pillars 300 may face the top surface 100U of the substrate 100 and may be spaced apart from the top surface 100U of the substrate 100. The surface 240S of each of the conductive pads 240 may be positioned at substantially the same level from the first surface 400S1 of the first semiconductor chip 400 to the level of the surface 300S of each of the conductive pillars 300.

[0043] The mold layer 350 may cover the lateral surfaces of the second semiconductor chip 200 and the lateral surfaces of the conductive pillars 300, and may extend onto the fourth surface 200S4 of the second semiconductor chip 200 to cover the conductive pad 240. The mold layer 350 may be spaced apart from the top surface 100U of the substrate 100, and the surface 350S of the mold layer 350 may be substantially coplanar with the surface 240S of the conductive pad 240 and with the surface 300S of the conductive pillar 300. The mold layer 350 may not cover but expose the surface 240S of the conductive pad 240 and the surface 300S of the conductive pillar 300.

[0044] A plurality of bumps 320 may be disposed between the substrate 100 and the conductive pillars 300 and between the substrate 100 and the conductive pads 240, and may be connected to the conductive pillars 300 and the conductive pads 240. The bumps 320 may be bonded to the substrate pad 110. Each of the conductive pillars 300 and the conductive pads 240 may be connected to the substrate 100 through a corresponding one of the bumps 320.

[0045] The first semiconductor chip 400 may be electrically connected to the substrate 100 through the conductive pillars 300. In addition, at least one of the through electrodes 230 may be used for electrical connection between the first semiconductor chip 400 and the substrate 100. In this case, the first semiconductor chip 400 may be electrically connected to the substrate 100 through a corresponding through electrode 230 of the through electrodes 230 in the second semiconductor chip 200. The second semiconductor chip 200 may be electrically connected to the substrate 100 through a corresponding through electrode 230 of the through electrodes 230.

[0046] Figure 6 Shown along Figure 1 A cross-sectional view taken along line II' of FIG. 1 shows an example of a semiconductor package 1000 according to some example embodiments of the inventive concept. For the sake of brevity of description, the following will focus on the semiconductor package 1000 described above. Figure 1 and Figure 2 The differences of the semiconductor package 1000 are discussed.

[0047] Reference Figure 1 and Figure 6 , a plurality of second semiconductor chips 200 may be disposed between the substrate 100 and the first semiconductor chip 400. The plurality of second semiconductor chips 200 may be placed on the first surface 400S1 of the first semiconductor chip 400 and may be horizontally spaced apart from each other along the first direction D1. Each of the plurality of second semiconductor chips 200 may be connected to the first surface 400S1 of the first semiconductor chip 400. Each of the plurality of second semiconductor chips 200 may include a third surface 200S3 and a fourth surface 200S4 facing away from each other. The third surface 200S3 of each of the plurality of second semiconductor chips 200 may face the first surface 400S1 of the first semiconductor chip 400, and the fourth surface 200S4 of each of the plurality of second semiconductor chips 200 may face the top surface 100U of the substrate 100. Each of the plurality of second semiconductor chips 200 may include a second circuit layer 220. The second circuit layer 220 included in one second semiconductor chip 200a of the plurality of second semiconductor chips 200 may be adjacent to the third surface 200S3 or the fourth surface 200S4. The second circuit layer 220 included in another second semiconductor chip 200 b among the plurality of second semiconductor chips 200 may be adjacent to the third surface 200S 3 .

[0048] The through-electrode 230 may be disposed in one second semiconductor chip 200a among the plurality of second semiconductor chips 200, and the conductive pad 240 may be disposed on the fourth surface 200S4 of the one second semiconductor chip 200a among the plurality of second semiconductor chips 200. Each of the through-electrodes 230 may penetrate one second semiconductor chip 200a among the plurality of second semiconductor chips 200, and may have connections with a corresponding one of the second chip pads 210 and with a corresponding one of the conductive pads 240. Neither the through-electrode 230 nor the conductive pad 240 may be disposed on the second semiconductor chip 200b of the plurality of second semiconductor chips 200.

[0049] Each of the conductive pads 240 may have a surface 240S facing the top surface 100U of the substrate 100 and spaced apart from the top surface 100U of the substrate 100. The surface 300S of each of the conductive pillars 300 may face the top surface 100U of the substrate 100 and may be spaced apart from the top surface 100U of the substrate 100. The surface 240S of each of the conductive pads 240 may be positioned at a level substantially the same as that of the first surface 400S1 of the first semiconductor chip 400 and the surface 300S of each of the conductive pillars 300. The fourth surface 200S4 of the second semiconductor chip 200b of the plurality of second semiconductor chips 200 may face the top surface 100U of the substrate 100 and may be spaced apart from the top surface 100U of the substrate 100. The fourth surface 200S4 of the second semiconductor chip 200 b of the plurality of second semiconductor chips 200 may be positioned at substantially the same level from the first surface 400S1 of the first semiconductor chip 400 and the surface 300S of each of the conductive pillars 300 , but the inventive concept is not limited thereto.

[0050] The mold layer 350 may cover the plurality of second semiconductor chips 200 and the conductive pillars 300. The mold layer 350 may extend onto the fourth surface 200S4 of a second semiconductor chip 200a among the plurality of second semiconductor chips 200, thereby covering the conductive pad 240. The mold layer 350 may be spaced apart from the top surface 100U of the substrate 100, and the surface 350S of the mold layer 350 may be substantially coplanar with the surface 240S of the conductive pad 240 and with the surface 300S of the conductive pillar 300. The mold layer 350 may not cover but expose the surface 240S of the conductive pad 240 and the surface 300S of the conductive pillar 300. In some example embodiments, the surface 350S of the mold layer 350 may be substantially coplanar with the fourth surface 200S4 of the second semiconductor chip 200b of the plurality of second semiconductor chips 200. In this case, the mold layer 350 may not cover but expose the fourth surface 200S4 of the second semiconductor chip 200b among the plurality of second semiconductor chips 200.

[0051] A plurality of bumps 320 may be disposed between the substrate 100 and the conductive pillars 300 and between the substrate 100 and the conductive pads 240, and may be connected to the conductive pillars 300 and the conductive pads 240. The bumps 320 may be bonded to the substrate pad 110. Each of the conductive pillars 300 and the conductive pads 240 may be connected to the substrate 100 through a corresponding one of the bumps 320.

[0052] The first semiconductor chip 400 may be electrically connected to the substrate 100 through the conductive pillars 300. In addition, at least one of the through electrodes 230 may be used for electrical connection between the first semiconductor chip 400 and the substrate 100. In this case, the first semiconductor chip 400 may be electrically connected to the substrate 100 through a corresponding through electrode 230 among the through electrodes 230 in one of the second semiconductor chips 200a among the plurality of second semiconductor chips 200.

[0053] One second semiconductor chip 200a among the plurality of second semiconductor chips 200 may be electrically connected to the substrate 100 through a corresponding through-electrode 230 among the through-electrodes 230. A second semiconductor chip 200b among the plurality of second semiconductor chips 200 may not include the through-electrode 230. In this case, a second semiconductor chip 200b among the plurality of second semiconductor chips 200 may be connected to a corresponding conductive pillar 300 among the conductive pillars 300 through an internal wiring line in the first semiconductor chip 400, and may be electrically connected to the substrate 100 through the corresponding conductive pillar 300.

[0054] Figure 7 Shown along Figure 1A cross-sectional view taken along line II' of FIG. 1 shows an example of a semiconductor package 1000 according to some example embodiments of the inventive concept. For the sake of brevity of description, the following will focus on the semiconductor package 1000 described above. Figure 1 and Figure 2 The differences of the semiconductor package 1000 are discussed.

[0055] Reference Figure 1 and Figure 7 , a plurality of second semiconductor chips 200 may be disposed between the substrate 100 and the first semiconductor chip 400. The plurality of second semiconductor chips 200 may be disposed on the first surface 400S1 of the first semiconductor chip 400 and may be horizontally spaced apart from each other along the first direction D1. Each of the plurality of second semiconductor chips 200 may be connected to the first surface 400S1 of the first semiconductor chip 400.

[0056] One second semiconductor chip 200a among the plurality of second semiconductor chips 200 may include a plurality of sub-semiconductor chips 202, 204, and 206 stacked along a second direction D2 perpendicular to the first surface 400S1 of the first semiconductor chip 400. Each of the sub-semiconductor chips 202, 204, and 206 may be a logic chip or a memory chip. A through-electrode 230 may be provided in one second semiconductor chip 200a among the plurality of second semiconductor chips 200, and a conductive pad 240 may be provided on a fourth surface 200S4 of the second semiconductor chip 200a among the plurality of second semiconductor chips 200. Each of the through-electrodes 230 may penetrate the sub-semiconductor chips 202, 204, and 206, and may have a connection with a corresponding one of the second chip pads 210 and a corresponding one of the conductive pads 240. In addition to what has been mentioned previously, the semiconductor package 1000 according to some example embodiments may be similar to the one described above with reference to FIG. Figure 1 and Figure 6 The semiconductor package 1000 discussed is substantially the same. Furthermore, one of ordinary skill in the art may appreciate that a plurality of sub-semiconductor chips 202 , 204 , and 206 may be present in any one of the second semiconductor chips 200 a , and the number of sub-semiconductor chips is not limited to the number shown.

[0057] Figures 8 to 10 A cross-sectional view showing a method of manufacturing a semiconductor package according to some example embodiments of the present inventive concept is shown. Figure 1 and Figure 2 The repeated explanation of the discussed semiconductor package will be omitted.

[0058] Reference Figure 8, a wafer 400WF including a plurality of first semiconductor chips 400 may be provided. The plurality of first semiconductor chips 400 may include a first circuit layer 420 correspondingly, and the first circuit layer 420 may be disposed adjacent to the top surface 400U of the wafer 400WF. The first circuit layer 420 may include an integrated circuit. The plurality of first semiconductor chips 400 may include a first chip pad 410, and the first chip pad 410 may be disposed adjacent to the top surface 400U of the wafer 400WF. The first chip pad 410 may be electrically connected to the first circuit layer 420.

[0059] A plurality of conductive pillars 300 may be formed on the top surface 400U of the wafer 400WF. A chip mounting region 400R may be defined in advance on the top surface 400U of the wafer 400WF, and the conductive pillars 300 may be formed on the top surface 400U other than the chip mounting region 400R of the wafer 400WF. The conductive pillars 300 may be connected to corresponding first chip pads 410 in the first chip pads 410. The conductive pillars 300 may be formed by adopting, for example, an electroplating process. For example, the formation of the conductive pillars 300 may include the following steps: forming a photoresist pattern having an opening on the top surface 400U of the wafer 400WF, the opening exposing an area where the conductive pillars 300 are formed; forming a seed layer on the photoresist pattern; and performing an electroplating process on the seed layer to form the conductive pillars 300. After the conductive pillars 300 are formed, the photoresist pattern may be removed.

[0060] Reference Fig. 9 , on the chip mounting region 400R, a connector 310 may be formed on the top surface 400U of the wafer 400WF. The connector 310 may be formed on a corresponding first chip pad 410 among the first chip pads 410 and may be connected to the corresponding first chip pad 410.

[0061] A plurality of second semiconductor chips 200 may be disposed on the corresponding chip mounting region 400R. Each of the plurality of second semiconductor chips 200 may include a second chip pad 210, and the second chip pad 210 may be disposed adjacent to one surface of each of the second semiconductor chips 200. Each of the second semiconductor chips 200 may be disposed on the top surface 400U of the wafer 400WF so that the second chip pad 210 may contact a corresponding one of the connectors 310.

[0062] The mold layer 350 may be formed on the top surface 400U of the wafer 400WF, and may be caused to cover the second semiconductor chips 200 and the conductive pillars 300. In some example embodiments, the mold layer 350 may extend between the wafer 400WF and each of the second semiconductor chips 200, thereby covering the connectors 310. The mold layer 350 may fill the space between the connectors 310. In some example embodiments, before forming the mold layer 350, a mold layer 350 may be formed. Figure 3 The underfill layer 370 discussed in hereinafter is formed to fill the space between the wafer 400WF and each of the second semiconductor chips 200 and to cover the connectors 310 .

[0063] Reference Fig.10 , the mold layer 350 may be subjected to a grinding process to remove an upper portion of the mold layer 350. The grinding process may expose one surface of each of the conductive pillars 300. In some example embodiments, the grinding process may expose one surface of each of the second semiconductor chips 200. In some example embodiments, as Figure 4 As discussed in , the second semiconductor chip 200 may not be exposed through the grinding process, but the second semiconductor chip 200 may be covered with the mold layer 350 .

[0064] A plurality of bumps 320 may be formed on the mold layer 350. The bumps 320 may be formed on the corresponding conductive pillars 300, and the bumps 320 may be connected to the corresponding conductive pillars 300. Through the above-mentioned processes, a stacked structure SS may be formed. The cutting process SP may divide the stacked structure SS into a plurality of chip stacks CS. The cutting process SP may separate the wafer 400WF into a plurality of first semiconductor chips 400, and the chip stack CS may include the corresponding first semiconductor chips 400. Each of the chip stacks CS may include one or more second semiconductor chips 200 stacked on the first semiconductor chip 400, and may also include a conductive pillar 300 formed on the first semiconductor chip 400.

[0065] Return to reference Figure 1 and Figure 2 , one of the chip stacks CS may be disposed on the substrate 100. The substrate 100 may be, for example, a printed circuit board (PCB). The substrate 100 may include a substrate pad 110 disposed on a top surface 100U of the substrate 100. The chip stack CS may be stacked on the top surface 100U of the substrate 100 so that the bump 320 may contact a corresponding one of the substrate pads 110. The substrate 100 and the chip stack CS may constitute a semiconductor package 1000.

[0066] Fig.11 and Fig.12A cross-sectional view showing a method of manufacturing a semiconductor package according to some example embodiments of the present inventive concept is shown. Figures 8 to 10 The differences in the methods of manufacturing semiconductor packages are discussed.

[0067] First, as mentioned above Figure 8 As discussed, a wafer 400WF including a plurality of first semiconductor chips 400 may be provided, and a plurality of conductive pillars 300 may be formed on a top surface 400U of the wafer 400WF. The conductive pillars 300 may be formed on the top surface 400U except for a chip mounting region 400R of the wafer 400WF.

[0068] Reference Fig.11 , on the chip mounting region 400R, a connector 310 may be formed on the top surface 400U of the wafer 400WF. The connector 310 may be formed on a corresponding first chip pad 410 among the first chip pads 410 and may be connected to the corresponding first chip pad 410.

[0069] A plurality of second semiconductor chips 200 may be disposed on the corresponding chip mounting region 400R. Each of the plurality of second semiconductor chips 200 may include a second chip pad 210, and the second chip pad 210 may be disposed adjacent to one surface of each of the second semiconductor chips 200. In some example embodiments, each of the second semiconductor chips 200 may include a through electrode 230 penetrating therethrough, and may also include a conductive pad 240 disposed on the other surface of each of the second semiconductor chips 200. The through electrode 230 may penetrate each of the second semiconductor chips 200, and may have a connection with the second chip pad 210 and the conductive pad 240. Each of the second semiconductor chips 200 may be disposed on the top surface 400U of the wafer 400WF so that the second chip pad 210 may contact the corresponding connector 310 of the connector 310. A mold layer 350 may be formed on the top surface 400U of the wafer 400WF, and the mold layer 350 may be covered with the second semiconductor chips 200 and the conductive pillars 300.

[0070] Reference Fig.12, the mold layer 350 may be subjected to a grinding process to remove an upper portion of the mold layer 350. The grinding process may expose one surface of each of the conductive pillars 300 and one surface of each of the conductive pads 240. A plurality of bumps 320 may be formed on the mold layer 350. The bumps 320 may be formed on corresponding conductive pillars 300 and corresponding conductive pads 240, and the bumps 320 may be connected to corresponding conductive pillars 300 and corresponding conductive pads 240. Through the above-mentioned processes, a stack structure SS may be formed. The cutting process SP may divide the stack structure SS into a plurality of chip stacks CS. Other processes are the same as those described above with reference to FIG. Figure 1 , Figure 2 and Figures 8 to 10 The discussed semiconductor package manufacturing methods are basically the same.

[0071] Fig.13 Shown along Figure 1 1 is a cross-sectional view taken along line II′ of FIG. 1 , which illustrates an example of a semiconductor package 1000 according to some example embodiments of the inventive concepts.

[0072] Reference Figure 1 and Fig.13 , the second chip pads 210 of the second semiconductor chip 200 may be in direct contact with corresponding first chip pads 410 of the first semiconductor chip 400. In some example embodiments, there may be no Figure 1 and Figure 2 The connector 310 discussed above. Each of the conductive pillars 300 of the second semiconductor chip 200 may have a height along a second direction D2 perpendicular to the first surface 400S1 of the first semiconductor chip 400. In some example embodiments, each of the conductive pillars 300 may have a height 300H substantially the same as the height 200H of the second semiconductor chip 200. In addition to the foregoing, the semiconductor package 1000 according to some example embodiments may be the same as described above with reference to Figure 1 and Figure 2 The semiconductor package 1000 discussed is substantially the same.

[0073] Fig.14 Shown along Figure 1 1 is a cross-sectional view taken along line II′ of FIG. 1 , which illustrates an example of a semiconductor package 1000 according to some example embodiments of the inventive concepts.

[0074] Reference Figure 1 and Fig.14 , the second chip pads 210 of the second semiconductor chip 200 may be in direct contact with corresponding first chip pads 410 of the first semiconductor chip 400. In some example embodiments, there may be no Figure 1 and Figure 2 Connector 310 discussed.

[0075] Each of the conductive pillars 300 of the second semiconductor chip 200 may have a height along a second direction D2 perpendicular to the first surface 400S1 of the first semiconductor chip 400. In some example embodiments, each of the conductive pillars 300 may have a height 300H greater than a height 200H of the second semiconductor chip 200. A surface 300S of each of the conductive pillars 300 may face the top surface 100U of the substrate 100 and may be spaced apart from the top surface 100U of the substrate 100. The surface 300S of each of the conductive pillars 300 may be located farther from the first surface 400S1 of the first semiconductor chip 400 than from the fourth surface 200S4 of the second semiconductor chip 200. In addition to the foregoing, the semiconductor package 1000 according to some example embodiments may be similar to the above-mentioned semiconductor package. Figure 1 and Figure 4 The semiconductor package 1000 discussed is substantially the same.

[0076] Fig.15 Shown along Figure 1 1 is a cross-sectional view taken along line II′ of FIG. 1 , which illustrates an example of a semiconductor package 1000 according to some example embodiments of the inventive concepts.

[0077] Reference Figure 1 and Fig.15 , the second chip pads 210 of the second semiconductor chip 200 may be in direct contact with corresponding first chip pads 410 of the first semiconductor chip 400. In some example embodiments, there may be no Figure 1 and Figure 2 In addition to the foregoing, the semiconductor package 1000 according to some example embodiments may be the same as that described above with reference to FIG. Figure 1 and Figure 5 The semiconductor package 1000 discussed is substantially the same.

[0078] Fig.16 Shown along Figure 1 1 is a cross-sectional view taken along line II′ of FIG. 1 , which illustrates an example of a semiconductor package 1000 according to some example embodiments of the inventive concepts.

[0079] Reference Figure 1 and Fig.16, a plurality of second semiconductor chips 200 may be disposed between the substrate 100 and the first semiconductor chip 400. Each of the plurality of second semiconductor chips 200 may be connected to the first surface 400S1 of the first semiconductor chip 400. The second chip pad 210 of each of the plurality of second semiconductor chips 200 may be in direct contact with a corresponding first chip pad 410 of the first chip pad 410 of the first semiconductor chip 400. In addition to the foregoing, the semiconductor package 1000 according to some example embodiments may be similar to the above-mentioned Figure 1 and Figure 6 The semiconductor package 1000 discussed is substantially the same.

[0080] Fig.17 A cross-sectional view showing a method of manufacturing a semiconductor package according to some example embodiments of the present inventive concept is shown. Figures 8 to 10 The differences in the methods of manufacturing semiconductor packages are discussed.

[0081] First, as mentioned above Figure 8 As discussed, a wafer 400WF including a plurality of first semiconductor chips 400 may be provided, and a plurality of conductive pillars 300 may be formed on a top surface 400U of the wafer 400WF. The conductive pillars 300 may be formed on the top surface 400U except for a chip mounting region 400R of the wafer 400WF.

[0082] Reference Fig.17 , a plurality of second semiconductor chips 200 may be disposed on the corresponding chip mounting region 400R. Each of the plurality of second semiconductor chips 200 may include a second chip pad 210, and the second chip pad 210 may be disposed adjacent to one surface of each of the second semiconductor chips 200. Each of the second semiconductor chips 200 may be stacked on the top surface 400U of the wafer 400WF so that the second chip pad 210 may be in direct contact with the corresponding first chip pad 410 of the first chip pads 410. Due to the heat treatment, the second chip pad 210 of each of the second semiconductor chips 200 may be bonded (or bonded) to the corresponding first chip pad 410. A mold layer 350 may be formed on the top surface 400U of the wafer 400WF, and the mold layer 350 may be made to cover the second semiconductor chips 200 and the conductive pillars 300. Other processes are the same as those referred to above. Figure 1 , Figure 2 and Figures 8 to 10 The discussed semiconductor package manufacturing methods are basically the same.

[0083] Fig.18 A cross-sectional view showing a method of manufacturing a semiconductor package according to some example embodiments of the present invention is shown. Figures 8 to 10The differences in the methods of manufacturing semiconductor packages are discussed.

[0084] First, as mentioned above Figure 8 As discussed, a wafer 400WF including a plurality of first semiconductor chips 400 may be provided, and a plurality of conductive pillars 300 may be formed on a top surface 400U of the wafer 400WF. The conductive pillars 300 may be formed on the top surface 400U except for a chip mounting region 400R of the wafer 400WF.

[0085] Reference Fig.18 , a plurality of second semiconductor chips 200 may be disposed on the corresponding chip mounting region 400R. Each of the plurality of second semiconductor chips 200 may include a second chip pad 210, and the second chip pad 210 may be disposed adjacent to one surface of each of the second semiconductor chips 200. In some example embodiments, each of the second semiconductor chips 200 may include a through electrode 230 penetrating therethrough, and may also include a conductive pad 240 disposed on the other surface of each of the second semiconductor chips 200. The through electrode 230 may penetrate each of the second semiconductor chips 200, and may have connections with the second chip pad 210 and the conductive pad 240. Each of the second semiconductor chips 200 may be stacked on the top surface 400U of the wafer 400WF so that the second chip pad 210 may be in direct contact with the corresponding first chip pad 410 of the first chip pad 410. Due to the heat treatment, the second chip pad 210 of each of the second semiconductor chips 200 may be bonded (or bonded) to the corresponding first chip pad 410. A mold layer 350 may be formed on the top surface 400U of the wafer 400WF, and the mold layer 350 may cover the second semiconductor chip 200 and the conductive pillars 300. Other processes are the same as those described above. Figure 1 , Figure 2 and Figures 8 to 10 The discussed semiconductor package manufacturing methods are basically the same.

[0086] Fig.19 A cross-sectional view of a semiconductor package 1100 is shown according to some example embodiments of the inventive concept. For the sake of brevity of description, the following will focus on the above reference Figure 1 and Figure 2 The differences of the semiconductor package 1000 are discussed.

[0087] Reference Fig.19, the first semiconductor chip 400 may be disposed on the redistribution layer 100R. The first semiconductor chip 400 may be disposed so that the first surface 400S1 faces the top surface 100RU of the redistribution layer 100R. The redistribution layer 100R may include a redistribution pattern 150. The redistribution pattern 150 may include a conductive material. For simplicity of explanation, a portion of the redistribution pattern 150 is indicated by a dotted line. The redistribution layer 100R and the first semiconductor chip 400 may each have a width in the first direction D1. The redistribution layer 100R may have a width 100RW greater than the width 400W of the first semiconductor chip 400. In this specification, the redistribution layer 100R may be referred to as a substrate.

[0088] The second semiconductor chip 200 may be disposed between the redistribution layer 100R and the first semiconductor chip 400. The second semiconductor chip 200 may be disposed on the first surface 400S1 of the first semiconductor chip 400 and connected to the first surface 400S1 of the first semiconductor chip 400. In some example embodiments, a plurality of second semiconductor chips 200 may be disposed between the redistribution layer 100R and the first semiconductor chip 400. The plurality of second semiconductor chips 200 may be disposed on the first surface 400S1 of the first semiconductor chip 400 and may be horizontally spaced apart from each other along a first direction D1 parallel to the first surface 400S1. Each of the plurality of second semiconductor chips 200 may be connected to the first surface 400S1 of the first semiconductor chip 400.

[0089] In some example embodiments, the through-electrodes 230 may be disposed in at least one of the plurality of second semiconductor chips 200, and the conductive pads 240 may be disposed on the fourth surface 200S4 of at least one of the plurality of second semiconductor chips 200. Each of the through-electrodes 230 may penetrate at least one of the plurality of second semiconductor chips 200, and may have a connection with a corresponding one of the second chip pads 210 and a corresponding one of the conductive pads 240. In some example embodiments, neither the through-electrodes 230 nor the conductive pads 240 may be disposed on another of the plurality of second semiconductor chips 200, but the inventive concept is not limited thereto.

[0090] A plurality of conductive pillars 300 may be disposed between the redistribution layer 100R and the first semiconductor chip 400. Each of the conductive pillars 300 may be connected to the first surface 400S1 of the first semiconductor chip 400. For example, the conductive pillars 300 may be connected to corresponding ones of the first chip pads 410 of the first semiconductor chip 400.

[0091] The mold layer 350 may be disposed between the redistribution layer 100R and the first semiconductor chip 400, and may cover the lateral surfaces of the second semiconductor chips 200 and the lateral surfaces of the conductive pillars 300. The mold layer 350 may extend onto the fourth surface 200S4 of each of the plurality of second semiconductor chips 200, thereby covering the fourth surface 200S4. The mold layer 350 may extend onto the fourth surface 200S4 of at least one of the plurality of second semiconductor chips 200, thereby covering the conductive pads 240. The mold layer 350 may contact the top surface 100RU of the redistribution layer 100R. The conductive pillars 300 and the conductive pads 240 may each penetrate at least a portion of the mold layer 350 and have a connection with a corresponding redistribution pattern 150 in the redistribution pattern 150.

[0092] A plurality of bumps 320 may be disposed on the bottom surface 100RL of the redistribution layer 100R. Each of the plurality of bumps 320 may be connected to a corresponding one of the redistribution patterns 150. The conductive pillars 300 and the conductive pads 240 may each be electrically connected to a corresponding one of the plurality of bumps 320 through the corresponding redistribution pattern 150.

[0093] The first semiconductor chip 400 may be electrically connected to the redistribution layer 100R through the conductive pillars 300. In addition, at least one of the through electrodes 230 may be used for electrical connection between the first semiconductor chip 400 and the redistribution layer 100R. In this case, the first semiconductor chip 400 may be electrically connected to the redistribution layer 100R through a corresponding through electrode 230 in at least one of the plurality of second semiconductor chips 200.

[0094] At least one of the plurality of second semiconductor chips 200 may be electrically connected to the redistribution layer 100R through a corresponding through-electrode 230 of the through-electrodes 230. Another one of the plurality of second semiconductor chips 200 may be connected to a corresponding conductive pillar 300 of the conductive pillars 300 through an internal wiring line in the first semiconductor chip 400, and may be electrically connected to the redistribution layer 100R through the corresponding conductive pillar 300.

[0095] An additional mold layer 500 covering the first semiconductor chip 400 and the mold layer 350 may be disposed on the redistribution layer 100R. The additional mold layer 500 may extend along the sidewalls of the first semiconductor chip 400 and the mold layer 350, and may contact the top surface 100RU of the redistribution layer 100R. The additional mold layer 500 may include a dielectric material (e.g., an epoxy-based mold compound). In some example embodiments, the additional mold layer 500 may be omitted. The semiconductor package 1100 according to some example embodiments may include a fan-out wafer-level package.

[0096] Fig. 20 A cross-sectional view of a semiconductor package 1200 is shown showing some example embodiments of the inventive concept. For the sake of brevity of description, the following will focus on the above reference Figure 1 and Figure 2 The differences of the semiconductor package 1000 are discussed.

[0097] Reference Fig. 20 , the lower semiconductor chip 600 may be disposed on the substrate 100. The substrate 100 may be, for example, a printed circuit board (PCB). The substrate 100 may include a substrate pad 110, and the substrate pad 110 may be disposed on the top surface 100U of the substrate 100.

[0098] The lower semiconductor chip 600 may have a fifth surface 600S5 and a sixth surface 600S6, and may include a lower chip pad 610 disposed on the fifth surface 600S5. The lower chip pad 610 may include a conductive material. The lower semiconductor chip 600 may be disposed so that the sixth surface 600S6 faces the top surface 100U of the substrate 100. The lower semiconductor chip 600 may be a logic chip or a memory chip.

[0099] The lower through-electrodes 650 may be disposed in the lower semiconductor chip 600, and the lower bumps 620 may be disposed on the sixth surface 600S6 of the lower semiconductor chip 600. Each of the lower through-electrodes 650 may penetrate the lower semiconductor chip 600, and may have a connection with a corresponding one of the lower chip pads 610 and a corresponding one of the lower bumps 620. Each of the lower bumps 620 may be connected to a corresponding one of the substrate pads 110. The lower through-electrodes 650 and the lower bumps 620 may include a conductive material.

[0100] The first semiconductor chip 400 may be disposed on the lower semiconductor chip 600. The first semiconductor chip 400 may be disposed so that the first surface 400S1 faces the fifth surface 600S5 of the lower semiconductor chip 600. The second semiconductor chip 200 may be disposed between the lower semiconductor chip 600 and the first semiconductor chip 400. The second semiconductor chip 200 may be disposed on the first surface 400S1 of the first semiconductor chip 400 and may be connected to the first surface 400S1 of the first semiconductor chip 400. In some example embodiments, a plurality of second semiconductor chips 200 may be disposed between the lower semiconductor chip 600 and the first semiconductor chip 400. A plurality of second semiconductor chips 200 may be disposed on the first surface 400S1 of the first semiconductor chip 400 and may be horizontally spaced apart from each other along a first direction D1 parallel to the first surface 400S1. Each of the plurality of second semiconductor chips 200 may be connected to the first surface 400S1 of the first semiconductor chip 400.

[0101] In some example embodiments, the through-electrodes 230 may be disposed in at least one of the plurality of second semiconductor chips 200, and the conductive pads 240 may be disposed on the fourth surface 200S4 of at least one of the plurality of second semiconductor chips 200. Each of the through-electrodes 230 may penetrate at least one of the plurality of second semiconductor chips 200, and may have a connection with a corresponding one of the second chip pads 210 and a corresponding one of the conductive pads 240. In some example embodiments, neither the through-electrodes 230 nor the conductive pads 240 may be disposed on another of the plurality of second semiconductor chips 200, but the inventive concept is not limited thereto.

[0102] A plurality of conductive pillars 300 may be disposed between the lower semiconductor chip 600 and the first semiconductor chip 400. Each of the conductive pillars 300 may be connected to the first surface 400S1 of the first semiconductor chip 400. For example, the conductive pillars 300 may be connected to corresponding ones of the first chip pads 410 of the first semiconductor chip 400.

[0103] The mold layer 350 may be disposed between the lower semiconductor chip 600 and the first semiconductor chip 400, and may cover the second semiconductor chip 200 and the conductive pillars 300. The mold layer 350 may extend onto the fourth surface 200S4 of at least one of the plurality of second semiconductor chips 200, thereby covering the conductive pad 240. The mold layer 350 may be spaced apart from the fifth surface 600S5 of the lower semiconductor chip 600.

[0104] A plurality of bumps 320 may be disposed between the lower semiconductor chip 600 and the conductive pillars 300 and between the lower semiconductor chip 600 and the conductive pads 240, and may be connected to the conductive pillars 300 and the conductive pads 240. The bumps 320 may be connected to the lower chip pad 610 of the lower semiconductor chip 600. The conductive pillars 300 and the conductive pads 240 may each be connected to the lower semiconductor chip 600 through a corresponding one of the bumps 320.

[0105] The first semiconductor chip 400 may be electrically connected to the lower semiconductor chip 600 through the conductive pillars 300. At least one of the through electrodes 230 may be used for electrical connection between the first semiconductor chip 400 and the lower semiconductor chip 600. In this case, the first semiconductor chip 400 may be electrically connected to the lower semiconductor chip 600 through a corresponding through electrode 230 among the through electrodes 230 in at least one of the plurality of second semiconductor chips 200. In addition, at least one of the lower through electrodes 650 may be used for electrical connection between the first semiconductor chip 400 and the substrate 100. In this case, the first semiconductor chip 400 may be electrically connected to the substrate 100 through a corresponding lower through electrode 650 among the lower through electrodes 650 in the lower semiconductor chip 600.

[0106] At least one of the plurality of second semiconductor chips 200 may be electrically connected to the lower semiconductor chip 600 through a corresponding through-electrode 230 of the through-electrodes 230. Another of the plurality of second semiconductor chips 200 may be connected to a corresponding conductive pillar 300 of the conductive pillars 300 through an internal wiring line in the first semiconductor chip 400, and may be electrically connected to the lower semiconductor chip 600 through the corresponding conductive pillar 300. One or more of the lower through-electrodes 650 may be used for electrical connection between the substrate 100 and the plurality of second semiconductor chips 200. In this case, the plurality of second semiconductor chips 200 may be electrically connected to the substrate 100 through a corresponding lower through-electrode 650 of the lower through-electrodes 650 of the lower semiconductor chips 600. The lower semiconductor chip 600 may be electrically connected to the substrate 100 through a corresponding lower through-electrode 650 of the lower through-electrodes 650.

[0107] Fig.21 A cross-sectional view of a semiconductor package 1300 according to some example embodiments of the inventive concept is shown. For the sake of brevity of description, the following will focus on the above reference Figure 1 and Figure 2 The differences of the semiconductor package 1000 are discussed.

[0108] Reference Fig.21, a lower semiconductor package PKG may be provided. The lower semiconductor package PKG may include a first substrate 700 and a semiconductor chip 800 located on the first substrate 700. The first substrate 700 may be a redistribution layer or a printed circuit substrate having a circuit pattern. The first substrate 700 may include a first substrate pad 710. The first substrate pad 710 may include a conductive material. The semiconductor chip 800 may include a chip pad 810 disposed on its bottom surface. The first substrate 700 and the semiconductor chip 800 may have a lower connector 820 located therebetween and correspondingly connected to the chip pad 810. The lower connector 820 may be connected to the corresponding first substrate pad 710 in the first substrate pad 710. The chip pad 810 and the lower connector 820 may include a conductive material. The lower connector 820 may have one or more shapes of a solder ball shape, a bump shape, and a column shape. The semiconductor chip 800 may include an integrated circuit (not shown), and the integrated circuit may be adjacent to the bottom surface of the semiconductor chip 800. The semiconductor chip 800 may be a logic chip or a memory chip.

[0109] The lower semiconductor package PKG may include a solder structure 850 on the first substrate 700. The solder structure 850 may be horizontally spaced apart from the semiconductor chip 800. The solder structure 850 may be connected to a corresponding first substrate pad 710 in the first substrate pads 710. The solder structure 850 may include a conductive material such as tin, lead, silver and / or an alloy thereof. Each of the solder structures 850 may be electrically connected to an external terminal or the semiconductor chip 800 through an internal wiring line in the first substrate 700.

[0110] The lower semiconductor package PKG may include a second substrate 900 disposed on the semiconductor chip 800. The second substrate 900 may be, for example, an intermediate substrate. The second substrate 900 may include a first pad 910 disposed on the bottom surface of the second substrate 900, and may also include a second pad 920 disposed on the top surface of the second substrate 900. The second substrate 900 may be provided with a wiring line therein that electrically connects the first pad 910 to the second pad 920. The first pad 910 and the second pad 920 may include a conductive material such as a metal (e.g., copper and / or aluminum). The solder structure 850 may be connected to the first pad 910. The second substrate 900 may be electrically connected to the first substrate 700 and the semiconductor chip 800 through the solder structure 850.

[0111] The lower semiconductor package PKG may include a lower molding layer 860 located between the first substrate 700 and the second substrate 900. The lower molding layer 860 may cover the semiconductor chip 800 and the solder structure 850. The lower molding layer 860 may extend between the first substrate 700 and the semiconductor chip 800, thereby encapsulating the lower connector 820. The lower molding layer 860 may include a dielectric material (e.g., an epoxy-based molding compound).

[0112] The first semiconductor chip 400 may be disposed on the second substrate 900 of the lower semiconductor package PKG. The first semiconductor chip 400 may be disposed so that the first surface 400S1 faces the second substrate 900. The second semiconductor chip 200 may be disposed between the second substrate 900 and the first semiconductor chip 400. In some example embodiments, a plurality of second semiconductor chips 200 may be disposed between the second substrate 900 and the first semiconductor chip 400.

[0113] In some example embodiments, the through-electrodes 230 may be disposed in at least one of the plurality of second semiconductor chips 200, and the conductive pads 240 may be disposed on the fourth surface 200S4 of at least one of the plurality of second semiconductor chips 200. Each of the through-electrodes 230 may penetrate at least one of the plurality of second semiconductor chips 200, and may have a connection with a corresponding one of the second chip pads 210 and a corresponding one of the conductive pads 240. In some example embodiments, neither the through-electrodes 230 nor the conductive pads 240 may be disposed on another of the plurality of second semiconductor chips 200, but the inventive concept is not limited thereto.

[0114] A plurality of conductive pillars 300 may be disposed between the second substrate 900 and the first semiconductor chip 400. Each of the conductive pillars 300 may be connected to the first surface 400S1 of the first semiconductor chip 400. For example, the conductive pillars 300 may be connected to a corresponding first chip pad 410 of the first semiconductor chip 400.

[0115] The mold layer 350 may be disposed between the second substrate 900 and the first semiconductor chip 400, and may cover the second semiconductor chip 200 and the conductive pillar 300. The mold layer 350 may extend onto the fourth surface 200S4 of at least one of the plurality of second semiconductor chips 200, thereby covering the conductive pad 240. The mold layer 350 may be spaced apart from the second substrate 900.

[0116] A plurality of bumps 320 may be disposed between the second substrate 900 and the conductive pillars 300 and between the second substrate 900 and the conductive pads 240, and may be connected to the conductive pillars 300 and the conductive pads 240. The bumps 320 may be connected to the second pads 920 of the second substrate 900. The conductive pillars 300 and the conductive pads 240 may each be connected to the second substrate 900 through a corresponding one of the bumps 320.

[0117] The first semiconductor chip 400 may be electrically connected to the lower semiconductor package PKG through the conductive pillars 300. At least one of the through electrodes 230 may be used for electrical connection between the first semiconductor chip 400 and the lower semiconductor package PKG. In this case, the first semiconductor chip 400 may be electrically connected to the lower semiconductor package PKG through a corresponding through electrode 230 of the through electrodes 230 in at least one of the plurality of second semiconductor chips 200.

[0118] At least one of the plurality of second semiconductor chips 200 may be electrically connected to the lower semiconductor package PKG through a corresponding through-electrode 230 of the through-electrodes 230. Another one of the plurality of second semiconductor chips 200 may be connected to a corresponding conductive pillar 300 of the conductive pillars 300 through an internal wiring line in the first semiconductor chip 400, and may be electrically connected to the lower semiconductor package PKG through the corresponding conductive pillar 300.

[0119] According to some example embodiments, the first semiconductor chip 400 having a relatively large width may be disposed in the upper region of the semiconductor package 1000 / 1100 / 1200 / 1300. Therefore, heat may be easily discharged outwardly from the first semiconductor chip 400. In addition, the semiconductor package 1000 / 1100 / 1200 / 1300 may include a conductive pillar 300 that electrically connects the first semiconductor chip 400 to a lower structure (e.g., a substrate 100, a redistribution layer 100R, a lower semiconductor chip 600, or a lower semiconductor package PKG). Because the first semiconductor chip 400 is electrically connected to the lower structure through the conductive pillar 300, the first semiconductor chip 400 may not require a through electrode therein. As a result, the semiconductor package may be able to easily stack a plurality of semiconductor chips with excellent reliability.

[0120] The above description provides some example embodiments for explaining the inventive concept. Therefore, the inventive concept is not limited to the embodiments described above, and it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and essential features of the inventive concept.

Claims

1. A semiconductor package, comprising: substrate; a first semiconductor chip; a plurality of second semiconductor chips located on the first surface of the first semiconductor chip and horizontally spaced apart from each other; as well as a plurality of conductive pillars located on the first surface of the first semiconductor chip and adjacent to at least one side of each of the plurality of second semiconductor chips, The first semiconductor chip includes a first circuit layer adjacent to a first surface of the first semiconductor chip, and wherein the plurality of second semiconductor chips and the plurality of conductive pillars are connected to the first surface of the first semiconductor chip, wherein one of the plurality of second semiconductor chips is spaced apart from the substrate and is electrically connected to the substrate through at least one of the plurality of conductive pillars, and there is no conductive pad between the one of the plurality of second semiconductor chips and the substrate, Another second semiconductor chip among the plurality of second semiconductor chips includes a through-electrode penetrating the another second semiconductor chip among the plurality of second semiconductor chips, and is electrically connected to the substrate through the through-electrode.

2. The semiconductor package according to claim 1, wherein: Each of the plurality of second semiconductor chips and the first semiconductor chip has a width along a first direction parallel to the first surface, The width of the first semiconductor chip is greater than the width of each of the plurality of second semiconductor chips.

3. The semiconductor package according to claim 1, wherein: A first surface of the first semiconductor chip faces a top surface of the substrate, and The plurality of second semiconductor chips and the plurality of conductive pillars are located between the first surface of the first semiconductor chip and the top surface of the substrate.

4. The semiconductor package according to claim 3, wherein: The plurality of conductive pillars are connected to a substrate.

5. The semiconductor package according to claim 4, wherein: Each of the plurality of second semiconductor chips has a height along a second direction perpendicular to the first surface, and Each of the plurality of conductive pillars has a height along the second direction, Wherein, the height of each of the plurality of conductive pillars is equal to or greater than the height of each of the plurality of second semiconductor chips.

6. The semiconductor package according to claim 4, wherein: The first semiconductor chip includes a plurality of first chip pads adjacent to the first surface, Each of the plurality of second semiconductor chips includes a plurality of second chip pads, The plurality of second chip pads are connected to corresponding first chip pads among the plurality of first chip pads, and The plurality of conductive pillars are connected to corresponding first chip pads among the plurality of first chip pads.

7. The semiconductor package according to claim 6, further comprising: a plurality of connectors located between the first semiconductor chip and each of the plurality of second semiconductor chips, Wherein, the plurality of second chip pads are connected to the corresponding first chip pads through the plurality of connectors.

8. The semiconductor package according to claim 6, wherein: The plurality of second chip pads are in direct contact with the corresponding first chip pads.

9. The semiconductor package according to claim 4, further comprising: A plurality of bumps are located between the substrate and the plurality of conductive pillars, Each of the plurality of conductive pillars is connected to the substrate through a corresponding one of the plurality of bumps.

10. The semiconductor package according to claim 4, further comprising: A plurality of bumps are located on the bottom surface of the substrate, wherein The substrate includes a plurality of redistribution patterns, and Each of the plurality of conductive pillars is connected to a corresponding one of the plurality of redistribution patterns.

11. The semiconductor package according to claim 10, wherein: Each of the first semiconductor chip and the substrate has a width along a first direction parallel to the first surface, The width of the substrate is greater than the width of the first semiconductor chip.

12. A semiconductor package, comprising: substrate; a first semiconductor chip; a plurality of second semiconductor chips located on the first surface of the first semiconductor chip and horizontally spaced apart from each other; as well as a plurality of conductive pillars located on the first surface of the first semiconductor chip and between the plurality of second semiconductor chips; wherein the plurality of second semiconductor chips and the plurality of conductive pillars are connected to the first surface of the first semiconductor chip, wherein one of the plurality of second semiconductor chips is spaced apart from the substrate and is electrically connected to the substrate through at least one of the plurality of conductive pillars, and there is no conductive pad between the one of the plurality of second semiconductor chips and the substrate, Another second semiconductor chip among the plurality of second semiconductor chips includes a through-electrode penetrating the another second semiconductor chip among the plurality of second semiconductor chips, and is electrically connected to the substrate through the through-electrode.

13. The semiconductor package according to claim 12, wherein: The first semiconductor chip includes a first circuit layer adjacent to the first surface, and the first circuit layer includes an integrated circuit.

14. The semiconductor package according to claim 12, wherein: The first semiconductor chip has a width along a first direction parallel to the first surface, and Each of the plurality of second semiconductor chips has a width along the first direction, The width of the first semiconductor chip is greater than the sum of the widths of the plurality of second semiconductor chips.

15. The semiconductor package according to claim 14, wherein: Each of the plurality of second semiconductor chips has a height along a second direction perpendicular to the first surface, and Each of the plurality of conductive pillars has a height along the second direction, Wherein, the height of each of the plurality of conductive pillars is equal to or greater than the height of each of the plurality of second semiconductor chips.

16. The semiconductor package according to claim 12, wherein: The plurality of second semiconductor chips and the plurality of conductive pillars are located between the first semiconductor chip and the substrate.

17. The semiconductor package according to claim 16, wherein: The plurality of conductive pillars are connected to a substrate.

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