Electronic panel and electronic device including the same

Abstract

An electronic panel and an electronic device including the same are provided. The electronic panel includes a base substrate including a first area and a second area, wherein the first area includes a module area and a display area adjacent to the module area, a display element layer including a plurality of display elements, wherein the plurality of display elements overlap the first area, an encapsulation layer configured to cover the display elements, a plurality of sensing patterns overlapping the first area and arranged on the encapsulation layer, a crack sensing pattern overlapping the module area and arranged on the encapsulation layer, an auxiliary pattern overlapping the module area and arranged on the encapsulation layer, wherein the auxiliary pattern has a shape extending along an edge of the crack sensing pattern and extending between the plurality of sensing patterns and the crack sensing pattern, and a signal line arranged on the encapsulation layer to electrically connect the crack sensing pattern to the auxiliary pattern.

Description

Technical Field

[0001] The present invention relates to electronic devices, and more specifically, to electronic panels having through holes and configured to sense external inputs, and electronic devices including such electronic panels. Background Technology

[0002] Typically, electronic devices are activated by electrical signals. Such electronic devices include various electronic components, such as electronic panels and electronic modules. For example, an electronic panel may include a display unit and a sensing unit that senses external input (e.g., a touch input by a user). Furthermore, the display unit may display images. Electronic components can be electrically connected to each other via signal lines arranged in various ways.

[0003] For example, the display unit includes a light-emitting element that generates an image. The sensing unit may include sensing electrodes for sensing external input. The sensing electrodes are arranged in the effective area. The sensing unit is designed to provide substantially uniform sensitivity across the entire surface of the effective area. Summary of the Invention

[0004] According to an exemplary embodiment of the present invention, an electronic panel includes a base substrate, a display element layer, an encapsulation layer, a plurality of sensing patterns, a crack sensing pattern, an auxiliary pattern, and signal lines. The base substrate includes a first region and a second region adjacent to the first region. The first region includes a module region and a display region adjacent to the module region. The display element layer includes a plurality of display elements, which overlap with the first region and are disposed on the base substrate. The encapsulation layer is configured to cover the display elements and is disposed on the base substrate. The plurality of sensing patterns overlap with the first region and are disposed on the encapsulation layer. The crack sensing pattern overlaps with the module region and is disposed on the encapsulation layer. The auxiliary pattern overlaps with the module region and is disposed on the encapsulation layer. The auxiliary pattern has a shape extending along the edge of the crack sensing pattern and extending between the plurality of sensing patterns. Signal lines are disposed on the encapsulation layer to electrically connect the crack sensing pattern to the auxiliary pattern.

[0005] In an exemplary embodiment of the present invention, the signal line includes a first detection line portion, a second detection line portion, and a third detection line portion, wherein the first detection line portion includes a first main line and a first connecting line configured to connect the first main line to a first end of a crack sensing pattern, wherein the first main line overlaps with a second region; the second detection line portion includes a second main line and a second connecting line configured to connect the second main line to a first end of an auxiliary pattern, wherein the second main line is connected to a second end of the crack sensing pattern; and the third detection line portion includes a third main line connected to a second end of the auxiliary pattern.

[0006] In an exemplary embodiment of the concept of the present invention, the first main line, the second main line, and the third main line are spaced apart from each other in a plan view.

[0007] In an exemplary embodiment of the concept of the present invention, the crack sensing pattern has a curved shape.

[0008] In an exemplary embodiment of the present invention, the electronic panel further includes a first pad portion and a second pad portion, wherein the first pad portion includes a first output pad and a first input pad connected to a first end of a second main line, wherein the first output pad is connected to the first end of the first main line, and the second pad portion includes a second output pad and a second input pad connected to a first end of a third main line, wherein the second output pad is connected to a second end of the first main line.

[0009] In an exemplary embodiment of the present invention, a first detection signal input to a first input pad is transmitted to a second end of a crack sensing pattern via a second main line, and the first detection signal is transmitted from the second end of the crack sensing pattern to the first end of the crack sensing pattern, wherein the first detection signal is transmitted from the first end of the crack sensing pattern to a first output pad and a second output pad via a first connecting line and a first main line.

[0010] In an exemplary embodiment of the present invention, a second detection signal input to a second input pad is transmitted to a second end of an auxiliary pattern via a third main line, and the second detection signal is transmitted from the second end of the auxiliary pattern to a first end of the auxiliary pattern, wherein the second detection signal is transmitted from the first end of the auxiliary pattern to the second end of a crack sensing pattern via a second connecting line and a second main line, and wherein the second detection signal is transmitted from the second end of the crack sensing pattern to a first output pad and a second output pad via a first connecting line and a first main line.

[0011] In an exemplary embodiment of the concept of the present invention, the second end of the second main line is connected to the second end of the crack sensing pattern, and the second end of the third main line is connected to the second end of the auxiliary pattern.

[0012] In an exemplary embodiment of the concept of the present invention, a first region surrounds a module region, and each of the plurality of sensing patterns and auxiliary patterns is configured as a grid pattern.

[0013] In an exemplary embodiment of the concept of the present invention, each of the second main line and the third main line includes a first portion overlapping the second region and a second portion overlapping the first region.

[0014] In an exemplary embodiment of the present invention, the signal line further includes a plurality of sensing signal lines spaced apart from the first detection line portion, the second detection line portion, and the third detection line portion and respectively connected to the plurality of sensing patterns.

[0015] In an exemplary embodiment of the present invention, each of the plurality of sensing patterns, crack sensing patterns, auxiliary patterns, and signal lines is directly arranged on the encapsulation layer.

[0016] In an exemplary embodiment of the present invention, the electronic panel further includes a hole configured to pass through the electronic panel in the module region, wherein a crack sensing pattern extends along the edge of the hole.

[0017] In an exemplary embodiment of the present invention, the first distance between the crack sensing pattern and the center of the hole is smaller than the second distance between the auxiliary pattern and the center of the hole.

[0018] In an exemplary embodiment of the present invention, the crack sensing pattern includes a first extension, a second extension, and a connecting portion, wherein the first extension extends along the edge of a hole, the second extension is arranged further from the center of the hole than the first extension and spaced apart from the first extension to extend along the edge of the first extension, and the connecting portion is configured to connect the first extension to the second extension.

[0019] In an exemplary embodiment of the concept of the present invention, the first region is a region for displaying images, and the module region and the second region are non-display regions where images are not displayed.

[0020] According to an exemplary embodiment of the present invention, an electronic device includes an electronic panel configured to display an image and sense external input, and an electronic module arranged to overlap with the electronic panel. The electronic panel includes a base substrate, a plurality of sensing patterns, a crack sensing pattern, an auxiliary pattern, and signal lines. The base substrate includes a module region, an effective region, and a peripheral region adjacent to the effective region. The module region includes a hole configured to pass through the electronic panel. The effective region surrounds the module region. The plurality of sensing patterns overlap with the effective region and are arranged on the base substrate. The crack sensing pattern overlaps with the module region and is arranged on the base substrate, wherein the crack sensing pattern has a curved shape extending along the edge of the hole. The auxiliary pattern overlaps with the module region and is arranged on the base substrate, wherein the auxiliary pattern extends along the edge of the crack sensing pattern and extends between the plurality of sensing patterns. The signal lines are configured to electrically connect the crack sensing pattern to the auxiliary pattern.

[0021] In an exemplary embodiment of the concept of the present invention, a plurality of sensing patterns, crack sensing patterns, auxiliary patterns and signal lines are arranged in the same layer as each other.

[0022] In an exemplary embodiment of the present invention, multiple sensing patterns, crack sensing patterns, auxiliary patterns, and signal lines are arranged on a base substrate using a one-off process with the same materials.

[0023] In an exemplary embodiment of the present invention, the electronic device further includes a first detection line portion, a second detection line portion, and a third detection line portion, wherein the first detection line portion includes a first main line and a first connecting line configured to connect the first main line to a first end of a crack sensing pattern, wherein the first main line overlaps with a peripheral region; the second detection line portion includes a second main line and a second connecting line configured to connect the second main line to a first end of an auxiliary pattern, wherein the second main line is connected to a second end of the crack sensing pattern; and the third detection line portion includes a third main line connected to a second end of the auxiliary pattern. Attached Figure Description

[0024] The above and other features of the present invention will become more apparent from the detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings, in which:

[0025] Figure 1A This is a perspective view illustrating an electronic device according to an exemplary embodiment of the concept of the present invention;

[0026] Figure 1B This is an exploded perspective view illustrating an electronic device according to an exemplary embodiment of the concept of the present invention;

[0027] Figure 2 yes Figure 1A A block diagram of an electronic device;

[0028] Figure 3 This is a cross-sectional view of an electronic panel according to an exemplary embodiment of the concept of the present invention;

[0029] Figure 4A This is a plan view illustrating an exemplary embodiment of a display panel according to a concept of the present invention;

[0030] Figure 4B yes Figure 1B A magnified view of region XX';

[0031] Figure 5 This is a cross-sectional view of an input sensing layer according to an exemplary embodiment of the concept of the present invention;

[0032] Figure 6 This is a plan view of an input sensing layer according to an exemplary embodiment of the concept of the present invention;

[0033] Figure 7A This is an exemplary embodiment of the concept according to the present invention. Figure 6 A cross-sectional view taken by line I-I';

[0034] Figure 7B This is a cross-sectional view showing a portion of an area of ​​an electronic panel according to an exemplary embodiment of the concept of the present invention;

[0035] Figure 8 This is a plan view of a crack sensing circuit according to an exemplary embodiment of the concept of the present invention;

[0036] Figure 9 It is along Figure 8 The cross-sectional view taken by line II-II'; and

[0037] Figure 10A , Figure 10B and Figure 10C This is a plan view of a crack sensing circuit according to an exemplary embodiment of the concept of the present invention. Detailed Implementation

[0038] In this specification, it will be understood that when a component (or area, layer, part) is referred to as being "on", "connected to" or "attached to" another component, the component (or area, layer, part) may be directly disposed on / connected to / attached to the other component, or there may be an intervening third component.

[0039] It will be understood that similar reference numerals indicate similar elements throughout the specification. Additionally, for clarity, the thickness, scale, and dimensions of layers, areas, and components may be exaggerated in the drawings.

[0040] The term “and / or” includes any and all combinations of one or more of the relevant listed items.

[0041] It will be understood that although terms such as “first” and “second” may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one component from another. For example, an element referred to as a first element in one embodiment may be referred to as a second element in another embodiment without departing from the spirit or scope of the invention. Unless otherwise indicated, singular terms may include plural forms.

[0042] Additionally, spatial relative terms such as “below,” “under,” “down,” “above,” “up,” and similar words may be used herein for the convenience of description to describe the relationship between one element or feature and another element or feature as shown in the figures. It will be understood that, in addition to the orientations depicted in the figures, spatial relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented above other elements or features. Thus, in instances, the terms “below” and “under” may encompass all orientations above, below, and under. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0043] In the following description, exemplary embodiments of the concept of the present invention will be described with reference to the accompanying drawings.

[0044] Figure 1A This is a perspective view illustrating an electronic device EA according to an exemplary embodiment of the concept of the present invention. Figure 1B This is an exploded perspective view illustrating an electronic device EA according to an exemplary embodiment of the concept of the present invention. Figure 2 yes Figure 1A A block diagram of the electronic device EA.

[0045] An electronic device EA can be a device that is activated and / or operated based on an electrical signal. An electronic device EA can include a variety of devices. For example, an electronic device EA can include a tablet computer, a laptop computer, a computer, a smart TV, and the like. In this embodiment, the electronic device EA will be described as a smartphone; however, the concept of the invention is not limited thereto.

[0046] Reference Figure 1A The electronic device EA can display an image IM on its front surface FS. The front surface FS may include a transmissive region TA and a border region BZA adjacent to the transmissive region TA.

[0047] The front surface FS may be parallel to the plane formed by the first direction DR1 and the second direction DR2 intersecting the first direction DR1. The normal direction of the front surface FS (e.g., the thickness direction of the electronic device EA) is indicated by the third direction DR3. In this specification, "when viewed in a plan view" may mean the case when viewed on the third direction DR3. The front surface (or, for example, the top surface) and rear surface (or, for example, the bottom surface) of each of the multiple layers or multiple units described below are distinguished by the third direction DR3. However, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 may be changed to different directions, for example, opposite directions.

[0048] Electronic device EA displays image IM through transmission area TA. Image IM may include at least one of still image and moving image. Figure 1A In the example, an image IM includes time and multiple icons.

[0049] The transmission region TA may have a rectangular shape parallel to the first direction DR1 and the second direction DR2. However, this is merely an example. For instance, the transmission region TA may have various shapes and is not limited to a particular shape.

[0050] The border region BZA may surround the transmission region TA. However, this is merely an example. For instance, the border region BZA may be arranged to be adjacent only to one side of the transmission region TA, or it may be omitted. However, the concept of the invention is not limited thereto.

[0051] An electronic device EA according to an exemplary embodiment of the present invention can sense user input TC applied from outside the electronic device EA. User input TC includes various types of external input, such as a part of the user's body, light, heat, pressure, or the like. Furthermore, the electronic device EA can sense not only inputs in contact with the electronic device EA, but also inputs that are nearby or adjacent to the electronic device EA but not in contact with it. In addition, the electronic device EA can sense moving inputs.

[0052] In this embodiment, the user input TC is shown as the user's hand applied to the front surface FS. However, this is merely an example. For example, as described above, various types of user input TC can be provided. The electronic device EA can sense the user input TC applied to the side or rear surface of the electronic device EA depending on the structure of the electronic device EA, but the concept of the invention is not limited thereto.

[0053] Reference Figure 1B The electronic device EA may include a window 100, an electronic panel 200, a circuit board 300, an electronic module 400, and a housing 500. The window 100 and the housing 500 may be connected to each other to provide the appearance of the electronic device EA. For example, when the window 100 and the housing 500 are connected to each other, they may house the electronic panel 200, the circuit board 300, and the electronic module 400.

[0054] Window 100 may be disposed on electronic panel 200 to cover the front surface IS of electronic panel 200. Window 100 may include, for example, an optically transparent insulating material. For example, window 100 may include glass or plastic. Window 100 may have a single-layer or multi-layer structure. For example, window 100 may have a laminated structure of multiple plastic films bonded together by using an adhesive, or a laminated structure of a glass substrate and plastic films bonded together by using an adhesive.

[0055] Window 100 includes a front surface FS exposed to the outside. The front surface FS of electronic device EA may correspond to the front surface FS of window 100.

[0056] For example, the transmissive region TA can be an optically transparent region. The transmissive region TA can have a shape corresponding to the shape of the effective region AA. For example, the transmissive region TA overlaps with at least a portion of the effective region AA. The image IM displayed in the effective region AA of the electronic panel 200 is visible from the outside through the transmissive region TA.

[0057] The border region BZA may be a region with a lower transmittance than the transmission region TA. The border region BZA forms the shape of the transmission region TA. The border region BZA may be arranged adjacent to the transmission region TA to at least partially surround the transmission region TA.

[0058] The border area BZA may have a predetermined color. When the window 100 includes a glass or plastic substrate, the border area BZA may be a color layer printed or deposited on at least one surface of the glass or plastic substrate. Alternatively, the border area BZA may be formed by coloring a corresponding area of ​​the glass or plastic substrate.

[0059] The border area BZA may cover the peripheral area NAA of the electronic panel 200 to prevent the peripheral area NAA from being visible from the outside. However, this is merely an example. For instance, in a window 100 of an exemplary embodiment according to the concept of the present invention, the border area BZA may be omitted.

[0060] The electronic panel 200 may include a display panel DP and an input sensing layer ISU, which will be referred to later. Figure 3 The display panel DP generates an image IM. The image IM generated by the display panel DP is visible to the user from the outside through the transmission area TA. The input sensing layer ISU senses external input TC applied from the outside. As described above, the input sensing layer ISU senses the external input TC provided to window 100.

[0061] According to an exemplary embodiment of the present invention, the front surface IS of the electronic panel 200 includes a first region and a second region adjacent to the first region. The first region may correspond to an effective region AA that at least partially surrounds the module region MA, and the second region may correspond to a peripheral region NAA. The effective region AA may be a region activated according to an electrical signal. The module region MA and the second region may be non-display regions that do not display images.

[0062] The effective area AA can be the area for displaying the image IM and also the area for sensing external input TC. The transmission area TA overlaps at least with the effective area AA. For example, the transmission area TA overlaps the entire surface of at least a portion of the effective area AA. Therefore, the user can observe the image IM or provide external input TC through the transmission area TA. However, this is merely an example. For example, the area of ​​the effective area AA for displaying the image IM can be separated from the area of ​​the effective area AA for sensing external input TC, but the concept of the invention is not limited thereto.

[0063] The peripheral region NAA can be the area covered by the border region BZA. The peripheral region NAA is adjacent to the active region AA. The peripheral region NAA may at least partially surround the active region AA. The drive circuitry or drive lines used to drive the active region AA may be arranged in the peripheral region NAA.

[0064] The peripheral area NAA can contain various signal lines that provide electrical signals to the active area AA, pads PD, or electronic components. The peripheral area NAA can be covered by the border area BZA and is therefore not visible from the outside.

[0065] In this embodiment, the electronic panel 200 can be assembled with the effective area AA and the peripheral area NAA substantially flat, facing the window 100. However, this is merely an example. For instance, a portion of the peripheral area NAA of the electronic panel 200 can be bent. Here, a portion of the peripheral area NAA can be arranged to face the rear surface of the electronic device EA to reduce the area of ​​the border area BZA on the front surface FS of the electronic device EA. For example, the bent peripheral area NAA can face the housing 500. Additionally, the electronic panel 200 can be assembled with a portion of the effective area AA bent. As an additional example, in the exemplary embodiment of the electronic panel 200 according to the concept of the present invention, the peripheral area NAA can be omitted.

[0066] Compared to the portion of the effective region AA that has the same surface area as the module region MA, the module region MA can have a relatively high transmittance. In the plan view, the module region MA is located at the position overlapping with the electronic module 400 described later.

[0067] At least a portion of the module region MA may be surrounded by an effective region AA. In this embodiment, the module region MA is spaced apart from the peripheral region NAA. For example, the module region MA is shown as being located within the effective region AA such that all edges are surrounded by the effective region AA.

[0068] The electronic panel 200 may include a panel aperture MH located in the module region MA and passing through the electronic panel 200. The panel aperture MH may pass through at least one of the display panel DP and the input sensing layer ISU. The edge of the module region MA may be substantially spaced apart from the edge of the panel aperture MH by a predetermined distance to extend along the edge of the panel aperture MH. The edge of the module region MA may have a shape corresponding to the panel aperture MH.

[0069] Circuit board 300 can be connected to electronic panel 200. Circuit board 300 may include flexible board CF and main board MB. Flexible board CF may include insulating film and wires mounted on the insulating film. Wires are connected to pads PD to electrically connect circuit board 300 to electronic panel 200.

[0070] In this embodiment, the flexible board CF can be assembled in a bent state so that the main board MB can be arranged on the rear surface of the electronic panel 200. Therefore, the main board MB can be arranged on the rear surface of the electronic panel 200 to be accommodated in the space provided by the housing 500. In this embodiment, the flexible board CF can be omitted. For example, the main board MB can be directly connected to the electronic panel 200.

[0071] The motherboard MB may include signal lines and electronic components. The electronic components may be connected to the signal lines for electrical connection to the electronic panel 200. The electronic components may generate various electrical signals, such as signals for generating an image IM or signals for sensing an external input TC. Additionally, the electronic components may include, for example, a processor for processing the sensed signals. For example, multiple motherboard MBs may exist for generating electrical signals, but the concept of the invention is not limited thereto.

[0072] In an electronic device EA according to an exemplary embodiment of the present invention, a driving circuit that provides electrical signals to an effective area AA can be mounted on an electronic panel 200. For example, the driving circuit can be directly mounted on the electronic panel 200. Here, the driving circuit can be mounted as a chip or formed together with the pixel PX to be described. Here, the surface area of ​​the circuit board 300 can be reduced or omitted. The electronic device EA according to an exemplary embodiment of the present invention can be implemented according to various embodiments and is not limited to a particular embodiment.

[0073] Electronic module 400 is positioned below window 100. Electronic module 400 may overlap with panel hole MH located in module area MA. Electronic module 400 may receive external input transmitted through module area MA, or may provide output through module area MA.

[0074] In electronic module 400, a receiver that receives external input and an output circuit that provides an output (e.g., a signal) may overlap with module region MA in a plan view. Part or all of electronic module 400 may be housed in module region MA or panel aperture MH. In an exemplary embodiment of the present invention, electronic module 400 may be arranged to overlap with effective region AA, thereby reducing the surface area of ​​border region BZA.

[0075] Reference Figure 2 The electronic device EA may include an electronic panel 200, a power module PM, a first electronic module EM1, and a second electronic module EM2. The electronic panel 200, the power module PM, the first electronic module EM1, and the second electronic module EM2 may be electrically connected to each other. Figure 2 Examples of the display panel DP and the input sensing layer ISU, which are components of the electronic panel 200, are shown.

[0076] The first electronic module EM1 and the second electronic module EM2 may include various functional modules for driving the electronic device EA. For example, the first electronic module EM1 may be directly mounted on a motherboard electrically connected to the electronic panel 200, or the first electronic module EM1 may be mounted on a separate board and electrically connected to the motherboard via connectors. For example, the first electronic module EM1 may be mounted on the motherboard MB; however, the concept of the invention is not limited thereto.

[0077] The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, an audio input module AIM, a memory MM, and an external interface IF. Some of these modules may not be mounted on the motherboard, but rather electrically connected to it via a flexible circuit board.

[0078] The control module CM controls the overall operation of the electronic device EA. For example, the control module CM may be a microprocessor. For example, the control module CM may activate or deactivate the electronic panel 200. The control module CM may control other modules, such as the image input module IIM and / or the audio input module AIM, based on touch signals received from the electronic panel 200.

[0079] The wireless communication module™ can transmit wireless signals to / receive wireless signals from other terminals via Bluetooth or Wi-Fi. It can also transmit / receive audio signals using a standard communication cable. The wireless communication module™ includes a transmitter TM1 and a receiver TM2. The transmitter TM1 modulates and transmits the signal to be transmitted, while the receiver TM2 demodulates the received signal.

[0080] The image input module IIM processes the image signal to convert it into image data that can be displayed on the electronic panel 200. The audio input module AIM receives external audio signals using a microphone during recording or voice recognition mode, converting the received audio signals into electronic sound data.

[0081] The external interface (IF) serves as an interface for connecting to external chargers, wired / wireless data ports, and card slots (e.g., memory cards and SIM / UIM cards).

[0082] The second electronic module EM2 may include an audio output module AOM, a light-emitting module LM, a light-receiving module LRM, and a camera module CMM. For example, these components can be directly mounted on a motherboard. As an additional example, the components can be mounted on a separate board and electrically connected to the electronic panel 200 via connectors. As yet another example, the components can be electrically connected to the first electronic module EM1.

[0083] The audio output module AOM converts audio data received from the wireless communication module TM or stored in the memory MM to output the converted audio data to the outside.

[0084] A light-emitting module (LM) generates and outputs light. The LM can output infrared light. For example, the LM may include LED elements. A light-receiving module (LRM) can sense infrared light. The LRM can be activated when infrared light of a predetermined level or higher is sensed. The LRM may include a CMOS sensor. The infrared light generated in the LM can be output and then reflected by an external object (e.g., a user's finger or face), and the reflected infrared light can be incident on the LRM. A camera module (CMM) captures external images.

[0085] An electronic module 400 according to an exemplary embodiment of the present invention may include at least one component of a first electronic module EM1 and a second electronic module EM2. For example, the electronic module 400 may include at least one of a camera, a speaker, an optical detection sensor, and a thermal detection sensor. The electronic module 400 may sense external objects received through the module region MA, or provide sound signals, such as speech, to the outside through the module region MA. Furthermore, the electronic module 400 may include multiple components, but the present invention is not limited thereto.

[0086] In an electronic module 400 arranged to overlap with a module region MA, external objects are visible through the module region MA, or output signals generated by the electronic module 400 can be transmitted to the outside. An electronic device EA according to an exemplary embodiment of the present invention may further include a transparent member disposed between the electronic module 400 and the electronic panel 200. The transparent member may be an optically transparent film, allowing external input transmitted through a panel aperture MH to pass through the transparent member and be transmitted to the electronic module 400. The transparent member may be attached to the rear surface of the electronic panel 200, or may be disposed between the electronic panel 200 and the electronic module 400 without an adhesive layer. An electronic device EA according to an exemplary embodiment of the present invention may have various shapes, but the present invention is not limited thereto.

[0087] According to the concept of the present invention, in a plan view, the electronic module 400 can be assembled such that the plan view overlaps with the transmission region TA. Therefore, it is possible to prevent an increase in the area of ​​the border region BZA due to accommodating the electronic module 400.

[0088] Figure 3 This is a cross-sectional view of an electronic panel 200 according to an exemplary embodiment of the concept of the present invention.

[0089] Reference Figure 3 The display panel DP includes a base substrate BS, a circuit element layer DP-CL, a display element layer DP-OLED, and a packaging layer TFL. The circuit element layer DP-CL is disposed on the base substrate BS.

[0090] In an exemplary embodiment of the present invention, the display panel DP may be an emissive display panel, but the present invention is not limited thereto. For example, the display panel DP may be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include organic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel may include quantum dots, quantum rods, and the like. Hereinafter, an organic light-emitting display panel will be described as an example of a display panel DP.

[0091] The display panel DP includes the display area DP-DA and the non-display area DP-NDA. The display area DP-DA of the display panel DP can correspond to... Figure 1B The effective area AA, and the non-display area DP-NDA can correspond to Figure 1B The outer region NAA.

[0092] The base substrate BS may include at least one plastic film. The base substrate BS may be a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite substrate as a flexible plate.

[0093] The circuit element layer DP-CL includes at least one intermediate insulating layer and circuit elements. For example, the intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film. The circuit elements include signal lines, pixel driving circuits, and the like.

[0094] The display element layer of a DP-OLED may include multiple display elements. For example, the display elements may be organic light-emitting elements. The display element layer of a DP-OLED may also include an organic layer, such as a pixel defining layer.

[0095] The encapsulation layer TFL seals the DP-OLED display element layer. For example, the encapsulation layer TFL can be a thin-film encapsulation layer. The encapsulation layer TFL protects the DP-OLED display element layer from foreign matter such as moisture, oxygen, and dust particles.

[0096] An input sensing layer (ISU) may be disposed between window 100 and display panel DP. The input sensing layer (ISU) senses input applied from the outside. Input applied from the outside can be provided in various ways. For example, external input may include various types of external input, such as a part of the user's body, a stylus, light, heat, pressure, or the like. In addition, input may be a physical touch (e.g., making contact) made by a part of the human body (e.g., the user's hand), or it may be a spatial touch (e.g., hovering) in an adjacent or nearby location.

[0097] The input sensing layer (ISU) can be disposed on the display panel (DP). For example, the input sensing layer (ISU) can be disposed directly on the display panel (DP). In this specification, "component A is disposed directly on component B" can mean that no adhesive member is disposed between component A and component B. In this embodiment, the input sensing layer (ISU) can be manufactured together with the display panel (DP) through a continuous process.

[0098] Figure 4A This is a plan view of a display panel DP illustrating an exemplary embodiment of the concept according to the present invention. Figure 4B yes Figure 1B A magnified view of region XX'.

[0099] The display panel DP includes a base substrate BS, multiple pixel PXs, multiple signal lines GL, DL and PL, and multiple display pads DPDs.

[0100] Reference Figure 4A The display panel DP includes a base substrate BS, multiple pixels PX, multiple signal lines GL, DL and PL, and multiple display pads DPD. The active area AA and the peripheral area NAA may be areas provided by the base substrate BS. The base substrate BS may include an insulating substrate. For example, the base substrate BS may be made of glass, plastic, or a combination thereof.

[0101] Multiple signal lines GL, DL, and PL are connected to pixel PX to transmit electrical signals to pixel PX. A scan line GL, a data line DL, and a power line PL, arranged in a display panel DP, are shown as an example. However, the multiple signal lines may also include at least one of a power line, an initialization voltage line, and an emission control line, but the concept of the invention is not limited thereto.

[0102] Pixel PX can be arranged in the display area DP-DA. In this embodiment, an amplification signal circuit diagram of one pixel PX among a plurality of pixels is shown as an example. Pixel PX may include a first thin-film transistor TR1, a capacitor CP, a second thin-film transistor TR2, and a light-emitting element EE. The first thin-film transistor TR1 may be a switching element that turns pixel PX on and off. The first thin-film transistor TR1 may transmit or block data signals transmitted via data lines DL in response to a scan signal transmitted to the gate terminal of the first thin-film transistor TR1 via scan line GL.

[0103] A capacitor CP is connected to a first thin-film transistor TR1 and a power supply line PL. The capacitor CP is charged with a charge, the amount of which corresponds to the difference between the data signal received from the first thin-film transistor TR1 and the first power supply signal applied to the first power supply line PL.

[0104] A second thin-film transistor TR2 is connected to a first thin-film transistor TR1, a capacitor CP, and a light-emitting element EE. The second thin-film transistor TR2 controls the drive current flowing to the light-emitting element EE based on the amount of charge stored in the capacitor CP. The on-time of the second thin-film transistor TR2 is determined according to the amount of charge charged in the capacitor CP. During the on-time, the second thin-film transistor TR2 provides a first power signal transmitted through the power line PL to the light-emitting element EE.

[0105] A light-emitting element (EE) can generate light or control the amount of light based on an electrical signal. For example, an EE may include an organic light-emitting element, a quantum dot light-emitting element, an electrophoretic element, or an electrowetting element.

[0106] The light-emitting element EE can be connected to the power terminal VSS to receive a power signal different from the first power signal provided by the power line PL (hereinafter referred to as the second power signal). A drive current corresponding to the difference between the electrical signal provided from the second thin-film transistor TR2 and the second power signal can flow through the light-emitting element EE, and the light-emitting element EE can generate light corresponding to the drive current. However, this is merely an example, and the concept of the invention is not limited thereto. For example, the pixel PX may include electronic components having various constructions and layouts.

[0107] Pixels PX can be arranged around the panel aperture MH to at least partially surround the panel aperture MH in a plan view. Figure 4B In the text, for ease of description, the module area MA is shown with a dashed line. Area XX' includes the area where the panel hole MH is located. Referring to the following text... Figure 4B The panel hole MH located in the display panel DP is described.

[0108] As described above, a panel aperture MH can be formed in the display area DP-DA. Therefore, at least a portion of the plurality of pixels PX can be arranged adjacent to the panel aperture MH. A portion of the plurality of pixels PX can at least partially surround the panel aperture MH.

[0109] A predetermined recessed pattern GV may be formed in the module region MA. The recessed pattern GV is arranged along the edge of the panel hole MH in a plan view, and in this embodiment, the recessed pattern GV has an annular shape surrounding the panel hole MH. However, this is merely an example. For example, the recessed pattern GV may have a different shape than the panel hole MH. For example, the recessed pattern GV may have a polygonal shape, an elliptical shape, a shape that is at least partially circular, or a shape comprising multiple partially cut patterns. However, the concept of the invention is not limited thereto.

[0110] The recessed pattern GV corresponds to the recessed portion from the front surface of the display panel DP and blocks the path of moisture or oxygen being introduced into the pixel PX through the panel aperture MH. This will be described in detail later.

[0111] Multiple signal lines SL1 and SL2 connected to pixel PX can be arranged in the module region MA. The multiple signal lines SL1 and SL2 can be connected to pixel PX via the module region MA. For ease of description, in... Figure 4B An example of the first signal line SL1 and the second signal line SL2 among the multiple signal lines connected to pixel PX is shown.

[0112] The first signal line SL1 extends along the first direction DR1. The first signal line SL1 is connected to a plurality of pixels PX arranged in the same row along the first direction DR1. The structure of the first signal line SL1 corresponding to the scan line GL is described as an example.

[0113] A portion of the plurality of pixels PX connected to the first signal line SL1 may be arranged on the left side of the panel hole MH, and the remaining portions of the plurality of pixels PX may be arranged on the right side of the panel hole MH. Therefore, even if a portion of the plurality of pixels PX relative to the panel hole MH is omitted, the pixels PX in the same row connected to the first signal line SL1 can be turned on / off by substantially the same gate signal.

[0114] The second signal line SL2 extends along the second direction DR2. The second signal line SL2 is connected to a column of pixels PX of the display panel DP arranged along the second direction DR2. As an example, the structure of the second signal line SL2 corresponding to the data line DL will be described.

[0115] In a plan view, a portion of the plurality of pixels PX connected to the second signal line SL2 may be arranged above the panel aperture MH, and another portion of the plurality of pixels PX may be arranged below the panel aperture MH. Therefore, even if a portion of the plurality of pixels PX relative to the panel aperture MH is omitted, the plurality of pixels PX in the same row connected to the second signal line SL2 can still receive data signals through the same line.

[0116] Refer again Figure 4A The power supply pattern VDD is arranged in the non-display area DP-NDA. For example, the non-display area DP-NDA may correspond to the peripheral area NAA (see, for example, see...). Figure 1B In this embodiment, the power pattern VDD is connected to multiple power lines PL. Therefore, since the display panel DP includes the power pattern VDD, the same first power signal can be provided to multiple pixels PX.

[0117] The display pad DPD may include a first pad P1 and a second pad P2. Multiple first pads P1 may be configured, and each first pad P1 may be connected to a multiple data lines DL. The second pad P2 may be connected to the power pattern VDD and electrically connected to the power line PL. The display panel DP can provide electrical signals from an external source (e.g., a controller) to multiple pixels PX via the display pad DPD. In addition to the first pads P1 and the second pads P2, the display pad DPD may also include pads for receiving other electrical signals, but the concept of the invention is not limited thereto.

[0118] Figure 5 This is a cross-sectional view of an input sensing layer (ISU) according to an exemplary embodiment of the concept of the present invention. Figure 6 This is a plan view of an input sensing layer (ISU) according to an exemplary embodiment of the concept of the present invention. Figure 7A This is an exemplary embodiment of the concept according to the present invention. Figure 6 The cross-sectional view taken by line I-I'. Figure 7B This is a cross-sectional view showing a portion of an area of ​​an electronic panel 200 according to an exemplary embodiment of the concept of the present invention.

[0119] Reference Figure 5 The input sensing layer ISU includes a conductive layer ISU-CL and a sensing insulating layer ISU-IL.

[0120] According to an exemplary embodiment of the concept of the present invention, the conductive layer ISU-CL can be formed on the encapsulation layer TFL via a continuous process. For example, the conductive layer ISU-CL of the input sensing layer ISU disposed on the encapsulation layer TFL can be configured as a single layer. Figure 1A The user input TC described herein can be sensed through the conductive layer ISU-CL of the input sensing layer ISU.

[0121] The sensing insulating layer ISU-IL may cover the conductive layer ISU-CL and may be disposed on the conductive layer ISU-CL. Window 100 may be disposed on the sensing insulating layer ISU-IL. Additionally, an adhesive layer may be disposed between the sensing insulating layer ISU-IL and the window 100. However, the concept of the present invention is not limited thereto.

[0122] Reference Figure 6 and Figure 7A The conductive layer ISU-CL may include multiple sensing patterns TE that overlap with the active area AA. As described above, since the active area AA corresponds to the display area DP-DA, the multiple sensing patterns TE may overlap with the display area DP-DA.

[0123] Multiple sensing patterns TE have unique coordinate information. For example, multiple sensing patterns TE can be arranged in a matrix and connected to multiple sensing signal lines SL respectively. The shape and layout of the multiple sensing patterns TE are not particularly limited. A portion of the multiple sensing signal lines SL can be arranged in the active area AA, and other portions can be arranged in the peripheral area NAA. In an exemplary embodiment of the present invention, the input sensing layer ISU can acquire coordinate information via capacitive means. However, the present invention is not limited thereto, and the input sensing layer ISU can acquire coordinate information in various ways.

[0124] The sensing signal pads TS-PD overlap with the peripheral area NAA and are disposed on the package layer TFL. For example, the sensing signal pads TS-PD can be disposed directly on the package layer TFL. Multiple sensing signal pads TS-PD are respectively connected to multiple sensing signal lines SL. As a result, the multiple sensing signal pads TS-PD can each receive multiple sensing signals output from multiple sensing patterns TE via the multiple sensing signal lines SL, to transmit the received sensing signals to the outside, or can each transmit multiple sensing signals transmitted from the outside to the multiple sensing patterns TE via the multiple sensing signal lines SL.

[0125] In an exemplary embodiment of the concept of the present invention, each of the plurality of sensing patterns TE may have a grid shape. For example... Figure 7A The diagram shows a cross-sectional view of one of a plurality of sensing patterns TE. A sensing pattern TE may include a plurality of patterns PT forming a grid shape.

[0126] The display area DP-DA may include a light-emitting region and a light-blocking region adjacent to the light-emitting region. The light-emitting region indicates the actual light emitted from the display element layer DP-OLED (see [link to DP-OLED]). Figure 3 The light-emitting area is indicated by the light-emitting area, and the light-blocking area indicates the area that absorbs light. Multiple sensing patterns TE can overlap with the light-blocking area.

[0127] Refer again Figure 6 For ease of description, the module region MA is shown in dashed lines. The module region MA includes the area where the panel aperture MH is formed. For example, in a plan view, the module region MA may be surrounded by one of a plurality of sensing patterns TE. In this case, the planar surface area of ​​this one sensing pattern TE may be smaller than the planar surface area of ​​the other sensing patterns TE. However, the concept of the invention is not limited thereto, and the module region MA may be arranged between two adjacent sensing patterns among a plurality of sensing patterns TE.

[0128] According to an exemplary embodiment of the concept of the present invention, the input sensing layer ISU may further include a crack sensing circuit HCP and a crack pad unit HPD electrically connected to the crack sensing circuit HCP. The crack sensing circuit HCP may be electrically isolated from multiple sensing patterns TE. For example, the crack sensing circuit HCP receives independent electrical signals. As an additional example, the crack sensing circuit HCP may be insulated from multiple sensing patterns TE.

[0129] The crack sensing circuit HCP includes a crack sensing pattern HCP-M, an auxiliary pattern HCP-S, and a detection line unit electrically connecting the crack sensing pattern HCP-M to the auxiliary pattern HCP-S. The crack sensing circuit HCP can be arranged on the encapsulation layer TFL using the same process as multiple sensing patterns TE. As a result, each of the multiple sensing patterns TE and the crack sensing circuit HCP can be directly arranged on the encapsulation layer TFL. However, the concept of the invention is not limited thereto. For example, an intervening layer may exist between the crack sensing circuit HCP and the encapsulation layer TFL.

[0130] For example, the crack sensing pattern HCP-M may overlap with the module region MA and be disposed on the encapsulation layer TFL. In a plan view, the crack sensing pattern HCP-M may be spaced apart from the panel aperture MH by a predetermined distance. For example, in this embodiment, the crack sensing pattern HCP-M may have an integrated shape extending along the edge of the panel aperture MH. For example, the crack sensing pattern HCP-M may have a curved shape extending along the edge of the panel aperture MH, and may have a first end and a second end. For example, the first end and the second end of the crack sensing pattern HCP-M are not directly connected to each other.

[0131] The auxiliary pattern HCP-S overlaps with the module region MA and can be disposed on the encapsulation layer TFL. The auxiliary pattern HCP-S may have a shape extending along the edge of the crack sensing pattern HCP-M between the crack sensing pattern HCP-M and multiple sensing patterns TE. The auxiliary pattern HCP-S may have a shape similar to that of the crack sensing pattern HCP-M. For example, the auxiliary pattern HCP-S may have a curved shape extending along the curved shape of the crack sensing pattern HCP-M, and may have a first end and a second end. For example, the auxiliary pattern HCP-S can be directly disposed on the encapsulation layer TFL using the same process as the multiple sensing patterns TE. For example, the aforementioned sensing patterns TE may have a grid shape, and the auxiliary pattern HCP-S may also have a grid shape.

[0132] In addition, each of the multiple sensing patterns TE, as well as the crack sensing pattern HCP-M and the auxiliary pattern HCP-S, includes a conductive material with conductivity. The conductive material may include a metal layer or a transparent conductive layer. The metal layer may be formed of, for example, molybdenum, silver, titanium, copper, aluminum, and alloys thereof. The transparent conductive layer may include, for example, transparent conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO). Alternatively, the transparent conductive layer may include PEDOT, metal nanowires, and graphene.

[0133] The detection line unit can electrically connect the crack sensing pattern HCP-M to the auxiliary pattern HCP-S, and can be electrically separated from multiple sensing patterns TE. For example, the detection line unit includes a first detection line section CL1, a second detection line section CL2, and a third detection line section.

[0134] The first detection line CL1 includes a first main line HL1 and a first connecting line BL1. The first main line HL1 overlaps with the peripheral region NAA and is disposed on the encapsulation layer TFL. The first connecting line BL1 connects the first main line HL1 to one end of the crack sensing pattern HCP-M. The first connecting line BL1 may overlap with each of the peripheral region NAA and the effective region AA. For example, the first main line HL1 and the first connecting line BL1 may be integrated with each other.

[0135] The second detection line CL2 includes a second main line HL2 and a second connecting line BL2. The second main line HL2 is disposed on the encapsulation layer TFL. The second connecting line BL2 connects the second main line HL2 to one end of the auxiliary pattern HCP-S. Each of the second main line HL2 and the second connecting line BL2 may overlap with each of the peripheral region NAA and the active region AA. For example, the second connecting line BL2 may be electrically connected to the auxiliary pattern HCP-S having a grid shape at at least one or more points. For example, the second main line HL2 and the second connecting line BL2 may be integrated with each other.

[0136] The third detection line includes a third main line HL3. The third main line HL3 is connected to the other end of the auxiliary pattern HCP-S and may overlap with each of the peripheral region NAA and the effective region AA. The third main line HL3 may be electrically connected to the auxiliary pattern HCP-S having a grid shape at at least one or more points.

[0137] According to an exemplary embodiment of the present invention, the first main line HL1, the second main line HL2, and the third main line HL3 may be spaced apart from each other in a plan view. For example, since the conductive layer ISU-CL of the input sensing layer ISU in the exemplary embodiment of the present invention is set to a single layer, the first detection line portion CL1, the second detection line portion CL2, and the third detection line portion may have a structure in which the first detection line portion CL1, the second detection line portion CL2, and the third detection line portion are spaced apart from each other.

[0138] Furthermore, the first detection line CL1, the second detection line CL2, and the third detection line can be arranged on the TFL packaging layer using the same process as the aforementioned sensing pattern TE and crack sensing circuit HCP. For example, the first detection line CL1, the second detection line CL2, and the third detection line can be directly arranged on the TFL packaging layer.

[0139] The cracked pad unit HPD includes a first pad portion HPD1 and a second pad portion HPD2. Each of the first pad portion HPD1 and the second pad portion HPD2 may overlap with the peripheral area NAA and be arranged on the package layer TFL.

[0140] The first pad section HPD1 includes a first output pad HO1 and a first input pad HIN1. The first output pad HO1 is connected to one end of a first main line HL1. The first input pad HIN1 is connected to one end of a second main line HL2. The other end of the second main line HL2 is connected to the other end of a crack sensing pattern HCP-M.

[0141] The second pad section HPD2 includes a second output pad HO2 and a second input pad HIN2. The second output pad HO2 is connected to the other end of the first main line HL1. The second input pad HIN2 is connected to one end of the third main line HL3. The other end of the third main line HL3 is connected to the other end of the auxiliary pattern HCP-S.

[0142] The first input pad HIN1 and the second input pad HIN2 receive data from... Figure 1B The diagram shows the detection signals transmitted from the motherboard MB. For example, the first input pad HIN1 receives a first detection signal transmitted from the motherboard MB, and the second input pad HIN2 receives a second detection signal transmitted from the motherboard MB. Each of the first and second detection signals can be transmitted back to the motherboard MB via the first output pad HO1 and the second output pad HO2. Hereinafter, the first and second detection signals output via the first output pad HO1 and the second output pad HO2 will be described as output detection signals.

[0143] For example, the first detection signal and the second detection signal can be provided simultaneously through the first input pad HIN1 and the second input pad HIN2. In this case, whether the crack sensing pattern HCP-M is damaged can be detected by whether the output detection signal is transmitted back to the motherboard MB through the first output pad HO1 and the second output pad HO2.

[0144] For example, if the output detection signal is not transmitted to the motherboard MB through the first output pad HO1 and the second output pad HO2, the crack detection pattern HCP-M is considered damaged. Additionally, if the output detection signal is transmitted to the motherboard MB through only one of the first output pad HO1 and the second output pad HO2, a portion of the aforementioned detection line unit may be considered damaged.

[0145] The presence of cracks in the module region MA can be determined using the aforementioned signals. According to an exemplary embodiment of the present invention, since a crack sensing circuit HCP is also provided, defects occurring in the input sensing layer ISU (e.g., in the module region MA) can be easily detected. Therefore, the reliability of the electronic device can be improved, and whether the electronic device is defective can be determined without a separate test circuit or test equipment, thereby improving process efficiency.

[0146] Reference Figure 7B The circuit element layer DP-CL is disposed on the base substrate BS. The circuit element layer DP-CL includes multiple insulating layers 10, 20, 31, 32 and 40, and Figure 4A The components shown in the equivalent circuit diagram are related to the second thin-film transistor TR2 (see...). Figure 4A The corresponding thin-film transistor TR (hereinafter referred to as a thin-film transistor) is used. Each of the plurality of insulating layers 10, 20, 31, 32 and 40 may include organic and / or inorganic materials and has a single-layer or multi-layer structure. The display element layer DP-OLED includes a pixel defining layer 50 and a light-emitting element EE. In this specification, the light-emitting element EE may be described as a display element.

[0147] A first insulating layer 10 is disposed on a base substrate BS to cover the entire surface of the base substrate BS. The first insulating layer 10 may include a barrier layer 11 and / or a buffer layer 12. Therefore, the first insulating layer 10 can prevent oxygen or moisture introduced through the base substrate BS from penetrating into the pixel or prevent a reduction in the rigidity of the base substrate BS, so as to stably form the pixel on the base substrate BS.

[0148] This is merely an example. For instance, in an exemplary embodiment of the electronic module 400 according to the concept of the present invention, at least one of the blocking layer 11 and the buffer layer 12 may be omitted, and multiple layers may be stacked, but the concept of the present invention is not limited thereto.

[0149] A thin-film transistor TR is disposed on a first insulating layer 10. The thin-film transistor TR includes a semiconductor pattern SP, a control electrode CE, an input electrode IE, and an output electrode OE. The semiconductor pattern SP is disposed on the first insulating layer 10. The semiconductor pattern SP may include a semiconductor material. With a second insulating layer 20 interposed therebetween, the control electrode CE is spaced apart from the semiconductor pattern SP. The control electrode CE may be connected to the first thin-film transistor TR1 (see [link to documentation]). Figure 4A ) and capacitor CP (see Figure 4A Each of the electrodes in )

[0150] The input electrode IE and the output electrode OE are arranged on a plurality of third insulating layers 31 and 32 and are spaced apart from each other in a plan view. The input electrode IE and the output electrode OE pass through the second insulating layer 20 and the plurality of third insulating layers 31 and 32, respectively, and are connected to one side and the other side of the semiconductor pattern SP.

[0151] The display panel DP of an exemplary embodiment of the present invention may further include an upper electrode UE. In this embodiment, a plurality of third insulating layers 31 and 32 are shown as comprising a lower layer 31 and an upper layer 32. However, this is merely an example. For instance, the plurality of third insulating layers 31 and 32 of an exemplary embodiment of the present invention may have a single-layer structure, but the present invention is not limited thereto.

[0152] The upper electrode UE is arranged between the lower layer 31 and the upper layer 32. In a plan view, the upper electrode UE may overlap with the control electrode CE. In this embodiment, the upper electrode UE may receive the same electrical signal as the control electrode CE, or it may receive an electrical signal different from the electrical signal of the control electrode CE to serve as an electrode of a capacitor. This is merely an example. In an exemplary embodiment of the electronic panel 200 according to the concept of the present invention, the upper electrode UE may be omitted, but is not limited to this particular embodiment.

[0153] A fourth insulating layer 40 may be disposed on the upper layer 32 to cover the input electrode IE and the output electrode OE. In the thin-film transistor TR, the semiconductor pattern SP may be disposed on the control electrode CE. Additionally, the semiconductor pattern SP may be disposed on the input electrode IE and the output electrode OE. Furthermore, the input electrode IE and the output electrode OE may be disposed on the same layer and directly connected to the semiconductor pattern SP. The thin-film transistor TR of the exemplary embodiment of the present invention may have various structures, but the present invention is not limited thereto.

[0154] The light-emitting element EE is disposed on the fourth insulating layer 40. The light-emitting element EE includes a first electrode E1, an organic layer EL, and a second electrode E2.

[0155] The first electrode E1 can be connected to the thin-film transistor TR through the fourth insulating layer 40. The electronic panel 200 may also include a separate connection electrode disposed between the first electrode E1 and the thin-film transistor TR. Here, the first electrode E1 can be electrically connected to the thin-film transistor TR through the connection electrode.

[0156] A pixel defining layer 50 is disposed on the fourth insulating layer 40. The pixel defining layer 50 may comprise organic and / or inorganic materials and have a single-layer or multi-layer structure. An opening may be provided in the pixel defining layer 50. The opening may expose at least a portion of the first electrode E1.

[0157] An organic layer EL is disposed between a first electrode E1 and a second electrode E2. The organic layer EL may include at least one light-emitting layer. For example, the organic layer EL may be made of at least one of a variety of materials that emit red, green, and blue light, and may include fluorescent or phosphorescent materials. The organic layer EL may include organic light-emitting materials or inorganic light-emitting materials. The organic layer EL may emit light in response to the potential difference between the first electrode E1 and the second electrode E2.

[0158] In this embodiment, the organic layer EL is shown as a layer having an integrated shape that overlaps with a plurality of openings in the pixel-defining layer 50. However, this is merely an example. For instance, the organic layer EL may be configured to include a plurality of patterns corresponding to each opening, but the concept of the invention is not limited thereto.

[0159] For example, in addition to the light-emitting layer, the organic EL layer may also include a charge control layer. The charge control layer can control the movement of charges to increase the luminous efficiency and lifespan of the light-emitting element. Here, the organic EL layer may include at least one of hole transport materials, hole injection materials, electron transport materials, and electron injection materials.

[0160] A second electrode E2 is disposed on the organic layer EL. The second electrode E2 may face the first electrode E1. The second electrode E2 may have an integrated shape extending from the active region AA to the peripheral region NAA. For example, the second electrode E2 may be commonly provided to multiple pixels PX. The light-emitting element EE disposed on each of the multiple pixels PX may receive a common power supply voltage through the second electrode E2.

[0161] The second electrode E2 may comprise a transmissive conductive material or a transmissive-reflective conductive material. Therefore, light generated in the organic layer EL can be readily emitted onto the third-direction DR3 via the second electrode E2. However, this is merely an example. For instance, the light-emitting element EE of an exemplary embodiment of the present invention may be driven in a bottom-emission mode, and the light-emitting element EE may comprise a transmissive or semi-transmissive material, or the light-emitting element EE may be driven in a bilateral-emission mode, in which light is emitted from both the front and rear surfaces; however, the present invention is not limited thereto.

[0162] The encapsulation layer TFL can be disposed on the light-emitting element EE to encapsulate the light-emitting element EE. A cover layer covering the second electrode E2 can also be disposed between the second electrode E2 and the encapsulation layer TFL.

[0163] The encapsulation layer TFL may include a first inorganic layer 61, an organic layer 62, and a second inorganic layer 63 sequentially stacked on the third-direction DR3. However, the concept of the invention is not limited thereto. For example, the encapsulation layer TFL may also include multiple inorganic layers and multiple organic layers.

[0164] The first inorganic layer 61 may cover the second electrode E2. The first inorganic layer 61 may prevent external moisture or oxygen from penetrating into the light-emitting element EE. For example, the first inorganic layer 61 may include silicon nitride, silicon oxide, or a combination thereof. The first inorganic layer 61 may be formed by a chemical vapor deposition process.

[0165] An organic layer 62 may be disposed on and in contact with the first inorganic layer 61. The organic layer 62 may provide a flat surface on the first inorganic layer 61. Curves disposed on the top surface of the first inorganic layer 61 or particles present on the first inorganic layer 61 may be covered by the organic layer 62 to prevent the surface condition of the top surface of the first inorganic layer 61 from affecting the components disposed on the organic layer 62. Additionally, the organic layer 62 may reduce stress between layers in contact with each other. For example, the organic layer 62 may comprise an organic material and may be formed by solution processes such as spin coating, slot coating, inkjet printing, and similar methods.

[0166] A second inorganic layer 63 may be disposed on the organic layer 62 to cover the organic layer 62. Compared to the organic layer 62 disposed on the first inorganic layer 61, the second inorganic layer 63 can be stably formed on a flat surface. The second inorganic layer 63 can encapsulate moisture escaping from the organic layer 62 to prevent moisture from being introduced. The second inorganic layer 63 may comprise, for example, silicon nitride, silicon oxide, or a combination thereof. The second inorganic layer 63 may be formed by a chemical vapor deposition process.

[0167] According to this embodiment, the module region MA may include a panel aperture MH and a line region LA. The line region LA may be the area between the panel aperture MH and the effective region AA. In a plan view, the line region LA may surround the panel aperture MH. In the line region LA, the light-emitting element EE and / or thin-film transistor TR arranged in the effective region AA may be omitted. Therefore, the transmittance may be relatively higher than the transmittance of the effective region AA.

[0168] The line area LA may contain multiple recesses GV1, GV2 and GV3 of the display panel DP, a dam section DMP, and multiple signal lines SL1 and SL2.

[0169] Multiple recesses GV1, GV2, and GV3 may be formed to be spaced apart from each other. The multiple recesses GV1, GV2, and GV3 are shown as a first recess GV1, a second recess GV2, and a third recess GV3 arranged sequentially in a direction approaching the panel aperture MH, spaced apart from the effective area AA. Each of the first recesses GV1, the second recess GV2, and the third recess GV3 has a closed-line (e.g., closed loop) shape around the panel aperture MH or a discontinuous line shape around at least a portion of the edge of the panel aperture MH, but the inventive concept is not limited thereto. For example, each of the first recesses GV1, the second recess GV2, and the third recess GV3 may have a circular shape.

[0170] Each of the plurality of recesses GV1, GV2, and GV3 is formed by a recess that extends from the top surface of the base substrate BS. In other words, the plurality of recesses GV1, GV2, and GV3 are recesses in the top surface of the base substrate BS. Each of the plurality of recesses GV1, GV2, and GV3 can be formed by removing at least a portion of the base substrate BS. A deposited pattern ELP can be disposed in each of the plurality of recesses GV1, GV2, and GV3 and can be covered by at least one of the first inorganic layer 61 and the second inorganic layer 63.

[0171] Since the electronic panel 200 according to an exemplary embodiment of the present invention also includes a plurality of recesses GV1, GV2 and GV3, continuity between the deposited pattern ELP and the light-emitting element EE can be prevented. Therefore, the penetration path of external moisture or oxygen can be blocked to prevent damage to the elements arranged in the effective area AA.

[0172] Furthermore, the deposited pattern ELP in each of the plurality of recesses GV1, GV2, and GV3 can be covered by the first inorganic layer 61 to prevent the deposited pattern ELP from affecting other components during the manufacturing of the electronic panel 200. Therefore, the process reliability of the electronic panel 200 can be increased. However, this is merely an example. For instance, in an exemplary embodiment of the electronic panel 200 according to the concept of the present invention, the plurality of recesses GV1, GV2, and GV3 may be provided individually or omitted, and the concept of the present invention is not limited thereto.

[0173] The dam section DMP is arranged in the online region LA to divide the formation area of ​​the organic layer 62 into predetermined regions and to prevent the organic layer 62 from expanding additionally. Multiple dam section DMPs can be configured and arranged between multiple recessed sections GV1, GV2, and GV3. The dam section DMP is shown in a stacked structure including a first layer P11, a second layer P12, and a third layer P13. However, this is merely an example. For instance, the dam section DMP can have a single-layer structure and is not limited thereto.

[0174] The encapsulation layer TFL according to an exemplary embodiment of the present invention may further include a planarization layer OC. The planarization layer OC comprises an organic material. The planarization layer OC is disposed in the line region LA, the active region AA, and the peripheral region NAA of the module region MA. The planarization layer OC covers multiple non-planar surfaces disposed in the module region MA caused by dam portions DMP or multiple recesses GV1, GV2, and GV3 to provide a flat surface on its top surface. Therefore, a flat surface can be stably disposed in the region of the module region MA where the organic layer 62 is not disposed.

[0175] According to an exemplary embodiment of the concept of the present invention, the crack sensing pattern HCP-M and the auxiliary pattern HCP-S can be arranged on the encapsulation layer TFL to overlap with the line region LA.

[0176] Figure 8 This is a plan view of a crack sensing circuit HCP according to an exemplary embodiment of the concept of the present invention. Figure 9 It is along Figure 8 The cross-sectional view taken from line II-II'.

[0177] Reference Figure 8 and Figure 6 The first detection signal IP1, input to the first input pad HIN1, is transmitted via the second main line HL2 to the second terminal ND1b of the crack detection pattern HCP-M, and from the second terminal ND1b to the first terminal ND1a of the crack detection pattern HCP-M. The first detection signal IP1 can be transmitted from the first terminal ND1a of the crack detection pattern HCP-M to the first output pad HO1 and the second output pad HO2 via the first connecting line BL1 and the first main line HL1.

[0178] The second detection signal IP2, input to the second input pad HIN2, is transmitted via the third main line HL3 to the second terminal ND2b of the auxiliary pattern HCP-S, and from the second terminal ND2b to the first terminal ND2a of the auxiliary pattern HCP-S. The second detection signal IP2 is also transmitted via the second connection line BL2 and the second main line HL2 from the first terminal ND2a of the auxiliary pattern HCP-S to the second terminal ND1b of the crack sensing pattern HCP-M. The second detection signal IP2 can also be transmitted from the second terminal ND1b of the crack sensing pattern HCP-M to the first output pad HO1 and the second output pad HO2 via the first connection line BL1 and the first main line HL1.

[0179] For example, when a first detection signal IP1 and a second detection signal IP2 (e.g., output detection signals) are detected at each of the first output pad HO1 and the second output pad HO2, the crack sensing pattern HCP-M can be considered undamaged.

[0180] For example, when no output detection signal is detected at either the first output pad HO1 or the second output pad HO2, the crack sensing pattern HCP-M is considered damaged. Furthermore, when an output detection signal is detected at only one of the first output pad HO1 or the second output pad HO2, then one of the first detection line CL1, the second detection line CL2, and the third detection line is considered damaged.

[0181] Furthermore, according to an exemplary embodiment of the concept of the present invention, the first shortest distance between the crack sensing pattern HCP-M and the center HC of the module region MA may be less than the second shortest distance between the auxiliary pattern HCP-S and the center HC of the module region MA. For example, the auxiliary pattern HCP-S may have a shape that is spaced apart from the crack sensing pattern HCP-M by a predetermined distance to surround the crack sensing pattern HCP-M.

[0182] Reference Figure 9 Each of the crack sensing pattern HCP-M, the auxiliary pattern HCP-S, and the multiple sensing patterns TE can be arranged on the encapsulation layer TFL. For example, each of the crack sensing pattern HCP-M, the auxiliary pattern HCP-S, and the multiple sensing patterns TE can be arranged directly on the encapsulation layer TFL. In addition, the crack sensing pattern HCP-M, the auxiliary pattern HCP-S, and the multiple sensing patterns TE can be spaced apart from each other in a plan view.

[0183] For example, the auxiliary pattern HCP-S and the crack sensing pattern HCP-M are electrically connected to each other, but each of the auxiliary pattern HCP-S and the crack sensing pattern HCP-M may not be electrically connected to multiple sensing patterns TE.

[0184] Additionally, the auxiliary pattern HCP-S may have a grid shape and include multiple patterns HCP-S1, HCP-S2, and HCP-S3 spaced apart from each other in a plan view. However, the shape of the auxiliary pattern HCP-S is not limited to this and can be modified in various ways.

[0185] Figures 10A to 10C This is a plan view of a crack sensing circuit HCP according to an exemplary embodiment of the concept of the present invention.

[0186] exist Figure 10A In the crack sensing circuit HCP shown, with Figure 8 Compared to the crack sensing circuit HCP shown, the connection structure between the detection line unit, the crack sensing pattern HCP-M, and the auxiliary pattern HCP-S has been modified.

[0187] For example, one end (e.g., the first end) ND1a of the crack sensing pattern HCP-M is connected to the third main line HL3a, and the other end (e.g., the second end) ND1b of the crack sensing pattern HCP-M is connected to one end of the first connecting line BL1a. The other end of the first connecting line BL1a is connected to the first main line HL1a. One end (e.g., the first end) ND2a of the auxiliary pattern HCP-S is connected to the second main line HL2a, and the other end (e.g., the second end) ND2b of the auxiliary pattern HCP-S is connected to one end of the second connecting line BL2a. The other end of the second connecting line BL2a is connected to the third main line HL3a.

[0188] Figure 10A The crack sensing circuit HCP shown also receives the detection signal through the first input pad HIN1 and the second input pad HIN2. Additionally, the detection signal can be transmitted back to the motherboard MB through the first output pad HO1 and the second output pad HO2.

[0189] Reference Figure 10B ,and Figure 8 Compared to the crack sensing circuit HCP shown, Figure 10B The crack sensing circuit HCP shown is modified only in the shape of the crack sensing pattern HCP-M1, and the structure of the remaining components and parts can be substantially the same.

[0190] The crack sensing pattern HCP-M1 may include a first extension EX1, a second extension EX2, a third extension EX3, a first connecting portion CP1, and a second connecting portion CP2. The first extension EX1, the second extension EX2, the third extension EX3, the first connecting portion CP1, and the second connecting portion CP2 may be connected to each other to provide an integrated shape.

[0191] The first extension EX1 and the second extension EX2 face each other with respect to the axis of symmetry VL. The first extension EX1 and the second extension EX2 are respectively arranged in the module region MA to extend along the edge of the panel hole MH. The first extension EX1 and the second extension EX2 can be substantially arranged in the line region LA.

[0192] A first extension EX1 is arranged to the left of the axis of symmetry VL, and a second extension EX2 is arranged to the right of the axis of symmetry VL. The first extension EX1 may have a semi-circular shape convex to the left, and the second extension EX2 may have a semi-circular shape convex to the right. The first extension EX1 and the second extension EX2 may be linearly symmetrical with respect to the axis of symmetry VL.

[0193] The third extension EX3 may be spaced apart from the first extension EX1 and the second extension EX2. The third extension EX3 may be arranged closer to the center HC of the module region MA than the first extension EX1 and the second extension EX2.

[0194] The third extension EX3 is arranged within the module region MA to extend along the edge of the module region MA. For example, the third extension EX3 may extend along the edge of the panel hole MH. In a plan view, the third extension EX3 may overlap with the axis of symmetry VL. The third extension EX3 may intersect with the axis of symmetry VL.

[0195] The first connecting part CP1 connects one end of the first extension EX1 to one end of the third extension EX3. The second connecting part CP2 is spaced apart from the first connecting part CP1 to connect one end of the second extension EX2 to the other end of the third extension EX3.

[0196] The first connecting portion CP1 and the second connecting portion CP2 may face each other with the axis of symmetry VL between them. Each of the first connecting portion CP1 and the second connecting portion CP2 may extend in a direction parallel to the extending direction of the axis of symmetry VL. In this embodiment, each of the first connecting portion CP1 and the second connecting portion CP2 may be parallel to the axis of symmetry VL. The first connecting portion CP1 and the second connecting portion CP2 may be linearly symmetrical to each other with respect to the axis of symmetry VL.

[0197] Reference Figure 10C ,and Figure 8 Compared to the crack sensing circuit HCP shown, Figure 10C The crack sensing circuit HCP shown is modified only in the shape of the crack sensing pattern HCP-M2, and the structure of the remaining components and parts can be substantially the same.

[0198] The crack sensing pattern HCP-M2 may include four first extensions EX11, EX12, EX13 and EX14, four second extensions EX21, EX22, EX23 and EX24, four first connecting parts CP11, CP12, CP13 and CP14, and four second connecting parts CP21, CP22, CP23 and CP24.

[0199] Among the multiple first extensions EX11, EX12, EX13 and EX14 and the multiple second extensions EX21, EX22, EX23 and EX24, the first first extension EX11 and the first second extension EX21, which are located at the outermost position of the center HC of the module region MA, are respectively connected to the second main line HL2 and the first connecting line BL1.

[0200] Among the multiple first extensions EX11, EX12, EX13 and EX14 and the multiple second extensions EX21, EX22, EX23 and EX24, the fourth first extension EX14 and the fourth second extension EX24, which are arranged closest to the center HC of the module region MA, are connected to the third extension EX3.

[0201] Multiple first connecting parts CP11, CP12, CP13 and CP14 connect multiple first extension parts EX11, EX12, EX13 and EX14 to a third extension part EX3. Multiple second connecting parts CP21, CP22, CP23 and CP24 connect multiple second extension parts EX21, EX22, EX23 and EX24 to the third extension part EX3.

[0202] Multiple first extensions EX11, EX12, EX13, and EX14, and multiple second extensions EX21, EX22, EX23, and EX24 are linearly symmetrical to each other with respect to the axis of symmetry VL. Additionally, multiple first connecting portions CP11, CP12, CP13, and CP14, and multiple second connecting portions CP21, CP22, CP23, and CP24 are linearly symmetrical to each other with respect to the axis of symmetry VL. Therefore, the crack sensing pattern HCP-M2 can have a shape that is linearly symmetrical with respect to the axis of symmetry VL.

[0203] According to an exemplary embodiment of the concept of the present invention, an electronic panel may include a panel aperture overlapping an effective area and a crack sensing pattern arranged adjacent to the panel aperture. The crack sensing pattern can detect external foreign objects that penetrate into the circuit elements through the panel aperture.

[0204] For example, an input sensing layer in an exemplary embodiment of the present invention may include a single conductive layer. As a result, crack sensing patterns and sensing patterns can be arranged in the same conductive layer of the input sensing layer using the same process. Therefore, the overall manufacturing speed of the electronic device can be improved.

[0205] Although the concept of the invention has been described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the scope and spirit of the concept of the invention.

Claims

1. An electronic panel, comprising: A base substrate, the base substrate including a first region and a second region adjacent to the first region, wherein the first region includes a module region and a display region adjacent to the module region; The display element layer includes a plurality of display elements, wherein the plurality of display elements overlap with the display area and are arranged on the base substrate; An encapsulation layer configured to cover the display element and disposed on the base substrate; Multiple sensing patterns, which overlap with the display area and are arranged on the encapsulation layer; A crack sensing pattern, which overlaps with the module region and is disposed on the encapsulation layer; An auxiliary pattern, overlapping the module region and disposed on the encapsulation layer, wherein the auxiliary pattern has a shape extending along the edge of the crack sensing pattern and extending between the plurality of sensing patterns and the crack sensing pattern; and Signal lines are arranged on the encapsulation layer to electrically connect the crack sensing pattern to the auxiliary pattern.

2. The electronic panel as claimed in claim 1, wherein, The signal line includes: A first detection line portion, the first detection line portion including a first main line and a first connecting line configured to connect the first main line to a first end of the crack sensing pattern, wherein the first main line overlaps with the second region; The second detection line portion includes a second main line and a second connecting line configured to connect the second main line to a first end of the auxiliary pattern, wherein the second main line is connected to a second end of the crack sensing pattern; and The third detection line section includes a third main line connected to the second end of the auxiliary pattern.

3. The electronic panel as claimed in claim 2, wherein, In the plan view, the first main line, the second main line, and the third main line are spaced apart from each other.

4. The electronic panel as claimed in claim 3, wherein, The crack sensing pattern has a curved shape.

5. The electronic panel as described in claim 2, further comprising: A first pad portion, comprising a first output pad and a first input pad connected to a first end of the second main line; wherein the first output pad is connected to the first end of the first main line; and The second pad section includes a second output pad and a second input pad connected to a first end of the third main line, wherein the second output pad is connected to a second end of the first main line.

6. The electronic panel as claimed in claim 5, wherein, The first detection signal input to the first input pad is transmitted to the second end of the crack sensing pattern via the second main line, and the first detection signal is transmitted from the second end of the crack sensing pattern to the first end of the crack sensing pattern. The first detection signal is transmitted from the first end of the crack sensing pattern to the first output pad and the second output pad via the first connecting line and the first main line.

7. The electronic panel as claimed in claim 6, wherein, The second detection signal input to the second input pad is transmitted to the second end of the auxiliary pattern via the third main line, and the second detection signal is transmitted from the second end of the auxiliary pattern to the first end of the auxiliary pattern. The second detection signal is transmitted from the first end of the auxiliary pattern to the second end of the crack sensing pattern via the second connecting line and the second main line. The second detection signal is transmitted from the second end of the crack sensing pattern to the first output pad and the second output pad via the first connecting line and the first main line.

8. The electronic panel as claimed in claim 5, wherein, The second end of the second main line is connected to the second end of the crack sensing pattern, and The second end of the third main line is connected to the second end of the auxiliary pattern.

9. The electronic panel as claimed in claim 2, wherein, The display area surrounds the module area, and Each of the plurality of sensing patterns and the auxiliary patterns is set as a grid pattern.

10. The electronic panel as claimed in claim 2, wherein, Each of the second main line and the third main line includes a first portion that overlaps with the second region and a second portion that overlaps with the display region.

11. The electronic panel as claimed in claim 2, wherein, The signal line also includes a plurality of sensing signal lines, which are spaced apart from the first detection line portion, the second detection line portion and the third detection line portion and are respectively connected to the plurality of sensing patterns.

12. The electronic panel as claimed in claim 1, wherein, Each of the plurality of sensing patterns, the crack sensing pattern, the auxiliary pattern, and the signal line is directly arranged on the encapsulation layer.

13. The electronic panel of claim 1, further comprising: A hole, wherein the hole is configured in the module region to pass through the electronic panel, The crack sensing pattern extends along the edge of the hole.

14. The electronic panel of claim 13, wherein, The first distance between the crack sensing pattern and the center of the hole is less than the second distance between the auxiliary pattern and the center of the hole.

15. The electronic panel of claim 13, wherein, The crack sensing pattern includes: A first extension extends along the edge of the hole; A second extension, the second extension being arranged further from the center of the hole than the first extension and spaced apart from the first extension to extend along the edge of the first extension; and A connecting portion configured to connect the first extension portion to the second extension portion.

16. The electronic panel as claimed in claim 1, wherein, The display area is the area for displaying images, and The module area and the second area are non-display areas where images are not displayed.

17. An electronic device comprising: An electronic panel configured to display images and sense external input; as well as An electronic module, the electronic module being arranged to overlap with the electronic panel, The electronic panel includes: A base substrate, the base substrate including a module region, an effective region and a peripheral region adjacent to the effective region, wherein the module region includes a hole configured to pass through the electronic panel, and wherein the effective region surrounds the module region; Multiple sensing patterns, which overlap with the effective area and are arranged on the base substrate; A crack sensing pattern, which overlaps with the module region and is disposed on the base substrate, wherein the crack sensing pattern has a curved shape extending along the edge of the hole; An auxiliary pattern, overlapping the module region and disposed on the base substrate, wherein the auxiliary pattern extends along the edge of the crack sensing pattern and extends between the plurality of sensing patterns and the crack sensing pattern; and A signal line configured to electrically connect the crack sensing pattern to the auxiliary pattern.

18. The electronic device of claim 17, wherein, The plurality of sensing patterns, the crack sensing pattern, the auxiliary pattern, and the signal lines are arranged in the same layer as each other.

19. The electronic device of claim 17, wherein, The plurality of sensing patterns, the crack sensing pattern, the auxiliary pattern, and the signal lines are arranged on the base substrate using a one-time process with the same materials.

20. The electronic device of claim 17, further comprising: A first detection line portion, the first detection line portion including a first main line and a first connecting line configured to connect the first main line to a first end of the crack sensing pattern, wherein the first main line overlaps with the peripheral region; The second detection line portion includes a second main line and a second connecting line configured to connect the second main line to a first end of the auxiliary pattern, wherein the second main line is connected to a second end of the crack sensing pattern; and The third detection line section includes a third main line connected to the second end of the auxiliary pattern.

Images