Intelligent electronic switch

Abstract

Embodiments of the present disclosure relate to intelligent electronic switches. An integrated circuit that can be used as an intelligent switch is described herein. According to one embodiment, the integrated circuit includes a power transistor coupled between a power pin and an output pin, and also includes a control circuit configured to trigger the power transistor to be turned on and off according to an input signal. The control circuit is configured to trigger the power transistor to be turned off when a load current through the power transistor is at or above a predetermined current and a power supply voltage received at the power pin is at or below a predetermined threshold voltage.

Description

Technical Field

[0001] The present disclosure relates to the field of intelligent semiconductor switches. Background Art

[0002] In many applications, semiconductor switches are used to switch electrical loads on and off. Semiconductor switches that include supplementary circuitry in addition to electronic switches (e.g., power transistors) are often referred to as intelligent electronic switches or simply smart switches. Examples of supplementary circuitry are temperature sensors for detecting overtemperature, load current sensors for measuring the load current through the switch, control logic for generating control signals that trigger switching on or off depending on input signals and measured parameters such as measured current and measured temperature, and interface circuits for outputting the measured parameters, etc.

[0003] Smart switches are increasingly used to replace traditional fuses, not only in automotive applications. Smart switches that can be used as a substitute for fuses can be called smart fuses or electronic fuses. In these cases, the smart switch can include a circuit system that is configured to monitor the measured load current and trigger on and off depending on the load current and a characteristic curve representing the wire characteristics of the wire connecting the smart switch and the electrical load. When the estimated wire temperature (relative to the ambient temperature) exceeds a specified limit, the wire characteristics allow the control circuit to trigger the load to be disconnected from the power supply. Additionally, the above-mentioned supplementary circuit system included in the smart switch can provide a load current limiting function.

[0004] When two or more loads are connected to a power supply (e.g., an automobile's onboard power supply), a defective load (die defect) that draws a relatively high current from the power supply may cause a drop in the power supply voltage, which may also affect other loads connected to the same power supply. Summary of the invention

[0005] An integrated circuit that can be used as an intelligent switch is described herein. According to one embodiment, the integrated circuit includes a power transistor coupled between a power pin and an output pin, and also includes a control circuit configured to trigger the power transistor to be turned on and off according to an input signal. The control circuit is configured to trigger the power transistor to be turned off when a load current through the power transistor is at or above a predetermined current and a power supply voltage received at the power pin is at or below a predetermined threshold voltage.

[0006] In addition, a method for switching a load is described herein. According to one embodiment, the method includes enabling and disabling a load current path between a power pin and an output pin using a power transistor based on an input signal. The method also includes triggering a shutdown of the power transistor when the load current is at or above a predetermined current and a power supply voltage received at the power pin is below a predetermined threshold voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention may be better understood with reference to the following drawings and description. The components in the drawings are not necessarily drawn to scale; instead, emphasis is placed on illustrating the principles of the present invention. Additionally, in the drawings, like reference numerals denote corresponding parts. In the drawings:

[0008] Figure 1 A general example of a smart switch is shown.

[0009] Figure 2 The operation of multiple loads at the same power source is shown, where each load can be individually switched on and off via a corresponding smart switch.

[0010] Figure 3 A timing diagram is included that illustrates the expected behavior of a smart switch according to embodiments described herein.

[0011] Figure 4 One embodiment of an intelligent switch that may operate as shown in FIG. 3 is shown.

[0012] Figure 5 Shown included in Figure 4 An exemplary implementation of control logic in a smart switch.

[0013] Figure 6 and Figure 7 Includes timing diagrams to further illustrate Figure 5 The function of the circuit.

[0014] Figure 8 Includes a timing diagram illustrating the functionality of an alternative intelligent switch embodiment, which is substantially similar to Figure 4 Same as the smart switch, but without the current limiting feature.

[0015] Figures 9 to 11 Additional embodiments of intelligent switches are shown.

[0016] Fig.12 is a flow chart illustrating one embodiment of a method for operating a smart switch. DETAILED DESCRIPTION

[0017] In the following detailed description, reference is made to the accompanying drawings which form a part of the description and which, for the purpose of illustration, show examples of how the invention may be used and implemented. Figure 1 A general example of an integrated smart switch circuit, referred to below as a smart switch 1, is shown. The smart switch 1 may be integrated in a single semiconductor die arranged in a chip package. However, in some embodiments, the smart switch 1 may include two or more semiconductor dies arranged in one chip package.

[0018] according to Figure 1 , the smart switch 1 includes an electronic switch 2, which may be a power transistor, such as a MOS transistor. A DMOS transistor may be used as a power transistor. Although the examples discussed herein use MOS transistors as the power transistor 2, it should be understood that bipolar transistors may be used instead. The application of the concepts described herein to bipolar transistors is of no problem to a technician in the relevant field. The power transistor 2 is coupled between the power pin SUP and the output pin OUT of the smart switch 1. Therefore, the power transistor 2 may connect the output pin OUT to the power pin SUP when turned on. Similarly, the power transistor 2 may disconnect the output pin from the power pin SUP when turned off. In other words, the power transistor 2 may be switched on or off according to a gate signal V applied to the gate electrode of the transistor. G The load current path between the power supply pin SUP and the output pin OUT is enabled and disabled. It should be understood that if a bipolar transistor is used as a power transistor, the transistor is turned on and off according to the base current rather than the gate voltage.

[0019] exist Figure 1 In the example, the gate signal V G Provided by the gate driver circuit 5, which is configured to ON Output gate signal V G , the control signal S ON It is a binary signal that can only present a high level (for example, indicating on) and a low level (for example, indicating off). ON The control logic 3 may include a combinational logic circuit and a sequential logic circuit as well as a synchronous circuit and an asynchronous circuit. The control logic 3 is configured to receive an input signal S at an input pin IN in the smart switch based on the input signal S received at the input pin IN in the smart switch. IN and other parameters to trigger the on and off of transistor 2 (by generating a control signal S with an appropriate logic level). ON ). Input signal S IN can be provided by an external (separate from the intelligent switch 1) circuit (such as, for example, Figure 1 In the example above the microcontroller labeled μC is generated.

[0020] Note that the input signal S is not necessarily received at the input pin of the smart switch. IN In some embodiments, the smart switch may have a digital communication interface, such as, for example, a serial peripheral interface (SPI) that allows receiving data (e.g., from a microcontroller μC), including on and off commands. In these embodiments, the smart switch may include generating an input signal S IN The circuit system and sets the input signal S according to the on command and the off command received via the digital communication interface INlogic level.

[0021] When a control signal S having a specific logic level is generated ON The above-mentioned other parameters that can be processed by the control logic 3 can be, for example, a measured value representing the chip temperature, a measured value representing the load current, a configurable threshold value (for example, an over-temperature threshold value), etc. The load current i output to the load Z at the output pin OUT L can be measured by the current sensing circuit 20. The current sensing circuit 20 may, for example, include a sensing transistor coupled to the power transistor 2 and operating in the same operating point. Current sensing using a sensing transistor is well known to those skilled in the art and is therefore not discussed in detail herein. For example, the power transistor may be composed of a plurality of transistor cells of a cell array, wherein one or several transistor cells of the cell array may be used to form the sensing transistor. In a simple embodiment, the current sensing circuit may include a current sensing resistor connected between a load terminal (e.g., a source terminal) of the transistor 2 and the output pin OUT. In this case, the voltage drop across the current sensing resistor indicates the load current and may be used as a current sensing signal. Another example of the above-mentioned parameter is a current threshold that can be used to implement an overcurrent shutdown function. For example, when the current sensing signal CS provided by the current sensing circuit 20 reaches or exceeds the threshold value V TRIP When the critical current value is reached, the control logic 3 triggers the transistor 2 to turn off until the switch is again input with the signal S IN trigger.

[0022] exist Figure 1 In the example of FIG. 1 , the smart switch 1 is configured as a high-side switch, that is, the smart switch 1 is connected between a power line (at a power pin SUP) providing a power voltage VB and a load Z, and the load Z is connected to an output pin OUT. The smart switch 2 also has a ground pin GND to receive a reference potential V GND , which can be defined as 0 Volts and used as a constant reference potential for the circuitry included in the smart switch 1 .

[0023] Figure 2 An example of a system including multiple (two or more) electric loads Z1, Z2, Z3 and Z4 is shown, wherein each electric load Z1, Z2, Z3 and Z4 is connected to a power supply (power supply voltage V B ) connection. In practice, the power supply pins SUP of the plurality of smart switches 1.1, 1.2, 1.3 and 1.4 will be connected to a circuit node N, which is connected to a voltage source (e.g., a car battery) via a relatively long wire or cable. In particular, a power supply voltage V BThe cable between the voltage source (not shown in the figure) and the circuit node N will be significantly longer (and therefore have a correspondingly high impedance Z0) than the short wiring between the circuit node N and the individual smart switches 1.1, 1.2, 1.3 and 1.4. It should be understood that in Figure 2, the impedance Z0 does not represent a specific resistor device, but rather represents the inherent resistance of the cable / wire between the voltage source (e.g., a battery) and the circuit node N. The input signal S for the smart switch IN1 , S IN2 , S IN3 and S IN4 Can be done by Figure 1 The microcontroller μC in the previous example is provided. The microcontroller μC and the intelligent switches 1.1, 1.2, 1.3 and 1.4 can be arranged on the same circuit board, however, this is not necessarily the case.

[0024] The load current through the intelligent switches 1.1, 1.2, 1.3 and 1.4 and the corresponding loads Z1, Z2, Z3 and Z4 is represented by i L1 、i L2 、i L3 and i L4 Therefore, the voltage source (which generates the power supply voltage V B ) and the total current i0 of the cable between the circuit node N is equal to the individual load current i L1 、i L2 、i L3 andi L4 (i0=i L1 +i L2 +i L3 +i L4 ). As a result, the supply voltage that “arrives” at circuit node N is slightly lower than voltage V due to the voltage drop i0·Z0 across the cable impedance Z0. B , and is denoted as V B '. That is, V B '=V B -i0·Z0=Z0·(i L1 +i L2 +i L3 +i L4 ). The voltage drop across the short wiring between the circuit node N and the smart switches 1.1, 1.2, 1.3 and 1.4 is negligible for this discussion because the corresponding resistance is small compared to the impedance Z0.

[0025] In practice, situations may occur where, for any reason, the load draws a relatively high load current. The increased load current, for example, the load current i L1This will result in an increased total current i0 through the wire / cable connecting the voltage source to the circuit node N. The increased total current i0 requires an increased voltage drop i0·R0 across the cable and a corresponding reduced voltage V at the circuit node N. B '. In other words, the supply voltage "seen" by loads Z1, Z2, Z3 and Z4 is the voltage V that will drop when one of loads Z1, Z2, Z3 and Z4 draws an increased load current. B '.

[0026] As discussed above, a single load (eg, load Z1) may draw excessive current (load current i in this example) due to, for example, a defect. L1 ), which may cause the power supply voltage V B ', which is also "seen" by all other loads Z2, Z3 and Z4. Supply voltage V B Such a drop in ' may cause undesirable effects and malfunctions in these loads Z2, Z3 and Z4, although they are not defective. In the worst case, a defect in one load (in this example, load Z1) may cause malfunctions in all other loads (in this example, loads Z2, Z3 and Z4) supplied via the same circuit node N. To detect such a situation, the microcontroller μC must monitor the voltage V at the circuit node N (for example, using an analog-to-digital converter that may be included in the microcontroller) B ' and the load current i L1 、i L2 、i L3 and i L4 , and triggers the switch to shut down when the smart switch is connected to a defective load (by generating an appropriate input signal). Monitoring the load current can be done, for example, by a microcontroller μC via a digital communication interface (e.g. a serial peripheral interface) or an analog diagnostic output pin (not shown in the figure) by reading the measured current information from the smart switches 1.1, 1.2, 1.3 and 1.4. Smart switches with diagnostic output pins for outputting the measured current information are known in this way (and are implemented, for example, in the smart switch BTS50010-1TAD of Infineon), and are therefore not discussed further in this document. It is obvious that the mentioned monitoring function will enable Figure 2 The circuit shown in is significantly more complex.

[0027] Reference below Figure 3 and Figure 4 The discussed examples may improve the situation and avoid the need to implement the above-mentioned monitoring functionality in the microcontroller μC. Figure 3 The input signal S applied to the input pin of the intelligent switch 1 is shown in FIG. IN The timing diagram (which can represent Figure 2Smart switch 1.1), power supply voltage V B 'The load current i of smart switch 1 (and other smart switches) and smart switch 1 L "See". Figure 4 An embodiment of an intelligent switch is shown, which can detect the power supply voltage V B ' decreases, and at the same time, when an excessively high load current passes through the power transistor 2, the power transistor 2 is turned off. Basically, Figure 3 The timing diagram shows the Figure 4 The behavior / function of the smart switch is shown in FIG.

[0028] according to Figure 3 , Figure 4 The smart switch 1 receives the input signal S IN , the input signal changes from low level to high level at time t0 to trigger the smart switch to be turned on. IN The control logic 3 will generate a control signal S with a high level. ON , so that the gate driver 5 generates a gate voltage V high enough to turn on the transistor 2 G . Almost immediately, the load current i L starts to rise. Later, the voltage V B starts to decrease (for any reason, such as due to a defect in the load connected to the adjacent smart switch), and at time t1, the voltage V B ' drops below the undervoltage threshold V UVTH At the same time, at the same time t1, the load current i L is low enough (i.e., at the current threshold i LIM When the operation of the intelligent switch 1 is involved, the voltage V B 'At the undervoltage threshold V UVTH The following does not have a specific result.

[0029] Later again, the load current i L starts to rise (eg, due to a defect in the load connected to the smart switch 1), and at time t2, the load current i L Reaching the mentioned current threshold i LIM , which results in current limiting (which may be included in the gate driver 5) being effective. Therefore, the gate driver 5 reduces the load current i L The limit is the threshold i mentioned above. LIM defines the maximum current. Then, the voltage V B 'Starts to decrease again until the voltage V B ' drops below the undervoltage threshold V UVTHAt time t3, both conditions are met, that is, the load current has reached the current threshold i LIM (which means that current limiting is effective in this example), and the voltage V B ' has fallen to or below the undervoltage threshold V UVTH These two conditions (i.e., L ≥i LIM and V B '≤V UVTH ) is being met strongly indicating that the high current drawn by the load connected to the smart switch 1 is the cause of the voltage drop, and in order to avoid negative effects on adjacent smart switches, the control logic 3 triggers the switching off of the transistor 2 (by generating a control signal S with an appropriate logic level) when it detects that the two mentioned conditions are met. ON ).exist Figure 4 In the example of L ≥i LIM ), and the second condition (V B '≤V UVTH ). The output signal of comparator 6 is represented as UV, and the output signal of comparator 7 is represented as LIM. The signal UV having a high level may indicate that the voltage V B ' has fallen to or below the threshold V UVTH , and the signal LIM having a high level may indicate that the current sensing signal CS has reached or exceeded the threshold C SLIM , where CS ≥ CS LIM Equal to i L ≥i LIM , because the threshold C SLIM Indicates the corresponding current limit i LIM .

[0030] In order to avoid the voltage V B The short fault in ' causes the transistor 2 to turn off. The turn-off of transistor 2 is not triggered immediately at time t3, but is triggered later at t4 = t3 + t FILT In other words, when the critical situation (i.e. L ≥i LIM And V B '≤V UVTH ) for a predetermined period of time t FILT (filter time), transistor 2 is only turned off and a short voltage drop (shorter than t FILT ) is filtered / blanked. A filter implementing such a function may be included in the control logic 3. Figure 5 To describe the example.

[0031] Figure 5An exemplary implementation of the control logic 3 is shown, which can be used in Figure 4 It should be understood that in the smart switch Figure 5 Only those parts and components of the control logic 3 that are relevant to the following explanation are depicted. Other parts and components not shown can be implemented in the same way as done in an existing intelligent switch (eg, the above-mentioned intelligent switch BTS50010-1TAD).

[0032] according to Figure 5 In FIG. (a), the control logic 3 receives the output signals of the comparator 6 and the comparator 7, namely, the signal UV and the signal LIM. The purpose and function of the comparator 6 and the comparator 7 have been discussed above, and reference has been made to Figure 3 And the corresponding explanation. Figure 5 In the embodiment of FIG. (a), the control logic 3 comprises an AND-gate 31, and the AND-gate 31 receives the signal UV and the signal LIM. If (and only if) the signal UV and the signal LIM respectively indicate the supply voltage V B ' drops below the threshold voltage V UVTH and is at or above the current threshold i LIM The load current i L , then the output signal of AND gate 31 will only present a high level. The output of AND gate 31 is provided to filter 32, which is configured to blank short pulses (short pulses are shorter than filter time t) at the output of AND gate 31. FILT When the output signal of AND gate 31 (logical combination UV & iLIM) changes from low level to high level, and the high level is maintained for at least the filter time t FILT , the output of the filter 32 follows the output of the AND gate 31 and also changes from a low level to a high level.

[0033] The output signal of filter 32 becomes high indicating two conditions (i.e., L ≥i LIM and V B '≤V UVTH ), these two conditions are at least equal to a filter time t FILT The output of the filter 32 is connected to the set input of the SR latch 33 (also called SR flip-flop), and therefore, when the output signal of the filter 32 becomes high, the SR latch 33 is set. When the SR latch 33 is set, the inverted output of the SR latch 33 (which provides a disconnect signal) becomes low (i.e., The signal OFF below the level indicates that the power transistor 2 will be turned off, which is related to the input signal S IN is supplied to the gate driver 5 (see Figure 3 ) control signal S ON , which is generated by an AND gate 35 which receives an input signal S at its input IN and signal OFF. Basically, when the SR latch is in the reset state (i.e., ), AND gate 35 responds to input signal S IN is transparent, but when the SR latch is in the set state (i.e., ), it blanks the input signal S IN SR latch 33 will not be reset until the input signal S IN returns to a low level (which must be controlled by external circuitry such as Figure 4 The microcontroller μC in the circuit is triggered. The input signal S IN The low level of causes SR latch 33 to reset, and SR latch 33 receives the inverted input signal (generated by inverter 34) at its reset input.

[0034] The filter 32 may be implemented in various ways. Figure 5 In the example of FIG. 3, in FIG. (a), the filter 32 includes a counter 321 having an enable input EN receiving the output signal of the AND gate 31. Therefore, when the logic is combined with UV & i LIM Indicates two conditions (i L ≥i LIM and V B '≤V UVTH ) are satisfied simultaneously, counter 321 is enabled. When enabled, counter 321 will increase the counter value CNT in each locked cycle of the clock signal CLK, which is supplied to the clock input of counter 321. If counter 321 is at CNT MAX If the counter value CNT reaches the reference value CNT after the clock cycle is still enabled, MAX The comparator 322 can detect the condition CNT=CNT MAX The comparator 322 is configured to compare the counter value CNT with the reference value CNT MAX The output of comparator 322 provides the output signal of filter 32, which, as described above, is supplied to the set input of SR latch 33. The reference value CNT of clock signal CLK MAX and clock frequency F CLK Defines the filter time t FILT , that is, t FILT =CNT MAX / f CLK It should be understood that the comparator 322 may be a digital comparator that compares two register values, one of which represents the counter value CNT and the other represents the reference value CNT.MAX .

[0035] Figure 5 FIG. (b) shows an alternative implementation of the filter 32. Thus, the filter 32 comprises a resistor R F and capacitor C F The RC-low-pass filter is configured to filter the output signal of the AND gate 31. The output signal of the RC-low-pass filter is supplied to the comparator 333 with hysteresis (Schmitt trigger). The comparator threshold and time constant (τ F =R F ·C F ) is designed so that only when the high level at the output of AND gate 31 is maintained for at least the filter time t FILT , the output of the comparator 333 changes from a low level to a high level.

[0036] Figure 5 The function of the circuit in Figure (a) also shows Figure 6 and Figure 7 The timing diagram in . Figure 6 The timing diagram and Figure 3 Timing Figure 1 That is, t1 indicates the first time that undervoltage (V B '≤V UVTH ) and t3 indicates the second time undervoltage is detected (V B '≤V UVTH ) (see Figure 6 Top-level diagram and Figure 3 Figure 2). At time t2, the load current i L reached by the signal LIM (see Figure 6 The second picture and Figure 3 The current threshold i indicated by the bottom diagram LIM (i L ≥i LIM ). In addition, the current limitation is effective at time t2. Figure 6 The third figure shows the output signal of the AND gate 31, which enables the counter 321 when it changes to a high level. If the output signal of the AND gate 31 remains high for a sufficiently long time (i.e., at least the holding time t FILT =CNT MAX / f CLK ), then the counter 321 will count up to CNT MAX (See Figure 6 By setting the SR latch 33, the comparator 322 will detect the condition CNT=CNT MAX, then comparator 322 will trigger transistor 2 to turn off, and as a result, SR latch 33 will cause AND gate 35 to blank input signal SIN (see Figure 6 Bottom figure, the inverted output signal OFF of SR latch 33 causes the input signal S IN of the blanking).

[0037] Figure 7 The timing diagram shows the Figure 6 Similar situation. However, unlike Figure 6 , the undervoltage condition (V B’ ≤V UVTH ) only lasts for a short time (shorter than the filter time t FILT , see Figure 7 (top image). Figure 7 The second figure shows the signal LIM, which indicates the load current i L At time t2, the current threshold i is reached or exceeded. LIM ,like Figure 6 's previous example. Figure 7 The third diagram of FIG. 3 shows the output signal of the AND gate 31, which enables the counter 321 at time t3. Unlike the previous example, the counter 321 is turned on when the counter value CNT reaches the reference value CNT. MAX Previously disabled again (see Figure 7 Therefore, the SR latch 33 will not be set, and the signal OFF received by the AND gate 35 is kept at a high level (see Figure 7 bottom figure), and no input signal S occurs IN of the disappearance.

[0038] Figure 8 Includes a timing diagram illustrating the functionality of an alternative intelligent switch embodiment, which is substantially similar to Figure 4 The same as the smart switch, but without the current limiting function. Therefore, when the load current i L Reaching the current threshold i LIM (equivalent to the current sensing signal CS reaching the threshold CS LIM ), the gate driver 5 (see Figure 4 ) does not perform current limiting. However, the current sensing signal CS is monitored and the comparator 7 will detect when the current sensing signal CS reaches or exceeds the threshold CS LIM . Omitting the current limit function is not required in Figure 5 Therefore, Figure 8 The first timing diagram and the second timing diagram are basically the same as Figure 3 The first and second figures are the same. Figure 8 The third timing diagram is Figure 3However, at time t2, there is no startup current limit and the load current can exceed the threshold i LIM As an option (and as an alternative to current limiting), an overcurrent shutdown function may be implemented in one embodiment of the intelligent switch 1. That is, when the load current i L reaches a current threshold i LIM The maximum allowable current i MAX , the transistor 2 is triggered to be turned off (regardless of the state of the signal UV).

[0039] Figures 9 to 11 Other embodiments of the intelligent switch are shown. These embodiments are Figure 3 and, to avoid repetition, the following discussion focuses on the modifications / enhancements of the embodiments compared to Figure 3 difference.

[0040] Various parameters used by the control logic 3 and other components integrated in the intelligent switch may be configurable. Fig. 9 For example, a resistor R connected to a dedicated configuration pin of the smart switch can be used. A and resistor R B To configure the threshold voltage V UVTH and current limit i LIM (denoted by CSLIM). In this example, the threshold voltage V UVTH is set to depend on (eg, be proportional to) the resistor R A resistance, and the current limit i LIM Depends on (eg, is proportional to) the resistor R B To this end, the intelligent switch may include a configuration circuit 8 configured to be based on the resistor R A and resistor R B The resistors are used to generate the current limit i LIM and threshold voltage VU VTH The concept of using external resistors to process configuration parameters in an integrated circuit is known (see, for example, US20180287365A1), and is therefore not described in detail here. For example, the configuration circuit 8 may include a circuit configured to provide an external resistor R A and resistor R B A current source that outputs a constant current. In this case, the voltage at the configuration pin (to which the resistor is connected) indicates the corresponding parameter. These voltages can be further processed by the configuration circuit 8 and output to, for example, comparator 6 and comparator 7. Alternatively, the configuration circuit 8 can include a circuit configured to connect an external resistor R A and resistor R BThe voltage across the terminals is regulated to a constant value. In this case, the current output at the configuration pin (to which the resistor is connected) indicates the corresponding parameter. It is within the knowledge of a person skilled in the art to design the configuration circuit 8 so that it can provide the received information in a form required for processing the information in the circuit system of the intelligent switch 1, and in particular in the control logic 3 and the comparators 6 and 7.

[0041] exist Fig.10 In the example of the smart switch, a communication interface such as a serial peripheral interface (SPI) is provided, which allows communication with an external device such as a microcontroller μC (e.g., via a serial bus). In this example, various data may be received via the communication interface 9 (e.g., from the microcontroller), including switch-on commands and switch-off commands, as mentioned above. Thus, the communication interface may be configured to generate an input signal S IN and sets the input signal S according to the on and off commands received via the digital communication interface IN In addition, the received data may include information about configurable parameters such as, for example, the current limit i LIM , voltage threshold V UVTH and the filter time t FILT (For example, by the reference value CNT MAX It is within the knowledge of a person skilled in the art to design the communication interface 9 so that it can provide the received information in the form required for processing the information in the circuit system of the intelligent switch 1, and in particular in the control logic 3 and the comparators 6 and 7.

[0042] exist Fig.11 In the example of, the smart switch includes a monitor circuit 4, which is configured to monitor the current sensing signal CS and determine when to trigger the shutdown of the transistor 2 based on the current sensing signal. To this end, the monitoring circuit 4 can be configured to "mimic" the characteristics of a fuse, which is blown when it becomes too hot. Smart switches including circuit systems are known (see, for example, US20180287365A1), which enable the smart switch to disconnect the load (connected to the output pin OUT) from the power pin SUP based on a predetermined fuse characteristic, and are therefore not further explained here. For example, the monitor circuit 4 can be configured to estimate a temperature value based on the current sensing signal CS, which temperature value represents the temperature of the wire connecting the output pin OUT and the load Z (relative to the ambient temperature), and generate a protection signal OC indicating whether the estimated temperature value is higher than a predetermined temperature threshold. If the protection signal indicates overtemperature, the control circuit 3 can trigger the shutdown of the power transistor 2 in response to the protection signal OC indicating that the estimated temperature value is higher than the predetermined temperature threshold. In such an embodiment, it can be with Figure 5The protection signal OC is processed in a similar manner to the output signal of the filter 32 in the example. That is, the SR latch can be set depending on the level of the protection signal OC, and the input signal S IN Can be blanked or not depending on the state of the SR latch.

[0043] Fig.12 is a flow chart showing one embodiment of a method for operating an intelligent switch. Basically, the flow chart represents the Figures 1 to 11 Therefore, the method includes using the smart switch 1 (see Fig.12 Step S1) uses a power transistor 2 to enable and disable the load current path between the power pin SUP and the output pin OUT of the smart switch 1. The power transistor 2 depends on the input signal S IN To switch on and off, in some embodiments, the input signal S IN The method further includes detecting a load current i through the load current path. L At or above a predetermined current i LIM (current limiting) case, and the power supply voltage V received at the power supply pin SUP B ' is at or below a predetermined threshold voltage V UVTH (See Fig.12 Step S2). After detecting the load current i passing through the load current path L At or above a predetermined current i LIM And the power supply voltage V B ' is at or below a predetermined threshold voltage V UVTH When , transistor 2 is triggered to turn off.

[0044] In some embodiments, when the detected condition (load current i L At or above a predetermined current i LIM And the power supply voltage V B 'Below the predetermined threshold voltage V UVTH ) for at least a predetermined period of time t FILT When , transistor 2 is triggered to turn off.

[0045] Although the present invention has been shown and described with respect to one or more embodiments, the illustrated examples may be changed and / or modified without departing from the spirit and scope of the appended claims. For example, the logic levels used to trigger a particular action may be inverted compared to the depicted examples. Logic gates may be replaced by other logic circuits that perform substantially the same functions, etc. In particular, with respect to the various functions performed by the above-mentioned components or structures (units, components, devices, circuits, systems, etc.), unless structurally equivalent to the disclosed structures that perform the functions in the exemplary embodiments of the present invention, the terms used to describe such components are intended to correspond to any component or structure (e.g., functionally equivalent) that performs the specified functions of the described components, even if not structurally equivalent.

Claims

1. An integrated circuit, comprising: A power transistor (2) is coupled between the power supply pin SUP and the output pin OUT; The control logic circuit (3) is configured to IN Triggering the power transistor (2) to turn on and off; The first comparator (6) is configured to detect the power supply voltage V received at the power supply pin SUP. B ' has dropped to or below a predetermined threshold voltage V UVTH ; The second comparator (7) is configured to detect the load current i passing through the power transistor (2). L At or above a predetermined current i LIM ; as well as A filter (32) receives a logic signal UV&LIM, wherein the logic signal UV&LIM indicates an AND combination of an output signal UV of the first comparator (6) and an output signal LIM of the second comparator (7), The control logic circuit (3) is configured to: L At or above the predetermined current i LIM and the power supply voltage V received at the power supply pin SUP B ' is at or below the predetermined threshold voltage V UVTH When the power transistor (2) is turned off, The control logic circuit (3) is configured to trigger the shutoff of the power transistor (2) based on the output signal of the filter (32).

2. The integrated circuit of claim 1 , further comprising: A current sensing circuit (20) is configured to provide a current sensing signal representing the load current i passing through the power transistor (2). L The current sensing signal i CS .

3. The integrated circuit of claim 2, further comprising: A current limiting circuit (5) is coupled to the power transistor (2) and the current sensing circuit (20) and is configured to limit the load current i L The maximum current is limited to the maximum current, and the maximum current is the predetermined current i LIM .

4. An integrated circuit according to any one of claims 1 to 3, An undervoltage detection circuit is coupled to the power supply pin SUP and is configured to detect the power supply voltage V received at the power supply pin SUP. B When it drops to or below the predetermined threshold voltage V UVTH .

5. The integrated circuit according to claim 1, The filter (32) is configured to suppress pulses in the logic signal UV&LIM that are shorter than the filter time.

6. The integrated circuit according to claim 1 or 5, The filter (32) includes a counter (331) or a low-pass filter R F , C F .

7. The integrated circuit according to any one of claims 1 to 3, further comprising: The digital communication interface is configured to receive, via a digital communication link, a digital value representing one or more of the following: the predetermined current i LIM , the predetermined threshold voltage V UVTH and filter time t FILT .

8. The integrated circuit according to any one of claims 1 to 3, further comprising: The first configuration pin and the second configuration pin are configured to receive signals indicating the predetermined current i LIM and the predetermined threshold voltage V UVTH The first configuration signal and the second configuration signal.

9. The integrated circuit according to any one of claims 1 to 3, further comprising: A monitoring circuit (4) is configured to determine a temperature value indicating a temperature of a wire connected to the output pin OUT and based on the load current i L and estimating the temperature value from the current-time characteristic associated with the conductor, The monitoring circuit (4) is further configured to provide a protection signal OC indicating whether the estimated temperature value is higher than a predetermined temperature threshold, and The control logic circuit (3) is configured to trigger the shutdown of the power transistor (2) in response to the protection signal OC indicating that the estimated temperature value is higher than a predetermined temperature threshold.

10. The integrated circuit according to any one of claims 1 to 3, The control logic circuit (3) is configured to: L At or above the predetermined current i LIM and the power supply voltage V received at the power supply pin SUP B is at or below the predetermined threshold voltage V UVTH Both last for at least a predetermined period of time t FILT When the power transistor (2) is turned off, the power transistor (2) is triggered.

11. A method for switching a load, comprising: According to the input signal S IN Using a power transistor (2) to enable and disable a load current path between the power supply pin SUP and the output pin OUT; A first comparator (6) is used to detect the power supply voltage V received at the power supply pin SUP. B ' drops to or below a predetermined threshold voltage V UVTH ; A second comparator (7) is used to detect a load current i passing through the power transistor (2). L At or above a predetermined current i LIM ; filtering a logic signal UV&LIM which is a combination of an output signal UV of the first comparator (6) and an output signal LIM of the second comparator (7); When the load current i L At or above the predetermined current i LIM and the power supply voltage V received at the power supply pin SUP B ' is lower than the predetermined threshold voltage V UVTH When the power transistor (2) is turned off, Wherein the triggering of the shut-off of the power transistor is based on a filtered logic signal.

12. The method according to claim 11, When the load current i L At or above the predetermined current i LIM and the power supply voltage V received at the power supply pin SUP B ' is lower than the predetermined threshold voltage V UVTH Both last for at least a predetermined period of time t FILT When the power transistor (2) is turned off, the power transistor (2) is triggered to be turned off.

13. The method according to claim 11 or 12, further comprising: Generates a load current i through the power transistor (2) L The current sensing signal i CS .

14. The method according to claim 13, further comprising: Using the current sensing signal i CS The load current i L The maximum current is limited to the maximum current, and the maximum current is the predetermined current i LIM .

15. The method according to claim 11, in, Use a counter (331) or a low pass filter R F , C F The filter circuit completes the filtering of the logic signals UV&LIM.

16. The method according to claim 11 or 12, further comprising: receiving, via a digital communication link, a digital value representing one or more of the following: the predetermined current i LIM , the predetermined threshold voltage V UVTH and filter time t FILT .

17. The method according to claim 11 or 12, further comprising: The predetermined current i is received at the first configuration pin and the second configuration pin respectively. LIM and the predetermined threshold voltage V UVTH The first configuration signal and the second configuration signal.

18. The method according to claim 11 or 12, further comprising: Determine a temperature value, the temperature value indicating the temperature of the wire connected to the output pin OUT, and the temperature value is based on the load current i L and a current versus time characteristic associated with the conductor being estimated; generating a protection signal OC indicating whether the estimated temperature value is higher than a predetermined temperature threshold; as well as In response to the protection signal OC indicating that the estimated temperature value is higher than a predetermined temperature threshold, the power transistor (2) is triggered to be turned off.

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