Method for achieving recessed gate enhancement-mode HEMT devices using wet etching

Abstract

The present application discloses a method for realizing a recessed gate enhanced HEMT device by wet etching, which comprises: providing an epitaxial wafer for manufacturing a recessed gate enhanced HEMT device; setting a patterned etching mask on the epitaxial wafer, and exposing a selected area of ​​the surface of the epitaxial wafer from the etching mask; contacting the selected area of ​​the surface of the epitaxial wafer with a persulfate solution, and irradiating the selected area of ​​the surface of the epitaxial wafer with ultraviolet light, thereby etching a recessed structure in the barrier layer of the epitaxial wafer, and the recessed structure is used to cooperate with the gate. The present application avoids the problem of damage introduced by the dry etching process by performing low-damage wet etching on the area under the gate of the HEMT device. The process is simple and efficient, the etching is uniform, the repeatability is good, and there is no need to add a process for removing the etching product. The recessed gate threshold voltage of the obtained device is stable and the gate reliability is strong.

Description

Technical Field

[0001] The present application relates to a method for manufacturing an enhanced HEMT device, and in particular to a method for realizing a recessed gate enhanced HEMT device by wet etching. Background Art

[0002] With the rapid development of the economy, people are paying more and more attention to resource conservation, requiring higher and higher efficiency of energy utilization in the process of electric energy conversion. In order to achieve this requirement, power electronics technology is needed to realize energy conversion, and power devices prepared by semiconductor technology are used to efficiently transform and control energy, thereby reducing energy loss in the conversion process and achieving a high-efficiency conversion process.

[0003] As an important third-generation semiconductor material, nitride semiconductors have a large bandgap, high electron mobility, high breakdown electric field, and high electron saturation drift velocity. They are widely used in industries, power systems, transportation, communications, consumer electronics, and other fields. AlGaN / GaN semiconductor heterojunctions can form high concentrations (>10 13 cm -2 ) and high electron mobility (>10 3 cm 2 / V·s) of two-dimensional electron gas (2DEG). Based on this characteristic of nitride semiconductor heterojunction, high electron mobility transistor (HEMT) is prepared as a power switching device, and its operating frequency can reach 10MHz. However, HEMT devices prepared using two-dimensional electron gas are all depletion devices, and negative voltage is required to turn them off in practical applications. Such circuits are both complex and have safety risks.

[0004] To prepare an enhancement-mode HEMT device, it is necessary to deplete the two-dimensional electron gas in the channel under the gate, which can be achieved by changing the device structure at the gate. Currently, there are several methods to achieve enhancement-mode devices: ① Recessed gate structure, etching the AlGaN under the gate to weaken the polarization effect; ② F ion treatment, injecting F ions into the AlGaN barrier under the gate to deplete the two-dimensional electron gas below; ③ Cascode structure, connecting the depletion-mode AlGaN / GaN HEMT device and the enhancement-mode Si metal oxide semiconductor field effect device (MOSFET) device; ④ p-type gate structure, inserting a p-(Al)GaN layer between the gate and the AlGaN layer, and using the built-in electric field of the pn junction to deplete the two-dimensional electron gas in the channel.

[0005] Through the above solution ①, that is, etching the AlGaN layer under the gate, enhanced AlGaN / GaN HEMT can be realized. However, the traditional etching method will cause great lattice damage, which will not only reduce the device saturation current, but also turn on when a certain positive voltage is applied to the gate, resulting in gate leakage, which not only affects the forward safe working voltage, but also increases switching losses and affects conversion efficiency.

[0006] Wet etching can significantly reduce the etching damage caused by recessed gate etching, increase the saturation current when the device is turned on, and reduce gate leakage. The inventor of this case has proposed a method for realizing enhanced HEMT devices by light-assisted electrochemical etching, which mainly utilizes the chemical reaction of H2SO4 or KOH solution with AlGaN, and removes part or all of the barrier layer under the gate in the HEMT epitaxial structure (wafer) through external electrodes and light assistance, so as to deplete the two-dimensional electron gas under the gate to prepare enhanced HEMT. However, this method has the following shortcomings, for example: the external electrode of the wafer will cause a potential gradient in the entire wafer, making the current density of the entire wafer uneven, resulting in uneven etching; the etching products of H2SO4 or KOH solution will not be removed immediately, but will be removed by other solutions that can dissolve the etching products, which makes the process complicated and the cost high; the etching rate is slow, which is not conducive to mass production. Summary of the invention

[0007] The purpose of the present application is to provide a method for realizing a recessed gate enhancement type HEMT device by wet etching, so as to overcome the deficiencies in the prior art.

[0008] To achieve the above objectives, this application provides the following technical solutions:

[0009] Some embodiments of the present application provide a method for implementing a recessed gate enhancement mode HEMT device by wet etching, comprising:

[0010] An epitaxial wafer for manufacturing a recessed gate enhanced HEMT device is provided, wherein the epitaxial wafer comprises a heterojunction, wherein the heterojunction comprises a first semiconductor layer body as a channel layer and a second semiconductor layer as a barrier layer, and a two-dimensional electron gas is formed in the heterojunction;

[0011] Disposing a patterned etching mask on the second semiconductor layer, and exposing a selected area of ​​the surface of the second semiconductor layer from the etching mask;

[0012] The selected area on the surface of the second semiconductor layer is brought into contact with an etching agent, and the selected area on the surface of the second semiconductor layer is irradiated with ultraviolet light, so as to form a groove structure by etching in the selected area of ​​the second semiconductor layer, and deplete the two-dimensional electron gas under the groove structure, wherein the groove structure is used to cooperate with the gate;

[0013] Wherein, the etching reagent is a persulfate solution.

[0014] Some embodiments of the present application also provide a system for implementing a recessed gate enhanced HEMT device by wet etching, which includes a persulfate solution as an etching agent and an ultraviolet light source;

[0015] When an etching area on the surface of an epitaxial wafer for manufacturing a recessed gate enhanced HEMT device is brought into contact with an etching agent and the etching area is irradiated with ultraviolet light emitted by an ultraviolet light source, the etching agent can produce a chemical reaction with the epitaxial wafer at the etching area, so that the epitaxial wafer is etched to form a recess structure that matches the gate.

[0016] Compared with the prior art, the method for realizing a recessed gate enhanced HEMT device by wet etching proposed in the embodiment of the present application has at least the following advantages:

[0017] (1) By performing low-damage wet etching on the region under the gate of the device, the problem of damage introduced by the dry etching process is avoided;

[0018] (2) The etching process does not require external electrodes, the etching device is simple, the etching is uniform, and the repeatability is good;

[0019] (3) The selected etching reagent can directly dissolve the etching products, without adding a process step to remove the etching products;

[0020] (4) The selected etching reagent can be combined with heating to increase the etching rate, which can not only perform low-damage etching but also make the process more efficient;

[0021] (5) The fabricated device has low damage, stable groove gate threshold voltage and strong gate reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 It is a process principle diagram of realizing a recessed gate enhancement type HEMT device by wet etching in a typical implementation scheme of the present invention;

[0024] Figure 2 This is a schematic structural diagram of an epitaxial wafer for manufacturing a recessed gate enhancement mode HEMT device in Embodiment 1 of the present invention;

[0025] Figure 3 is a schematic diagram of providing a patterned metal mask on the epitaxial wafer in Embodiment 1 of the present invention;

[0026] Figure 4 is a schematic diagram of forming a dielectric layer on the surface of the epitaxial wafer in Embodiment 1 of the present invention;

[0027] Figure 5 is a schematic diagram of partially removing the dielectric layer covering the surface of the epitaxial wafer in Embodiment 1 of the present invention;

[0028] Figure 6 is a schematic diagram of manufacturing source and drain electrodes on the epitaxial wafer in Example 1 of the present invention;

[0029] Figure 7 It is a schematic structural diagram of a recessed gate enhancement type HEMT device manufactured in Example 1 of the present invention. Specific implementation plan

[0030] As mentioned above, in view of the many deficiencies in the prior art, the inventor of this case, after long-term and in-depth research and extensive practice, was able to propose the technical solution of the present invention, as detailed below.

[0031] An aspect of an embodiment of the present invention provides a method for implementing a recessed gate enhancement mode HEMT device by wet etching, comprising:

[0032] An epitaxial wafer for manufacturing a recessed gate enhanced HEMT device is provided, wherein the epitaxial wafer comprises a heterojunction, wherein the heterojunction comprises a first semiconductor layer body as a channel layer and a second semiconductor layer as a barrier layer, and a two-dimensional electron gas is formed in the heterojunction;

[0033] Disposing a patterned etching mask on the second semiconductor layer, and exposing a selected area of ​​the surface of the second semiconductor layer from the etching mask;

[0034] The selected area on the surface of the second semiconductor layer is brought into contact with an etching agent, and the selected area on the surface of the second semiconductor layer is irradiated with ultraviolet light, so as to form a groove structure by etching in the selected area of ​​the second semiconductor layer, and deplete the two-dimensional electron gas under the groove structure, wherein the groove structure is used to cooperate with the gate;

[0035] The etching reagent is a persulfate solution, in which the solute is single and the solution is easy to prepare. At the same time, the persulfate solution is acidic and has no corrosiveness to the semiconductor except in the illuminated area.

[0036] In some embodiments, the method for implementing a recessed gate enhanced HEMT device by wet etching specifically includes: immersing at least the second semiconductor layer in an etching agent.

[0037] In some embodiments, the method for implementing a recessed gate enhanced HEMT device by wet etching specifically includes: immersing the entire epitaxial wafer in an etching agent.

[0038] In some embodiments, the concentration of the persulfate solution is 0.05 mol / L-0.18 mol / L, and the pH value is 2-5.

[0039] In some embodiments, the persulfate includes sodium persulfate (Na2S2O8), ammonium persulfate ((NH4)2S2O8), and the like, but is not limited thereto.

[0040] In the above embodiments of the present invention, low-damage wet etching is performed on the gate region under the HEMT device to form a groove gate, thereby avoiding the problem of damage introduced by the dry etching process. In addition, the etching process does not require an external electrode, the etching device is simple, the etching is uniform, and the repeatability is good. At the same time, the selected etching agent can directly dissolve the etching product, and there is no need to add a process step for removing the etching product. The removal of the etching product will not cause secondary etching damage to the groove, and a low-damage groove can be obtained at one time, and the process is simple.

[0041] Taking potassium persulfate (K2S2O8) solution as an etchant as an example, the etching principle of the embodiment of the present invention is that after ultraviolet irradiation or ultraviolet irradiation and heating, the following reaction occurs in the potassium persulfate solution:

[0042] S2O8 2- →2S,

[0043] Furthermore, when the etched area on the barrier layer (the area below the gate) is irradiated with ultraviolet light, the following reaction occurs:

[0044] GaN(S)+photocarries(3h + +3e - )+3S→3SO4 2- +Ga 3+ +1 / 2N2↑

[0045] AlGaN(S)+photocarries(6h + +6e - )+6S→6SO4 2- +Ga 3+ +Al 3+ +1 / 2N2↑;

[0046] It can be seen from the above reaction that the etching product is directly dissolved in the solution, and the higher the solution temperature, the more S The faster the etching reaction, the faster the etching reaction. Therefore, the etching speed can be controlled by controlling the temperature, and the etching solution concentration can be increased to increase the etching speed. The aforementioned photocarries are photogenerated carriers.

[0047] Furthermore, after the groove structure is formed on the device using the method described in the above embodiment, the surface thereof is smooth.

[0048] In some embodiments, the wet etching method for realizing a recessed gate enhanced HEMT device further includes: before or during etching the selected area of ​​the second semiconductor layer to form the recessed structure, heating the etching agent to 50-80° C., wherein if the temperature is too high, it is not conducive to obtaining a high-quality etched surface. In this way, low-damage etching can be performed, and the etching rate can be increased, making the process more efficient.

[0049] In some embodiments, the wavelength of the ultraviolet light is 200-400 nm.

[0050] In some embodiments, the barrier layer comprises Al x Ga 1-x N, AlInN, AlInGaN or GaN, wherein 0<x≤1, but not limited thereto.

[0051] In some embodiments, the constituent material of the channel layer includes GaN or InGaN, etc., but is not limited thereto.

[0052] For example, the heterojunction may be an AlGaN / GaN heterojunction, a GaN / InGaN heterojunction, etc., and is not limited thereto.

[0053] In some embodiments, the material of the etching mask includes any one of silicon dioxide, silicon nitride, and photoresist, but is not limited thereto.

[0054] Furthermore, an etching mask can be formed by first forming a mask layer on the surface of the etching sample and then performing a patterning process, wherein the patterning method can be selected from but is not limited to using laser direct writing, electron beam lithography or ultraviolet lithography.

[0055] Furthermore, the depth of the groove structure is sufficient to deplete the two-dimensional electron gas thereunder.

[0056] Furthermore, the etching depth of the recessed gate structure depends on the aluminum component in the barrier layer and the total thickness of the barrier layer. For example, the depth of the recessed gate structure may be 10 nm-30 nm.

[0057] In some embodiments, the method for implementing a recessed gate enhanced HEMT device by wet etching further includes: after etching to form the recessed structure, covering the surface of the epitaxial wafer with an insulating dielectric layer, and then manufacturing a source, a drain, and a gate.

[0058] Furthermore, the source and drain can be made on the epitaxial wafer, and then a dielectric layer can be grown on the epitaxial wafer, and a gate can be formed on the dielectric layer in a region corresponding to the recessed gate structure, and then the dielectric layer on the source and drain can be removed to form a HEMT device.

[0059] The methods for processing and forming the source electrode, the drain electrode, the gate electrode and the dielectric layer may be well known in the industry.

[0060] The dielectric layer (gate dielectric) should have high insulation and breakdown resistance characteristics, and be able to form a low interface state with the heterojunction, such as the GaN or AlGaN semiconductor therein.

[0061] Furthermore, the material of the insulating dielectric layer may be silicon nitride, aluminum oxide, silicon oxide, etc., but is not limited thereto.

[0062] Furthermore, after the recessed gate structure is formed, the mask may be removed by a common method known in the industry.

[0063] See also Figure 1 As shown, a method for implementing a recessed gate enhanced HEMT device by wet etching in a typical implementation case of the present invention includes:

[0064] An epitaxial wafer for manufacturing a recessed gate enhanced HEMT device is provided, which includes a substrate, a buffer layer, a channel layer, a barrier layer, etc., wherein a two-dimensional electron gas (not shown in the figure) is formed in a heterojunction mainly composed of the channel layer and the barrier layer;

[0065] A patterned etching mask is disposed on the barrier layer, and a region below the gate (also defined as a selected region) of the barrier layer is exposed from the etching mask;

[0066] The epitaxial wafer is immersed in a persulfate solution (also called etching solution) as an etchant;

[0067] The ultraviolet light emitted by the ultraviolet light source is irradiated to the gate area under the barrier layer, so as to etch a groove structure in the gate area under the barrier layer (the barrier layer in this area is partially or completely removed), and the groove structure has a sufficient depth to weaken the polarization effect there, so as to deplete the two-dimensional electron gas thereunder.

[0068] The ultraviolet light is vertically irradiated on the region below the gate of the barrier layer.

[0069] The etching solution may be contained in a container, and the container may be placed on a hot plate to conveniently heat the etching solution, thereby accelerating the etching rate.

[0070] When the HEMT device of this typical embodiment is used, if V gs <V th , the high concentration of two-dimensional electron gas under the recessed gate is depleted, and the device is not conducting. gs >V th When the gate is turned on, the channel layer below the gate is inverted, accumulating a large number of freely movable electrons, and the device is turned on.

[0071] Another aspect of the embodiments of the present application also provides a system for implementing a recessed gate enhanced HEMT device by wet etching, which includes a persulfate solution as an etching agent and an ultraviolet light source;

[0072] When an etching area on the surface of an epitaxial wafer for manufacturing a recessed gate enhanced HEMT device is brought into contact with an etching agent and the etching area is irradiated with ultraviolet light emitted by an ultraviolet light source, the etching agent can produce a chemical reaction with the epitaxial wafer at the etching area, so that the epitaxial wafer is etched to form a recess structure that matches the gate.

[0073] In some embodiments, the system further comprises a heating mechanism, which is at least used to heat the etching reagent, wherein the heating mechanism can adopt various known heaters, such as a hot plate.

[0074] In some embodiments, the system further comprises a container, which is at least used to contain the etching reagent.

[0075] Furthermore, when the epitaxial wafer is etched with an etchant, the epitaxial wafer and the etching agent are both contained in the container.

[0076] Furthermore, when the epitaxial wafer is etched with an etchant, the epitaxial wafer is entirely immersed in the etching agent.

[0077] Furthermore, the container is transparent to the ultraviolet light, or the container has a window through which the ultraviolet light can pass and illuminate the etched area on the surface of the epitaxial wafer.

[0078] Another aspect of an embodiment of the present invention further provides a recessed gate enhanced HEMT device manufactured using the aforementioned method and system, which includes a heterojunction, wherein the heterojunction includes a first semiconductor layer body as a channel layer and a second semiconductor layer as a barrier layer, and a two-dimensional electron gas is formed in the heterojunction, the second semiconductor layer is formed with a recessed structure matching the gate, and a gate dielectric layer is distributed between the gate and the second semiconductor layer, and the second semiconductor layer also forms an ohmic contact with the source and the drain.

[0079] Furthermore, for the recessed gate enhanced HEMT device, since its recessed gate is low in damage, the threshold voltage is stable and the gate reliability is strong.

[0080] When the gate voltage V gs <Threshold voltage V th When V gs >V th When the gate is turned on, the channel layer below the gate is inverted, accumulating a large number of freely movable electrons, and the device is turned on.

[0081] The following will be combined with the drawings in the embodiments of the present application to describe the technical solutions in the embodiments of the present application in detail. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0082] Embodiment 1 The present embodiment provides a method for implementing a recessed gate enhancement mode HEMT device by wet etching, comprising the following steps:

[0083] (1) Providing an epitaxial wafer for manufacturing a recessed gate enhancement mode HEMT device, the structure of which is as follows: Figure 2 As shown, it includes a substrate (such as a silicon substrate, a sapphire substrate, a silicon carbide substrate or a gallium nitride substrate, etc.), a buffer layer (such as GaN, Al 0.05 Ga 0.95 N, thickness of about 4μm), GaN channel layer (thickness of about 300-500nm) and AlGaN barrier layer (thickness of about 20-30nm), the epitaxial wafer can be grown by epitaxial technology such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) or hydride vapor phase epitaxy (HVPE);

[0084] (2) If Figure 3As shown, a graphic etching mask is arranged on the barrier layer, and the gate area under the barrier layer is exposed from the etching mask. The etching mask can be prepared by methods known in the art. For example, the etching mask can be a metal mask prepared by photolithography and metal stripping technology. The specific steps of the photolithography process include pretreatment, coating, pre-baking, exposure and development. The metal mask can be made of titanium, nickel, platinum, gold and other materials. In addition, silicon dioxide grown by PECVD and other processes can also be used as a mask. The thickness of the mask can be about 50-100nm.

[0085] (3) If Figure 1 As shown, the epitaxial wafer and the metal mask are immersed in a potassium persulfate (K2S2O8) solution contained in an open container, and a hot plate is set under the container to heat the potassium persulfate solution with a pH value of 2-5 and a concentration of 0.05mol / L-0.18mol / L to 50-80°C, and at the same time, ultraviolet light with a wavelength of 200-400nm is vertically irradiated to the gate area under the barrier layer, thereby partially or completely removing the gate area under the barrier layer to form a sufficiently deep groove (groove depth of about 25-30nm) to deplete the two-dimensional electron gas under the gate. After etching is completed, the metal mask can be removed using a hydrochloric acid / nitric acid mixed solution. The surface of the device structure finally obtained in this step (including the inner wall of the groove) is smooth and flat, and the side wall of the groove is perpendicular to the surface of the epitaxial wafer.

[0086] (4) forming an insulating dielectric layer on the surface of the device obtained in step (3), such as Figure 4 As shown. The insulating dielectric layer can be formed by dielectric layer deposition techniques such as atomic layer deposition (ALD) or chemical vapor deposition. The insulating dielectric layer is made of silicon oxide, silicon nitride or aluminum nitride, and has a thickness of about 15-25 nm.

[0087] (5) Using methods known in the art, removing the source and drain regions of the insulating dielectric layer on the surface of the device obtained in step (4), obtaining Figure 5 The device structure shown in the figure can be removed by plasma etching, etc. The source and drain regions of the insulating dielectric layer can be determined by a photolithography process, and the specific steps of the photolithography process include pretreatment, photoresist, pre-baking, exposure and development.

[0088] (6) using a method known in the art (such as electron beam evaporation), depositing source and drain metals (such as Ti / Al / Ni / Au) on the source and drain regions of the device surface obtained in step (5) to form source and drain electrodes, thereby obtaining Figure 6 The device structure is shown.

[0089] (7) using a method known in the art (such as electron beam evaporation), depositing a gate metal (such as Ni / Au) on the gate region (the region where the aforementioned groove is located) on the surface of the device obtained in step (5) to form a gate, thereby obtaining Figure 7 The device structure shown, i.e., a recessed gate enhancement type HEMT device, has a large device current density, a large gate voltage swing, a small leakage current, and a high reliability.

[0090] When the HEMT device of this typical embodiment is used, if V gs <V th , the high concentration of two-dimensional electron gas under the recessed gate is depleted, and the device is not conducting. gs >V th When the gate is turned on, the channel layer below the gate is inverted, accumulating a large number of freely movable electrons, and the device is turned on.

[0091] Comparative Example 1: This comparative example 1 is substantially the same as Example 1, except that:

[0092] In step (3), an alkaline solution containing NaOH and 0.05 mol / L-0.18 mol / L potassium persulfate is used instead of the potassium persulfate solution.

[0093] Comparative Example 2: This comparative example 1 is substantially the same as Example 1, except that:

[0094] In step (3), sulfuric acid or oxalic acid solution or NaOH solution is used to replace the potassium persulfate solution.

[0095] The device surface roughness formed by etching in Comparative Example 1-Comparative Example 2 is very large, the device electron mobility is low, the on-resistance is large, and the saturation current density is small.

[0096] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including any one of..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0097] The above is only a specific implementation scheme of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A method for realizing a recessed gate enhancement mode HEMT device by wet etching, characterized in that: include: An epitaxial wafer for manufacturing a recessed gate enhanced HEMT device is provided, wherein the epitaxial wafer comprises a heterojunction, wherein the heterojunction comprises a first semiconductor layer body as a channel layer and a second semiconductor layer as a barrier layer, and a two-dimensional electron gas is formed in the heterojunction; Disposing a patterned etching mask on the second semiconductor layer, and exposing the gate-under-region on the surface of the second semiconductor layer from the etching mask; The etching mask and the epitaxial wafer are immersed in an etching agent as a whole, and ultraviolet light is vertically irradiated on the gate region of the second semiconductor layer to partially or completely remove the gate region of the second semiconductor layer, thereby etching a groove with a depth of 25-30 nm in the gate region of the second semiconductor layer, wherein the groove is used to cooperate with the gate and deplete the two-dimensional electron gas located below the groove, the etching product can be directly dissolved by the etching agent, the inner wall of the groove is smooth and flat, and the side wall of the groove is perpendicular to the surface of the epitaxial wafer; The etching reagent is a persulfate solution with a temperature of 50-80°C, a pH value of 2-5, and a concentration of 0.05 mol / L-0.18 mol / L. The wavelength of the ultraviolet light is 200-400 nm. The barrier layer is made of Al x Ga 1-x N,0<x<1.

2. The method for realizing a recessed gate enhancement mode HEMT device by wet etching according to claim 1, characterized in that: The channel layer is made of GaN or InGaN.

3. The method for realizing a recessed gate enhancement mode HEMT device by wet etching according to claim 1, characterized in that: The material of the etching mask includes any one of silicon dioxide, silicon nitride and photoresist.

4. The method for realizing a recessed gate enhancement mode HEMT device by wet etching according to claim 1, characterized in that: Also includes: After the groove structure is formed by etching, an insulating dielectric layer is covered on the surface of the epitaxial wafer, and then a source electrode, a drain electrode and a gate electrode are manufactured.

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