Memory element and method of manufacturing the same

Abstract

A memory element and a manufacturing method thereof, the memory element comprising a stacking structure, a column, a stop layer and a contact plug. The stacking structure comprises a plurality of conductor layers. The column passes through the stacking structure. The column comprises a plurality of memory cells connected in series, and the plurality of memory cells connected in series are located at a plurality of intersections of the column and the conductor layer in the column position layout pattern. The first stop layer covers the stacking structure and a portion of the top surface of the column. The contact plug passes through the first stop layer, extends into the column, and is electrically connected to the plurality of memory cells connected in series. The contact window lands on the contact plug and is electrically connected to a portion of the column channel layer through the contact plug.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices and relates to a memory element and a manufacturing method thereof. Background Art

[0002] As technology advances, the advancement of electronic components has increased the need for greater storage capacity. In order to meet the demand for high storage density, memory devices have become smaller and more integrated. Therefore, the morphology of memory devices has evolved from two-dimensional memory devices (2D memory devices) with planar gate structures to three-dimensional memory devices (3D memory devices) with vertical channel (VC) structures. However, three-dimensional memory devices with vertical channel structures still face many challenges. Summary of the invention

[0003] The invention provides a memory element which can increase the process margin and improve the reliability of the memory element.

[0004] An embodiment of the present invention provides a memory element, comprising a stacked structure, a column, a first stop layer and a contact plug. The stacked structure comprises a plurality of stacked conductor layers. The column passes through the stacked structure. The column comprises a plurality of memory cells connected in series, and the plurality of memory cells connected in series are located at a plurality of intersections of the column and the conductor layer in a column position layout pattern. The first stop layer covers the top surface of the stacked structure and a portion of the column. The contact plug passes through the first stop layer, extends into the column, and is electrically connected to the plurality of memory cells connected in series. The contact window lands on the first stop layer and the contact plug, and is electrically connected to a portion of the column through the contact plug.

[0005] The embodiment of the present invention also provides a method for manufacturing a memory element, comprising forming a stacked structure on a substrate. Forming a column in the stacked structure, wherein the column has a groove. Forming a stop material layer on the stacked structure and the column and in the groove. Removing the stop material layer on the sidewall of the groove to form a first stop layer on the stacked structure, and forming a second stop layer on the bottom surface of the groove. Forming a contact plug in the groove. Forming a dielectric layer on the first stop layer and the contact plug. Forming a contact window in the dielectric layer, wherein the contact window is electrically connected to the contact plug.

[0006] Based on the above, the embodiment of the present invention can protect the pillar by forming the first stop layer so that it will not be damaged by etching when forming the contact window opening. In addition, the contact window can not only land on the contact plug, but also on the stop layer. Therefore, the embodiment of the present invention can increase the process margin and improve the reliability of the memory element with a vertical channel structure.

[0007] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 1H FIG. 4 is a cross-sectional view of a manufacturing process of a memory device according to a first embodiment of the present invention.

[0009] Figure 2 yes Figure 1H Schematic diagram of the top view.

[0010] FIG. 3A to FIG. 3F FIG. 4 is a cross-sectional schematic diagram of a manufacturing process of a memory element according to a second embodiment of the present invention.

[0011] Figure 4 FIG. 4 is a top view schematically showing a memory element according to a second embodiment of the present invention.

[0012]

Explanation of symbols

[0013] 10: Memory components

[0014] 92, 92a: Dielectric layer

[0015] 94: Sacrificial Layer

[0016] 99: Doping area

[0017] 100, 200: base

[0018] 101, 201: stacked structure

[0019] 110, 210: first stacking structure

[0020] 112, 212: bottom dielectric layer

[0021] 116, 216: Top dielectric layer

[0022] 120, 220: Second stacking structure

[0023] 121: Insulation layer

[0024] 104, 104a, 204, 204a: Channel layer

[0025] 129, 148: Contact window

[0026] 130: Filling material layer

[0027] 131: Groove

[0028] 134, 234: Column

[0029] 136: Stop material layer

[0030] 138, 238: Contact plug

[0031] 144: Contact window opening

[0032] 150: Insulation layer

[0033] 152: Conductor layer

[0034] 234_1: First Column

[0035] 234_2: Second Pillar

[0036] 234_3: Connection

[0037] 236: Separating material layers

[0038] 237: Dielectric material layer

[0039] 238_1: First plug

[0040] 238_2: Second plug

[0041] 239: Mask pattern

[0042] 240: Insulating separator

[0043] 245: First contact window opening

[0044] 246: Second contact window opening

[0045] 247: First contact window

[0046] 248: Second contact window

[0047] C1, C2: Center line

[0048] DWL: Virtual Word Line

[0049] GSL: Ground Select Line

[0050] P1, P2'_1: Part I

[0051] P1': First part / first stop layer

[0052] P2, P2'_2: Part II

[0053] P2': Second part / second stop layer

[0054] P3: Part 3

[0055] SSL: Serial Select Line

[0056] 102, 102a, 202, 202a: charge storage layer

[0057] WL0, WL1, WL2, WL3, WL4, WL5: word lines

[0058] 101t, 102t, 104t, 129t, 130t, 138t, 142t, 148t, 201t, 242t, 247t, 248t, P1't: Top

[0059] 104s, 125s, 131s, 138s, 225s, P1's: Sidewall

[0060] 114, 122a, 122b, 122c, 122d, 122e, 122f, 122g, 214, 222a, 222b, 222c, 222d, 222e, 222f, 222g, 222h: conductor layer

[0061] 122h: Top conductor layer / conductor layer

[0062] 125, 225, 249, 250: Open

[0063] 142, 224a, 224b, 224c, 224d, 224e, 224f, 224g, 224h, 242: dielectric layer

[0064] 125b, 129b, 131b, 134b, 142b, 148b, 225b, 242b, 247b, 248b: bottom

[0065] 130a, 230a, 230b: Insulation filler DETAILED DESCRIPTION

[0066] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0067] Figures 1A to 1H FIG. 4 is a cross-sectional view of a manufacturing process of a memory device according to a first embodiment of the present invention. Figure 2 yes Figure 1H The memory element described in the following embodiments may be a single gate vertical channel (SGVC) NAND memory, but the present invention is not limited thereto.

[0068] Please refer to Figure 1A, the memory element 10 (eg, Figure 1H The manufacturing method of the present invention is as follows. First, a substrate 100 is provided. In one embodiment, the substrate 100 includes a semiconductor substrate, such as a silicon substrate. Then, a stacked structure 101 is formed on the substrate 100. The substrate 100 includes a semiconductor substrate, such as a silicon substrate. In some embodiments, a doped region (e.g., an N+ doped region, or an N-type well region) 99 may be formed in the substrate 100 according to design requirements. The stacked structure 101 includes a plurality of dielectric layers 92 and a plurality of sacrificial layers 94 stacked alternately. The material of the dielectric layer 92 includes a dielectric material, such as silicon oxide. The material of the sacrificial layer 94 is different from that of the dielectric layer 92, and has a sufficient etching selectivity with the dielectric layer 92, and there is no special limitation. In some embodiments, the material of the sacrificial layer 94 is, for example, silicon nitride. The dielectric layer 92 and the sacrificial layer 94 are, for example, formed by performing multiple chemical vapor deposition processes. Furthermore, the thickness of each dielectric layer 92 may be the same or different. For example, the thickness of the top dielectric layer 92 may be greater than the thickness of other dielectric layers. The number of sacrificial layers 94 in the stacked structure 101 may be, for example, 8 layers, 16 layers, 32 layers, 56 layers, 64 layers, or 96 layers. However, the present invention is not limited thereto, and the number of dielectric layers 92 and sacrificial layers 94 in the stacked structure 101 may depend on the design and density of the memory device.

[0069] The stacked structure 101 is patterned to form an opening 125 passing through the stacked structure 101. Figure 2 As shown, the opening 125 can be a hole. The shape of the cross section of the opening 125 can be circular, elliptical, etc. The number of the openings 125 can be multiple. Afterwards, a contact window 129 is formed in the opening 125. The contact window 129 can be doped polysilicon or doped single crystal silicon. In some embodiments, the bottom surface 129b of the contact window 129 can contact the doped region 99 in the substrate 100. The doped region 99 can be used as a source region. The contact window 129 is also called a source contact window.

[0070] Next, a charge storage layer 102 is formed on the substrate 100. In one embodiment, the charge storage layer 102 covers the top surface 101t of the stacked structure 101 and extends to cover the sidewall 125s of the opening 125. In another embodiment, before forming the channel layer 104, the charge storage layer 102 covering the top surface 101t of the stacked structure 101 has been removed. The charge storage layer 102 may be a composite layer of oxide / nitride / oxide (ONO), a composite layer of oxide / nitride / oxide / nitride / oxide (ONONO), silicon / oxide / nitride / oxide / silicon (SONOS), or other suitable composite layers. The charge storage layer 102 may be formed by chemical vapor deposition, thermal oxidation, nitridation, etching, and the like.

[0071] Afterwards, a channel layer 104 is formed on the substrate 100. The channel layer 104 may conformally cover the charge storage layer 102 and the top surface 129t of the contact window 129. In one embodiment, the channel layer 104 includes a doped semiconductor material, an undoped semiconductor material, or a combination thereof. For example, the channel layer 104 may be formed by first forming an undoped polysilicon layer through a chemical vapor deposition process or a physical vapor deposition process, and then through an annealing process. In some embodiments, the contact window 129 is single crystal silicon, the channel layer 104 is polycrystalline silicon, and the polycrystalline silicon channel layer 104 in contact with the contact window 129 is crystallized into single crystal silicon after the annealing process, and is merged with the contact window 129.

[0072] Next, a filling material layer 130 is formed on the substrate 100. The filling material layer 130 covers the channel layer 104 and fills the opening 125. The filling material layer 130 includes an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials or combinations thereof formed by chemical vapor deposition.

[0073] Afterwards, please refer to Figure 1B , a portion of the filling material layer 130 is removed by a method such as anisotropic etching, isotropic etching or a combination thereof, so as to form an insulating filler 130a in the opening 125, and a groove 131 is formed on the insulating filler 130a. A method of removing a portion of the filling material layer 130. The removal process may be a single-stage etching process, a two-stage etching process, a multi-stage etching process, a chemical mechanical polishing process or a combination thereof.

[0074] In one embodiment, a two-stage etching process is used to remove part of the filling material layer 130. The first stage etching process is a first etch-back process to remove part of the filling material layer 130 until the surface of the channel layer 104 on the top surface 101t of the stacked structure 101 is exposed. The second stage etching process is a second etch-back process to remove part of the insulating filler remaining in the opening 125 to form an insulating filler 130a with a groove 131. The etching rate of the first stage can be greater than or equal to the etching rate of the second stage. The etching selectivity of the second stage will be greater than the etching selectivity of the first stage. That is, compared with the second stage, the first stage can adopt an etching process with a lower etching selectivity between the channel layer 104 and the insulating filler 130, such as a dry etching process using hydrogen bromide (HBr) and oxygen (O2), or chlorine (Cl2) and oxygen (O2) as etching gases. Compared with the etching process in the first stage, the etching process in the second stage can adopt an etching process with high etching selectivity between the channel layer 104 and the insulating filler 130, such as a SICONI etching process. After the groove 131 is formed, the channel layer 104 and the charge storage layer 102 are etched back to expose the top surface 101t of the stacked structure 101, leaving the channel layer 104a and the charge storage layer 102a in the opening 125. The method of etching back the channel layer 104 and the charge storage layer 102 is, for example, anisotropic etching, isotropic etching or a combination thereof.

[0075] In another embodiment, the insulating filler 130, the channel layer 104, and the charge storage layer 102 on the top surface 101t of the stacked structure 101 may be removed by chemical mechanical polishing or etching back to expose the top surface 101t of the stacked structure 101. Then, an etching back process is performed to remove a portion of the insulating filler in the opening 125. Thus, the channel layer 104a, the charge storage layer 102a, and the insulating filler 130a having the groove 131 are formed.

[0076] The top surface 102t of the charge storage layer 102a, the top surface 104t of the channel layer 104a, and the top surface 101t of the stacked structure 101 have substantially equal heights. In some embodiments, the top surface 102t of the charge storage layer 102a, the top surface 104t of the channel layer 104a, and the top surface 101t of the stacked structure 101 are coplanar. In some embodiments, the top surface 102t of the charge storage layer 102a and the top surface 104t of the channel layer 104a are slightly lower than the top surface 101t of the stacked structure 101, but higher than the top surface 130t of the insulating filler 130a.

[0077] At this point, a column 134 has been formed in the stacked structure 101. The column 134 passes through the stacked structure 101 and extends along the Z direction. The bottom surface 134b of the column 134 is in physical contact with the contact window 129. The top surface of the column 134 has a groove 131. The column 134 includes a charge storage layer 102a, a channel layer 104a and an insulating filler 130a. The insulating filler 130a is the core of the column 134 and is located in the stacked structure 101. The top surface 130t of the insulating filler 130a is lower than the top surface 101t of the stacked structure 101, forming a groove 131. The bottom surface 131b of the groove 131 exposes the insulating filler 130a. The sidewall 131s of the groove 131 exposes the channel layer 104a.

[0078] The channel layer 104a is a vertical channel layer. The channel layer 104a is disposed in the stacked structure 101, located on the sidewall of the insulating filler 130a, and extends upward and protrudes from the top surface 130t of the insulating filler 130a. The channel layer 104a located on the bottom surface 130b of the insulating filler 130a can be retained, or crystallized during the tempering process and merged with the contact window 129. The charge storage layer 102a is located between the channel layer 104a and the stacked structure 101.

[0079] Afterwards, please refer to Figure 1C , a stop material layer 136 is formed on the substrate 100. The stop material layer 136 includes a first portion P1, a second portion P2, and a third portion P3. The first portion P1 covers the top surface of the stacked structure 101 and the column 134. The second portion P2 covers the insulating filler 130a located below the bottom surface 131b of the groove 131. The third portion P3 is located on the sidewall 131s of the groove 131 and covers the channel layer 104a. In this embodiment, the thicknesses of the first portion P1, the second portion P2, and the third portion P3 may be different. The thickness of the third portion P3 is less than the thickness of the second portion P2, and less than the thickness of the first portion P1. The thickness of the second portion P2 may be less than or equal to the thickness of the first portion P1. For example, the thickness of P2 is 50% to 80% of the thickness of P1; the thickness of P3 is 10% to 30% of the thickness of P1. The material of the stop material layer 136 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or a combination thereof formed by CVD. In some embodiments, the stopping material layer 136 includes a material different from that of the topmost dielectric layer 92 .

[0080] Please refer to Figure 1C and Figure 1D, an etching process, such as a dry etching process, a wet etching process or a combination thereof, is performed to partially remove the stop material layer 136 until the sidewall 131s of the groove 131 is exposed. In one embodiment, the etching process is, for example, a SICONI process. When the etching process is performed, the first portion P1, the third portion P3 and the second portion P2 of the stop material layer 136 are all etched. However, since the third portion P3 is the thinnest, the sidewall 131s of the groove 131 is exposed first. Although the first portion P1 and the second portion P2 will also be lost and their thickness will be reduced, the first portion P1' and the second portion P2' will remain. The first portion P1' (also referred to as the first stop layer P1') will still cover the stacked structure 101 and the charge storage layer 102a and the channel layer 104a of the pillar 134. The second portion P2' (also referred to as the second stop layer P2') will still cover the insulating filler 130a.

[0081] Please refer to Figure 1D , forming a contact plug 138 in the groove 131. The material of the contact plug 138 includes a semiconductor, a metal, a metal alloy or a combination thereof. The material of the contact plug 138 is, for example, doped polysilicon, tungsten, platinum or a combination thereof. The method for forming the contact plug 138 is, for example, first forming a conductive material layer to cover the first stop layer P1' and fill the groove 131. Thereafter, an etch-back or chemical mechanical polishing process is performed to remove the conductive material layer on the first stop layer P1'. The contact plug 138 passes through the first stop layer P1' and extends along the Z direction to physically contact the second stop layer P2'. In one embodiment, the top surface 138t of the contact plug 138 may be coplanar with the top surface P1't of the first stop layer P1'. In another embodiment, the top surface 138t of the contact plug 138 may be slightly lower than the top surface P1't of the first stop layer P1'. In addition, the contact plug 138 is surrounded by the first stop layer P1 ′ and the channel layer 104 a , and a sidewall 138 s of the contact plug 138 is in physical contact with the sidewall P1 ′s of the first stop layer P1 ′ and the sidewall 104 s of the channel layer 104 a .

[0082] Please refer to Figure 1D and Figure 1E , the stop material layer 136 and the stacked structure 101 are patterned to form an opening (also referred to as a channel) 118. In some embodiments, during the patterning process, a portion of the substrate 100 is also removed so that the opening 118 exposes the doped region 99 in the substrate 100. In addition, after the insulating material layer 102 is patterned, the remaining portion of the dielectric layer 92 forms a dielectric layer 92a.

[0083] Next, the sacrificial layer 94 exposed by the opening 118 is removed to form a plurality of lateral openings 120 exposing a portion of the charge storage layer 102a, the dielectric layer 92a, and the contact window 129. The method of removing the sacrificial layer 94 exposed by the opening 118 is, for example, dry etching or wet etching. The etchant used in the dry etching method is, for example, NF3, H2, HBr, O2, N2, He, or a combination thereof. The etchant used in the wet etching method is, for example, a phosphoric acid (H3PO4) solution.

[0084] Please refer to Figure 1E and 1F , a thermal oxidation process is performed to oxidize the surface of the contact window 129 exposed by the lateral opening 120 to form a contact window 129a whose sidewall is covered by the insulating layer 121. Afterwards, a conductor layer 122 is formed in the lateral opening 120. The conductor layer 122 can be formed by depositing a gate material layer in the opening 118 and the lateral opening 120, and then performing an etch-back process. The gate material layer may include a buffer material layer, a mask material layer, and a gate conductor material layer formed in sequence. The buffer material layer is formed between the mask material layer and the charge storage layer 102a and on the surface of the dielectric layer 92a. The material of the buffer material layer is, for example, a high dielectric constant material with a dielectric constant greater than 7, such as aluminum oxide (Al2O3), HfO2, La2O5, transition metal oxides, lanthanide oxides, or a combination thereof. The buffer material layer is formed by, for example, chemical vapor deposition or atomic layer deposition (ALD). The buffer material layer can be used to improve erase and programming characteristics. The material of the mask material layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The mask material layer is located between the buffer material layer and the gate conductor material layer. The mask material layer is formed by, for example, chemical vapor deposition. The material of the gate conductor material layer is, for example, polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi x ) or cobalt silicide (CoSi x ). The gate conductor material layer is formed by, for example, chemical vapor deposition.

[0085] The conductor layer 122 includes conductor layers 122a to 122h. The conductor layer 122a is electrically insulated from the contact window 129a by the insulating layer 121. In some embodiments, the conductor layer 122a may be a ground select line (GSL). The topmost gate layer 122h may be a string select line SSL. The gate layer 122g may be a dummy word line DWL. The gate layers 122f, 122e, 122d, 122c, 122b may be word lines WL0, WL1, WL2, WL3, WL4. The thickness of the serial select line SSL may be equal to or greater than the thickness of the word lines WL0, WL1, WL2, WL3, WL4. The dummy word line DWL may be disposed below the serial select line SSL and above the topmost word line, or below the bottommost word line, or a combination thereof. The dummy word line DWL may be one layer, two layers, or multiple layers. Although Figure 1F Only five word lines WL0, WL1, WL2, WL3, and WL4 are shown, but the present invention is not limited thereto. In addition, the column 134 includes a plurality of serially connected memory cells, which are located at a plurality of intersections between the column 134 and a plurality of conductive layers 122f, 122e, 122d, 122c, and 122b of the stacked structure 101 in the column 134 position layout pattern.

[0086] Please refer to Figure 1E and 1F , an insulating layer 150 is formed on the sidewall of the opening 118. The material of the insulating layer 150 is, for example, silicon oxide. The insulating layer 150 is formed by, for example, chemical vapor deposition or atomic layer deposition (ALD) to deposit an insulating material layer. Next, an anisotropic etching process is performed to remove the insulating material layer at the bottom of the opening 118.

[0087] Next, a conductor layer 152 is filled in the opening 118 to electrically connect to the doped region 99 in the substrate 100. The conductor layer 152 may include a mask layer and a metal layer. The material of the mask layer may be, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof. The mask layer may be formed by, for example, chemical vapor deposition. The material of the metal layer may be, for example, tungsten (W), polysilicon, cobalt, tungsten silicide (WSi x ) or cobalt silicide (CoSi x The method of forming the metal layer is, for example, chemical vapor deposition. In some embodiments, the conductor layer 152 can be used as a common source line.

[0088] Afterwards, please refer to Figure 1GA dielectric layer 142 is formed on the first stop layer P1' and the contact plug 138. The material of the dielectric layer 142 is different from that of the first stop layer P1'. The material of the dielectric layer 142 includes, for example, silicon oxide, silicon nitride, silicon oxynitride or a combination thereof formed by chemical vapor deposition.

[0089] Next, please refer to Figure 1G and Figure 2 , photolithography and etching processes are performed to form a contact window opening 144 in the dielectric layer 142. The contact window opening 144 exposes the first stop layer P1' and the contact plug 138. Since the material of the first stop layer P1' is different from that of the dielectric layer 142, the first stop layer P1' can be used as an etching stop layer during the etching process. Therefore, even if misalignment occurs and the formed contact window is offset (as shown by the dotted line), the first stop layer P1' can still protect the charge storage layer 102a and the channel layer 104a from being damaged by etching, thereby increasing the process margin. Furthermore, since the first stop layer P1' can be used as an etching stop layer during the etching process, even if the size of the contact window opening 144 to be formed is large, the charge storage layer 102a and the channel layer 104a will not be damaged by the etchant during the etching process of forming the contact window opening 144. In some embodiments, the projected area of ​​the contact window opening 144 projected on the first stop layer P1 ′ is greater than or equal to the projected area of ​​the pillar 134 projected on the first stop layer P1 ′.

[0090] Please refer to Figure 1G and Figure 1H , a contact window 148 is formed in the contact window opening 144 of the dielectric layer 142. The material of the contact window 148 includes a semiconductor, a metal, a metal alloy or a combination thereof. The material of the contact window 148 is, for example, doped polysilicon, tungsten, platinum or a combination thereof. The method for forming the contact window 148 is, for example, to first form a conductive material layer to cover the dielectric layer 142 and fill the contact window opening 144. Thereafter, an etch-back or chemical mechanical polishing process is performed to remove the conductive material layer on the dielectric layer 142.

[0091] The top surface 148t of the contact window 148 may be coplanar with the top surface 142t of the dielectric layer 142, or slightly lower than the top surface 142t of the dielectric layer 142. The bottom surface 148b of the contact window 148 may be coplanar with the bottom surface 142b of the dielectric layer 142. In addition, the bottom surface 148b of the contact window 148 is in physical contact with the contact plug 138. The contact window 148 is physically and electrically connected to the channel layer 104a through the contact plug 138. In one embodiment, the contact window 148 may serve as a drain contact window; and the contact window 129a may serve as a source contact window. The channel layer 104a, at a portion close to the top surface of the stacked structure 101, is in physical contact with the sidewall 138s of the contact plug 138, and is electrically connected to the drain through the contact plug 138. The channel layer 104 a is in physical contact with the contact window 129 at a portion close to the bottom surface of the stacked structure 101 , and is electrically connected to the doped region (source region) 99 in the substrate 100 through the contact window 129 a .

[0092] In the present embodiment, the area where the contact window 148 can land is not limited to the contact plug 138. The contact window 148 can land not only on the contact plug 138, but also on the first stop layer P1'. The bottom surface 148b of the contact window 148 is not only in physical contact with the contact plug 138, but also in physical contact with the first stop layer P1'. In the Z direction (the normal direction of the surface of the substrate 100), the contact window 148 is separated from the charge storage layer 102a of the column 134 and from the channel layer 104a by the first stop layer P1'. In some embodiments, the area of ​​the contact window 148 projected on the first stop layer P1' can be equal to or greater than the area of ​​the column 134 projected on the first stop layer P1'. When the photolithography process for forming the contact window opening 144 is fully aligned, the center line C2 of the contact window 148 coincides with the center line C1 of the column 134. When the photolithography process for forming the contact window opening 144 is misaligned (such as Figure 1H The center line C2 of the contact window 148 will be offset.

[0093] The vertical channel memory described above is based on a bottom source structure, however, the embodiments of the present invention are not limited thereto. The present invention can be used in various vertical channel memories. The vertical channel memory with a hemi-cylindrical structure is used as an example for description.

[0094] FIG. 3A to FIG. 3F FIG. 4 is a cross-sectional schematic diagram of a manufacturing process of a memory element according to a second embodiment of the present invention. Figure 41 is a top view of a memory element according to a second embodiment of the present invention. The same or similar reference numerals in the second embodiment and the first embodiment represent the same or similar elements, and will not be described in detail in the following paragraphs.

[0095] Please refer to Figure 3A , a stacking structure 201 is formed on a substrate 200. The stacking structure 201 includes a first stacking structure 210 and a second stacking structure 220. The first stacking structure 210 includes a bottom dielectric layer 212, a conductor layer 214, and a top dielectric layer 216 stacked along the Z direction. The second stacking structure 220 includes a plurality of conductor layers 222a, 222b, 222c, 222d, 222e, 222f, 222g, 222h and a plurality of dielectric layers 224a, 224b, 224c, 224d, 224e, 224f, 224g, 224h alternately stacked along the Z direction. In other embodiments, the number of conductor layers and dielectric layers in the stacking structure 201 can be 8 layers, 16 layers, 32 layers, 56 layers, 64 layers, or 96 layers, respectively.

[0096] In one embodiment, the material of the conductor layer 214, the conductor layers 222a, 222b, 222c, 222d, 222e, 222f, 222g, 222h include doped semiconductor materials (e.g., silicon, germanium, or a combination thereof), metal materials (e.g., tungsten, platinum, or a combination thereof), and conductive compounds (e.g., titanium nitride, tantalum nitride, silicon carbide, or a combination thereof). In one embodiment, the material of the bottom dielectric layer 212, the top dielectric layer 216, the dielectric layers 224a, 224b, 224c, 224d, 224e, 224f, 224g, 224h include silicon oxide, silicon nitride, silicon oxynitride, a suitable dielectric material, or a combination thereof. In some embodiments, the material of the dielectric layers 224a, 224b, 224c, 224d, 224e, 224f, 224g, 224h may be the same (e.g., all silicon oxide). In alternative embodiments, the materials of the dielectric layers 224a, 224b, 224c, 224d, 224e, 224f, 224g, and 224h may be different from each other. For example, the materials of the dielectric layers 224a, 224b, 224c, 224d, 224e, 224f, and 224g may be silicon oxide; and the material of the top dielectric layer 224h may be silicon nitride. When the top dielectric layer 224h is a silicon nitride layer, it may be used to provide tensile stress; or it may be used as a substrate for subsequently forming a high aspect ratio opening 225 (such as Figure 3B ) to prevent the entire stacked structure 201 from bending.

[0097] In some embodiments, the conductor layer 214 can serve as an inversion gate control gate. The topmost conductor layer 222h can be a string select line SSL. The conductor layer 222g can be a dummy word line DWL. The conductor layers 222f, 222e, 222d, 222c, 222b, 222a can be word lines WL0, WL1, WL2, WL3, WL4, WL5. The thickness of the string select line SSL can be equal to or greater than the thickness of the word lines WL0, WL1, WL2, WL3, WL4, WL5. The dummy word line DWL can be disposed below the string select line SSL and above the topmost word line, or below the bottommost word line, or a combination thereof. The dummy word line DWL can be one layer, two layers, or multiple layers. Although Figure 3A Only six word lines WL0 , WL1 , WL2 , WL3 , WL4 , and WL5 are shown, but the present invention is not limited thereto.

[0098] Afterwards, an opening 225 is formed that penetrates the second stacked structure 220 and extends to a portion of the first stacked structure 210. The opening 225 extends into the conductor layer 214 of the first stacked structure 210. Part of the sidewall 225s and the bottom surface 225b of the opening 225 expose the conductor layer 214 of the first stacked structure 210. The opening 225 can be a hole. The cross-sectional shape of the opening 225 can be circular, elliptical, etc. The number of the openings 225 can be multiple.

[0099] Please refer to Figure 3B , a charge storage layer 202 and a channel layer 204 are formed in the opening 225 . The charge storage layer 202 and the channel layer 204 cover the top surface 201 t of the stack structure 201 and the sidewalls 225 s and the bottom surface 225 b of the opening 225 .

[0100] Thereafter, an insulating filler 230a is formed in the opening 225. When the insulating filler 230a is formed, the charge storage layer 202 and the channel layer 204 still cover the sidewalls 225s and the bottom surface 225b of the opening 225. In other words, the conductor layer 214 and the channel layer 204 of the first stacked structure 210 are not in physical contact, but are separated by the charge storage layer 202.

[0101] Next, please refer to Figure 3C , the charge storage layer 202a and the channel layer 204a on the stack structure 201 are removed, leaving the charge storage layer 202a and the channel layer 204a in the opening 225. Then, a first stop layer P1', a second stop layer P2' and a contact plug 238 are formed.

[0102] Afterwards, please refer to Figure 3C and Figure 3D , a mask pattern 239 is formed on the first stop layer P1' and the contact plug 238. The mask pattern 239 has an opening 249 to expose the contact plug 238. In some embodiments, the opening 249 can simultaneously expose a plurality of contact plugs 238 in the same column or row and the first stop layer P1' (not shown) between two adjacent contact plugs 238. Thereafter, an etching process, such as an anisotropic etching process, is performed to etch the contact plug 238 exposed by the opening 249 and the second stop layer P2' and the insulating filler 230a to form an opening 250. Thereafter, the mask pattern 239 is removed.

[0103] Afterwards, please refer to Figure 3D The opening 250 divides the contact plug 238 into a first plug 238_1 and a second plug 238_2 separated from each other, and divides the second stop layer P2' into a first portion P2'_1 and a second portion P2'_2 separated from each other. In addition, the opening 250 also makes the cross section of the insulating filler 230b have a cup-shaped structure or a U-shaped structure. In other words, the opening 250 divides the column 234 into a first column 234_1, a second column 234_2 and a connecting portion 234_3. The first column 234_1 is located at a first side of the opening 250; the second column 234_2 is located at a second side of the opening 250; and the connecting portion 234_3 is located at the bottom of the opening 250, connecting the first column 234_1 and the second column 234_2.

[0104] Please refer to Figure 3E , a separation material layer 236 is formed on the substrate 200 and in the opening 250. Thereafter, a dielectric material layer 237 is formed on the substrate 200. The separation material layer 236 in the opening 250 is referred to as an insulating spacer 240, or a slit. The separation material layer 236 and the dielectric material layer 237 on the first stop layer P1' may be collectively referred to as a dielectric layer 242. Before forming the dielectric material layer 237, the separation material layer 236 may be selectively etched back or planarized. The separation material layer 236 includes an insulating material, and the material of the separation material layer 236 may be the same as or different from the insulating filler 230b. The dielectric material layer 237 includes an insulating material, which may be the same as or different from the separation material layer 236.

[0105] Afterwards, photolithography and etching processes are performed to form a first contact window opening 245 and a second contact window opening 246 in the dielectric layer 242. Similarly, during the etching process of forming the first contact window opening 245 and the second contact window opening 246, the first stop layer P1' can protect the underlying charge storage layer 202a and the channel layer 204a from being damaged by etching.

[0106] Thereafter, a first contact window 247 and a second contact window 248 are formed in the first contact window opening 245 and the second contact window opening 246, respectively. The materials and forming methods of the first contact window 247 and the second contact window 248 are similar to the materials and forming methods of the contact window 148 described above, and are not described in detail here. The top surface 247t of the first contact window 247 and the top surface 248t of the second contact window 248 can be coplanar with the top surface 242t of the dielectric layer 242, or slightly lower than the top surface 242t of the dielectric layer 242. The bottom surface 247b of the first contact window 247 and the bottom surface 248b of the second contact window 248 can be coplanar with the bottom surface 242b of the dielectric layer 242. The first contact window 247 and the second contact window 248 are separated by the dielectric layer 242.

[0107] Please refer to Figure 3F In this embodiment, the first contact window 247 can be used as a source contact window; the second contact window 248 can be used as a drain contact window. The bottom surface 247b of the first contact window 247 is in physical and electrical contact with the first plug 238_1 located on the first side of the insulating spacer 240. The sidewall of the first plug 238_1 is in physical and electrical contact with the channel layer 204a located on the first side of the insulating spacer 240. The bottom surface 248b of the second contact window 248 is in physical and electrical contact with the second plug 238_2 located on the second side of the insulating spacer 240. The sidewall of the second plug 238_2 is in physical and electrical contact with the channel layer 204a located on the second side of the insulating spacer 240. In other words, the first contact window 247 is in physical and electrical contact with the channel layer 204a located on the first side of the insulating spacer 240 through the first plug 238_1. The second contact window 248 is in physical and electrical contact with the channel layer 204 a located on the second side of the insulating spacer 240 through the second plug 238_2 .

[0108] Please refer to Figure 3F and Figure 4 In some embodiments, the first contact window 247 and the second contact window 248 may only land on the first plug 238_1 and the second plug 238_2 (eg, Figure 4 In another embodiment, the first contact window 247 and the second contact window 248 may not only land on the first plug 238_1 and the second plug 238_2, but may also land on the first stop layer P1' (as shown in FIG. Figure 3F). In other words, the bottom surface 247b of the first contact window 247 and the bottom surface 248b of the second contact window 248 are not only in physical contact with the first plug 238_1 and the second plug 238_2, but also in physical contact with the first stop layer P1'. In the Z direction (the normal direction of the surface of the substrate 200), the first contact window 247 is separated from the charge storage layer 202a and the channel layer 204a of the first pillar 234_1 by the first stop layer P1'; the second contact window 248 is separated from the charge storage layer 202a and the channel layer 204a of the second pillar 234_2 by the first stop layer P1'.

[0109] In summary, after forming the charge storage layer and the channel layer in the opening of the stacked structure and before forming the contact plug, the embodiment of the present invention first forms a stop layer on the stacked structure and the charge storage layer and the channel layer. Since the stop layer can protect the charge storage layer and the channel layer from being damaged by etching, the area where the contact window formed subsequently can land is not limited to the contact plug, but can also land on the stop layer. Therefore, the embodiment of the present invention can increase the process margin and improve the reliability of the memory element with a vertical channel structure.

[0110] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any technician with common knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be based on the scope defined by the claims.

[0111] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory element, characterized in that: include: A stacked structure including a plurality of conductor layers; a column passing through the stacked structure, wherein the column comprises a plurality of memory cells connected in series, the plurality of memory cells connected in series being located at a plurality of intersections of the column and the conductor layer in a column position layout pattern; a first stop layer, covering the stacked structure and a portion of the top surface of the column; a contact plug passing through the first stop layer and extending into the pillar, wherein the contact plug is electrically connected to the plurality of memory cells connected in series; as well as A contact window landed on the contact plug or the first stop layer and electrically connected to a portion of the pillar through the contact plug; Wherein, a top surface of the contact plug is coplanar with a top surface of the first stop layer. 2 . The memory element according to claim 1 , wherein the contact window is further landed on the first stop layer.

3. The memory element of claim 1 , wherein the pillar further comprises: an insulating filler, passing through the stack structure and located below the contact plug; A channel layer surrounding the sidewalls of the contact plug and the sidewalls of the insulating filler; as well as A charge storage layer is located between the channel layer and the stack structure, wherein the plurality of serially connected memory cells are located at a plurality of intersections of the channel layer, the charge storage layer and the conductor layer in the pillar position layout pattern. 4 . The memory device according to claim 3 , wherein the first stop layer covers the channel layer and the charge storage layer. 5 . The memory element according to claim 3 , wherein the pillar further comprises a second stop layer disposed between the contact plug, the insulating filler, and the channel layer. 6 . The memory device according to claim 5 , further comprising an insulating spacer passing through the contact plug and the second stop layer and extending into the insulating filling, wherein the contact plug is divided into a first plug and a second plug.

7. The memory element according to claim 6, wherein the contact window comprises: a first contact window, contacting the first plug; as well as The second contact window contacts the second plug.

8. A method for manufacturing a memory element, characterized in that: include: forming a stacked structure on a substrate; forming a column in the stacked structure, wherein the column has a groove; forming a stop material layer on the stacked structure and the pillar and in the groove; removing the stop material layer on the sidewall of the groove to form a first stop layer on the stacked structure, and forming a second stop layer on the bottom surface of the groove; forming a contact plug in the groove, wherein a top surface of the contact plug is coplanar with a top surface of the first stop layer; forming a dielectric layer on the first stop layer and the contact plug; as well as A contact window is formed in the dielectric layer, wherein the contact window is electrically connected to the contact plug and the contact window lands on the contact plug or on the first stop layer.

9. The method for manufacturing a memory device according to claim 8, wherein the stop material layer comprises: A first part, located on the top surface of the stacked structure; A second portion, located on the bottom surface of the groove; as well as The third part is located on the side wall of the groove, The thickness of the first portion is greater than the thickness of the second portion, and the thickness of the second portion is greater than the thickness of the third portion.

10. The method for manufacturing a memory element according to claim 8, further comprising: Before forming the contact window in the dielectric layer, forming an opening in the contact plug, the second stop layer and the pillar, wherein the contact plug is separated into a first plug and a second plug; forming an insulating partition in the opening; as well as Forming the contact window in the dielectric layer comprises: forming a first contact window in the dielectric layer, wherein the first contact window is electrically connected to the first plug; as well as A second contact window is formed in the dielectric layer, wherein the second contact window is electrically connected to the second plug.

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