Package structure and method of manufacturing the same

Abstract

A package structure and a method of fabricating the same are provided. The method includes forming a conductive structure over a carrier substrate. The conductive structure has a lower portion and an upper portion, and the upper portion is wider than the lower portion. The method also includes disposing a semiconductor chip over the carrier substrate. The method also includes forming a protective layer to surround the conductive structure and the semiconductor chip. In addition, the method includes forming a conductive bump over the conductive structure. The lower portion of the conductive structure is between the conductive bump and the upper portion of the conductive structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to a semiconductor technology, and more particularly, to a package structure and a method of fabricating the same. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Increasing semiconductor manufacturing processes have resulted in increasingly smaller feature sizes, which has led to a trend of higher integration, higher speed, and higher performance of very-large-scale integration (VLSI) and ultra-large-scale integration (ULSI) circuits. In the course of IC evolution, the feature size of memory devices has been scaled down by half with each generation of devices being designed and manufactured.

[0003] Chip packaging not only provides protection from environmental contaminants for semiconductor devices, but also provides connection interfaces for semiconductor devices packaged therein. Smaller package structures using less area or lower height have been developed for packaging semiconductor devices.

[0004] New packaging technologies have been developed to further increase the density and functionality of semiconductor chips. These relatively new semiconductor chip packaging technologies face challenges in manufacturing. SUMMARY

[0005] A method of fabricating a package structure includes forming a conductive structure on a carrier substrate. The conductive structure has a lower portion and an upper portion, and the upper portion is wider than the lower portion. The method also includes disposing a semiconductor chip on the carrier substrate. The method further includes forming a protective layer around the conductive structure and the semiconductor chip. In addition, the method includes forming a conductive bump on the conductive structure. The lower portion of the conductive structure is between the conductive bump and the upper portion of the conductive structure.

[0006] A method of fabricating a package structure includes forming a conductive structure, and a lower portion of the conductive structure narrows in a direction toward a bottom of the conductive structure. The method also includes disposing a semiconductor chip next to the conductive structure. The method further includes forming a protective layer around the conductive structure and the semiconductor chip. In addition, the method includes forming a conductive bump on the bottom of the conductive structure.

[0007] A package structure includes a conductive structure and a semiconductor chip laterally spaced apart from each other. The package structure also includes a protective layer around the conductive structure and the semiconductor chip. The package structure further includes a conductive bump electrically connected to the conductive structure. The conductive structure has a first portion and a second portion, the first portion is between the conductive bump and the second portion, and the second portion is wider than the first portion. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figures 1A-1MCross-sectional schematic views showing various process stages of fabricating a package structure according to some embodiments.

[0009] Figure 2 Cross-sectional schematic views showing a partial package structure according to some embodiments.

[0010] Figure 3 Cross-sectional schematic views showing a process stage of fabricating a package structure according to some embodiments.

[0011] Figure 4 Cross-sectional schematic views showing a partial package structure according to some embodiments.

[0012] Wherein the reference numerals are explained as follows:

[0013] 100: carrier substrate

[0014] 102: adhesive layer

[0015] 104: seed layer

[0016] 106: photosensitive layer

[0017] 108: opening

[0018] 110: footing structure

[0019] 112: plasma operation

[0020] 114, 116: conductive structure

[0021] 118A, 118B, 140A, 140B: semiconductor chip

[0022] 120: semiconductor substrate

[0023] 122: internal connection structure

[0024] 124: passivation cap

[0025] 126: conductive pad

[0026] 128, 142: protective layer

[0027] 130: redistribution structure

[0028] 132, 134: conductive bump

[0029] 136: package

[0030] 138: redistribution substrate

[0031] 144: underfill element

[0032] 302: sidewall surface

[0033] P1: first portion

[0034] P2: second portion

[0035] S1, S2: symbolic tangent

[0036] W1, W2, W3: width

[0037] θ, θ': angle DETAILED DESCRIPTION

[0038] The following detailed description is presented to enable any person skilled in the art to make and use the application. Descriptions of specific embodiments are included to provide a sufficient understanding of the application. It will be apparent to one skilled in the art, however, that the application can be practiced without the specific details. The following detailed description is not intended to limit the scope of the application, but to describe the most typical embodiments. In some embodiments, well-known structures, materials, and / or processes have not been described in detail in order to avoid obscuring aspects of the application. In the following description, numerous specific details are discussed to provide a thorough understanding of the application. However, one skilled in the relevant art will recognize that the application can be practiced without one or more of the specific details. In other instances, well-known structures have not been described in order to avoid

[0039] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of describing one element or feature to

[0040] One skilled in the art will appreciate that the term "substantially" is used in the specification to refer to the relative terms "substantially flat" or "substantially coplanar" and the like. In some embodiments, the adjective substantially can be removed. Where applicable, the term "substantially" can also include embodiments having "entirely", "completely", "all", and the like. Where applicable, the term "substantially" can also refer to 90% or more, such as 95% or more, and especially 99% or more, including 100%. Moreover, terms such as "substantially parallel" or "substantially perpendicular" are to be interpreted as not precluding minor deviations from the specified arrangement, and can include deviations of, for example, up to 10°. The term "substantially" does not preclude "completely". For example, a composition that is "substantially free" of Y can be completely free of Y.

[0041] The use of the term "about" in connection with a particular distance or dimension means that deviations of up to 10% are not excluded, and can include deviations of up to 10%. The term "about" in relation to a numerical value x can mean x ± 5 or 10%.

[0042] The following describes some embodiments of the present disclosure. Additional operations can be provided before, during, and / or after these described step phases in these embodiments. For different embodiments, some of the described steps phases can be replaced or eliminated. Additional features can be added to the semiconductor device structure. For different embodiments, some of the described functionality can be replaced or eliminated. Although some embodiments are discussed with operations performed in a particular order, these operations can be performed in another logical order.

[0043] Embodiments of the present disclosure relate to three-dimensional (3D) packaging or 3D-IC devices. Other features and processes are also included. For example, test structures can be included to facilitate verification testing of the 3D packaging or 3D-IC devices. The test structures can include test pads formed in a redistribution layer or on a substrate, for example, that allow for testing of the 3D packaging or 3D-IC devices, use of probes and / or probe cards, etc. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with testing methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0044] Figures 1A-1M Cross-sectional schematic diagrams of various process phases of fabricating a package structure according to some embodiments are shown. As shown in Figure 1A A carrier substrate 100 is provided or received. In some embodiments, the carrier substrate 100 serves as a temporary support substrate that will be removed later. The carrier substrate 100 can include or be formed of a semiconductor material, a ceramic material, a polymer material, a metal material, one or more other suitable materials, or a combination thereof. In some embodiments, the carrier substrate 100 is a glass substrate, such as a glass wafer. In some other embodiments, the carrier substrate 100 is a semiconductor substrate, such as a silicon wafer.

[0045] Thereafter, according to some embodiments, as shown in Figure 1AAs shown, an adhesive layer 102 is formed or attached to a support substrate 100. The adhesive layer 102 may include or be formed of an adhesive, a laminating material, one or more other suitable materials, or a combination thereof. In some embodiments, the adhesive layer 102 is sensitive to energy beam irradiation. In some embodiments, the adhesive layer 102 may be a release layer formed of a light-to-heat conversion (LTHC) material. For example, a laser beam and / or ultraviolet (UV) light can be used to irradiate the adhesive layer 102. After irradiation, the adhesive layer 102 can be easily peeled off from the support substrate 100. In some other embodiments, the adhesive layer 102 is heat-sensitive. Thermal processing can be used to peel off the adhesive layer 102.

[0046] Subsequently, according to some embodiments, such as Figure 1A As shown, a seed layer 104 is deposited on the adhesive layer 102. The seed layer 104 may include or be formed of a metallic material. The seed layer 104 may include or be formed of Ti, Ti alloys, Cu, Cu alloys, one or more other suitable materials, or combinations thereof. Titanium alloys or copper alloys may include silver, chromium, nickel, tin, gold, tungsten, one or more other suitable elements, or combinations thereof. In some embodiments, the seed layer 104 is a single layer. In some other embodiments, the seed layer 104 includes multiple sublayers. The seed layer 104 may be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), spin coating, atomic layer deposition (ALD), one or more other suitable processes or combinations thereof.

[0047] like Figure 1B As shown, according to some embodiments, a photosensitive layer 106 is formed on a seed layer 104. The photosensitive layer 106 has a plurality of openings 108 exposing portions of the seed layer 104. The openings 108 of the photosensitive layer 106 define locations for forming conductive structures (e.g., via electrodes). In some embodiments, the photosensitive layer 106 comprises or is formed of a photoresist material. The openings 108 of the photosensitive layer 106 can be formed using a lithography process that includes exposure and development operations.

[0048] In some embodiments, the photosensitive layer 106 has a foot structure 110 near the bottom of the opening 108, such as Figure 1BAs shown. Each opening 108 has a lower portion that tapers gradually in the direction toward the seed layer 104. In some embodiments, the lower portion of each opening 108 is narrowed and tapers gradually in the direction toward the seed layer 104. Photoresist residue remains near the unexposed portion of the lower portion, forming a foot structure 110. The foot structure 110 may have a sloping surface. In some other embodiments, the foot structure 110 has a curved surface. Residue of the photosensitive layer 106 remains near the unexposed area of ​​the lower portion, resulting in a foot effect or other profile anomalies. The foot structure 110 may be caused by the loss of acid (or other complexes) in the exposed area after exposure and before development. Each foot structure 110 may extend outward from the corresponding sidewall of the photosensitive layer 106 by a distance ranging from approximately 0.1 μm to 20 μm.

[0049] like Figure 1C As shown, according to some embodiments, a plasma operation 112 is performed to clean and / or modify the surface of the photosensitive layer 106. Due to the plasma operation 112, the sidewalls of the photosensitive layer 106 used to define the opening 108 can be modified to be more hydrophilic, which facilitates the formation of a conductive structure within the opening 108 in subsequent electroplating processes. Because the surface of the photosensitive layer 106 becomes more hydrophilic, the electroplating solution can more easily enter the opening 108. The reactive gas used to generate the plasma in the plasma operation 112 may include CF4, O2, N2, one or more other suitable gases, or combinations thereof.

[0050] However, the embodiments of this disclosure are not limited thereto. Many variations and / or modifications can be made to the embodiments of this disclosure. In some other embodiments, plasma operation 112 is not performed.

[0051] like Figure 1D As shown, according to some embodiments, a conductive structure 114 is formed within the opening 108. The conductive structure 114 may include or be formed of copper, cobalt, tin, titanium, gold, one or more other suitable materials, or combinations thereof. Electroplating, electroless plating, one or more other suitable processes, or combinations thereof, can be used to form the conductive structure 114. A conductive material is plated onto the exposed portion of the seed layer 104 to form the conductive structure 114.

[0052] In some embodiments, unlike some other conventional processes for forming patterned photoresist layers, in forming Figure 1C The opening shown is after and in the formation Figure 1D The conductive structure shown is not subjected to a heat-baking process before formation. Figure 1C The opening shown is after and in the formation Figure 1D The conductive structure 114 shown is not previously subjected to a heat-baking process. In some embodiments, during... Figure 1C and Figure 1DDuring the process shown, the workpiece can be maintained at a constant operating temperature, such as at room temperature. The constant operating temperature can be in the range of about 15 degrees Celsius to about 30 degrees Celsius. Since no heat baking operation is performed, the shape and cross-sectional profile of the opening 108 can be substantially maintained during the formation of the conductive structure 114. The base structure 110 of the photosensitive layer 106 will also not be damaged by any heat baking operation.

[0053] In some embodiments, the upper portion of the opening 108 has substantially vertical sidewalls, such as... Figure 1C and Figure 1D As shown. Therefore, the upper portion of the conductive structure 114 also has substantially vertical sidewalls. In some embodiments, the lower portion of the opening 108 gradually narrows due to the foot structure 110 of the photosensitive layer 106. Therefore, the lower portion of the conductive structure 114 also has a cross-sectional profile corresponding to the foot structure 110, as shown. Figure 1C and Figure 1D As shown.

[0054] like Figure 1E As shown, according to some embodiments, the photosensitive layer 106 is removed to expose the seed layer 104 and the sidewalls of the conductive structure 104. The photosensitive layer 106 can be removed using a stripping operation and / or an ashing operation.

[0055] Subsequently, according to some embodiments, the portion of the seed layer 104 not covering the conductive structure 114 is removed to expose the adhesive layer 102. Thus, according to some embodiments, the remaining portion of the seed layer 104 and the conductive structure 114 are integrated to form the conductive structure 116, such as... Figure 1F As shown. The seed layer 104 can be partially removed using an etching process (e.g., a wet etching process). Surface portions of the conductive structure 114 can also be etched during the etching process. In some embodiments, the etching process is a wet etching process. The remaining portion of the seed layer 104 may substantially follow the contour of the conductive structure 116 located above it. In some other embodiments, the etching process is a dry etching process. The sidewalls of the remaining portion of the seed layer 104 may be substantially vertical.

[0056] Each conductive structure 116 has an upper part and a lower part, such as Figure 1F As shown. In some embodiments, the upper portion is wider than the lower portion. In some embodiments, the lower portion of the conductive structure 116 gradually tapers in the direction toward the lower portion of the conductive structure 116. In some embodiments, the lower portion of the conductive structure 116 tapers in the direction toward the lower portion of the conductive structure 116. In some embodiments, the lower portion of the conductive structure 116 gradually tapers in the direction toward the lower portion of the conductive structure 116.

[0057] like Figure 1GAs shown, semiconductor chips 118A and 118B are disposed on adhesive layer 102, according to some embodiments. In some embodiments, semiconductor chips 118A or 118B comprise a system-on-chip (SoC) chip that includes multiple functions. In some embodiments, the backside of semiconductor chips 118A and 118B face adhesive layer 102, while the frontside of semiconductor chips 118A and 118B face upward. An adhesive layer (not shown) can be used to secure semiconductor chips 118A and 118B on adhesive layer 102. The adhesive layer can comprise a die attach film (DAF), glue, or other suitable film. Pick-and-place operations can be used to dispose semiconductor chips 118A and 118B.

[0058] Each of semiconductor chips 118A and 118B can include a semiconductor substrate 120, an interconnect structure 122, conductive pads 126 at the frontside of the semiconductor chip, and a passivation layer 124 surrounding conductive pads 126. In some embodiments, conductive pads 126 are conductive pillars, such as copper pillars. In some embodiments, various device elements are formed within and / or on semiconductor substrate 120. Examples of various device elements include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), etc.), diodes, or other suitable elements.

[0059] Device elements are interconnected through conductive features formed within interconnect structure 122 to form an integrated circuit device. Interconnect structure 122 can include a plurality of dielectric layers and a plurality of conductive features. The conductive features can include a plurality of wires, conductive contact electrodes, and conductive via electrodes. The integrated circuit device includes a logic device, a memory device (e.g., static random access memory (SRAM)), a radio frequency (RF) device, an input / output (I / O) device, a system-on-chip (SoC) device, other suitable device types, or a combination thereof. In some embodiments, semiconductor chips 118A or 118B is a system-on-chip (SoC) chip that includes multiple functions.

[0060] The conductive pad 126 may be a wider portion of some wires formed on the internal connection structure 122. The conductive pad 126 may be partially embedded within the passivation sheath 124. Each conductive pad 126 is electrically connected to one or more device elements through some conductive features within the internal connection structure 122. Therefore, device elements within and / or on the semiconductor substrate 120 can be electrically connected to other elements via the conductive pad 126.

[0061] like Figure 1H As shown, according to some embodiments, a protective layer 128 is formed on a support substrate 100 to surround and protect semiconductor chips 118A and 118B and conductive structure 116. In some embodiments, the protective layer 128 is in direct contact with the lower and upper portions of the conductive structure 116. In some embodiments, the protective layer 128 comprises or is formed of an insulating material, such as a molding material. The molding material may include a polymeric material, such as an epoxy resin in which one or more fillers are dispersed. The filler may include insulating particles, insulating fibers, one or more other elements, or combinations thereof. For example, the filler includes silica particles, silica fibers, carbon-containing particles, carbon fibers, one or more other fillers, or combinations thereof.

[0062] In some embodiments, a molding material (e.g., a liquid molding material) is introduced or injected to cover the conductive structure 116 and the semiconductor chips 118A and 118B. In some embodiments, a thermal process is then used to cure the liquid molding material and transform it into a protective layer 128.

[0063] like Figure 1I As shown, according to some embodiments, the protective layer 128 is planarized to reduce its thickness. In some embodiments, the protective layer 128 is planarized to expose the conductive pads 126 and conductive structures 116 of the semiconductor chips 118A and 118B. The planarization of the protective layer 128 can be performed using mechanical grinding, chemical mechanical polishing (CMP), dry polishing, etching, one or more other suitable processes, or a combination thereof. In some embodiments, the conductive structures 116 and / or the semiconductor chips 118A and 118B are also partially removed during the planarization process. In some embodiments, the upper surfaces of the conductive structures 116 and the semiconductor chips 118A and 118B are substantially flush with each other.

[0064] like Figure 1J As shown, according to some embodiments, a re-woven structure 130 is formed. Figure 1IThe redistribution structure 130 is used for routing, which can form a package structure with fan-out features. In some embodiments, the redistribution structure 130 includes a plurality of insulating layers and a plurality of conductive features. The insulating layers surround the conductive features. The conductive features can include wires, conductive via electrodes, and / or conductive pads.

[0065] The redistribution structure 130 also includes conductive pads for holding or accommodating other elements. In some embodiments, the conductive pads are exposed or protrude from the uppermost surface of the insulating layers. The conductive pads can be used to hold or accommodate one or more semiconductor chips and / or one or more passive elements. The conductive pads can also be used to hold or accommodate conductive features, such as conductive pillars and / or conductive bumps. In some embodiments, the conductive pads are underneath under bump metallization (UBM) pads.

[0066] The insulating layers of the redistribution structure 130 can include or be formed of one or more polymeric materials. The polymeric materials can include polybenzoxazole (PBO), polyimide (PI), epoxy-based resins, one or more other suitable polymeric materials, or combinations thereof. In some embodiments, the polymeric materials are photosensitive. Thus, openings with desired patterns can be formed in the insulating layers using lithography processes. These openings can be used to accommodate the conductive features and / or the conductive pads.

[0067] In some other embodiments, some or all of the insulating layers include or are formed of dielectric materials other than polymeric materials. The dielectric materials can include silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, one or more other suitable materials, or combinations thereof.

[0068] The conductive features can include wires that provide electrical connections in a horizontal direction and conductive via electrodes that provide electrical connections in a vertical direction. In some embodiments, some of the conductive via electrodes are stacked on top of each other. The upper conductive via electrodes are substantially aligned with the lower conductive via electrodes. In some embodiments, some of the conductive via electrodes are staggered via electrodes. The upper conductive via electrodes are misaligned with the lower conductive via electrodes.

[0069] The conductive features and / or the conductive pads of the redistribution structure 130 can include or be formed of copper, aluminum, gold, cobalt, titanium, nickel, silver, graphene, one or more other suitable conductive materials, or combinations thereof. In some embodiments, the conductive features include a plurality of sub-layers. For example, each conductive feature includes a plurality of sub-layers that include Ti / Cu, Ti / Ni / Cu, Ti / Cu / Ti, Al / Ti / Ni / Ag, other suitable sub-layers, or combinations thereof.

[0070] The fabrication of the redistribution structure 130 may include multiple deposition or coating processes, multiple patterning processes, and / or multiple planarization processes.

[0071] Deposition or coating processes can be used to form insulating and / or conductive layers. Deposition or coating processes may include spin coating, electroplating, electroless electroplating, CVD, PVD, ALD, one or more other suitable processes, or combinations thereof.

[0072] Patterning processes can be used to pattern insulating layers and / or conductive layers. Patterning processes may include lithography, energy beam drilling (e.g., laser drilling, ion beam drilling, or electron beam drilling), etching, mechanical drilling, one or more other suitable processes, or combinations thereof.

[0073] Planarization processes can be used to provide a flat upper surface for the formed insulating layer and / or conductive layer to facilitate subsequent processes. Planarization processes may include mechanical grinding processes, CMP processes, dry polishing processes, etching processes, one or more other suitable processes, or combinations thereof.

[0074] Subsequently, according to some embodiments, such as Figure 1J As shown, conductive bumps 132 are formed on the re-laid structure 130. The conductive bumps 132 may be formed on conductive pads. In some embodiments, the conductive bumps 132 are tin-containing solder bumps. Tin-containing solder bumps may also include copper, silver, gold, aluminum, lead, one or more other suitable materials, or combinations thereof. In some other embodiments, the conductive bumps 132 are lead-free. The conductive bumps 132 can be formed using a solder ball placement process and a thermal reflow process.

[0075] According to some embodiments, such as Figure 1K As shown, Figure 1J The structure shown is inverted, and the supporting substrate 100 and adhesive layer 102 are removed. After removing the supporting substrate 100 and adhesive layer 102, the end of the conductive structure 116 is exposed. Then, according to some embodiments, conductive bumps 134 are formed on the conductive structure 116, such as... Figure 1K As shown. In some embodiments, conductive bumps 134 are formed directly on the conductive structure 116 exposed after the adhesive layer 102 and the carrier substrate 100 are removed. In some embodiments, conductive bumps 134 are solder bumps. Conductive bumps 134 are in direct contact with conductive structure 116. In some embodiments, each conductive structure 116 has a top that is substantially the same size as the bottom of the conductive bump 134 located directly above the corresponding conductive structure 116. The material and formation method of conductive bumps 134 may be the same as or similar to the material and formation method of conductive bumps 132.

[0076] Figure 2A cross-sectional schematic view of a portion of a package structure is shown in accordance with some embodiments. In some embodiments, Figure 2 is a partial view Figure 1K of the structure shown. In Figure 2 , a conductive bump 134, a conductive structure 116, and a protective layer 128 are shown.

[0077] As shown, Figure 2 the conductive structure 116 has a first portion P1 and a second portion P2. The first portion P1 is between the second portion P2 and the conductive bump 134. In some embodiments, the second portion P2 is wider than the first portion P1.

[0078] In some embodiments, the second portion P2 has substantially vertical sidewall surfaces. The second portion P2 has a width W1. The width W1 can be in a range from about 100 μm to about 300 μm. In some embodiments, the first portion P1 has sloped sidewall surfaces. In some embodiments, the first portion P1 tapers in a direction toward the conductive bump 134. In some embodiments, a bottom of the first portion P1 is substantially the same width as the second portion P2. In some embodiments, the first portion P1 tapers from a first portion having the width W1 to a second portion having a width W2 in a direction from a bottom of the first portion P1 toward a top of the first portion P1. The width W2 can be in a range from about 90 μm to about 290 μm. The width W2 can be the shortest width of the first portion P1 of the conductive structure 116. The width W2 can be the width of a top end of the conductive structure 116. The conductive bump 134 has a width W3. The width W3 can be the widest width of the conductive bump 134. In some embodiments, the width W3 is greater than the width W2. The width W3 can be in a range from about 100 μm to about 320 μm.

[0079] A ratio of the width W2 to the width W1 (W2 / W1) can be in a range from about 0.5 to about 0.9. A symbolic tangent S1 at an intersection of the first portion P1 and the conductive bump 134 to a surface of the conductive bump 134 forms an angle Θ with sidewall surfaces of the first portion P1. In some embodiments, the angle Θ is in a range from about 30 degrees to about 110 degrees. In some other embodiments, the angle Θ is in a range from about 60 degrees to about 100 degrees.

[0080] Because the first portion P1 is reduced in size, the edge of the interface between the conductive structure 116 and the conductive bump 134 is not aligned with the main sidewall surface of the conductive structure 116 (i.e., the sidewall surface of the second portion P2). Therefore, stress from the conductive bump 134 is prevented from directly reaching the main sidewall surface of the conductive structure 116 adjacent to the protective layer 128. This significantly reduces the likelihood of delamination between the conductive structure 116 and the protective layer 128. In some other cases, if the conductive structure 116 does not have a reduced portion adjacent to the conductive bump 134, the edge of the interface between the conductive structure 116 and the conductive bump 134 is substantially aligned with the main sidewall surface of the conductive structure. Stress may directly affect the main sidewall surface of the conductive structure 116. Delamination may occur between the conductive structure 116 and the protective layer 128.

[0081] like Figure 1L As shown, according to some embodiments, the package 136 is stacked to Figure 1K As shown in the structure, each package 136 may include a fabric substrate 138, one or more semiconductor chips (e.g., semiconductor chips 140A and 140B), and a protective layer 142 surrounding and protecting the semiconductor chips 140A and 140B. The material and method of forming the protective layer 142 may be the same as or similar to the material and method of forming the protective layer 128.

[0082] As with the redistribution structure 130, the redistribution substrate 138 may include one or more insulating layers and multiple conductive features. Each device element within semiconductor chips 140A and 140B may be electrically connected to one or more conductive features within the redistribution substrate 138. For example, wiring may form an electrical connection therebetween. Electrical connections between semiconductor chips 118A (or 118B) and semiconductor chips 140A and 140B may be formed via the redistribution substrate 138, conductive bumps 134, conductive structures 116, and redistribution structure 130. In some embodiments, an adhesive element 144 is formed to surround and protect the conductive bumps. In some embodiments, the redistribution substrate 138 is an interposer substrate.

[0083] In some embodiments, the stacking of package 136 is associated with applying compressive force to conductive bump 134. In some embodiments, a thermocompression process is used to bond package 136 to conductive bump 134. As previously described, the interface edge between conductive structure 116 and conductive bump 134 is not aligned with the main sidewall surface of conductive structure 116 (i.e., the sidewall surface of the second portion P2). Therefore, stress caused by the thermocompression process is prevented from being directly concentrated on the main sidewall surface of conductive structure 116. The possibility of delamination between conductive structure 116 and protective layer 128 is significantly reduced or prevented.

[0084] Then, a cutting process is used to... Figure 1LThe illustrated structure is cut into a plurality of individual package structures. According to some embodiments, Figure 1M One of the package structures is shown in

[0085] Many changes and / or modifications can be made to embodiments of the disclosure. Figure 3 Cross-sectional schematic views of process stages of fabricating a package structure according to some embodiments are shown. In some embodiments, the photosensitive layer 106 has a footing structure 310 with a curved surface, as shown. Figure 3 In some embodiments, each footing structure 310 has an upwardly facing concave surface. The exposure operation and / or the development operation used to form the opening 108 can be fine-tuned to adjust the cross-sectional profile of the footing structure 310.

[0086] Many changes and / or modifications can be made to embodiments of the disclosure. Figure 4 Cross-sectional schematic views of process stages of fabricating a package structure according to some embodiments are shown. In some embodiments, the processes that are the same as or similar to those shown in FIGS. 1C-1K can be indicated by the same reference numbers. As such, a structure similar to the structure shown in Figure 1K is formed. In some embodiments, Figure 4 A partial enlarged cross-sectional schematic view of the structure is shown. In Figure 4 The conductive bump 134, the conductive structure 116, and the protective layer 128 are shown in

[0087] As shown, Figure 4 The conductive structure 116 has a first portion P1 and a second portion P2. The first portion P1 is located between the second portion P2 and the conductive bump 134. In some embodiments, the second portion P2 is wider than the first portion P1.

[0088] In some embodiments, the second portion P2 has a substantially vertical sidewall surface. In some embodiments, the first portion P1 has a curved sidewall surface 302. In some embodiments, the curved sidewall surface 302 is an upwardly facing convex surface. In some embodiments, the first portion P1 tapers in a direction toward the conductive bump 134. In some embodiments, the first portion P1 gradually tapers in a direction toward the conductive bump 134.

[0089] An exemplary tangent line S2 of the curved sidewall surface 302 of the first portion P1 forms an angle Θ' with an exemplary tangent line SI of the conductive bump 134. In some embodiments, the angle Θ' is in a range of about 30 degrees to about 110 degrees. In some other embodiments, the angle Θ' is in a range of about 60 degrees to about 100 degrees.

[0090] Because the first portion P1 is tapered, the interface edge between the conductive structure 116 and the conductive bump 134 is not aligned with the main sidewall surface of the conductive structure 116 (i.e., the sidewall surface of the second portion P2). Thus, stress from the conductive bump 134 is prevented from directly reaching the main sidewall surface of the conductive structure 116 adjacent to the protective layer 128. The likelihood of delamination between the conductive structure 116 and the protective layer 128 is significantly reduced. In some other cases, if the conductive structure 116 does not have a tapered portion adjacent to the conductive bump 134, the interface edge between the conductive structure 116 and the conductive bump 134 is substantially aligned with the main sidewall surface of the conductive structure. Stress can directly affect the main sidewall surface of the conductive structure 116. Delamination can occur between the conductive structure 116 and the protective layer 128.

[0091] Embodiments of the present disclosure form a package structure including a conductive structure, a conductive bump over the conductive structure, and a protective layer surrounding the conductive structure. The conductive structure has a tapered portion adjacent to the conductive bump. The tapered portion has a sloped surface or a curved surface. Due to the profile of the tapered portion, stress from the conductive bump is prevented from directly reaching the main sidewall surface of the conductive structure adjacent to the protective layer. Thus, the likelihood of delamination between the conductive structure and the protective layer is significantly reduced. The performance and reliability of the package structure are greatly improved.

[0092] According to some embodiments, a method of fabricating a package structure is provided. The method includes forming a conductive structure on a carrier substrate. The conductive structure has a lower portion and an upper portion, and the upper portion is wider than the lower portion. The method also includes disposing a semiconductor chip on the carrier substrate. The method further includes forming a protective layer to surround the conductive structure and the semiconductor chip. In addition, the method includes forming a conductive bump on the conductive structure. The lower portion of the conductive structure is between the conductive bump and the upper portion of the conductive structure.

[0093] According to some embodiments, a method of fabricating a package structure is provided. The method includes forming a conductive structure, and a lower portion of the conductive structure is tapered in a direction toward a bottom of the conductive structure. The method also includes disposing a semiconductor chip next to the conductive structure. The method further includes forming a protective layer to surround the conductive structure and the semiconductor chip. In addition, the method includes forming a conductive bump on the bottom of the conductive structure.

[0094] According to some embodiments, a package structure is provided. The package structure includes a conductive structure and a semiconductor chip laterally spaced apart from each other. The package structure also includes a protective layer surrounding the conductive structure and the semiconductor chip. The package structure further includes a conductive bump electrically connected to the conductive structure. The conductive structure has a first portion and a second portion, the first portion is between the conductive bump and the second portion, and the second portion is wider than the first portion.

[0095] The foregoing outlines features of several embodiments of the present disclosure so that those skilled in the art can better understand the present disclosure. Any embodiments of the present disclosure as a basis for the variation or design of other processes or structures by those skilled in the art without departing from the spirit and scope of the present disclosure. Those skilled in the art should appreciate that they can readily use the conception and specific embodiments disclosed as a basis for modifying or designing other processes and structures for carrying out the same purposes and / or obtaining the same advantages of the present disclosure without departing from the spirit and scope of the present disclosure. Those skilled in the art should appreciate that they can readily use the conception and specific embodiments disclosed as a basis for modifying or designing other processes and structures for carrying out the same purposes and / or obtaining the same advantages of the present disclosure without departing from the spirit and scope of the present disclosure. It is therefore intended that the present disclosure not be limited to the disclosed embodiments, but construed to include all changes, equivalents and substitutes that do not depart from the spirit and technical scope of the present disclosure.

Claims

1. A method for manufacturing a packaging structure, comprising: A conductive structure is formed on a supporting substrate, wherein the conductive structure has a lower part and an upper part, and the upper part is wider than the lower part, wherein the upper part and the lower part have different sidewall slopes. A semiconductor chip is disposed on the substrate; A protective layer is formed to surround the conductive structure and the semiconductor chip, wherein the protective layer laterally surrounds the entire lower and upper portions of the conductive structure, which have different sidewall slopes, and the protective layer is a single layer. as well as A conductive bump is formed on the conductive structure, wherein a joint interface is formed between the lower part of the conductive structure and the conductive bump, wherein the upper part of the conductive structure with a larger width is further away from the conductive bump than the lower part of the conductive structure with a smaller width, and the sidewall of the lower part forms an obtuse angle with the joint interface.

2. The method for manufacturing the packaging structure as claimed in claim 1, wherein forming the conductive structure on the carrier substrate further includes: A sublayer is formed on the supporting substrate; A photosensitive layer is formed on the seed layer; An opening is formed in the photosensitive layer by an exposure operation and a development operation to expose a portion of the seed layer; as well as The conductive structure is formed by filling at least a portion of the opening with a conductive material.

3. The method for manufacturing the packaging structure as described in claim 2, further comprising: Before forming the conductive structure, the photosensitive layer is subjected to a plasma operation.

4. The method of manufacturing the packaging structure as claimed in claim 3, wherein the operating temperature is maintained after the plasma operation and before the formation of the conductive structure.

5. The method of manufacturing the packaging structure as claimed in claim 2, wherein the operating temperature is maintained after the opening is formed and before the conductive structure is formed.

6. The method for manufacturing the packaging structure as described in claim 2, further comprising: The photosensitive layer is removed after the conductive structure is formed.

7. The method for manufacturing the packaging structure as described in claim 6, further comprising: After removing the photosensitive layer, the seed layer is locally removed.

8. The method of manufacturing the encapsulation structure as claimed in claim 2, wherein the photosensitive layer has a foot structure near the bottom of the opening.

9. The method of manufacturing the packaging structure as claimed in claim 1, wherein the formed protective layer is in direct contact with the lower and upper portions of the conductive structure.

10. The method of manufacturing the packaging structure as claimed in claim 1, wherein the conductive structure is formed by an electroplating process.

11. A method for manufacturing a packaging structure, comprising: A conductive structure is formed, wherein a lower portion of the conductive structure tapers toward a bottom of the conductive structure, and an upper portion and a lower portion of the conductive structure have different sidewall slopes. A semiconductor chip is placed next to the conductive structure; A protective layer is formed to surround the conductive structure and the semiconductor chip, wherein the protective layer laterally surrounds the entire lower and upper parts of the conductive structure with different sidewall slopes, and the protective layer is a single layer. as well as A conductive bump is formed on the bottom of the conductive structure, wherein a joint interface is formed between the lower part of the conductive structure and the conductive bump, wherein the upper part of the conductive structure with a larger width is further away from the conductive bump than the lower part of the conductive structure with a smaller width, and the sidewall of the lower part forms an obtuse angle with the joint interface.

12. The method of manufacturing the packaging structure as claimed in claim 11, wherein the conductive structure is formed on a carrier substrate, and the manufacturing method further includes: A sublayer is formed on the supporting substrate; A photosensitive layer is formed on the seed layer; An opening is formed within the photosensitive layer to partially expose the seed layer; as well as A conductive material is formed on the seed layer exposed through the opening, wherein the conductive material forms the conductive structure.

13. The method for manufacturing the packaging structure as described in claim 12, further comprising: The photosensitive layer is subjected to a plasma operation before the conductive material is formed.

14. The method of manufacturing the packaging structure as claimed in claim 13, wherein a thermal baking operation is not performed after the plasma operation and before the formation of the conductive material.

15. The method for manufacturing the packaging structure as described in claim 12, further comprising: The carrier substrate is removed before the conductive bump is formed to expose the bottom of the conductive structure, wherein the conductive bump is formed directly on the bottom of the conductive structure.

16. A packaging structure, comprising: A conductive structure and a semiconductor chip are laterally separated from each other. A protective layer surrounds the conductive structure and the semiconductor chip; A conductive bump is electrically connected to the conductive structure, wherein the conductive structure has a first portion and a second portion, and the second portion is wider than the first portion, wherein the first portion and the second portion of the conductive structure have different sidewall slopes, wherein a protective layer laterally surrounds the entire first portion and the second portion of the conductive structure with different sidewall slopes, and the protective layer is a single layer, wherein a bonding interface is formed between the first portion of the conductive structure and the conductive bump, wherein the second portion of the conductive structure with a larger width is further away from the conductive bump than the first portion of the conductive structure with a smaller width, and the sidewall of the first portion forms an obtuse angle with the bonding interface.

17. The packaging structure of claim 16, wherein the first portion of the conductive structure has an inclined sidewall surface.

18. The packaging structure of claim 16, wherein the first portion of the conductive structure has a curved sidewall surface.

19. The packaging structure of claim 16, wherein a sidewall surface of the first portion of the conductive structure forms an angle with a symbolic tangent of a conductive bump adjacent to the conductive structure, and the angle is in the range of 30 degrees to 110 degrees.

20. The packaging structure of claim 16, wherein the first portion of the conductive structure has a first width, the second portion of the conductive structure has a second width, and the ratio of the first width to the second width is in the range of 0.5 to 0.9.

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