Semiconductor device and method of forming the same

Abstract

A semiconductor device includes a channel region between a source region and a drain region, a gate over the channel region, a dielectric layer over the gate, a capacitive field plate over the dielectric layer, and a word line electrically coupled to the capacitive field plate.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for forming the same. Background Art

[0002] Semiconductor components are implemented in numerous electronic devices, such as mobile phones, laptop computers, desktop computers, tablet computers, watches, gaming systems, and a variety of other industrial, commercial, and consumer electronic products. Technological advances in the semiconductor field have resulted in electronic circuits having many more components than those of previous generations. Furthermore, the number of components per semiconductor chip area continues to increase. Summary of the Invention

[0003] According to an embodiment of the present invention, a semiconductor device includes a transistor, a dielectric layer, a capacitor field plate, and a word line. The transistor includes a first source / drain region, a second source / drain region, a channel region, and a gate electrode. The channel region is located between the first source / drain region and the second source / drain region. The gate electrode is located above the channel region. The dielectric layer is located above the gate electrode. The capacitor field plate is located above the dielectric layer. The word line is electrically coupled to the capacitor field plate.

[0004] According to an embodiment of the present invention, a method for forming a semiconductor device includes at least the following steps: forming a first dielectric layer over a gate electrode and a first source / drain region of a transistor; removing a first portion of the first dielectric layer over the first source / drain region to expose a first portion of the first source / drain region; forming a capacitor field plate over the first dielectric layer after removing the first portion of the first dielectric layer; and coupling a word line to the capacitor field plate.

[0005] According to an embodiment of the present invention, a semiconductor device includes a transistor, a capacitor field plate, and a word line. The transistor includes a first source / drain region, a second source / drain region, a channel region, and a gate electrode. The first source / drain region is coupled to the source line. The channel region is located between the first source / drain region and the second source / drain region. The gate electrode is located above the channel region. The capacitor field plate overlies the gate electrode. The word line is coupled to and overlies the gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A According to some embodiments Figure 1B XX is a cross-sectional view of the semiconductor device taken along line XX in FIG.

[0008] Figure 1Bis a top view of a semiconductor device according to some embodiments.

[0009] Figures 2 to 11 According to some embodiments Figure 1B XX in FIG. 1 is a cross-sectional view of a semiconductor device at various fabrication stages.

[0010] Figure 12 Various contact signals for performing a memory function of a semiconductor device according to some embodiments are shown.

[0011] Figure 13 A semiconductor device according to some embodiments is shown.

[0012] Figure 14 According to some embodiments Figure 13 : A cross-sectional view of the semiconductor device taken along line YY in FIG.

[0013] Figures 15 to 16 According to some embodiments Figure 1B XX in FIG. 1 is a cross-sectional view of a semiconductor device at various fabrication stages.

[0014] Explanation of Figure Numbers

[0015] 100, 1300: semiconductor devices;

[0016] 102, 1302: substrate;

[0017] 104: buried layer;

[0018] 106a, 106b, 106c, 1308: quarantine area;

[0019] 107, 1310: trap;

[0020] 108: doping region;

[0021] 110a, 1312a: first source / drain region;

[0022] 110b, 1312b: second source / drain region;

[0023] 112a: first ion implantation region;

[0024] 112b: second ion implantation region;

[0025] 114, 1400: channel area;

[0026] 116: gate electrode;

[0027] 118, 1004: length;

[0028] 120: transistor;

[0029] 122: gate insulating layer;

[0030] 124a, 124b, 1600: side surfaces;

[0031] 126a: first spacer;

[0032] 126b: second spacer;

[0033] 200, 1500: thickness;

[0034] 202, 1318: dielectric layer;

[0035] 204a: Part I;

[0036] 204b: Part II;

[0037] 204c: Part III;

[0038] 206a: a first portion of a first source / drain region;

[0039] 206b: a first portion of a second source / drain region;

[0040] 208a: a second portion of the first source / drain region;

[0041] 208b: a second portion of the second source / drain region;

[0042] 210a: first bottom surface;

[0043] 210b: second bottom surface;

[0044] 210c: third bottom surface;

[0045] 212: distance;

[0046] 300: photoresist layer;

[0047] 400: photomask;

[0048] 402: light source;

[0049] 404: soluble region;

[0050] 406, 408: width;

[0051] 500: solvent;

[0052] 600: etching process;

[0053] 700a, 700b, 700c: silicide regions;

[0054] 800: interlayer dielectric layer;

[0055] 900: gate vertical interconnection channel hole;

[0056] 902a: vertical interconnection channel hole in the doped region;

[0057] 902b: first source / drain vertical interconnect channel hole;

[0058] 902c: second source / drain vertical interconnect channel hole;

[0059] 1000: vertical internal connection channel;

[0060] 1002, 1320: capacitor field plates;

[0061] 1006: capacitor;

[0062] 1100: contact layer;

[0063] 1102a, 1102b, 1102c: vertical interconnect channel contacts;

[0064] 1104, 1322: word lines;

[0065] 1200: table;

[0066] 1304a: first fin structure;

[0067] 1304b: second fin structure;

[0068] 1306: buried oxide layer;

[0069] 1314: gate insulation region;

[0070] 1316: Gate;

[0071] XX, YY: line. DETAILED DESCRIPTION

[0072] The following disclosure provides several different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments or configurations discussed.

[0073] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and similar terms, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative terms used herein should be interpreted accordingly.

[0074] A non-volatile memory (NVM) bit cell includes a word line capacitor stacked above a memory cell. The NVM bit cell stack includes: a channel region in a doped well of a substrate; a gate above the channel region; a dielectric layer above the gate; a capacitor field plate above the dielectric layer; and a word line located above and electrically coupled to the capacitor field plate. By stacking the capacitor field plate above the gate and the dielectric layer above the capacitor field plate, the NVM bit cell has a smaller footprint compared to a conventional NVM bit cell that includes both a word line capacitor transistor and a cell transistor adjacent to the word line capacitor transistor. Thus, cell density can be increased. Similarly, because the word line capacitor is stacked above the memory cell and not adjacent to the memory cell, the doped well region of the memory cell forms a channel region, and compared to a conventional NVM bit cell, the channel region does not require implants. Because implants are not required in the channel region, the design and manufacturing costs of the NVM bit cell process are lower than those of an NVM bit cell process that requires implants in the channel region.

[0075] Go to Figure 1A and Figure 1B At least some of the semiconductor devices 100 are formed on a substrate 102. In some embodiments, the substrate 102 includes at least one of an epitaxial layer, a silicon-on-insulator (SOI) structure, a wafer, or a die formed from a wafer. In some embodiments, the substrate 102 includes at least one of silicon, germanium, carbide, gallium, arsenide, arsenic, indium, an oxide, sapphire, or other suitable materials. In some embodiments, the substrate 102 is at least one of a p-type substrate (P substrate) or an n-type substrate (N substrate). In some embodiments, the substrate 102 includes one or more of a p-doped well region or an n-doped well region.

[0076] In some embodiments, substrate 102 includes a buried layer 104. In some embodiments, buried layer 104 includes at least one of phosphorus, arsenic, lithium, boron, aluminum, gallium, indium, or other suitable dopants. In some embodiments, buried layer 104 is at least one of an n-type buried layer (NBL) or a p-type buried layer (PBL). In some embodiments, ion implantation or other suitable techniques are used to introduce n-type dopants or p-type dopants into substrate 102 to form buried layer 104.

[0077] According to some embodiments, semiconductor device 100 includes one or more isolation regions, such as first isolation region (also referred to as isolation region) 106a, second isolation region (also referred to as isolation region) 106b, or third isolation region (also referred to as isolation region) 106c. Isolation regions 106a, 106b, and 106c include dielectric materials and are formed in substrate 102. According to some embodiments, one or more of first isolation region 106a, second isolation region 106b, and third isolation region 106c are shallow trench isolation (STI) regions including at least one of oxide, nitride, or other suitable materials.

[0078] According to some embodiments, semiconductor device 100 includes a well 107 formed in substrate 102. Well 107 includes a dopant implanted into substrate 102. According to some embodiments, well 107 includes an n-type dopant, such as at least one of phosphorus (P), arsenic (As), antimony (Sb), at least one Group V element, or other suitable materials. According to some embodiments, well 107 includes a p-type dopant, such as at least one of boron (B), aluminum (Al), gallium (Ga), indium (In), at least one Group III element, or other suitable materials.

[0079] According to some embodiments, the semiconductor device 100 includes a gate insulating layer 122 formed over the substrate 102. According to some embodiments, the gate insulating layer 122 is a high-k dielectric layer. As used herein, the term "high-k dielectric" refers to a material having a dielectric constant k greater than or equal to about 3.9 (which is the k value of SiO2). The material of the high-k dielectric layer can be any suitable material. Examples of materials for the high-k dielectric layer include, but are not limited to, Al2O3, HfO2, ZrO2, La2O3, TiO2, SrTiO3, LaAlO3, Y2O3, Al2O x N y , HfO x N y 、ZrO x N y 、La2Ox N y 、TiO x N y 、SrTiO x N y 、LaAlO x N y 、Y2O x N y 、SiON、SiN x , silicates thereof, and alloys thereof. Each value of x is independently 0.5 to 3, and each value of y is independently 0 to 2. According to some embodiments, gate insulating layer 122 is an oxide formed by thermally oxidizing silicon in a region of substrate 102 to form an insulating layer of silicon dioxide. According to some embodiments, gate insulating layer 122 is formed by a self-limiting oxidation process.

[0080] According to some embodiments, semiconductor device 100 includes a gate electrode 116 formed over gate insulating layer 122. According to some embodiments, gate electrode 116 includes a conductive material. According to some embodiments, gate electrode 116 includes at least one of polysilicon, metal, or other suitable materials. According to some embodiments, gate electrode 116 is formed using one or more of photolithography, etching, or other suitable processes. According to some embodiments, gate electrode material is formed over a substrate, and a photoresist layer is formed over the gate electrode material. According to some embodiments, the photoresist layer is exposed to light to form a pattern, and a post-exposure development process is performed to form a mask element. The mask element protects portions of the gate electrode material during the etching process, so that gate electrode 116 remains over substrate 102 and between a region where first source / drain region 110 a will be formed and a region where second source / drain region 110 b will be formed. In some embodiments, the gate electrode 116 is formed via a replacement gate process, in which a dummy gate material (e.g., polysilicon) is used to initially form the gate electrode 116, and later in the process, for example, after forming the first source / drain region 110a and the second source / drain region 110b, the dummy gate material is replaced with another gate electrode material (e.g., metal). In such embodiments, the gate insulating layer 122 is also etched during the etching process. According to some embodiments, the gate electrode 116 has a length 118 defined by the distance between side surfaces 124a and 124b of the gate electrode 116.

[0081] In some embodiments, semiconductor device 100 includes one or more memory cell (MCEL) implantation regions, such as first and second ion implantation regions 112a and 112b, formed in substrate 102 adjacent to gate insulating layer 122 and gate electrode 116. In some embodiments, one or more of first and second ion implantation regions 112a and 112b are formed by at least one of ion implantation, molecular diffusion, or other suitable techniques. In some embodiments, one or more of first and second ion implantation regions 112a and 112b include at least one of a p-type dopant or an n-type dopant. In some embodiments, one or more of first and second ion implantation regions 112a and 112b have a p-type dopant or an n-type dopant concentration greater than a p-type dopant concentration or an n-type dopant concentration of first and second source / drain regions 110a and 110b.

[0082] According to some embodiments, the semiconductor device 100 includes one or more spacers, such as a first spacer 126a and a second spacer 126b, formed adjacent to the gate insulating layer 122 and the gate electrode 116. In some embodiments, the first spacer 126a is formed above the first ion implanted region 112a, and the second spacer 126b is formed above the second ion implanted region 112b. One or more of the first spacer 126a or the second spacer 126b includes at least one of an oxide, a nitride, or other suitable material. In other embodiments, the spacer (e.g., at least one of the first spacer 126a or the second spacer 126b) is not formed adjacent to at least one of the gate insulating layer 122 or the gate electrode 116.

[0083] According to some embodiments, semiconductor device 100 includes one or more source / drain regions, such as first source / drain region 110a and second source / drain region 110b, formed in substrate 102 between isolation regions 106b and 106c and gate insulation layer 122 and gate electrode 116. In some embodiments, after forming first spacers 126a, first source / drain region 110a is formed between second isolation region 106b and first ion-implanted region 112a. In some embodiments, after forming second spacers 126b, second source / drain region 110b is formed between third isolation region 106c and second ion-implanted region 112b. One or more of first source / drain region 110a and second source / drain region 110b may be formed by at least one of ion implantation, molecular diffusion, or other suitable techniques. In some embodiments, one or more of the first source / drain region 110 a or the second source / drain region 110 b includes at least one of a p-type dopant or an n-type dopant.

[0084] According to some embodiments, semiconductor device 100 includes one or more doped regions, such as doped region 108 formed in substrate 102 between isolation region 106a and isolation region 106b. Doped region 108 can be formed by at least one of ion implantation, molecular diffusion, or other suitable techniques. The number or amount of dopants implanted into substrate 102 is controlled to control the dopant concentration in doped region 108. According to some embodiments, the energy of the dopants implanted into substrate 102 is controlled to control the depth of the dopants implanted into substrate 102. According to some embodiments, the depth of the dopants in substrate 102 is controlled by increasing or decreasing the voltage used to direct the dopants into substrate 102. In some embodiments, doped region 108 includes at least one of a p-type dopant or an n-type dopant.

[0085] According to some embodiments, the number or amount of dopants implanted into the substrate 102 to form one or more of the first source / drain region 110 a or the second source / drain region 110 b is controlled in the same or similar manner as the number or amount of dopants used to form the doped region 108, or in another suitable manner. In some embodiments, at least one of the first source / drain region 110 a or the second source / drain region 110 b includes a different type of dopant than the doped region 108. For example, in some embodiments, when the doped region 108 includes a p-type dopant, the first source / drain region 110 a and the second source / drain region 110 b include an n-type dopant.

[0086] According to some embodiments, semiconductor device 100 includes a transistor 120 including a first source / drain region 110 a, a second source / drain region 110 b, a gate insulating layer 122, a gate electrode 116, and at least a portion of a substrate 102 below the gate insulating layer 122. According to some embodiments, the portion of substrate 102 below the gate insulating layer 122 defines a channel region 114 of transistor 120.

[0087] refer to Figure 2 According to some embodiments, dielectric layer 202 is formed over substrate 102, first spacer 126a, second spacer 126b, and gate electrode 116. In some embodiments where at least one of first spacer 126a or second spacer 126b is not formed, dielectric layer 202 is formed in direct contact with at least one of the sidewalls of gate insulating layer 122 or the sidewalls of gate electrode 116. In some embodiments, dielectric layer 202 includes a dielectric material such as oxide, silicon oxide, silicon nitride, silicon carbon nitride, silicon oxynitride, silicon carbide, or silicon oxycarbide, or combinations thereof, or other suitable materials. According to some embodiments, dielectric layer 202 is a resist-protection-oxide film (RPO film). According to some embodiments, dielectric layer 202 includes a single oxide layer. According to some embodiments, dielectric layer 202 includes multiple layers. For example, the dielectric layer 202 may include a first oxide layer over the substrate 102 , the first spacer 126 a , the second spacer 126 b , and the gate electrode 116 , a silicon nitride layer over the first oxide layer, and a second oxide layer over the silicon nitride layer.

[0088] According to some embodiments, dielectric layer 202 is formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or other suitable processes. In some embodiments, dielectric layer 202 is formed to have a thickness 200 greater than 2 nanometers (nm). According to some embodiments, by having a thickness 200 greater than 2 nm, dielectric layer 202 prevents gate electrode 116 from being formed during the silicide formation process (e.g., subsequently). Figure 7According to some embodiments, by forming the dielectric layer 202 to have a thickness 200 greater than 2 nanometers, a photoresist layer resistant to silicidation is not required over the dielectric layer 202 to protect the gate electrode 116 during the silicide formation process. According to some embodiments, the dielectric layer 202 is formed to have a thickness 200 less than 10 nanometers.

[0089] According to some embodiments, the dielectric layer 202 includes a first portion 204a, a second portion 204b, and a third portion 204c. According to some embodiments, the first portion 204a of the dielectric layer 202 overlies the first portion 206a of the first source / drain region 110a, the isolation region 106b, the doped region 108, and the isolation region 106a. According to some embodiments, the second portion 204b of the dielectric layer 202 overlies the first portion 206b of the second source / drain region 110b and the isolation region 106c. According to some embodiments, the third portion 204c of the dielectric layer 202 is adjacent to the gate electrode 116, the first spacer 126a, the second spacer 126b, the first portion 204a of the dielectric layer 202, the second portion 204b of the dielectric layer 202, the second portion 208a of the first source / drain region 110a, and the second portion 208b of the second source / drain region 110b. According to some embodiments, the second portion 208a of the first source / drain region 110a is disposed between the first portion 206a of the first source / drain region 110a and the first ion-implanted region 112a. According to some embodiments, the second portion 208b of the second source / drain region 110b is disposed between the first portion 206b of the second source / drain region 110b and the second ion-implanted region 112b. According to some embodiments, a first bottom surface 210a of the third portion 204c of the dielectric layer 202 overlies the second portion 208a of the first source / drain region 110a, and a second bottom surface 210b of the third portion 204c of the dielectric layer 202 overlies the second portion 208b of the second source / drain region 110b. According to some embodiments, a third bottom surface 210c of the third portion 204c of the dielectric layer 202 overlies the gate electrode 116, the first spacer 126a, and the second spacer 126b. In accordance with some embodiments, the first bottom surface 210 a of the third portion 204 c of the dielectric layer 202 and the third bottom surface 210 c of the third portion 204 c of the dielectric layer 202 are separated by a distance 212 in a vertical direction.

[0090] refer to Figure 3According to some embodiments, a photoresist layer 300 is formed above the dielectric layer 202. The photoresist layer 300 can be formed by one or more of spin coating, spray coating or other suitable processes. The photoresist layer 300 includes a photosensitive material so that the properties (e.g., solubility) of the photoresist layer 300 are affected by light. The photoresist layer 300 is a negative photoresist or a positive photoresist. In the case of a negative photoresist, the area of ​​the negative photoresist becomes insoluble when irradiated by a light source, so that a solvent is applied to the negative photoresist during a subsequent development stage to remove the unirradiated area of ​​the negative photoresist. Therefore, the pattern formed in the negative photoresist is the negative of the pattern defined by the opaque area of ​​the template between the light source and the negative photoresist. In a positive photoresist, the irradiated area of ​​the positive photoresist becomes soluble and is removed by applying a solvent during development. Therefore, the pattern formed in the positive photoresist is a positive image of the opaque area of ​​the template between the light source and the positive photoresist.

[0091] refer to Figure 4 When the photoresist layer 300 is a positive photoresist, a photomask 400 is formed over a portion of the photoresist layer 300 overlying the third portion 204 c of the dielectric layer 202. According to some embodiments, a width 406 of the photomask 400 is the same as, greater than, or less than a width 408 of the third portion 204 c of the dielectric layer 202. According to some embodiments, the exposed portions of the photoresist layer 300 (not concealed by the photomask 400) over the first portion 204 a of the dielectric layer 202 and the second portion 204 b of the dielectric layer 202 and the photomask 400 are illuminated by the light source 402 to polymerize the exposed portions of the photoresist layer 300, thereby forming soluble regions 404 in the photoresist layer 300.

[0092] When photoresist layer 300 is a negative-tone photoresist, a photomask (not shown) is formed over first portion 204 a of dielectric layer 202 and second portion 204 b of dielectric layer 202. According to some embodiments, the exposed portion of photoresist layer 300 over third portion 204 c of dielectric layer 202 and the photomask over first portion 204 a of dielectric layer 202 and second portion 204 b of dielectric layer 202 are illuminated by light source 402 to polymerize the exposed portion of photoresist layer 300.

[0093] refer to Figure 5 According to some embodiments, regardless of whether the photoresist layer 300 is a positive-tone photoresist or a negative-tone photoresist, the photomask 400 is removed after the exposed portions of the photoresist layer 300 and the photomask 400 have been illuminated by the light source 402. According to some embodiments, the photomask 400 is removed by one or more of chemical mechanical polishing, wet etching, dry etching, or other suitable processes. For example, in some embodiments, a solvent 500 is applied to remove the soluble regions 404 of the photoresist layer 300.

[0094] refer to Figure 6 According to some embodiments, an etching process 600 is performed to remove portions of dielectric layer 202 not protected by photoresist layer 300. In some embodiments, etching process 600 comprises a dry etching process. In some embodiments, etching process 600 comprises a wet etching process using hydrofluoric acid or diluted hydrofluoric acid as an etchant. In some embodiments, etching process 600 comprises a combination of dry etching and wet etching. According to some embodiments, etching process 600 removes first portion 204a of dielectric layer 202 and second portion 204b of dielectric layer 202.

[0095] refer to Figure 7 According to some embodiments, the photoresist layer 300 is removed. In some embodiments, the photoresist layer 300 is removed by a photoresist ashing or stripping process. According to some embodiments, the removal of the photoresist layer 300 exposes an unremoved portion of the dielectric layer 202, such as the third portion 204c of the dielectric layer 202.

[0096] In some embodiments, the silicide region 700a, the silicide region 700b, and the silicide region 700c are formed on the doped region 108, the first source / drain region 110a, and the second source / drain region 110b, respectively. In some embodiments, the silicide region 700b and the silicide region 700c are formed only on a portion of the first source / drain region 110a and a portion of the second source / drain region 110b that are not obscured by the third portion 204c of the dielectric layer 202. For example, the silicide region 700b and the silicide region 700c may be formed only on the first portion 206a of the first source / drain region 110a and the first portion 206b of the second source / drain region 110b.

[0097] According to some embodiments, silicide regions 700a, 700b, and 700c are formed using a self-aligned silicide process, also known as a salicide process. In some embodiments, the salicide process includes depositing a metal material on the surface of substrate 102 via sputtering at a temperature between 500 degrees Celsius and 900 degrees Celsius, causing a reaction between the underlying silicon and the metal material to form silicide regions 700a, 700b, and 700c. According to some embodiments, unreacted metal material is etched away. In some embodiments, silicide regions 700a, 700b, and 700c include one or more of titanium silicide, cobalt silicide, nickel silicide, platinum silicide, erbium silicide, palladium silicide, or other suitable materials.

[0098] refer to Figure 8In some embodiments, an interlayer dielectric (ILD) layer 800 is formed over substrate 102 and dielectric layer 202. In some embodiments, ILD layer 800 comprises a dielectric material. In some embodiments, the dielectric material comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG), fluorinated silica glass (FSG), carbon-doped silicon oxide (e.g., SiCOH), amorphous fluorinated carbon, bis-benzocyclobutene (BCB), polyimide, combinations thereof, or other suitable materials. In some embodiments, ILD layer 800 is deposited by CVD, high-density plasma (HDP) CVD, sub-atmospheric CVD (SACVD), spin coating, sputtering, or other suitable processes.

[0099] refer to Figure 9 According to some embodiments, the ILD layer 800 is etched through an etching process to form one or more of the following: a gate vertical interconnect access (VIA) hole 900, a doped region vertical interconnect access hole (also referred to as a VIA hole) 902a, a first source / drain vertical interconnect access hole (also referred to as a VIA hole) 902b, or a second source / drain vertical interconnect access hole (also referred to as a VIA hole) 902c. According to some embodiments, the ILD layer 800 is etched through one or more photolithography processes or other suitable processes.

[0100] In some embodiments, the gate vertical interconnection via hole 900 is formed before forming the doped region vertical interconnection via hole 902a, the first source / drain vertical interconnection via hole 902b, or the second source / drain vertical interconnection via hole 902c. According to some embodiments, the gate vertical interconnection via hole 900 is at least partially filled with one or more materials. In some embodiments, the layer of the capacitor field plate (with respect to Figure 10In the embodiment of the present invention, a mask layer (not shown) may be formed in the gate vertical interconnect via hole 900 before forming the doped region vertical interconnect via hole 902a, the first source / drain vertical interconnect via hole 902b, or the second source / drain vertical interconnect via hole 902c. As another example, a mask layer (not shown) may be formed over the gate vertical interconnect via hole 900 and at least partially fill the gate vertical interconnect via hole 900 before forming the doped region vertical interconnect via hole 902a, the first source / drain vertical interconnect via hole 902b, or the second source / drain vertical interconnect via hole 902c. The mask layer may be removed after at least one of the doped region vertical interconnect via hole 902a, the first source / drain vertical interconnect via hole 902b, or the second source / drain vertical interconnect via hole 902c is formed and filled with a conductive material.

[0101] According to some embodiments, at least one of the doped region vertical interconnect via hole 902a, the first source / drain vertical interconnect via hole 902b, or the second source / drain vertical interconnect via hole 902c is formed and filled with a conductive material before forming and filling the gate vertical interconnect via hole 900. Therefore, the order of process actions for forming and filling the vertical interconnect via hole 902a, the vertical interconnect via hole 902b, or the vertical interconnect via hole 902c before forming and filling the gate vertical interconnect via hole 900 may be reversed from the order of process actions discussed above for forming and filling the gate vertical interconnect via hole 900 before forming and filling the vertical interconnect via hole 902a, the vertical interconnect via hole 902b, or the vertical interconnect via hole 902c.

[0102] refer to Figure 10According to some embodiments, the doped region vertical interconnect via hole 902a, the first source / drain vertical interconnect via hole 902b, and the second source / drain vertical interconnect via hole 902c are filled with one or more conductive materials to form a vertical interconnect via 1000. In some embodiments, one or more of the plurality of vertical interconnect vias 1000 are filled with one or more of W, Ti, Co, Cu, Sn, Ni, Au, Ag, or other suitable materials. In some embodiments, one or more of the vertical interconnect channels 1000 are formed by at least one of physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), low pressure CVD (LPCVD), atomic layer chemical vapor deposition (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or other suitable techniques.

[0103] According to some embodiments, the gate vertical interconnect via hole 900 is filled with one or more of W, Ti, Co, Cu, Sn, Ni, Au, Ag, or other suitable materials. According to some embodiments, a capacitive field plate (CFP) 1002 is formed in the gate vertical interconnect via hole 900. According to some embodiments, CFP 1002 includes one or more layers of conductive material. According to some embodiments, CFP 1002 includes one or more conductive layers and one or more dielectric films. According to some embodiments, CFP 1002 includes one or more oxide film layers. According to some embodiments, CFP 1002 includes one or more conductive plates. According to some embodiments, CFP 1002 includes one or more oxide plates. According to some embodiments, CFP 1002 includes an oxide film material between two conductive plates. According to some embodiments, CFP 1002 includes conductive plates comprising one or more of W, Ti, Co, Cu, Sn, Ni, Au, Ag, or other suitable materials. According to some embodiments, CFP 1002 includes a dielectric plate or film comprising one or more of a ceramic material, a synthetic or semi-synthetic organic compound, an oxide, or other suitable materials. According to some embodiments, CFP 1002 includes a dielectric plate or film comprising the same or similar material as dielectric layer 202 or an RPO film. According to some embodiments, both CFP 1002 and dielectric layer 202 include an oxide film. According to some embodiments, semiconductor device 100 includes capacitor 1006, which includes CFP 1002 as a first (upper) conductor, dielectric layer 202 as a dielectric, and gate electrode 116 as a second (lower) conductor.

[0104] According to some embodiments, CFP 1002 has a length 1004. According to some embodiments, length 1004 of CFP 1002 is one of greater than, equal to, or less than length 118 of gate electrode 116. According to some embodiments, at least a portion of CFP 1002 is located above gate electrode 116. According to some embodiments, at least a portion of CFP 1002 is located directly above or overlying gate electrode 116.

[0105] According to some embodiments, if the length 1004 of the CFP 1002 is greater than the length 118 of the gate electrode 116, the coupling ratio between the CFP 1002 and the gate electrode 116 is greater than a configuration in which the length 1004 of the CFP 1002 is not greater than the length 118 of the gate electrode 116. According to some embodiments, the greater the coupling ratio between the CFP 1002 and the gate electrode 116, the higher the performance of the semiconductor device 100 at a lower operating voltage. According to some embodiments, the operating voltage of the semiconductor device 100 is the voltage applied to the CFP 1002 to charge the gate electrode 116. According to some embodiments, if the length 1004 of the CFP 1002 is greater than the length 118 of the gate electrode 116, a lower voltage applied to the CFP 1002 will be sufficient to charge the gate electrode 116 compared to the voltage required to charge the gate electrode 116 when the length 1004 of the CFP 1002 is not greater than the length 118 of the gate electrode 116. According to some embodiments, the length 118 of the gate electrode 116 is less than, equal to, or greater than 0.18 micrometers (μm), and the length 1004 of the CFP 1002 is equal to or greater than 0.3 μm.

[0106] According to some embodiments, at least 0.12 microns of the CFP 1002 are located above the gate electrode 116 in the length direction. According to some embodiments, at least 0.12 microns of the CFP 1002 are located directly above or overlying the gate electrode 116 in the length direction. According to some embodiments, the CFP 1002 is located at least 0.12 microns above the gate electrode 116 in the length direction. According to some embodiments, the CFP 1002 is located directly above or overlying the gate electrode 116 in the length direction by at least 0.12 microns. According to some embodiments, overlapping the CFP 1002 with the gate electrode 116 in the length direction by at least 0.12 microns provides a coupling ratio of sufficiently high magnitude to allow the use of a lower operating voltage relative to the operating voltage required if the CFP 1002 overlaps the gate electrode by less than 0.12 microns.

[0107] refer to Figure 11According to some embodiments, the semiconductor device 100 includes a contact layer 1100 formed over the ILD layer 800 after forming the vertical interconnect channel 1000 and the CFP 1002. In some embodiments, the contact layer 1100 includes a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG), fluorinated silicate glass (FSG), carbon-doped silicon oxide (e.g., SiCOH), amorphous fluorinated carbon, bis-benzocyclobutene (BCB), polyimide, combinations thereof, or other suitable materials. In some embodiments, the contact layer 1100 is deposited by CVD, high-density plasma (HDP) CVD, sub-atmospheric pressure CVD (SACVD), spin coating, sputtering, or other suitable processes.

[0108] According to some embodiments, contact layer 1100 includes vertical interconnect trench contact 1102a, vertical interconnect trench contact 1102b, and vertical interconnect trench contact 1102c. According to some embodiments, vertical interconnect trench contact 1102a is electrically coupled to doped region 108, vertical interconnect trench contact 1102b is electrically coupled to first source / drain region 110a, or vertical interconnect trench contact 1102c is electrically coupled to second source / drain region 110b. According to some embodiments, contact layer 1100 includes word line 1104 electrically coupled to CFP 1002.

[0109] According to some embodiments, Figure 11 The semiconductor device 100 functions as a memory cell. Figure 12 is a diagram illustrating a method for executing Figure 11 Table 1200 shows relative amplitudes of various contact signals for the memory function of semiconductor device 100. In some embodiments, vertical interconnect channel contact 1102c is a drain contact electrically coupled to second source / drain region 110b, word line 1104 is a gate contact electrically coupled to gate electrode 116, and vertical interconnect channel contact 1102b is a source contact electrically coupled to first source / drain region 110a. According to some embodiments, memory cell conditions of semiconductor device 100 include disturb, program, erase, and read. According to some embodiments, each contact is set to a signal level according to table 1200 to place semiconductor device 100 in one or more of the illustrated memory cell conditions.

[0110] refer to Figure 13 and Figure 14, semiconductor device 1300 includes a substrate 1302 including a first fin structure 1304a and a second fin structure 1304b overlying a buried oxide layer 1306. According to some embodiments, semiconductor device 1300 includes one or more isolation regions, such as isolation region 1308. Isolation region 1308 includes a dielectric material and is disposed in substrate 1302. According to some embodiments, isolation region 1308 is a shallow trench isolation (STI) region including at least one of oxide, nitride, or other suitable material.

[0111] According to some embodiments, semiconductor device 1300 includes a well 1310 including a dopant implanted into substrate 1302. According to some embodiments, well 1310 includes an n-type dopant, such as at least one of phosphorus (P), arsenic (As), antimony (Sb), at least one Group V element, or other suitable materials. According to some embodiments, well 1310 includes a p-type dopant, such as at least one of boron (B), aluminum (Al), gallium (Ga), indium (In), at least one Group III element, or other suitable materials. According to some embodiments, well 1310 is adjacent to isolation region 1308.

[0112] In some embodiments, a channel region 1400 is located between the first fin structure 1304a and the second fin structure 1304b, and a gate insulation region 1314 is located above the channel region 1400. The semiconductor device 1300 includes a gate 1316 above the gate insulation region 1314 and a dielectric layer 1318 above the gate 1316. According to some embodiments, the semiconductor device 1300 includes a capacitor field plate 1320 above the dielectric layer 1318 and a word line 1322 electrically coupled to the capacitor field plate 1320. According to some embodiments, the first fin structure 1304a includes a first source / drain region 1312a, and the second fin structure 1304b includes a second source / drain region 1312b. In some embodiments, one or more of the first source / drain region 1312a or the second source / drain region 1312b is formed by at least one of ion implantation, molecular diffusion, or other suitable techniques.

[0113] and Figures 2 to 8 8 shows a process in which a dielectric layer 202 and an ILD layer 800 are formed separately. In some embodiments, the dielectric layer 202 can function as an ILD layer. Figure 15 In some embodiments, when forming Figure 1A After the semiconductor device 100 is shown in FIG, the dielectric layer 202 may be formed to be larger than Figure 2 The thickness of the dielectric layer 202 is 200 to a thickness of 1500 Å.

[0114] Figure 15 The dielectric layer 202 can be formed by one or more of the deposition methods described above for forming the dielectric layer 202 or the ILD layer 800 or other suitable processes. In some embodiments, the dielectric layer 202 can function as an ILD layer. Figures 3 to 8 The formation of the features shown in may be omitted from the formation of semiconductor device 100 .

[0115] refer to Figure 16 , the dielectric layer 202 is etched by an etching process to form Figure 9 One or more of the gate vertical interconnect via hole 900, the doped region vertical interconnect via hole 902a, the first source / drain vertical interconnect via hole 902b, or the second source / drain vertical interconnect via hole 902c are depicted.

[0116] In some embodiments, silicide regions 700a, 700b, and 700c are formed on doped regions 108, first source / drain regions 110a, and second source / drain regions 110b, respectively. According to some embodiments, silicide regions 700a, 700b, and 700c are formed by depositing metal material on doped regions 108, first source / drain regions 110a, and second source / drain regions 110b. Forming silicide regions 700a, 700b, and 700c may include etching away silicide-forming material from side surfaces 1600 that define one or more of doped region vertical interconnect via holes 902a, first source / drain vertical interconnect via holes 902b, or second source / drain vertical interconnect via holes 902c. According to some embodiments, the material of dielectric layer 202 includes an etch stop layer. For example, dielectric layer 202 may include an RPO film that can be used as an etch stop layer when etching away the silicide-forming material from side surface 1600. Figure 10 and Figure 11 The process continues as described.

[0117] According to some embodiments, a wordline signal is transmitted through the CFP 1002 to the dielectric layer 202 and from the dielectric layer 202 to a floating gate electrode, such as the gate electrode 116 of the NVM bit cell. Capacitive coupling of the wordline signal to the floating gate electrode is established by the dielectric layer 202 under the CFP 1002. Disturb, program, erase, and read conditions of the NVM bit cell are established by applying predetermined signal levels to the drain, source, and wordline contacts of the NVM bit cell.

[0118] According to some embodiments, a semiconductor device includes: a transistor including a first source / drain region and a second source / drain region, a channel region located between the first source / drain region and the second source / drain region, and a gate electrode located above the channel region; a dielectric layer located above the gate electrode; a capacitor field plate located above the dielectric layer; and a word line electrically coupled to the capacitor field plate. In some embodiments, the semiconductor device includes a first ion-implanted region disposed between the first source / drain region and the channel region; and a second ion-implanted region disposed between the second source / drain region and the channel region. In some embodiments, the semiconductor device includes a spacer disposed between the gate electrode and the dielectric layer. In some embodiments, the semiconductor device includes an isolation region adjacent to the first source / drain region; and a doped region adjacent to the isolation region. In some embodiments, the semiconductor device includes a vertical interconnect channel electrically coupled to the doped region; and a body contact electrically coupled to the vertical interconnect channel. In some embodiments, the gate electrode has a first length, and the capacitor field plate has a second length different from the first length. In some embodiments, the second length is greater than the first length. In some embodiments, the capacitor field plate overlies the gate electrode. In some embodiments, the dielectric layer comprises an anti-corrosion protective oxide film. In some embodiments, the anti-corrosion protective oxide film comprises an oxide-silicon nitride-oxide stack. In some embodiments, the gate electrode, the dielectric layer, and the capacitor field plate form a capacitor. In some embodiments, the first source / drain region and the second source / drain region comprise a fin structure.

[0119] According to some embodiments, a method of forming a semiconductor device includes: forming a first dielectric layer over a gate electrode and a first source / drain region of a transistor; removing a first portion of the first dielectric layer over the first source / drain region to expose a first portion of the first source / drain region; forming a capacitor field plate over the first dielectric layer after removing the first portion of the first dielectric layer; and coupling a word line to the capacitor field plate. In some embodiments, removing the first portion of the first dielectric layer over the first source / drain region of the transistor includes: forming a photoresist layer over the gate electrode and the first source / drain region of the transistor; and etching the first dielectric layer while the photoresist layer is over a second portion of the gate electrode and the first source / drain region to remove the first portion of the first dielectric layer. In some embodiments, forming the capacitor field plate includes: forming the capacitor field plate overlying the gate electrode and the second portion of the first source / drain region. In some embodiments, the method of forming a semiconductor device includes: forming a second dielectric layer over the first source / drain region after removing the first portion of the first dielectric layer; and etching the second dielectric layer after removing the first portion of the first dielectric layer. In some embodiments, the first dielectric layer includes an anti-etching protective oxide film.

[0120] According to some embodiments, a semiconductor device includes a transistor comprising a first source / drain region coupled to a source line, a second source / drain region, a channel region located between the first source / drain region and the second source / drain region, and a gate electrode located above the channel region. According to some embodiments, the semiconductor device includes a capacitive field plate overlying the gate electrode and a word line coupled to and overlying the gate electrode. In some embodiments, the semiconductor device includes a dielectric layer located between the gate electrode and the capacitive field plate, wherein the word line is electrically coupled to the gate electrode via the capacitive field plate and the dielectric layer. In some embodiments, the capacitive field plate overlies the first source / drain region, and the capacitive field plate is separated from the first source / drain region by the dielectric layer.

[0121] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present disclosure.

[0122] Although the subject matter has been described in language specific to structural features or methodological acts, it should be understood that the subject matter of the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing at least some of the claims.

[0123] Various operations of the embodiments are provided herein. The order in which some or all of the operations are described should not be interpreted as implying that these operations are necessarily order-dependent. It should be understood that alternative orderings have the benefit of this specification. In addition, it should be understood that not all operations are necessarily present in every embodiment provided herein. In addition, it should be understood that not all operations are necessarily present in some embodiments.

[0124] It should be understood that, for example, for simplicity and ease of understanding, the layers, features, elements, etc. depicted herein are shown with specific dimensions (e.g., structural dimensions or orientations) relative to each other, and in some embodiments, the actual dimensions of the layers, features, elements, etc. are substantially different from the dimensions shown herein.

[0125] In addition, "exemplary" is used herein to mean serving as an example, instance, illustration, etc., and is not necessarily advantageous. As used in this application, "or" is intended to mean inclusive "or" rather than exclusive "or". In addition, unless otherwise specified or known from the context to be related to the singular form, "a and an" as used in this application and the appended claims are generally interpreted to mean "one or more". In addition, at least one of A and B and / or the like generally means A or B, or both A and B. In addition, with respect to the use of "including", "having / has / with" or its variants, these terms are intended to be inclusive in a manner similar to the term "including". In addition, unless otherwise specified, "first", "second" or similar terms are not intended to imply time, space, order, etc. On the contrary, these terms are only used as identifiers, names, etc. for features, elements, articles, etc. For example, the first element and the second element generally correspond to element A and element B, or two different or two identical elements, or the same element.

[0126] In addition, although the present disclosure has been shown and described with respect to one or more embodiments, other technical personnel in the art will think of equivalent changes and modifications based on reading and understanding of this specification and the drawings. The present disclosure includes all such modifications and changes and is only limited by the scope of the appended claims. In particular, for the various functions performed by the above-mentioned components (e.g., elements, resources, etc.), unless otherwise indicated, the terms used to describe these components are intended to correspond to any component (e.g., functionally equivalent) that performs the specified function of the described components, even if structurally not equivalent to the disclosed structure. In addition, although specific features of the present disclosure may have been disclosed for only one of several embodiments, these features may be combined with one or more other features of other embodiments, which may be desirable and advantageous for any given or specific application.

Claims

1. A semiconductor device comprising: Transistors, including: a first source / drain region; a second source / drain region; a channel region located between the first source / drain region and the second source / drain region; a gate electrode located above the channel region; and a spacer laterally adjacent to the gate electrode; a first dielectric layer overlying and directly contacting the gate electrode and laterally adjacent to the spacer, wherein the first dielectric layer has a first bottom surface, a second bottom surface, and a third bottom surface, the first bottom surface overlying the first source / drain region, the second bottom surface overlying the second source / drain region, the third bottom surface overlying the gate electrode, and the first bottom surface and the third bottom surface being separated by a distance in a vertical direction; a second dielectric layer laterally adjacent to the first dielectric layer, wherein the second dielectric layer is separated from the spacer by the first dielectric layer; a capacitor field plate positioned above the dielectric layer; and A word line is electrically coupled to the capacitive field plate.

2. The semiconductor device according to claim 1, comprising: a first ion implantation region disposed between the first source / drain region and the channel region; as well as The second ion implantation region is disposed between the second source / drain region and the channel region.

3. The semiconductor device according to claim 1, comprising: an isolation region, adjacent to the first source / drain region; as well as A doped region is adjacent to the isolation region.

4. The semiconductor device according to claim 3, comprising: a vertical interconnect channel electrically coupled to the doped region; as well as The main body contact is electrically coupled to the vertical inner connecting channel.

5. The semiconductor device according to claim 1, wherein: The gate electrode has a first length, and The capacitive field plate has a second length different from the first length. The semiconductor device according to claim 5 , wherein the second length is greater than the first length. The semiconductor device according to claim 1 , wherein the capacitor field plate overlies the gate electrode. 8 . The semiconductor device according to claim 1 , wherein the first dielectric layer comprises a resist protective oxide film. 9 . The semiconductor device according to claim 8 , wherein the anti-etching protective oxide film comprises an oxide-silicon nitride-oxide stack. 10 . The semiconductor device of claim 1 , wherein the gate electrode, the first dielectric layer, and the capacitive field plate constitute a capacitor. 11 . The semiconductor device according to claim 1 , wherein the first source / drain region and the second source / drain region comprise fin structures.

12. A method of forming a semiconductor device, comprising: forming a dielectric layer over the gate electrode and the first source / drain region of the transistor in direct contact with the gate electrode; removing a first portion of the dielectric layer over the first source / drain region to expose a first portion of the first source / drain region, wherein after removing the first portion of the dielectric layer, the dielectric layer has a first bottom surface and a third bottom surface, the first bottom surface overlying the first source / drain region, the third bottom surface overlying the gate electrode, and the first bottom surface and the third bottom surface being separated by a distance in a vertical direction; forming an interlayer dielectric layer overlying the first portion of the first source / drain region and laterally adjacent to the dielectric layer; forming a capacitor field plate over the dielectric layer after removing the first portion of the dielectric layer, wherein a top surface of the interlayer dielectric layer is connected to a top surface of the capacitor field plate; as well as A word line is coupled to the capacitive field plate.

13. The method of forming a semiconductor device according to claim 12, wherein removing the first portion of the dielectric layer above the first source / drain region of the transistor comprises: forming a photoresist layer over the gate electrode and the first source / drain region of the transistor; as well as The dielectric layer is etched to remove the first portion of the dielectric layer when the photoresist layer is located over the gate electrode and the second portion of the first source / drain region.

14. The method of forming a semiconductor device according to claim 12, wherein forming the capacitor field plate comprises: The capacitor field plate is formed to overly the gate electrode and a second portion of the first source / drain region.

15. The method of forming a semiconductor device according to claim 12, wherein the dielectric layer comprises a resist protective oxide film.

16. A semiconductor device comprising: Transistors, including: a first source / drain region coupled to a source line; a second source / drain region; a channel region located between the first source / drain region and the second source / drain region; and a gate electrode located above the channel region; a capacitor, wherein the capacitor is formed by the gate electrode, a dielectric layer over the gate electrode, and a capacitive field plate over the dielectric layer, wherein the dielectric layer has a first bottom surface, a second bottom surface, and a third bottom surface, the first bottom surface overlying the first source / drain region, the second bottom surface overlying the second source / drain region, the third bottom surface overlying the gate electrode, and the first bottom surface and the third bottom surface are separated by a distance in a vertical direction; an interlayer dielectric layer laterally adjacent to the dielectric layer and the capacitor field plate, wherein a top surface of the interlayer dielectric layer is connected to a top surface of the capacitor field plate; and A word line is coupled to and overlies the gate electrode. 17 . The semiconductor device of claim 16 , wherein the word line is electrically coupled to the gate electrode via the capacitive field plate and the dielectric layer.

18. The semiconductor device according to claim 17, wherein: The capacitor field plate overlies the first source / drain region, and The capacitive field plate is separated from the first source / drain region by the dielectric layer.

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