Integrated circuit device and method of manufacturing the same

Abstract

The present invention relates to an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes a channel layer in a channel hole penetrating a conductive layer and an insulating layer, a charge trapping pattern inside the channel hole between the conductive layer and the channel layer, and a dummy charge trapping pattern inside the channel hole between the insulating layer and the channel layer. To manufacture the integrated circuit device, a channel hole penetrating an insulating layer and a molding layer is formed. A molding recess connected to the channel hole is formed. An initial dielectric pattern is formed in the molding recess. The initial dielectric pattern is oxidized to form a first blocking dielectric pattern. A charge trapping layer is formed in the channel hole. The molding layer is removed to form a conductive space. A portion of the charge trapping layer is removed to form the charge trapping pattern and the dummy charge trapping pattern.

Description

Technical Field

[0001] This disclosure relates to integrated circuit devices and methods of manufacturing them, and more specifically, to integrated circuit devices including non-volatile vertical memory devices and methods of manufacturing such integrated circuit devices including non-volatile vertical memory devices. Background Technology

[0002] With the increasing capacity and high integration of integrated circuit devices, vertical memory devices have been developed, which have increased storage capacity by including multiple memory cells stacked on a substrate in a vertical direction. When the cell stacking density in the vertical direction is increased in a vertical memory device, the gap between adjacent cells in the vertical direction can be reduced. Therefore, the reliability of the integrated circuit device may be degraded due to cell interference caused by charge diffusion between adjacent cells. Summary of the Invention

[0003] On the one hand, an integrated circuit device with a structure that prevents cell interference attributable to charge diffusion between adjacent cells in the vertical direction and improves reliability in a highly scaled vertical memory device, even when the gap between adjacent cells is relatively small.

[0004] On the other hand, a method is provided for easily and efficiently manufacturing integrated circuit devices having a structure that prevents cell interference attributable to charge diffusion between adjacent cells in the vertical direction and improves reliability in highly scaled vertical memory devices, even when the gap between adjacent cells is relatively small.

[0005] According to one aspect of an embodiment, an integrated circuit device is provided, comprising: a conductive pattern extending on a substrate in a horizontal direction parallel to a surface of the substrate; an insulating layer extending on the substrate in the horizontal direction, adjacent to and parallel to the conductive pattern; a channel layer extending in a vertical direction perpendicular to the surface of the substrate in a channel hole penetrating the conductive pattern and the insulating layer; a charge storage pattern between the conductive pattern and the channel layer inside the channel hole; and a dummy charge storage pattern between the insulating layer and the channel layer inside the channel hole, the dummy charge storage pattern being separate from the charge storage pattern.

[0006] According to another aspect of one embodiment, an integrated circuit device is provided, comprising: a plurality of conductive patterns extending on a substrate in a horizontal direction parallel to a surface of the substrate, the plurality of conductive patterns overlapping each other in a vertical direction perpendicular to the surface; a plurality of insulating layers disposed between adjacent conductive patterns in the plurality of conductive patterns, the plurality of insulating layers extending in the horizontal direction; a channel layer extending in a vertical direction within a channel aperture penetrating the plurality of conductive patterns and the plurality of insulating layers; a plurality of charge trapping patterns spaced apart from each other within the channel aperture and interposed between the plurality of conductive patterns and the channel layer; and a plurality of dummy... The plurality of charge-trapping patterns are spaced apart from each other within the channel aperture and are also spaced apart from the plurality of charge-trapping patterns, the plurality of dummy charge-trapping patterns being interposed between the plurality of insulating layers and the channel layer; and the plurality of barrier dielectric patterns include a plurality of first pattern portions and a plurality of second pattern portions, the plurality of first pattern portions being respectively arranged between adjacent insulating layers in the plurality of insulating layers and interposed between the plurality of conductive patterns and the plurality of charge-trapping patterns, the plurality of second pattern portions surrounding corresponding portions of the plurality of conductive patterns and filling corresponding spaces between the plurality of charge-trapping patterns and the plurality of dummy charge-trapping patterns.

[0007] According to another aspect of one embodiment, an integrated circuit device is provided, comprising: a lower conductive line and an upper conductive line extending parallel to each other in a horizontal direction on a substrate; an insulating layer extending in a horizontal direction between the lower conductive line and the upper conductive line; a channel layer in a channel via extending in a vertical direction through the lower conductive line, the upper conductive line and the insulating layer; a lower charge trapping pattern in the channel via, the lower charge trapping pattern being interposed between the lower conductive line and the channel layer; an upper charge trapping pattern in the channel via, the upper charge trapping pattern being interposed between the upper conductive line and the channel layer and spaced apart from the lower charge trapping pattern in a vertical direction; and a dummy charge trapping pattern. A charge-capturing pattern is formed between the insulating layer and the channel layer. A dummy charge-capturing pattern is separated from the lower charge-capturing pattern by a lower partition space and from the upper charge-capturing pattern by an upper partition space. A lower first barrier dielectric pattern is formed between the lower conductive line and the channel layer. An upper first barrier dielectric pattern is formed between the upper conductive line and the channel layer. A lower second barrier dielectric pattern is formed between the lower conductive line and the lower first barrier dielectric pattern, and the lower second barrier dielectric pattern fills the lower partition space. An upper second barrier dielectric pattern is formed between the upper conductive line and the upper first barrier dielectric pattern, and the upper second barrier dielectric pattern fills the upper partition space.

[0008] According to another aspect of one embodiment, an integrated circuit device is provided, comprising: a plurality of conductive lines extending on a substrate in a horizontal direction parallel to a surface of the substrate, the plurality of conductive lines overlapping each other in a vertical direction perpendicular to the surface; a plurality of insulating layers disposed between adjacent conductive lines, the plurality of insulating layers extending in the horizontal direction; a channel layer extending vertically in a channel via penetrating the plurality of conductive lines and the plurality of insulating layers; a plurality of charge trapping patterns spaced apart from each other inside the channel via and interposed between the plurality of conductive lines and the channel layer; and a plurality of dummy charge trapping patterns spaced apart from each other inside the channel via. The plurality of dummy charge trapping patterns are spaced apart from the plurality of charge trapping patterns and are inserted between the plurality of insulating layers and the channel layer; a plurality of first barrier dielectric patterns are respectively arranged between adjacent insulating layers in the plurality of insulating layers and are inserted between the plurality of conductive lines and the plurality of charge trapping patterns; a plurality of second barrier dielectric patterns surround corresponding portions of the plurality of first barrier dielectric patterns and corresponding portions of the plurality of conductive lines, and include portions that fill the corresponding spaces between the plurality of charge trapping patterns and the plurality of dummy charge trapping patterns; and a tunneling dielectric layer is disposed between the plurality of first barrier dielectric patterns and the channel layer.

[0009] According to another aspect of one embodiment, a method of manufacturing an integrated circuit device is provided, the method comprising: forming a structure in which a plurality of insulating layers and a plurality of molding layers are alternately stacked on a substrate; forming a channel via penetrating the structure; forming a plurality of molding recesses connected to the channel via by removing portions of the plurality of molding layers through the channel via; forming a sacrificial layer and an initial dielectric pattern filling each of the plurality of molding recesses; forming a first barrier dielectric pattern by oxidizing the initial dielectric pattern; forming a charge storage layer in the channel via; forming a tunneling dielectric layer on the charge storage layer in the channel via; forming a channel layer on the tunneling dielectric layer in the channel via; forming conductive spaces by removing the plurality of molding layers, each conductive space between each of the plurality of insulating layers; forming a plurality of partition spaces by removing portions of the charge storage layer and the sacrificial layer through a respective conductive space, the plurality of partition spaces dividing the charge storage layer into a plurality of charge storage patterns and a plurality of dummy charge storage patterns; forming a second barrier dielectric pattern that fills the plurality of partition spaces and covers the inner walls of the respective conductive spaces; and forming a conductive pattern on the second barrier dielectric pattern in the respective conductive space.

[0010] According to another aspect of one embodiment, a method for manufacturing an integrated circuit device is provided, the method comprising: forming a structure in which a plurality of insulating layers and a plurality of molding layers are alternately stacked on a substrate; forming a channel via penetrating the structure; forming a plurality of molding recesses connected to the channel via by removing portions of the plurality of molding layers through the channel via; forming a first barrier dielectric pattern in each of the plurality of molding recesses; forming a charge trapping layer covering the first barrier dielectric pattern in the channel via; forming a conductive space exposing the first barrier dielectric pattern by removing the plurality of molding layers; forming a plurality of partition spaces by removing portions of the charge trapping layer through the conductive spaces, the plurality of partition spaces dividing the charge trapping layer into a plurality of charge trapping patterns and a plurality of dummy charge trapping patterns; forming a second barrier dielectric pattern that fills the plurality of partition spaces and covers the first barrier dielectric pattern in the conductive spaces; and forming conductive lines in the conductive spaces.

[0011] According to another aspect of one embodiment, a method of manufacturing an integrated circuit device is provided, the method comprising: forming a structure in which a plurality of insulating layers and a plurality of molding layers are alternately stacked on a substrate; forming a channel via penetrating the structure; forming a plurality of molding recesses connected to the channel via by removing portions of the plurality of molding layers through the channel via; forming a sacrificial layer and an initial dielectric pattern filling each of the plurality of molding recesses; forming a charge trapping layer covering the initial dielectric pattern in the channel via; forming a conductive space exposing the initial dielectric pattern by removing the plurality of molding layers; forming a plurality of partition spaces by removing portions of the charge trapping layer through the conductive spaces, the plurality of partition spaces dividing the charge trapping layer into a plurality of charge trapping patterns and a plurality of dummy charge trapping patterns; forming a first barrier dielectric pattern by oxidizing the initial dielectric pattern through the conductive spaces; forming a second barrier dielectric pattern that fills the plurality of partition spaces and covers the first barrier dielectric pattern in the conductive spaces; and forming conductive lines in the conductive spaces. Attached Figure Description

[0012] Various embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 It is an equivalent circuit diagram of the memory cell array of an integrated circuit device according to an embodiment;

[0014] Figure 2 It is a plan view of an integrated circuit device according to an implementation method;

[0015] Figure 3A It is along Figure 2 The sectional view taken by line X1-X1'. Figure 3B It is by Figure 3AAn enlarged sectional view of the dashed area indicated by BX1;

[0016] Figure 4A and Figure 4B This is a schematic cross-sectional view of an integrated circuit device according to other embodiments;

[0017] Figure 5 This is a schematic cross-sectional view of an integrated circuit device according to other embodiments;

[0018] Figure 6A This is a schematic cross-sectional view of an integrated circuit device according to other embodiments. Figure 6B It is by Figure 6A An enlarged sectional view of the dashed area indicated by BX2;

[0019] Figure 7 This is a schematic cross-sectional view of an integrated circuit device according to other embodiments;

[0020] Figure 8A This is a schematic cross-sectional view of an integrated circuit device according to other embodiments. Figure 8B It is by Figure 8A An enlarged sectional view of the dashed area indicated by BX3;

[0021] Figure 9 This is a schematic cross-sectional view of an integrated circuit device according to other embodiments;

[0022] Figure 10A and Figure 10B This is a schematic cross-sectional view of an integrated circuit device according to other embodiments;

[0023] Figure 11A It is a planar layout diagram of an integrated circuit device according to other embodiments. Figure 11B yes Figure 11A A schematic perspective view of one or more regions of an integrated circuit device shown. Figure 11C yes Figure 11A A schematic cross-sectional view of one or more regions of the integrated circuit device shown;

[0024] Figures 12A to 12M It is a cross-sectional view shown in process sequence for describing a method of manufacturing an integrated circuit device according to an embodiment;

[0025] Figures 13A to 13I This is a cross-sectional view shown in process sequence for describing a method of manufacturing an integrated circuit device according to other embodiments;

[0026] Figures 14A to 14D This is a cross-sectional view shown in process sequence for describing a method of manufacturing an integrated circuit device according to other embodiments;

[0027] Figure 15A and Figure 15B This is a cross-sectional view shown in process sequence for describing a method of manufacturing an integrated circuit device according to other embodiments;

[0028] Figure 16 This is a cross-sectional view shown in process sequence for describing a method of manufacturing an integrated circuit device according to other embodiments;

[0029] Figures 17A to 17C This is a cross-sectional view shown in process sequence for describing a method of manufacturing an integrated circuit device according to other embodiments; and

[0030] Figure 18A and Figure 18B This is a cross-sectional view shown in process sequence for describing a method of manufacturing an integrated circuit device according to other embodiments. Detailed Implementation

[0031] In the following description, various embodiments will be described in detail with reference to the accompanying drawings. Identical parts are indicated by the same reference numerals, and for the sake of brevity, their repeated descriptions will not be repeated.

[0032] Figure 1 This is an equivalent circuit diagram of the memory cell array (MCA) of an integrated circuit device according to an embodiment. The equivalent circuit diagram of a vertical NAND flash memory device with a vertical channel structure is shown below. Figure 1 As shown in the image.

[0033] Reference Figure 1 A memory cell array (MCA) may include multiple memory cell strings (MS). The MCA may include multiple bit lines BL1, BL2, ..., BLm (BL), multiple word lines WL1, WL2, ..., WLn-1 and WLn (WL), at least one string select line (SSL), at least one ground select line (GSL), and a common source line (CSL). The multiple memory cell strings (MS) may be formed between the multiple bit lines BL1, BL2, ..., BLm (BL) and the common source line (CSL).

[0034] Each of the multiple memory cell strings MS may include a string select transistor SST, a ground select transistor GST, and multiple memory cell transistors MC1, MC2, ..., MCn-1 and MCn. The drain region of the string select transistor SST may be connected to bit lines BL1, BL2, ... and BLm(BL), and the source region of the ground select transistor GST may be connected to a common source line CSL. The source regions of the multiple ground select transistors GST may be collectively connected to the common source line CSL.

[0035] The serial select transistor SST can be connected to at least one serial select line SSL, and the ground select transistor GST can be connected to at least one ground select line GSL. Multiple memory cell transistors MC1, MC2, ..., MCn-1 and MCn can be connected to multiple word lines WL1, WL2, ..., WLn-1 and WLn(WL), respectively.

[0036] Figure 2 This is a plan view of the integrated circuit device 100A according to the embodiment. Figure 3A It is along Figure 2 The sectional view taken by line X1-X1'. Figure 3B It is by Figure 3A An enlarged sectional view of the dashed area indicated by BX1.

[0037] Reference Figure 2 , Figure 3A and Figure 3B The integrated circuit device 100A may include a substrate 102 having an active region AC. A memory cell array MCA may be formed on the active region AC of the substrate 102. The memory cell array MCA may have a reference... Figure 1 The circuit structure described.

[0038] Substrate 102 may have a main surface 102M extending in the X and Y directions. According to an example embodiment, substrate 102 may include Si, Ge, or SiGe. According to other example embodiments, substrate 102 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0039] Multiple conductive lines CL can extend along the XY plane in a horizontal direction parallel to the main surface 102M on the substrate 102, and can be arranged to be separated from each other while overlapping each other in a vertical direction (Z direction) perpendicular to the main surface 102M of the substrate 102. In this specification, "conductive line CL" may be referred to as "conductive pattern CL," and it should be understood that "conductive line CL" and "conductive pattern CL" refer to the same component. Multiple insulating layers 110 can extend in a horizontal direction on the substrate 102. Each of the multiple insulating layers 110 can be arranged between each of the multiple conductive lines CL. In other words, the insulating layers 110 can alternate with the conductive lines CL, such as, for example... Figure 3A As shown.

[0040] Multiple channel vias CHH can be formed to penetrate multiple conductive lines CL and multiple insulating layers 110, and multiple channel structures CHS1 can extend in the multiple channel vias CHH in the vertical direction (Z direction). Each of the multiple channel structures CHS1 may include: a semiconductor pattern 120, contacting the substrate 102 and partially filling the channel via CHH; a channel layer 150, contacting the semiconductor pattern 120 and extending in the vertical direction (Z direction) in the channel via CHH; a buried insulating layer 156, filling the internal space of the channel layer 150; and a drain region 158, contacting the channel layer 150 and filling the upper entrance portion of the channel via CHH. According to an example embodiment, the channel layer 150 may have a cylindrical shape including an internal space, and the internal space of the channel layer 150 may be filled with the buried insulating layer 156. The channel layer 150 may include doped polysilicon or undoped polysilicon. The buried insulating layer 156 may include silicon oxide, silicon nitride, silicon oxide nitride, or a combination thereof. In some example embodiments, the buried insulating layer 156 may be omitted, in which case the channel layer 150 may have a pillar structure without internal space. The drain region 158 may include a doped polysilicon layer. Multiple drain regions 158 may be insulated from each other by an insulating pattern 114. The insulating pattern 114 may include an oxide layer, a nitride layer, or a combination thereof.

[0041] The multiple channel structure CHS1 may include multiple charge trapping patterns 134P and multiple dummy charge trapping patterns 134D. The terms "charge trapping pattern" and "dummy charge trapping pattern" may be used interchangeably with respect to the terms "charge storage pattern" and "dummy charge storage pattern," respectively, and the terms "charge trapping pattern" and "charge storage pattern" may be used to have the same meaning. The multiple charge trapping patterns 134P may be located in the channel via CHH between the conductive line CL and the channel layer 150 while being separated from each other. The multiple dummy charge trapping patterns 134D may be located between the insulating layer 110 and the channel layer 150, and may be separated from the multiple charge trapping patterns 134P. The multiple dummy charge trapping patterns 134D may be separated from each other, and a charge trapping pattern 134P may be between each of the multiple dummy charge trapping patterns 134D. In other words, the charge trapping patterns 134P may alternate with the dummy charge trapping patterns 134D. In some example embodiments, a plurality of charge trapping patterns 134P and a plurality of dummy charge trapping patterns 134D may extend in the channel via CHH along a straight line extending in a direction away from the substrate 102, and may be arranged alternately along said straight line. The plurality of charge trapping patterns 134P and the plurality of dummy charge trapping patterns 134D may have the same width in the horizontal direction. Each of the plurality of charge trapping patterns 134P and the plurality of dummy charge trapping patterns 134D may have a constant width in the horizontal direction along said straight line. For example, each of the plurality of charge trapping patterns 134P and the plurality of dummy charge trapping patterns 134D may have a width of about 3 nm to about 10 nm in the horizontal direction.

[0042] The minimum horizontal distance between the multiple charge trapping patterns 134P and the channel layer 150 can be substantially the same as the minimum horizontal distance between the multiple dummy charge trapping patterns 134D and the channel layer 150. Each of the multiple charge trapping patterns 134P and the multiple dummy charge trapping patterns 134D may include a silicon nitride layer.

[0043] As in Figure 3B As best shown, in the vertical direction, the length W1 of the charge trapping pattern 134P can be equal to or less than the length Lg1 of the conductive line CL, and equal to or greater than half the length Lg1 of the conductive line CL. The charge trapping pattern 134P may exclude the portion facing the conductive line CL closest to the insulating layer 110 at the corner. Therefore, the adverse effects on the charge trapping pattern 134P caused by the electric field concentrated at the corner of the conductive line CL can be minimized.

[0044] A plurality of first barrier dielectric patterns 132B may be disposed between a plurality of conductive lines CL and a channel structure CHS1. Each of the plurality of first barrier dielectric patterns 132B may be disposed between each of a plurality of insulating layers 110. In other words, a first barrier dielectric pattern 132B may be disposed between two adjacent insulating layers 110. At least a portion of each of the plurality of first barrier dielectric patterns 132B may overlap perpendicularly with the plurality of insulating layers 110. Each of the plurality of first barrier dielectric patterns 132B may be disposed between a conductive line CL and a charge trapping pattern 134P. The sidewalls of the plurality of first barrier dielectric patterns 132B facing the channel layer 150 may contact the sidewalls of the charge trapping pattern 134P facing the conductive line CL and may extend in a straight line relative to the sidewalls of the plurality of insulating layers 110 facing the channel layer 150. The plurality of first barrier dielectric patterns 132B may include a silicon oxide layer. The horizontal width of the plurality of first blocking dielectric patterns 132B can be from about 3 nm to about 10 nm, and in some embodiments, it can be, for example, from about 3 nm to about 5 nm.

[0045] A second barrier dielectric pattern 162 may be formed between each of the plurality of insulating layers 110, surrounding a portion of the first barrier dielectric pattern 132B and a portion of the conductive line CL. In other words, a portion of the second barrier dielectric pattern 162 may extend into the region between the charge trapping pattern 134P and the first barrier dielectric pattern 132B, and similarly, a portion of the second barrier dielectric pattern 162 may extend into the region between the dummy charge trapping pattern 134D and the insulating layer 110. The second barrier dielectric pattern 162 may include a first portion 162A between the conductive line CL and the insulating layer 110, a second portion 162B between the first barrier dielectric pattern 132B and the insulating layer 110, a third portion 162C between the charge trapping pattern 134P and the dummy charge trapping pattern 134D, and a fourth portion 162D between the conductive line CL and the first barrier dielectric pattern 132B. The third portion 162C can extend into the region between the charge-trapping pattern 134P and the first barrier dielectric pattern 132B, and into the region between the dummy charge-trapping portion 134D and the insulating layer 110, such that the charge-trapping pattern 134P does not include the portion of the corner closest to the insulating layer 110 facing the conductive line CL. In this configuration, the first portion 162A, the second portion 162B, and the third portion 162C can together form a T-shaped portion, such as... Figure 3BAs shown. The first portion 162A, the second portion 162B, the third portion 162C, and the fourth portion 162D of the second barrier dielectric pattern 162 can be integrally connected to each other. The third portion 162C of the second barrier dielectric pattern 162 can fill the corresponding space between the plurality of charge trapping patterns 134P and the plurality of dummy charge trapping patterns 134D, and can contact the charge trapping patterns 134P and the dummy charge trapping patterns 134D. The second barrier dielectric pattern 162 may include a silicon oxide layer, a high dielectric constant (high k) dielectric layer, or a combination thereof. The high k dielectric layer may have a higher dielectric constant than the silicon oxide layer. For example, the high k dielectric layer may include HfO2, Al2O3, or ZrO2, but the example embodiments are not limited thereto.

[0046] Charge trapping pattern 134P and tunneling dielectric layer 140 may be arranged in a channel via CHH between a plurality of first blocking dielectric patterns 132B and channel layer 150. Tunneling dielectric layer 140 may extend elongatedly between charge trapping pattern 134P and channel layer 150 and between dummy charge trapping pattern 134D and channel layer 150 in the direction in which channel layer 150 extends. Charge trapping pattern 134P may include a silicon oxide layer. Each of charge trapping pattern 134P and channel layer 150 may have a constant horizontal width in its longitudinal direction. For example, the horizontal width of each of charge trapping pattern 134P and channel layer 150 may be from about 3 nm to about 10 nm.

[0047] The width of each of the plurality of conductive lines CL and each of the plurality of insulating layers 110 in the first horizontal direction (X direction) can be defined by a plurality of word line cut regions WLC. Due to the plurality of word line cut regions WLC, the plurality of conductive lines CL can be arranged repeatedly at intervals from each other.

[0048] Multiple common source regions 160 may extend on the substrate 102 in a second horizontal direction (Y direction). The multiple common source regions 160 may be highly doped n-type impurity regions. A portion of the multiple word line cut regions (WLCs) may be filled with a common source pattern (CSP). The common source pattern (CSP) may be included within... Figure 1In the common source line CSL shown. The common source pattern CSP can extend long in a second horizontal direction (Y direction) over multiple common source regions 160. Insulating spacers 170 covering the sidewalls of the common source pattern CSP can be formed in the word line cut region WLC. The insulating spacers 170 can electrically insulate the common source pattern CSP from the multiple conductive lines CL. The common source pattern CSP and the insulating spacers 170 can be covered by a cover insulating layer 172. The common source pattern CSP can include a metal (such as tungsten, copper, or aluminum), a conductive metal nitride (such as titanium nitride or tantalum nitride), a transition metal (such as titanium or tantalum), or a combination thereof. Each of the insulating spacers 170 and the cover insulating layer 172 can include a silicon oxide layer, a silicon nitride layer, a silicon oxide nitride layer, or a combination thereof. A metal silicide layer (not shown) for reducing contact resistance can be interposed between the common source region 160 and the common source pattern CSP. For example, the metal silicide layer may include cobalt silicide, tungsten silicide, nickel silicide, etc.

[0049] Multiple conductive lines CL between two adjacent word line cutting regions WLC can form a reference. Figure 1 The description includes a ground select line GSL, multiple word lines WL1, WL2, ..., WLn-1 and WLn(WL), and a string select line SSL. The number of multiple conductive lines CL stacked on the substrate 102 in the Z direction can be selected in various ways. For example, the conductive line CL closest to the substrate 102 among the multiple conductive lines CL can form the ground select line GSL. Each of the two conductive lines furthest from the substrate 102 among the multiple conductive lines CL can form the string select line SSL. The string select line SSL may include portions spaced apart from each other and having string select line cut regions SSLC therebetween. The string select line cut regions SSLC may be filled with a string select line cut insulating layer 184. The string select line cut insulating layer 184 may include an oxide layer, a nitride layer, an air gap, or a combination thereof. The term "air gap" as used in this specification can refer to a space that includes air or other gases that may be present during the manufacturing process.

[0050] Multiple conductive lines CL may include: metals, such as tungsten, nickel, cobalt, or tantalum; metal silicides, such as tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide; doped polycrystalline silicon; or combinations thereof.

[0051] In a memory cell array (MCA), multiple bit lines BL can extend in a first horizontal direction (X direction) over multiple channel structures CHS1. Multiple bit line contact pads 182 can be located between the multiple channel structures CHS1 and the multiple bit lines BL. The drain regions 158 of the multiple channel structures CHS1 can be connected to a corresponding bit line BL among the multiple bit lines BL via the bit line contact pads 182. The multiple bit line contact pads 182 can be insulated from each other by an upper insulating layer 180. The upper insulating layer 180 may include an oxide layer, a nitride layer, or a combination thereof.

[0052] Figure 3A and Figure 3B The illustrated integrated circuit device 100A can have multiple charge trapping patterns 134P arranged in a channel via CHH. Therefore, compared to integrated circuit devices with multiple charge trapping patterns arranged outside the channel via CHH, as in related art, the integrated circuit device 100A can be more advantageously implemented to achieve a highly scaled integrated circuit device in both the horizontal and vertical directions. Furthermore, the multiple charge trapping patterns 134P can be separated from each other in the vertical direction (Z direction) within a single channel via CHH, with a dummy charge trapping pattern 134D and a second blocking dielectric pattern 162 between them. Therefore, even when a vertical memory device has relatively small gaps between cells adjacent to each other in the vertical direction, cell interference attributable to charge diffusion between adjacent cells can be prevented, and reliability can be improved.

[0053] Figure 4A This is a schematic cross-sectional view of an integrated circuit device 100B according to other embodiments. Figure 4A It shows the relationship with the Figure 3A The enlarged cross-sectional structure of the area corresponding to the dashed line area indicated by BX1.

[0054] Reference Figure 4A Integrated circuit device 100B can have the same Figure 3A and Figure 3B The integrated circuit device 100A shown has a substantially the same structure. However, in integrated circuit device 100B, each of the plurality of first blocking dielectric patterns 132B can be integrally connected to a second blocking dielectric pattern 162. The first blocking dielectric pattern 132B can be referred to as the "first pattern portion," and the second blocking dielectric pattern 162 can be referred to as the "second pattern portion." Figure 4AIn this illustration, for purposes of illustration, the first barrier dielectric pattern 132B and the second barrier dielectric pattern 162 are separated from each other by a virtual line indicated by the dashed line DL. However, in practice, the first barrier dielectric pattern 132B and the second barrier dielectric pattern 162 can be integrally formed such that the first barrier dielectric pattern 132B and the second barrier dielectric pattern 162 are connected to each other without a visual interface therebetween. In the integrated circuit device 100B, a plurality of first barrier dielectric patterns 132B and a plurality of second barrier dielectric patterns 162 may comprise the same material as each other. For example, each of the plurality of first barrier dielectric patterns 132B and a plurality of second barrier dielectric patterns 162 may comprise a silicon oxide layer. As another example, each of the plurality of first barrier dielectric patterns 132B and a plurality of second barrier dielectric patterns 162 may comprise a high-k dielectric layer having the same material as each other. The high-k dielectric layer may comprise HfO2, Al2O3, or ZrO2, but the example embodiment is not limited thereto.

[0055] Figure 4B This is a schematic cross-sectional view of an integrated circuit device 100C according to other embodiments. Figure 4B It shows the relationship with the Figure 3A The enlarged cross-sectional structure of the area corresponding to the dashed line area indicated by BX1.

[0056] Reference Figure 4B The integrated circuit device 100C can have the same characteristics as... Figure 3A and Figure 3B The integrated circuit device 100A shown has a structure substantially the same as that of the integrated circuit device 100C. However, the integrated circuit device 100C may include a second blocking dielectric pattern 164. The second blocking dielectric pattern 164 may have the same structure as the integrated circuit device 100C. Figure 3A and Figure 3B The second barrier dielectric pattern 162 shown has a substantially the same structure. However, the third portion 162C of the second barrier dielectric pattern 164 may include an air gap AG1. The cross-sectional shape of the air gap AG1 is not limited to... Figure 4B The shape shown. The air gap AG1 can have various widths and heights. Because the third portion 162C of the second blocking dielectric pattern 164 includes the air gap AG1, the dielectric constant between the multiple charge trapping patterns 134P can be reduced, and the effect of preventing cell interference caused by charge diffusion between adjacent cells in a vertical memory device can be improved. In some embodiments, in Figure 4B In the integrated circuit device 100C shown, the interface between the first barrier dielectric pattern 132B and the second barrier dielectric pattern 162 is shown. Figure 4A As described in the text, there may be no visual interface between the first barrier dielectric pattern 132B and the second barrier dielectric pattern 164. In other words, it is possible to... Figure 4Aand Figure 4B The implementation methods are combined and used together. In this case, the plurality of first barrier dielectric patterns 132B and the plurality of second barrier dielectric patterns 164 may comprise the same material as each other.

[0057] Figure 5 This is a schematic cross-sectional view of an integrated circuit device 100D according to other embodiments. Figure 5 It shows the relationship with the Figure 3A The enlarged cross-sectional structure of the area corresponding to the dashed line area indicated by BX1.

[0058] Reference Figure 5 The integrated circuit device 100D can have the same characteristics as... Figure 3A and Figure 3B The integrated circuit device 100A shown has a substantially the same structure. However, the integrated circuit device 100D may also include a plurality of third blocking dielectric patterns 166. Each of the plurality of third blocking dielectric patterns 166 may be located between the conductive line CL and the second blocking dielectric pattern 162. Each of the plurality of third blocking dielectric patterns 166 may include a silicon oxide layer, a high-k dielectric layer, or a combination thereof. The high-k dielectric layer may include HfO2, Al2O3, or ZrO2, but the example embodiment is not limited thereto. For example, the plurality of second blocking dielectric patterns 162 may include silicon oxide layers, and the plurality of third blocking dielectric patterns 166 may include high-k dielectric layers. As another example, the plurality of second blocking dielectric patterns 162 may include high-k dielectric layers, and the plurality of third blocking dielectric patterns 166 may include silicon oxide layers.

[0059] In the integrated circuit device 100D, the vertical length W1C of the charge trapping pattern 134P can be equal to or less than the vertical length Lg1C of the conductive line CL, and can be equal to or greater than half the length Lg1C of the conductive line CL.

[0060] Figure 5 An example is described in which integrated circuit device 100D has a relationship with Figure 3A and Figure 3B The integrated circuit device 100A shown has the same structure as the referenced one, but also includes a third barrier dielectric pattern 166. However, the example embodiment is not limited to this. For example, in some embodiments, the integrated circuit device 100D has the same structure as the referenced one. Figure 4B The described integrated circuit device 100C has the same structure and may also include Figure 5 The third barrier dielectric pattern 166 is shown. Furthermore, in some other embodiments, in... Figure 5 In the integrated circuit device 100D shown, similar to the reference... Figure 4AIn the described scenario, there may be no interface between the first barrier dielectric pattern 132B and the second barrier dielectric pattern 162. In this case, the plurality of first barrier dielectric patterns 132B and the plurality of second barrier dielectric patterns 162 may comprise the same material as each other. In other embodiments, the material may be... Figure 4A , Figure 4B and Figure 5 The features of the implementation methods are combined together.

[0061] Figure 6A This is a schematic cross-sectional view of an integrated circuit device 200A according to other embodiments. Figure 6B It is by Figure 6A An enlarged sectional view of the dashed area indicated by BX2. Figure 6A It shows the relationship with along Figure 2 The cross-sectional structure of the region corresponding to the section cut by line X1-X1'.

[0062] Reference Figure 6A and Figure 6B The integrated circuit device 200A can have the same characteristics as... Figure 3A and Figure 3B The integrated circuit device 100A shown has a basically the same structure. However, the integrated circuit device 200A may include multiple channel structures CHS2.

[0063] Multiple channel structures CHS2 can have the same characteristics as the reference. Figure 3A and Figure 3B The multiple channel structures CHS1 described are substantially identical in structure. However, the multiple channel structures CHS2 may include multiple charge trapping patterns 234P and multiple dummy charge trapping patterns 234D.

[0064] Multiple charge-capturing patterns 234P may be located in the channel via CHH between multiple conductive lines CL and the channel layer 150, while being separated from each other. Multiple dummy charge-capturing patterns 234D may be located between multiple insulating layers 110 and the channel layer 150, and may be separated from the multiple charge-capturing patterns 234P. The multiple dummy charge-capturing patterns 234D may be separated from each other, and a charge-capturing pattern 234P may be located between each of the multiple dummy charge-capturing patterns 234D. In some embodiments, the multiple charge-capturing patterns 234P and the multiple dummy charge-capturing patterns 234D may extend in the channel via CHH along a straight line extending in a direction away from the substrate 102, and may be arranged alternately along said straight line, respectively.

[0065] The plurality of charge-capturing patterns 234P may have a width in the horizontal direction different from the width of the plurality of dummy charge-capturing patterns 234D. In some embodiments, the sidewalls of the plurality of charge-capturing patterns 234P facing the channel layer 150 and the sidewalls of the plurality of dummy charge-capturing patterns 234D facing the channel layer 150 may extend in a straight line. In the horizontal direction, the minimum distance between the plurality of charge-capturing patterns 234P and the channel layer 150 may be substantially the same as the minimum distance between the plurality of dummy charge-capturing patterns 234D and the channel layer 150. The plurality of charge-capturing patterns 234P and the plurality of dummy charge-capturing patterns 234D may include a silicon nitride layer.

[0066] In the vertical direction, the length W2 of the charge trapping pattern 234P can be equal to or less than the length Lg2 of the conductive line CL, and equal to or greater than half the length Lg2 of the conductive line CL. The charge trapping pattern 234P may exclude the portion facing the corner of the conductive line CL, which is closest to the insulating layer 110. Therefore, the adverse effects on the charge trapping pattern 234P caused by the electric field concentrated at the corner of the conductive line CL can be minimized.

[0067] Multiple first barrier dielectric patterns 232B may be arranged between multiple conductive lines CL and the channel structure CHS2. Each of the multiple first barrier dielectric patterns 232B may be arranged between each of the multiple insulating layers 110. A portion of each of the multiple first barrier dielectric patterns 232B may overlap perpendicularly with the multiple insulating layers 110. Each of the multiple first barrier dielectric patterns 232B may be between the conductive line CL and the charge trapping pattern 234P. A portion of each of the multiple first barrier dielectric patterns 232B may protrude further toward the channel layer 150 than the sidewalls of the multiple insulating layers 110 facing the channel layer 150. The sidewalls of the multiple first barrier dielectric patterns 232B facing the channel layer 150 may be closer to the channel layer 150 than the sidewalls of the multiple insulating layers 110 facing the channel layer 150. The multiple first barrier dielectric patterns 232B may include a silicon oxide layer. The horizontal width of the plurality of first blocking dielectric patterns 232B can be from about 3 nm to about 10 nm, and in some embodiments, it can be, for example, from about 3 nm to about 5 nm.

[0068] A second barrier dielectric pattern 262 may be formed between each of the plurality of insulating layers 110, surrounding a portion of the first barrier dielectric pattern 232B and a portion of the conductive line CL. The second barrier dielectric pattern 262 may include a first portion 262A between the conductive line CL and the insulating layer 110, a second portion 262B between the first barrier dielectric pattern 232B and the insulating layer 110, a third portion 262C between the charge trapping pattern 234P and the dummy charge trapping pattern 234D, and a fourth portion 262D between the conductive line CL and the first barrier dielectric pattern 232B. The first portion 262A, the second portion 262B, the third portion 262C, and the fourth portion 262D of the second barrier dielectric pattern 262 may be integrally connected to each other. The third portion 262C of the second barrier dielectric pattern 262 may fill the corresponding space between the charge trapping pattern 234P and the dummy charge trapping pattern 234D. The second portion 262B of the second barrier dielectric pattern 262 may include a portion that vertically overlaps with the first barrier dielectric pattern 232B.

[0069] Charge trapping pattern 234P and tunneling dielectric layer 140 can be arranged between multiple first barrier dielectric patterns 232B and channel layer 150.

[0070] According to the example implementation, similar to the reference... Figure 5 In the described scenario, the integrated circuit device 200A may also include a plurality of third blocking dielectric patterns 166. Each of the plurality of third blocking dielectric patterns 166 may be located between the conductive line CL and the second blocking dielectric pattern 262.

[0071] In some implementations, in Figure 6A and Figure 6B In the integrated circuit device 200A shown, the interface between the first barrier dielectric pattern 132B and the second barrier dielectric pattern 162 is as follows: Figure 4A As described in the text, there may be no visual interface between the first barrier dielectric pattern 232B and the second barrier dielectric pattern 262. In this case, the plurality of first barrier dielectric patterns 232B and the plurality of second barrier dielectric patterns 262 may comprise the same material as each other. Similarly, in some other embodiments, it may be provided that... Figures 4A-6B Various combinations of features of the embodiments shown.

[0072] Figure 7 This is a schematic cross-sectional view of an integrated circuit device 200B according to other embodiments. Figure 7 It shows the relationship with the Figure 6A The enlarged cross-sectional structure of the area corresponding to the dashed line area indicated by BX2.

[0073] Reference Figure 7 The integrated circuit device 200B can have the same characteristics as... Figure 6A and Figure 6B The integrated circuit device 200A shown has a structure substantially the same as that of the integrated circuit device 200B. However, the integrated circuit device 200B may include a second blocking dielectric pattern 264. The second blocking dielectric pattern 264 may have the same structure as the integrated circuit device 200B. Figure 6A and Figure 6B The second barrier dielectric pattern 262 shown has a substantially the same structure. However, the third portion 262C of the second barrier dielectric pattern 264 may include an air gap AG2. The cross-sectional shape of the air gap AG2 is not limited to... Figure 7 The shape shown. The air gap AG2 can have various widths and heights. Because the third portion 262C of the second blocking dielectric pattern 264 includes the air gap AG2, the dielectric constant between the multiple charge trapping patterns 234P can be reduced, and the effect of preventing cell interference caused by charge diffusion between adjacent cells in a vertical memory device can be improved.

[0074] exist Figure 7 In the integrated circuit device 200B shown, the interface between the first barrier dielectric pattern 132B and the second barrier dielectric pattern 162 is as follows: Figure 4A As described in the text, there may be no visual interface between the first barrier dielectric pattern 232B and the second barrier dielectric pattern 264. In this case, the plurality of first barrier dielectric patterns 232B and the plurality of second barrier dielectric patterns 264 may comprise the same material as each other. Similarly, in some other embodiments, it may be provided that... Figures 4A-7 Various combinations of features of the embodiments shown.

[0075] Figure 8A This is a schematic cross-sectional view of an integrated circuit device 300A according to other embodiments. Figure 8B It is by Figure 8A An enlarged sectional view of the dashed area indicated by BX3. Figure 8A It shows the relationship with along Figure 2 The cross-sectional structure of the region corresponding to the section cut by line X1-X1'.

[0076] Reference Figure 8A and Figure 8B The integrated circuit device 300A can have the same characteristics as... Figure 6A and Figure 6B The integrated circuit device 200A shown has a basically the same structure. However, the integrated circuit device 300A may include multiple channel structures CHS3.

[0077] Multiple channel structures CHS3 can have the same characteristics as the reference. Figure 6A and Figure 6BThe multiple channel structures CHS2 described are substantially identical in structure. However, the multiple channel structures CHS3 may include multiple charge trapping patterns 334P and multiple dummy charge trapping patterns 334D.

[0078] Multiple charge trapping patterns 334P can be located in the channel via CLH between the conductive line CL and the channel layer 150, and are separated from each other. Multiple dummy charge trapping patterns 334D can be located between multiple insulating layers 110 and the channel layer 150, and can be separated from the multiple charge trapping patterns 334P. The multiple dummy charge trapping patterns 334D can be separated from each other. A charge trapping pattern 334P can be located between each of the multiple dummy charge trapping patterns 334D. The multiple charge trapping patterns 334P can extend in the channel via CHH along a first straight line extending in a direction away from the substrate 102, and the multiple dummy charge trapping patterns 334D can extend in the channel via CHH along a second straight line extending in a direction away from the substrate 102, wherein the first straight line and the second straight line may not meet each other in the channel via CHH. The multiple charge trapping patterns 334P and the multiple dummy charge trapping patterns 334D can be arranged alternately in the channel via CHH in a direction away from the substrate 102.

[0079] Multiple charge-capturing patterns 334P and multiple dummy charge-capturing patterns 334D may have the same width in the horizontal direction. The sidewalls of the multiple charge-capturing patterns 334P facing the channel layer 150 may be closer to the channel layer 150 than the sidewalls of the multiple dummy charge-capturing patterns 334D facing the channel layer 150. Therefore, the minimum horizontal distance between the multiple charge-capturing patterns 334P and the channel layer 150 may be less than the minimum horizontal distance between the multiple dummy charge-capturing patterns 334D and the channel layer 150. The multiple charge-capturing patterns 334P and the multiple dummy charge-capturing patterns 334D may include a silicon nitride layer.

[0080] In the vertical direction, the length W3 of the charge trapping pattern 334P can be equal to or less than the length Lg3 of the conductive line CL, and equal to or greater than half the length Lg3 of the conductive line CL. The charge trapping pattern 334P may exclude the portion facing the corner of the conductive line CL, which is closest to the insulating layer 110. Therefore, the adverse effects on the charge trapping pattern 334P caused by the electric field concentrated at the corner of the conductive line CL can be minimized.

[0081] A second barrier dielectric pattern 362 may be formed between each of the plurality of insulating layers 110, surrounding a portion of the first barrier dielectric pattern 232B and a portion of the conductive line CL. The second barrier dielectric pattern 362 may include a first portion 362A between the conductive line CL and the insulating layer 110, a second portion 362B between the first barrier dielectric pattern 232B and the insulating layer 110, a third portion 362C between the charge trapping pattern 334P and the dummy charge trapping pattern 334D, and a fourth portion 362D between the conductive line CL and the first barrier dielectric pattern 232B. The first portion 362A, the second portion 362B, the third portion 362C, and the fourth portion 362D of the second barrier dielectric pattern 362 may be integrally connected to each other. The third portion 362C of the second barrier dielectric pattern 362 may fill the corresponding space between the plurality of charge trapping patterns 334P and the plurality of dummy charge trapping patterns 334D.

[0082] Multiple charge trapping patterns 334P and tunneling dielectric layers 340 can be arranged between multiple first barrier dielectric patterns 232B and channel layer 150. Figure 8A and Figure 8B In the illustrated embodiment, the tunneling dielectric layer 340 may have a variable width in the channel hole CHH in a direction away from the substrate 102. In the horizontal direction, the width of the portion of the tunneling dielectric layer 340 between the charge trapping pattern 334P and the channel layer 150 may be smaller than the width of the portion of the tunneling dielectric layer 340 between the dummy charge trapping pattern 334D and the channel layer 150. The sidewalls of the tunneling dielectric layer 340 facing the channel layer 150 may extend straight in the longitudinal direction of the channel hole CHH. The sidewalls of the tunneling dielectric layer 340 facing the plurality of charge trapping patterns 334P and the plurality of dummy charge trapping patterns 334D may have uneven portions in the longitudinal direction of the channel hole CHH. For example, one end of the uneven portion may begin at the top of the dummy charge trapping pattern 334D, and the other end of the uneven portion may end at the top of the next dummy charge trapping pattern 334D in a direction extending away from the substrate 102. The tunneling dielectric layer 340 may include a silicon oxide layer.

[0083] According to the example implementation, similar to the reference... Figure 5 In the described scenario, the integrated circuit device 300A may also include a plurality of third blocking dielectric patterns 166. Each of the plurality of third blocking dielectric patterns 166 may be located between the conductive line CL and the second blocking dielectric pattern 362.

[0084] In some example implementations, in Figure 8A and Figure 8BIn the integrated circuit device 300A shown, the interface reference between the first barrier dielectric pattern 132B and the second barrier dielectric pattern 162 is shown. Figure 4A As described, there may be no visual interface between the first barrier dielectric pattern 232B and the second barrier dielectric pattern 362. In this case, the plurality of first barrier dielectric patterns 232B and the plurality of second barrier dielectric patterns 362 may comprise the same material as each other.

[0085] Figure 9 This is a schematic cross-sectional view of an integrated circuit device 300B according to other embodiments. Figure 9 It shows the relationship with the Figure 8A The enlarged cross-sectional structure of the area corresponding to the dashed area indicated by BX3.

[0086] Reference Figure 9 The integrated circuit device 300B can have the same characteristics as... Figure 8A and Figure 8B The integrated circuit device 300A shown has a structure substantially the same as that of the integrated circuit device 300B. However, the integrated circuit device 300B may include a second blocking dielectric pattern 364. The second blocking dielectric pattern 364 may have the same structure as the integrated circuit device 300B. Figure 8A and Figure 8B The second barrier dielectric pattern 362 shown has a substantially the same structure. However, the third portion 362C of the second barrier dielectric pattern 364 may include an air gap AG3. The cross-sectional shape of the air gap AG3 is not limited to... Figure 9 The shape shown. The air gap AG3 can have various widths and heights. Because the third portion 362C of the second blocking dielectric pattern 364 includes the air gap AG3, the dielectric constant between the multiple charge trapping patterns 334P can be reduced, and the effect of preventing cell interference caused by charge diffusion between adjacent cells in a vertical memory device can be improved.

[0087] exist Figure 9 In the integrated circuit device 300B shown, the interface between the first barrier dielectric pattern 132B and the second barrier dielectric pattern 162 is shown. Figure 4A As described in the text, there may be no visual interface between the first barrier dielectric pattern 232B and the second barrier dielectric pattern 364. In this case, the plurality of first barrier dielectric patterns 232B and the plurality of second barrier dielectric patterns 364 may comprise the same material as each other. Similarly, in some other embodiments, it may be provided that... Figures 4A-9 Various combinations of features of the embodiments shown.

[0088] Figure 10A This is a schematic cross-sectional view of an integrated circuit device 400A according to other embodiments. Figure 10A It shows the relationship with Figure 3A The enlarged cross-sectional structure of the region corresponding to the region.

[0089] Reference Figure 10A The integrated circuit device 400A can have Figure 1 The equivalent circuit of the memory cell array MCA of the integrated circuit device 100A shown is illustrated, and it can have the same... Figure 3A and Figure 3B The integrated circuit device 100A shown has a basically the same structure. Specifically, it forms... Figure 1 The multiple word lines WL1, WL2, ..., WLn-1 and WLn(WL) in the text can have the following characteristics: Figure 3A and Figure 3B The structure shown. However, in the integrated circuit device 400A, a structure is formed... Figure 1 A portion of at least one of the ground select line GSL and the string select line SSL may include conductive line CL4, instead of Figure 3A and Figure 3B The conductive line CL4 is shown. The vertical thickness of the conductive line CL4 can be greater than... Figure 3A and Figure 3B The vertical thickness of the conductive line CL is shown. For example, the vertical thickness of the conductive line CL4 in integrated circuit device 400A can be the conductive line CL that forms multiple word lines WL1, WL2, ..., WLn-1 and WLn(WL) (see...). Figure 3A and Figure 3B It must be at least twice the vertical thickness of the material. However, it is not limited to this.

[0090] Integrated circuit device 400A may include a channel structure CHS4, a portion of which penetrates a conductive line CL4. The channel structure CHS4 may include a channel layer 450 extending vertically within a channel via CHH and a buried insulating layer 456 filling the internal space of the channel layer 450. A first barrier dielectric pattern 432B may be disposed between the conductive line CL4 and the channel structure CHS4. The first barrier dielectric pattern 432B may be disposed between two adjacent insulating layers 110, and at least a portion of the first barrier dielectric pattern 432B may perpendicularly overlap with the insulating layer 110. The first barrier dielectric pattern 432B may have concave sidewalls 432BS recessed relative to the channel layer 450. The horizontal width of the first barrier dielectric pattern 432B may be from about 3 nm to about 10 nm, for example, from about 3 nm to about 5 nm.

[0091] A charge trapping pattern 434P and a tunneling dielectric layer 440 may be disposed between a first blocking dielectric pattern 432B and a channel layer 450. The tunneling dielectric layer 440 may extend in the direction in which the channel layer 450 extends, between the charge trapping pattern 434P and the channel layer 450, and between the dummy charge trapping pattern 134D and the channel layer 450. The charge trapping pattern 434P may include a silicon oxide layer. Each of the charge trapping pattern 434P, the tunneling dielectric layer 440, and the channel layer 450 may have a constant horizontal width in its longitudinal direction. In the vertical direction, the length W4 of the charge trapping pattern 434P may be equal to or less than the length Lg4 of the conductive line CL4, and equal to or greater than half the length Lg4 of the conductive line CL4. The charge trapping pattern 434P may exclude the corner portion facing the conductive line CL4, the corner being closest to the insulating layer 110. Therefore, the adverse effects on the charge trapping pattern 434P caused by the electric field concentrated at the corner of the conductive line CL4 can be minimized.

[0092] The charge trapping pattern 434P may include a convex sidewall 434PS facing the concave sidewall 432BS of the first barrier dielectric pattern 432B. The convex sidewall 434PS of the charge trapping pattern 434P may contact the concave sidewall 432BS of the first barrier dielectric pattern 432B. The tunneling dielectric layer 440 may have a convex sidewall 440S facing the concave sidewall 432BS of the first barrier dielectric pattern 432B. The channel layer 450 may have a convex sidewall 450S facing the concave sidewall 432BS of the first barrier dielectric pattern 432B. The buried insulating layer 456 may have a convex sidewall 456S facing the concave sidewall 432BS of the first barrier dielectric pattern 432B.

[0093] The conductive line CL4 may be surrounded by a second barrier dielectric pattern 462. The second barrier dielectric pattern 462 may include a first portion 462A between the conductive line CL4 and the insulating layer 110, a second portion 462B between the first barrier dielectric pattern 432B and the insulating layer 110, a third portion 462C between the charge trapping pattern 434P and the dummy charge trapping pattern 134D, and a fourth portion 462D between the conductive line CL4 and the first barrier dielectric pattern 432B. The first portion 462A, the second portion 462B, the third portion 462C, and the fourth portion 462D of the second barrier dielectric pattern 462 may be integrally connected to each other. The third portion 462C of the second barrier dielectric pattern 462 may fill the corresponding spaces between the plurality of charge trapping patterns 434P and the plurality of dummy charge trapping patterns 134D. More detailed structures of each of the first barrier dielectric pattern 432B, charge trapping pattern 434P, tunneling dielectric layer 440, channel layer 450, buried insulating layer 456, second barrier dielectric pattern 462, and conductive line CL4 are related to... Figure 3A and Figure 3B The first barrier dielectric pattern 132B, charge trapping pattern 134P, tunneling dielectric layer 140, channel layer 150, buried insulating layer 156, second barrier dielectric pattern 162, and conductive line CL are described in the same way, so for the sake of brevity, their repeated descriptions are omitted.

[0094] exist Figure 10A In the integrated circuit device 400A shown, the interface between the first barrier dielectric pattern 132B and the second barrier dielectric pattern 162 is as follows: Figure 4A As described in the text, there may be no visual interface between the first barrier dielectric pattern 432B and the second barrier dielectric pattern 462. In this case, the plurality of first barrier dielectric patterns 432B and the plurality of second barrier dielectric patterns 462 may comprise the same material as each other.

[0095] Figure 10B This is a schematic cross-sectional view of an integrated circuit device 400B according to other embodiments.

[0096] Reference Figure 10B The integrated circuit device 400B can have the same characteristics as... Figure 10A The integrated circuit device 400A shown has a structure substantially the same as that of the integrated circuit device 400B. However, the integrated circuit device 400B may include a second blocking dielectric pattern 464. The second blocking dielectric pattern 464 may have the same structure as the integrated circuit device 400B. Figure 10A The second barrier dielectric pattern 462 shown has a substantially the same structure. However, the third portion 462C of the second barrier dielectric pattern 464 may include an air gap AG4. The cross-sectional shape of the air gap AG4 is not limited to... Figure 10A The shape shown. The air gap AG4 can have various widths and heights. Because the third portion 462C of the second blocking dielectric pattern 464 includes the air gap AG4, the dielectric constant between the multiple charge trapping patterns 434P can be reduced, and the effect of preventing cell interference caused by charge diffusion between adjacent cells in a vertical memory device can be improved.

[0097] exist Figure 10B In the integrated circuit device 400B shown, the interface between the first barrier dielectric pattern 132B and the second barrier dielectric pattern 162 is as follows: Figure 4A As described, there may be no visual interface between the first barrier dielectric pattern 432B and the second barrier dielectric pattern 464. In this case, the plurality of first barrier dielectric patterns 432B and the plurality of second barrier dielectric patterns 464 may comprise the same material as each other. Similarly, in some other embodiments, it may be provided that... Figures 4A-10B Various combinations of features of the embodiments shown.

[0098] Figure 11A This is a planar layout diagram of an integrated circuit device 500 according to other embodiments.

[0099] Reference Figure 11A The integrated circuit device 500 may include a memory cell array region 512, a first peripheral circuit region 514, a second peripheral circuit region 516, and a bonding pad region 518. The memory cell array region 512 may include a reference... Figure 1 The described structure comprises multiple memory cell arrays (MCAs). A first peripheral circuit region 514 and a second peripheral circuit region 516 may include a control unit that controls data input to or output from the memory cell array region 512. Peripheral circuitry driving the vertical memory cells included in the memory cell array region 512 may be arranged in the first peripheral circuit region 514 and the second peripheral circuit region 516.

[0100] The first peripheral circuitry region 514 can be arranged to overlap vertically with the memory cell array region 512, thereby reducing the planar size of the chip including the integrated circuit device 500. In some embodiments, the peripheral circuitry arranged in the first peripheral circuitry region 514 can be circuitry capable of high-speed processing of data input to / output from the memory cell array region 512. For example, the peripheral circuitry arranged in the first peripheral circuitry region 514 may include page buffers, latch circuits, cache circuits, column decoders, sense amplifiers, or data input / output circuits.

[0101] The second peripheral circuit region 516 can be arranged below the memory cell array region 512 to avoid overlapping with the memory cell array region 512 and the first peripheral circuit region 514. The peripheral circuitry formed in the second peripheral circuit region 516 can be, for example, a line decoder. In some embodiments, with... Figure 11A Unlike the example shown, at least a portion of the second peripheral circuit region 516 may be on one side of the memory cell array region 512.

[0102] Bonding pad area 518 may be formed on the other side of memory cell array area 512. Bonding pad area 518 may be an area in which wiring for word line connections from each of the vertical memory cells in memory cell array area 512 is formed.

[0103] Figure 11B and Figure 11C They are Figure 11A Schematic perspective view and schematic cross-sectional view of a region of the integrated circuit device 500 shown. Figure 11B and Figure 11C In, with Figures 1 to 3B The same reference numerals in the accompanying drawings indicate the same components, and for the sake of brevity, their detailed descriptions will not be repeated.

[0104] Reference Figure 11B and Figure 11C The integrated circuit device 500 may include a first peripheral circuit region 514 formed at a first horizontal level on a substrate 502 and a memory cell array region 512 formed at a second horizontal level on the substrate 502, wherein the second horizontal level is higher than the first horizontal level. Here, the term "horizontal" means relative to the substrate 502 in the vertical direction ( Figure 11B and Figure 11C The height in the Z direction (of the substrate). In other words, the first level on substrate 502 is closer to substrate 502 than the second level.

[0105] Substrate 502 may have a main surface 502M extending in both the X and Y directions. More detailed aspects of substrate 502 are shown in the reference. Figure 3A and Figure 3B The details of the substrate 102 described are substantially the same. A peripheral active region PAC can be defined on the substrate 502 by a device isolation layer 504. A plurality of transistors TR5 forming a first peripheral circuit region 514 can be formed on the peripheral active region PAC of the substrate 502. Each of the plurality of transistors TR5 may include a peripheral gate PG and peripheral source / drain regions PSD formed on both sides of the peripheral gate PG in the peripheral active region PAC. In some embodiments, unit devices such as resistors, capacitors, etc., may also be arranged in the first peripheral circuit region 514. A peripheral interlayer insulating layer 508 can be formed on the plurality of transistors TR5. The peripheral interlayer insulating layer 508 may include silicon oxide, SiON, SiOCN, etc.

[0106] The first peripheral circuit region 514 may include a plurality of peripheral circuit routing layers MTL5 and a plurality of peripheral circuit contacts MC5. Some of the plurality of peripheral circuit routing layers MTL5 may be configured to be electrically connected to a plurality of transistors TR5. The plurality of peripheral circuit contacts MC5 may be configured to interconnect some of the peripheral circuit routing layers selected from the plurality of peripheral circuit routing layers MTL5. The plurality of peripheral circuit routing layers MTL5 and the plurality of peripheral circuit contacts MC5 may be covered by a peripheral interlayer insulating layer 508.

[0107] Each of the multiple peripheral circuit wiring layers MTL5 and the multiple peripheral circuit contacts MC5 may include a metal, a conductive metal nitride, a metal silicide, or a combination thereof. For example, each of the multiple peripheral circuit wiring layers MTL5 and the multiple peripheral circuit contacts MC5 may include a conductive material such as tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, nickel silicide, etc. Figure 11CThe diagram illustrates a three-layer wiring structure for multiple peripheral circuit wiring layers (MTL5) in the vertical direction (Z direction). However, the inventive concept is not limited to this. Figure 11C The example shown. For instance, multiple peripheral circuit routing layers MTL5 can have multi-layer routing structures, such as two-layer routing structures or four-layer or higher routing structures.

[0108] A semiconductor layer 520 covering the peripheral interlayer insulating layer 508 can be formed on the first peripheral circuit region 514. The semiconductor layer 520 may include Si, Ge, or a combination thereof. The semiconductor layer 520 may include a doped semiconductor or an undoped semiconductor. The semiconductor layer 520 may have a single-crystal structure, an amorphous structure, or a polycrystalline structure. Multiple common source regions 572 can be formed on the semiconductor layer 520. A more detailed structure of the multiple common source regions 572 is shown in the reference. Figure 3A and Figure 3B The structures of the common source regions 160 described are basically the same. Multiple common source regions 572 can be formed in the semiconductor layer 520 by doping with impurities.

[0109] The memory cell array region 512 can be formed on the semiconductor layer 520. The memory cell array region 512 can have the same characteristics as the reference layer. Figure 3A and Figure 3B The memory cell array MCA of the described integrated circuit device 100A has a structure that is basically the same. Specifically, the memory cell array region 512 is similar in structure to... Figure 1 The parts corresponding to multiple word lines WL1, WL2, ..., WLn-1 and WLn(WL) in the text can have the same characteristics as... Figure 3A and Figure 3B The structure shown is the same. However, in integrated circuit device 500, it is the same as... Figure 1 The ground select line GSL and the serial select line SSL corresponding parts can have the same characteristics as the reference. Figure 10A The structures described are the same.

[0110] More specifically, in integrated circuit device 500, with Figure 1 The portions corresponding to the multiple word lines WL1, WL2, ..., WLn-1 and WLn(WL) in the text may include Figure 3A and Figure 3B , Figure 6A and Figure 6B or Figure 8A and Figure 8B The conductive line CL shown is... Figure 1 The parts corresponding to the ground select line GSL and the serial select line SSL in the code can include Figure 10AThe conductive line CL4 is shown. Integrated circuit device 500 may include a plurality of conductive lines CL, a plurality of conductive lines CL4, and a channel structure CHS5 penetrating the plurality of conductive lines CL and CL4. A portion of the channel structure CHS5 (which penetrates the plurality of conductive lines CL) may have the same characteristics as referenced. Figure 3A and Figure 3B The described channel structure CHS1 has the same structure and can be combined in other embodiments. Figures 4A-9 The illustrated example embodiment features a portion of the channel structure CHS5 (which penetrates multiple conductive lines CL4) that may have the same characteristics as the referenced embodiment. Figure 10A or Figure 10B The channel structure described is the same as that of CHS4.

[0111] Next, a method for manufacturing an integrated circuit device according to an embodiment will be described in detail.

[0112] Figures 12A to 12M This is a cross-sectional view shown in process sequence for describing a method of manufacturing an integrated circuit device 100A according to an embodiment. The manufacturing reference will be described. Figure 3A and Figure 3B An example method for describing the integrated circuit device 100A. Figures 12A to 12M The process sequence is shown, along with the process flow. Figure 3A The enlarged cross-sectional structure of the area corresponding to the dashed area indicated by Q1.

[0113] Reference Figure 12A An active region AC can be defined on a substrate 102, and multiple insulating layers 110 and multiple molding layers ML can be alternately stacked on the substrate 102. The lowermost insulating layer 110L, which is in contact with the substrate 102, can have a smaller thickness D1 than the other insulating layers 110. The multiple insulating layers 110 can include silicon oxide layers, and the multiple molding layers ML can include silicon nitride layers.

[0114] Multiple molding layers ML can provide space for the formation of ground select line GSL, multiple word lines WL, and multiple string select lines SSL in subsequent processes. The first molding layer ML, the one closest to the substrate 102 among the multiple molding layers ML, can provide space for the formation of the ground select line GSL. The insulating layer 110 that contacts the upper surface of the first molding layer ML can have a greater thickness D2 than the other insulating layers 110. Each of the multiple insulating layers 110 and the multiple molding layers ML can be formed using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or atomic layer deposition (ALD).

[0115] Reference Figure 12BAfter forming an insulating pattern 114 on the uppermost insulating layer 110 among multiple insulating layers 110, anisotropic etching can be performed on the multiple insulating layers 110 and multiple molding layers ML by using the insulating pattern 114 as an etching mask, thereby forming a channel hole CHH that exposes the substrate 102.

[0116] The horizontal width of the channel hole CHH can decrease towards the substrate 102. In other words, the horizontal width of the channel hole CHH can gradually decrease as the distance from the substrate 102 decreases. The insulating pattern 114 can include a single layer or multiple layers, which include oxide layers, nitride layers, or combinations thereof.

[0117] Reference Figure 12C A semiconductor pattern 120 partially filling the channel hole CHH can be formed by performing a selective epitaxial growth process starting from the bottom of the channel hole CHH. The semiconductor pattern 120 may include a doped semiconductor layer, such as a doped Si layer or a doped Ge layer.

[0118] A portion of each of the plurality of molded layers ML can be selectively trimmed from the sidewalls exposed by the channel hole CHH of each of the plurality of molded layers ML. Thus, a plurality of molded notches MLA connected to the channel hole CHH can be formed between each of the plurality of insulating layers 110. The horizontal width WH1 of each of the plurality of molded notches MLA can be from about 3 nm to about 10 nm. In some embodiments, the horizontal width WH1 can be, for example, from about 3 nm to about 5 nm.

[0119] An etching process for selectively etching multiple molding layers ML and multiple insulating layers 110 can be used to trim the multiple molding layers ML. For example, when the multiple molding layers ML comprise silicon nitride layers and the multiple insulating layers 110 comprise silicon oxide layers, etchants such as ammonia-based etchants, phosphoric acid-based etchants, sulfuric acid-based etchants, acetic acid-based etchants, or combinations thereof, can be used to selectively trim portions of each of the multiple molding layers ML. The process of trimming the multiple molding layers ML can be performed while the semiconductor pattern 120 is covered by a protective layer (not shown).

[0120] Reference Figure 12D According to Figure 12C The resulting structure has a sacrificial layer 130 and an initial barrier insulating layer 132 formed sequentially.

[0121] The sacrificial layer 130 can be formed conformally covering the surfaces exposed through the channel via CHH and the plurality of molded notches MLAs. The sacrificial layer 130 can comprise the same material as the plurality of molded layers ML, or a material having the same or substantially the same etch properties as the material of the plurality of molded layers ML. For example, the sacrificial layer 130 can comprise a silicon nitride layer. The sacrificial layer 130 can be formed with a horizontal width of about 3 nm to about 10 nm. The initial barrier insulating layer 132 can extend elongated in the longitudinal direction of the channel via CHH and fill a portion of each of the plurality of molded notches MLA on the sacrificial layer 130. The initial barrier insulating layer 132 can comprise a doped polysilicon layer or an undoped polysilicon layer. The initial barrier insulating layer 132 can have a sufficient thickness to fill the plurality of molded notches MLA on the sacrificial layer 130. To form the sacrificial layer 130 and the initial barrier insulating layer 132, an ALD process, a CVD process, or a combination thereof can be used.

[0122] Reference Figure 12E According to Figure 12D The resulting structure allows for the modification of the initial barrier insulating layer 132, retaining only the portion of the initial barrier insulating layer 132 that fills the plurality of molded notches MLA. Consequently, the plurality of initial barrier dielectric patterns 132P formed by the remaining portion of the initial barrier insulating layer 132 can remain within the plurality of molded notches MLA. Each of the plurality of initial barrier dielectric patterns 132P can fill only the internal space of the plurality of molded notches MLA without protruding into the channel via CHH.

[0123] A wet etching process using an etchant can be used to trim the initial barrier insulating layer 132. The etchant may include: a mixed solution containing nitric acid and hydrofluoric acid; a mixed solution containing ammonia, peroxide, and water; or a mixed solution containing an alkylammonium hydroxide compound, peroxide, and water. However, the exemplary embodiments are not limited thereto.

[0124] Reference Figure 12F According to Figure 12E The resulting structure can be formed by oxidizing a plurality of initial barrier dielectric patterns 132P to form a first barrier dielectric pattern 132B including an oxide layer. When the plurality of initial barrier dielectric patterns 132P include a polysilicon layer, the first barrier dielectric pattern 132B may include a silicon oxide layer.

[0125] To oxidize multiple initial barrier dielectric patterns 132P, either a dry oxidation process or a wet oxidation process can be used. For example, when multiple initial barrier dielectric patterns 132P are dry oxidized, a plasma oxidation process or a gas flow process utilizing gases such as O2, N2O, NO, or combinations thereof can be used.

[0126] Reference Figure 12GAccording to Figure 12F The resulting structure undergoes a trimming process to remove portions of the sacrificial layer 130 exposed within the channel hole CHH and through the upper surface of the insulating pattern 114. Thus, the sidewalls of the plurality of insulating layers 110 can be exposed within the channel hole CHH, and the upper surface of the insulating pattern 114 can be exposed. To trim the sacrificial layer 130, etchants such as ammonia-based etchants, phosphoric acid-based etchants, sulfuric acid-based etchants, acetic acid-based etchants, or combinations thereof can be used.

[0127] Reference Figure 12H Based on Figure 12G The resulting structure allows for the sequential formation of a charge trapping layer 134, a tunneling dielectric layer 140, a channel layer 150, and a buried insulating layer 156 within the channel hole CHH, and can also form a drain region 158 filling the upper entrance portion of the channel hole CHH. The term "charge trapping layer" as used in this specification can be used interchangeably with the term "charge storage layer," and both "charge trapping layer" and "charge storage layer" refer to the same object.

[0128] Each of the charge trapping layer 134, tunneling dielectric layer 140, and channel layer 150 may have a cylindrical shape within the channel via CHH. During the formation of the charge trapping layer 134, tunneling dielectric layer 140, and channel layer 150, a portion of the upper surface of the semiconductor pattern 120 may be removed, thus forming a recessed surface 120R on the upper surface of the semiconductor pattern 120. The channel layer 150 may contact the recessed surface 120R of the semiconductor pattern 120.

[0129] The deposition and etch-back processes can be performed multiple times to form a charge trapping layer 134, a tunneling dielectric layer 140, a channel layer 150, and a buried insulating layer 156. The deposition process can include CVD, low-voltage CVD (LPCVD), or ALD. The charge trapping layer 134 can include a silicon nitride layer. The tunneling dielectric layer 140 can include a silicon oxide layer. The channel layer 150 can include doped polysilicon or undoped polysilicon. The buried insulating layer 156 can include silicon oxide, silicon nitride, silicon oxide nitride, or a combination thereof. The drain region 158 can include doped polysilicon, metal, conductive metal nitride, or a combination thereof. The metal included in the drain region 158 can include tungsten, nickel, cobalt, or tantalum.

[0130] Reference Figure 12IAnisotropic etching of insulating pattern 114, multiple insulating layers 110 and multiple molding layers ML can be performed to form word line cut regions WLC that expose the substrate 102 by penetrating the insulating pattern 114, multiple insulating layers 110 and multiple molding layers ML. Then, impurity ions can be implanted into the substrate 102 through the word line cut regions WLC to form a common source region 160.

[0131] Reference Figure 12J Multiple molding layers ML can be removed through the word line cutting region WLC to form multiple conductive spaces LS1, and the exposed sacrificial layer 130 can be removed through the multiple conductive spaces LS1. Next, a portion of the charge trapping layer 134 (which is exposed due to the removal of the sacrificial layer 130) can be removed to divide the charge trapping layer 134 into multiple charge trapping patterns 134P and multiple dummy charge trapping patterns 134D. Corresponding separating spaces TSS can be formed between the multiple charge trapping patterns 134P and the multiple dummy charge trapping patterns 134D.

[0132] When each of the multiple molding layers ML, sacrificial layer 130 and charge trapping layer 134 includes a silicon nitride layer, a phosphoric acid-based etchant can be used to form the conductive space LS1 and the separating space TSS.

[0133] Reference Figure 12K According to Figure 12J A second barrier dielectric pattern 162 is formed on the resulting structure. The second barrier dielectric pattern 162 can be formed to conformally cover the surface exposed through the conductive space LS1 and the word line cut region WLC while filling the separation space TSS. The second barrier dielectric pattern 162 may include a first portion 162A covering the insulating layer 110, a second portion 162B between the first barrier dielectric pattern 132B and the insulating layer 110, a third portion 162C filling the separation space TSS between the charge trapping pattern 134P and the dummy charge trapping pattern 134D, and a fourth portion 162D covering the sidewall of the first barrier dielectric pattern 132B facing the conductive space LS1. The second barrier dielectric pattern 162 can be formed using an ALD process, a CVD process, or a plasma oxidation process.

[0134] Reference Figure 12L Multiple conductive lines CL can be formed in multiple conductive spaces LS1. For this purpose, the regions of the multiple conductive spaces LS1 defined by the second barrier dielectric pattern 162 through multiple word line cut regions WLC can be filled with a conductive layer. The conductive layer may include a metal, such as tungsten. In the conductive spaces LS1, the sidewalls, bottom surface, and top surface of the conductive lines CL can be covered by the second barrier dielectric pattern 162.

[0135] Reference Figure 12MInsulating spacers 170, common source pattern CSP, and cover insulating layer 172 can be formed in the word line cutting area WLC.

[0136] According to an example embodiment, in order to form an insulating spacer 170 in the word line cut region WLC, firstly, a spacer insulating layer covering the inner wall of the word line cut region WLC can be formed. Subsequently, the spacer insulating layer can be etched back to expose the common source region 160 through the lower surface of the word line cut region WLC, thus the insulating spacer 170 can remain at the inner sidewall of the word line cut region WLC.

[0137] Conductive layers can be formed inside and outside the word line cut region (WLC) to fill the space defined by the insulating spacer 170 in the word line cut region (WLC) with conductive material. Then, unwanted portions of the conductive layer can be removed by chemical mechanical polishing (CMP) or etch-back process to form a common source pattern (CSP).

[0138] An insulating layer can be formed over the remaining space of the fill word line cut region WLC on the resulting object with respect to the insulating spacer 170 and the common source pattern CSP. Then, a portion of the insulating layer can be removed via CMP or etch-back process to expose the upper surface of the insulating pattern 114 and the upper surface of the drain region 158, thereby forming the cap insulating layer 172.

[0139] After that, as Figure 3A As shown, an upper insulating layer 180 can be formed covering the insulating pattern 114, the drain region 158, and the cap insulating layer 172. A portion of the upper insulating layer 180, a portion of the insulating pattern 114, a portion of the insulating layer 110, and portions of two of the multiple conductive lines CL can be removed to form a string selection wire cut region SSLC (see...). Figure 3A ), and the string select wire cut area SSLC can be filled with string select wire cut insulation layer 184.

[0140] Subsequently, multiple bit line contact holes 180H can be formed penetrating some areas of the upper insulating layer 180, and conductive material can be buried in the multiple bit line contact holes 180H to form multiple bit line contact pads 182. Multiple bit lines BL connected to the multiple bit line contact pads 182 can be formed on the upper insulating layer 180 to manufacture... Figure 3A The integrated circuit device shown is 100A.

[0141] In order to manufacture Figure 4B The integrated circuit device 100C shown can be used with reference to Figures 12A to 12M The described process. However, in reference... Figure 12K The described process can form a TSS (Temporary Space Segment) that occupies the partition space. Figure 12JThe second barrier dielectric pattern 164 is used in some regions of the air gap AG1, instead of the second barrier dielectric pattern 162. In order to form the second barrier dielectric pattern 164 including the air gap AG1, the deposition process atmosphere used to form the second barrier dielectric pattern 164 can be controlled, such as deposition temperature, deposition pressure, etc.

[0142] In order to manufacture Figure 5 The integrated circuit device 100D shown can be used with reference to Figures 12A to 12M The described process. However, in reference... Figure 12K After the formation of the second barrier dielectric pattern 162, as shown in the reference Figure 12L Before forming the plurality of conductive lines CL, a third barrier dielectric pattern 166 may be further formed, which conformally covers the second barrier dielectric pattern 162 in the plurality of conductive spaces LS1 and word line cutting regions WLC. Thereafter, as referred to Figure 12L In the process of forming multiple conductive lines CL, the portion of the third blocking dielectric pattern 166 outside the conductive space LS1 can be removed, and the multiple third blocking dielectric patterns 166 and the multiple conductive lines CL can be retained in the multiple conductive spaces LS1.

[0143] Figures 13A to 13I This is a cross-sectional view shown in process sequence for describing a method of manufacturing an integrated circuit device 200A according to other embodiments. The manufacturing process will be described. Figure 6A and Figure 6B The method of the integrated circuit device 200A shown. Figures 13A to 13I The process sequence is shown, along with the process flow. Figure 6A The enlarged cross-sectional structure of the area corresponding to the dashed line region indicated by Q2. Figures 13A to 13I In, with Figures 12A to 12M The same reference numerals are used to indicate the same as those in the accompanying drawings. Figures 12A to 12M The same components will not be described in detail again for the sake of brevity.

[0144] Reference Figure 13A The sacrificial layer 130, which conformally covers the surfaces exposed through the channel holes CHH and the plurality of molded notches MLA, and the initial barrier insulating layer that fills a portion of each of the plurality of molded notches MLA on the sacrificial layer 130, can be achieved by performing a reference... Figures 12A to 12D After the process described is completed, it can be used with reference. Figure 12E The method described is essentially the same as that used to trim the initial barrier insulating layer. However, in this example, after trimming the initial barrier insulating layer, multiple initial barrier dielectric patterns 232P can be retained in multiple molded notches MLA. Each of the multiple initial barrier dielectric patterns 232P may include a portion filling the molded notch MLA and a portion extending from the molded notch MLA into the channel hole CHH.

[0145] Reference Figure 13B By using and referencing Figure 12F The methods described are basically the same, relative to those based on Figure 13A The resulting object can be formed by oxidizing a plurality of initial barrier dielectric patterns 232P to form a first barrier dielectric pattern 232B including an oxide layer. The first barrier dielectric pattern 232B may include a silicon oxide layer.

[0146] Reference Figure 13C By using and referencing Figure 12G The methods described are basically the same, and can be used to... Figure 13B The resulting structure undergoes a trimming process to remove exposed portions of the sacrificial layer 130. Therefore, the sidewalls of the plurality of insulating layers 110 can be exposed in the channel hole CHH, and the upper surface of the insulating pattern 114 can be exposed. After trimming the sacrificial layer 130, the plurality of first barrier dielectric patterns 232B can protrude horizontally toward the central axis of the channel hole CHH more than the exposed sidewalls of the plurality of insulating layers 110 in the channel hole CHH.

[0147] Reference Figure 13D According to Figure 13C The resulting structure allows for the formation of a charge trapping layer 233 within the channel hole CHH. The charge trapping layer 233 can be formed to have a thickness greater than the horizontal thickness of the charge trapping layer 234, which will be formed sequentially later in the process sequence. The profile of the sidewalls of the charge trapping layer 233 facing the interior of the channel hole CHH can extend in a straight line in a direction away from the substrate 102. The charge trapping layer 233 may include a silicon nitride layer. A CVD process can be used to form the charge trapping layer 233. In the process of forming the charge trapping layer 233, although the deposition process can be performed in a region relatively adjacent to the first barrier dielectric pattern 232B, the sidewall profile of the charge trapping layer 233 facing the interior of the channel hole CHH can have uneven portions corresponding to the cross-sectional profile of the first barrier dielectric pattern 232B. In this state, when a deposition process for forming the charge trapping layer 233 is further performed to increase the horizontal thickness of the charge trapping layer 233, the sidewall profile of the sidewall facing the interior of the channel hole CHH of the charge trapping layer 233 can have a shape that extends substantially in a straight line in a direction away from the substrate 102.

[0148] Reference Figure 13E According to Figure 13D The resulting structure allows for the back etching of the charge trapping layer 233 to form a charge trapping layer 234 in the channel hole CHH. The sidewall profile of the charge trapping layer 234 facing the interior of the channel hole CHH can extend substantially in a straight line in a direction away from the substrate 102.

[0149] The charge trapping layer 234 can extend in the longitudinal direction (Z direction) of the channel aperture CHH to have a variable width. The charge trapping layer 234 may include a first charge trapping layer portion 234A covering a first barrier dielectric pattern 232B with a first width 234T1, and a second charge trapping layer portion 234B covering an insulating layer 110 with a second width 234T2 greater than the first width 234T1. More detailed structures and methods for manufacturing the charge trapping layer 234 are described in reference to [reference needed]. Figure 12H The case of charge trapping layer 134 is basically the same, so for the sake of brevity, its repeated description is omitted.

[0150] Reference Figure 13F Based on Figure 13E The resulting structure can sequentially form a tunneling dielectric layer 140, a channel layer 150, and a buried insulating layer 156 covering the charge trapping layer 234 in the channel hole CHH, and can be used with reference to Figure 12H The same method described is used to form the drain region 158 of the upper inlet portion of the filling channel orifice CHH.

[0151] Reference Figure 13G By using and referencing Figure 12I The methods described are the same, and can be based on... Figure 13F The resulting structure forms the word line cut region WLC and the common source region 160. Subsequently, by using a reference... Figure 12J The same method described herein allows for the removal of multiple molding layers ML through word line cutting regions WLC to form multiple conductive spaces LS2, and the removal of exposed sacrificial layer 130 through the multiple conductive spaces LS2. Subsequently, portions of charge trapping layer 234 exposed due to the removal of sacrificial layer 130 can be removed to divide charge trapping layer 234 into multiple charge trapping patterns 234P and multiple dummy charge trapping patterns 234D. The multiple charge trapping patterns 234P and multiple dummy charge trapping patterns 234D can be arranged alternately in the longitudinal direction (Z direction) of the channel via CHH. In the horizontal direction, the multiple charge trapping patterns 234P can have a first width 234T1, and the multiple dummy charge trapping patterns 234D can have a second width 234T2 greater than the first width 234T1. Corresponding separating spaces TSS2 can be formed between the multiple charge trapping patterns 234P and the multiple dummy charge trapping patterns 234D.

[0152] Reference Figure 13H By using and referencing Figure 12K The method for forming the second barrier dielectric pattern 162 described herein is essentially the same as that described herein, and can be performed according to... Figure 13GThe resulting structure forms a second barrier dielectric pattern 262.

[0153] The second barrier dielectric pattern 262 can be formed to conformally cover the surface exposed through the conductive space LS2 and the word line cutting region WLC while filling the separation space TSS2. The second barrier dielectric pattern 262 may include a first portion 262A covering the insulating layer 110, a second portion 262B between the first barrier dielectric pattern 232B and the insulating layer 110, a third portion 262C filling the separation space TSS2 between the charge trapping pattern 234P and the dummy charge trapping pattern 234D, and a fourth portion 262D covering the sidewall of the first barrier dielectric pattern 232B (the sidewall facing the conductive space LS2).

[0154] Reference Figure 13I According to Figure 13H The resulting structure, through the use of reference Figure 12L The same method described herein can be used to form multiple conductive lines CL in multiple conductive spaces LS2, and can form insulating spacers 170, a common source pattern CSP, and a cover insulating layer 172 in the word line cutting region WLC, and can be performed as described above. Figure 12M The described sequence of processes for manufacturing Figure 6A and Figure 6B The integrated circuit device shown is 200A.

[0155] In order to manufacture Figure 7 The integrated circuit device 200B shown can be used with reference to Figures 13A to 13I The described process. However, in reference... Figure 13H In the described process, a second barrier dielectric pattern 264, including an air gap AG2, can be formed instead of a second barrier dielectric pattern 262. The air gap AG2 can occupy the separation space TSS2 (see...). Figure 13G As part of the process atmosphere used to form the second barrier dielectric pattern 264, including the air gap AG2, the deposition process atmosphere, such as deposition temperature and deposition pressure, can be controlled.

[0156] Figures 14A to 14D This is a cross-sectional view shown in process sequence for illustrating a method of manufacturing an integrated circuit device 300A according to other embodiments. The manufacturing process will be described. Figure 8A and Figure 8B The method of the integrated circuit device 300A shown. Figures 14A to 14D The process sequence is shown, along with the... Figure 8A The enlarged cross-sectional structure of the area corresponding to the dashed line region indicated by Q3. Figures 14A to 14D In, with Figures 12A to 12M and Figures 13A to 13IThe same reference numerals in the figures indicate the same as those in the figures below. Figures 12A to 12M and Figures 13A to 13I The components in this document are the same as those in the document, and for the sake of brevity, their detailed descriptions will not be repeated.

[0157] Reference Figure 14A By using and referencing Figures 13A to 13C Using the same method described, a plurality of first blocking dielectric patterns 232B can be formed to protrude horizontally toward the central axis of the channel holes CHH more than the sidewalls of the plurality of insulating layers 110 exposed on the substrate. Furthermore, the sidewalls of the plurality of insulating layers 110 can be exposed in the channel holes CHH. Subsequently, by using the method described with reference to... Figure 13D The method described is essentially the same, in which a charge trapping layer 334 can be formed, which conformally covers the surfaces of a plurality of first blocking dielectric patterns 232B exposed in the channel hole CHH and the sidewalls of a plurality of insulating layers 110 exposed in the channel hole CHH. Next, a tunneling dielectric layer 340, a channel layer 150, and a buried insulating layer 156 that sequentially cover the charge trapping layer 334 in the channel hole CHH can be formed in sequence, and a drain region 158 filling the upper entrance portion of the channel hole CHH can be formed.

[0158] The charge trapping layer 334 can be formed to have a constant horizontal width in the longitudinal direction (Y direction) of the channel hole CHH. The tunneling dielectric layer 340 can have a variable width in the channel hole CHH in the direction away from the substrate 102. In the horizontal direction, the first width 340T1 of the first tunneling dielectric layer portion 340A of the tunneling dielectric layer 340 between the molding layer ML and the channel layer 150 can be smaller than the second width 340T2 of the second tunneling dielectric layer portion 340B of the tunneling dielectric layer 340 between the insulating layer 110 and the channel layer 150.

[0159] Reference Figure 14B According to Figure 14A The resulting structure, through the use of reference Figure 13G Using essentially the same method described, a word line cut region WLC and a common source region 160 can be formed. Multiple molding layers ML can be removed through the word line cut region WLC to form multiple conductive spaces LS3. Exposed sacrificial layers 130 can be removed through the multiple conductive spaces LS3. Furthermore, portions of the charge trapping layer 334 exposed due to the removal of sacrificial layers 130 can be removed to divide the charge trapping layer 334 into multiple charge trapping patterns 334P and multiple dummy charge trapping patterns 334D. As a result, corresponding separation spaces TSS3 can be formed between the multiple charge trapping patterns 334P and the multiple dummy charge trapping patterns 334D.

[0160] Reference Figure 14CBy using and referencing Figure 12K The method for forming the second barrier dielectric pattern 162 described herein is essentially the same as that described herein, and can be performed according to... Figure 14B The resulting structure forms a second barrier dielectric pattern 362.

[0161] The second barrier dielectric pattern 362 can be formed to conformally cover the surface exposed through the conductive space LS3 and the word line cutting region WLC while filling the separation space TSS3. The second barrier dielectric pattern 362 may include a first portion 362A covering the insulating layer 110, a second portion 362B between the first barrier dielectric pattern 232B and the insulating layer 110, a third portion 362C filling the separation space TSS3 between the charge trapping pattern 334P and the dummy charge trapping pattern 334D, and a fourth portion 362D covering the sidewall of the first barrier dielectric pattern 232B (the sidewall facing the conductive space LS3).

[0162] Reference Figure 14D According to Figure 14C The resulting structure, through the use of reference Figure 12L The same method described can be used to form multiple conductive lines CL in multiple conductive spaces LS3, and can form insulating spacers 170, common source pattern CSP, and cover insulating layer 172 in word line cut regions WLC, and can be performed according to reference. Figure 12M The described sequence of processes for manufacturing Figure 8A and Figure 8B The integrated circuit device shown is 300A.

[0163] In order to manufacture Figure 9 The integrated circuit device 300B shown can be used with reference to Figure 14A and Figure 14B The described process. However, in reference... Figure 14C In the described process, a second barrier dielectric pattern 364, including an air gap AG3, can be formed instead of a second barrier dielectric pattern 362. The air gap AG3 can occupy the separation space TSS3 (see...). Figure 14B As part of the process atmosphere used to form the second barrier dielectric pattern 364, including the air gap AG3, the deposition process atmosphere, such as deposition temperature and deposition pressure, can be controlled.

[0164] Figure 15A and Figure 15B This is a cross-sectional view shown in process sequence for describing a method of manufacturing an integrated circuit device 100A according to other embodiments. The manufacturing reference will be described. Figure 3A and Figure 3B Another example method for describing the integrated circuit device 100A. Figure 15Aand Figure 15B The process sequence is shown, along with the process flow. Figure 3A The enlarged cross-sectional structure of the area corresponding to the dashed line region indicated by Q1. Figure 15A and Figure 15B In, with Figures 12A to 12M The same reference numerals in the figures indicate the same as those in the figures below. Figures 12A to 12M The components in this document are the same as those in the document, and for the sake of brevity, their detailed descriptions will not be repeated.

[0165] Reference Figure 15A It can be used and referenced Figures 12A to 12J The method described is the same as the process used to form the word line cut region WLC, multiple conductive spaces LS1, and multiple separating spaces TSS. However, in this example, the reference can be omitted. Figure 12F The described process, namely, the process of forming a first barrier dielectric pattern 132B by oxidizing multiple initial barrier dielectric patterns 132P, and can be applied according to... Figure 12E The resulting structure, which retains multiple initial blocking dielectric patterns 132P, is subject to reference. Figure 12G The described process. Therefore, when using with reference... Figure 12H When forming the charge trapping layer 134, tunneling dielectric layer 140, channel layer 150, and buried insulating layer 156 using the same method described, the charge trapping layer 134, tunneling dielectric layer 140, channel layer 150, and buried insulating layer 156 can be formed on multiple initial barrier dielectric patterns 132P. After forming multiple conductive spaces LS1 and multiple separating spaces TSS, multiple initial barrier dielectric patterns 132P can be exposed through the multiple conductive spaces LS1, such as... Figure 15A As shown.

[0166] Reference Figure 15B According to Figure 15A The resulting structure, through the use of reference Figure 12F The method described is essentially the same as that used to oxidize multiple initial barrier dielectric patterns 132P, which can form a first barrier dielectric pattern 132B including an oxide layer.

[0167] After that, the reference can be executed. Figures 12K to 12M The described process for manufacturing Figure 3A and Figure 3B The integrated circuit device shown is 100A.

[0168] Figure 16 This is a cross-sectional view shown in process sequence for describing a method of manufacturing an integrated circuit device 200A according to other embodiments. The manufacturing reference will be described. Figure 6A and Figure 6B Another example method for describing the integrated circuit device 200A. Figure 16 The process sequence is shown, along with the process flow. Figure 6A The enlarged cross-sectional structure of the area corresponding to the dashed line region indicated by Q2. Figure 16 In, with Figures 13A to 13I The same reference numerals in the figures indicate the same as those in the figures below. Figures 13A to 13I The components in this document are the same as those in the document, and for the sake of brevity, their detailed descriptions will not be repeated.

[0169] Reference Figure 16 By using and referencing Figures 13A to 13G The same method described can be used to perform the process of forming the word line cut region WLC, multiple conductive spaces LS2, and multiple separating spaces TSS2. However, in this example, the reference can be omitted. Figure 13B The described process, namely, the process of forming a first barrier dielectric pattern 232B by oxidizing multiple initial barrier dielectric patterns 232P, and can be applied according to... Figure 13A The resulting structure, which retains multiple initial blocking dielectric patterns 232P, is subject to reference. Figure 13C The described process. Therefore, when using with reference... Figure 13D When forming the charge trapping layer 233 using the same method described, the charge trapping layer 233 can be formed over multiple initial barrier dielectric patterns 232P. Furthermore, after forming multiple conductive spaces LS2 and multiple separating spaces TSS2, multiple initial barrier dielectric patterns 232P can be exposed through the multiple conductive spaces LS2, such as... Figure 16 As shown.

[0170] Subsequently, relative to the basis Figure 16 The resulting structure, through the use of reference Figure 13B The method described is essentially the same as oxidizing multiple initial barrier dielectric patterns 232P to form a first barrier dielectric pattern 232B including an oxide layer. Thereafter, reference can be performed... Figure 13H and Figure 13I The described process for manufacturing Figure 6A and Figure 6B The integrated circuit device shown is 200A.

[0171] Figures 17A to 17C This is a cross-sectional view shown in process sequence for describing a method of manufacturing an integrated circuit device 300A according to other embodiments. The manufacturing reference will be described. Figure 8A and Figure 8B Another example method for describing the integrated circuit device 300A. Figures 17A to 17C The process sequence is shown, along with the process flow. Figure 8A The enlarged cross-sectional structure of the area corresponding to the dashed line region indicated by Q3. Figures 17A to 17C In, with Figures 12A to 12M, Figures 13A to 13I and Figures 14A to 14D The same reference numerals in the figures indicate the same as those in the figures below. Figures 12A to 12M , Figures 13A to 13I and Figures 14A to 14D The components in this document are the same as those in the document, and for the sake of brevity, their detailed descriptions will not be repeated.

[0172] Reference Figure 17A , can execute reference Figures 13A to 13D The described process. However, in this example, the reference can be omitted. Figure 13B The process described is the oxidation of multiple initial barrier dielectric patterns 232P, and can be applied according to... Figure 13A The resulting structure, which retains multiple initial blocking dielectric patterns 232P, is subject to reference. Figure 13C The described process. Subsequently, by reference... Figure 13A The described process forms multiple initial barrier dielectric patterns 232P that remain on the substrate 102. These patterns can be used in conjunction with a reference. Figure 14A The method for manufacturing the charge trapping layer 334 described is essentially the same method in which the charge trapping layer 334 is formed on a plurality of initial blocking dielectric patterns 232P, and then a tunneling dielectric layer 340, a channel layer 150 and a buried insulating layer 156 can be sequentially formed on the charge trapping layer 334.

[0173] Reference Figure 17B According to Figure 17A The resulting structure, through the use of reference Figure 14B The same method described can be used to perform the process of forming a word line cut region WLC, multiple conductive spaces LS3, and multiple separating spaces TSS3. After forming the multiple conductive spaces LS3 and multiple separating spaces TSS3, multiple initial blocking dielectric patterns 232P can be exposed through the multiple conductive spaces LS3.

[0174] Reference Figure 17C According to Figure 17B The resulting structure, through the use of reference Figure 13B The method described is essentially the same as that used to oxidize multiple initial barrier dielectric patterns 232P to form a first barrier dielectric pattern 232B. Afterwards, the following steps can be performed: Figure 14C and Figure 14D The described process for manufacturing Figure 8A and Figure 8B The integrated circuit device shown is 300A.

[0175] Figure 18A and Figure 18B This is a cross-sectional view shown in process sequence for describing a method of manufacturing an integrated circuit device 400A according to other embodiments. The manufacturing process will be described. Figure 10A The method of the integrated circuit device 400A shown.

[0176] Reference Figure 18A , can execute reference Figures 12A to 12E The described process. However, in this example, in reference... Figure 12A In the described process, a serial select line SSL can be formed therein (see...). Figure 1 A molding layer ML4 with a relatively larger thickness than other molding layers ML is formed at the portion corresponding to the area where the multiple word lines WL will be formed (see example embodiment). According to the example embodiment, the first thickness of the molding layer ML4 can be greater than that formed in the area where multiple word lines WL will be formed (see example embodiment). Figure 1 The second thickness of the molding layer ML at the portion corresponding to the area of ​​the region. For example, the first thickness may be at least twice the second thickness. However, the example implementation is not limited to this.

[0177] Because the thickness of molding layer ML4 is greater than the thickness of molding layer ML, therefore, when completing... Figure 12E Following the process, the plurality of initial barrier dielectric patterns 432P formed on the sidewalls of the molding layer ML4 facing the interior of the channel hole CHH can have sidewalls recessed relative to the channel hole CHH. However, in some embodiments, the plurality of initial barrier dielectric patterns 132P formed on the sidewalls of the molding layer ML can have flat sidewalls facing the interior of the channel hole CHH.

[0178] Reference Figure 18B According to Figure 18A The resulting structure can be executed using the reference method. Figures 12F to 12J The described process or reference Figure 15A and Figure 15B The described process is used to form a structure in which first barrier dielectric patterns 432B and 132B are exposed through multiple conductive spaces LS1. The first barrier dielectric patterns 432B and 132B can be obtained by oxidizing multiple initial barrier dielectric patterns 432P and multiple initial barrier dielectric patterns 132P. Thereafter, processes can be performed in accordance with reference to... Figures 12K to 12M The processes described are essentially the same, used to manufacture Figure 10A The integrated circuit device shown is 400A.

[0179] In order to manufacture Figure 10B The integrated circuit device 400B shown may, in some embodiments, form a second barrier dielectric pattern 464 including an air gap AG4, instead of Figure 10A The second barrier dielectric pattern 462 is shown. In order to form the second barrier dielectric pattern 464 including the air gap AG4, the deposition process atmosphere used to form the second barrier dielectric pattern 464 can be controlled, such as deposition temperature, deposition pressure, etc.

[0180] According to the method of manufacturing an integrated circuit device based on the various exemplary embodiments described above, a structure is provided that improves reliability even when the gap between adjacent cells is relatively small by preventing cell interference caused by charge diffusion between cells perpendicularly adjacent to each other in a channel via of a vertical memory device.

[0181] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0182] This application claims priority to Korean Patent Application No. 10-2019-0104983, filed on August 27, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit device, comprising: A conductive pattern extends on a substrate in a horizontal direction parallel to the surface of the substrate; An insulating layer extends on the substrate in the horizontal direction, is adjacent to and parallel to the conductive pattern in a vertical direction perpendicular to the surface of the substrate; A channel layer extends in the vertical direction through channel holes that penetrate the conductive pattern and the insulating layer; A charge storage pattern is located between the conductive pattern and the channel layer inside the channel aperture; A dummy charge storage pattern is provided between the insulating layer and the channel layer, inside the channel hole, and the dummy charge storage pattern is separate from the charge storage pattern. as well as A barrier dielectric pattern, spaced apart from the channel layer and having the charge storage pattern therebetween, the barrier dielectric pattern contacting the upper and lower surfaces of the charge storage pattern that are opposite to each other in the vertical direction. The charge storage pattern and the dummy charge storage pattern are formed of the same material.

2. The integrated circuit device according to claim 1, wherein the blocking dielectric pattern comprises: A first blocking dielectric pattern is located between the conductive pattern and the charge storage pattern; as well as The second barrier dielectric pattern has a first portion between the conductive pattern and the insulating layer, a second portion between the first barrier dielectric pattern and the insulating layer, and a third portion between the charge storage pattern and the dummy charge storage pattern. The first part, the second part, and the third part are integrally connected.

3. The integrated circuit device according to claim 2, wherein... The third portion of the second blocking dielectric pattern has an air gap between the charge storage pattern and the dummy charge storage pattern.

4. The integrated circuit device according to claim 1, wherein... The sidewall of the charge storage pattern facing the conductive pattern is closer to the channel layer than the sidewall of the dummy charge storage pattern facing the insulating layer. The barrier dielectric pattern has more sidewalls protruding toward the channel layer than the insulating layer.

5. The integrated circuit device of claim 1, wherein the blocking dielectric pattern has a concave sidewall that contacts the sidewall of the charge storage pattern facing the conductive pattern.

6. The integrated circuit device of claim 1, wherein the blocking dielectric pattern comprises: A first blocking dielectric pattern is located between the conductive pattern and the charge storage pattern; The second barrier dielectric pattern has a first portion between the conductive pattern and the insulating layer, a second portion between the first barrier dielectric pattern and the insulating layer, and a third portion between the charge storage pattern and the dummy charge storage pattern. as well as A third barrier dielectric pattern is spaced apart from the first barrier dielectric pattern and the insulating layer, and the second barrier dielectric pattern is present therebetween. The third barrier dielectric pattern surrounds a portion of the conductive pattern. The first barrier dielectric pattern includes a silicon oxide layer, and Each of the second and third barrier dielectric patterns includes a silicon oxide layer, a high-k dielectric layer, or a combination of a silicon oxide layer and a high-k dielectric layer.

7. The integrated circuit device according to claim 1, The barrier dielectric pattern includes a first pattern portion and a second pattern portion. The first pattern portion contacts the sidewall of the charge storage pattern facing the conductive pattern. The second pattern portion contacts the charge storage pattern and the dummy charge storage pattern in the space between the charge storage pattern and the dummy charge storage pattern. The second pattern portion surrounds a portion of the conductive pattern. The first and second pattern portions of the blocking dielectric pattern are connected to each other and there is no visible interface therebetween.

8. The integrated circuit device according to claim 1, The blocking dielectric pattern contacts the charge storage pattern and the dummy charge storage pattern, and surrounds a portion of the conductive pattern. The blocking dielectric pattern includes: A first blocking dielectric pattern contacts the charge storage pattern and is spaced apart from the conductive pattern and the dummy charge storage pattern; as well as The second barrier dielectric pattern includes a portion that contacts the charge storage pattern and the dummy charge storage pattern, and a portion that is inserted between the first barrier dielectric pattern and the conductive pattern.

9. The integrated circuit device according to claim 1, further comprising: A tunneling dielectric layer extends in the direction in which the channel layer extends, between the charge storage pattern and the channel layer and between the dummy charge storage pattern and the channel layer.

10. The integrated circuit device according to claim 1, wherein The charge storage pattern and the dummy charge storage pattern extend along a straight line.

11. The integrated circuit device according to claim 1, wherein The width of the charge storage pattern in the horizontal direction is different from the width of the dummy charge storage pattern in the horizontal direction.

12. The integrated circuit device according to claim 1, wherein The width of the charge storage pattern in the horizontal direction is the same as the width of the dummy charge storage pattern in the horizontal direction, and the minimum horizontal distance between the charge storage pattern and the channel layer is less than the minimum horizontal distance between the dummy charge storage pattern and the channel layer.

13. An integrated circuit device, comprising: Multiple conductive patterns extend on a substrate in a horizontal direction parallel to the surface of the substrate, and the multiple conductive patterns overlap each other in a vertical direction perpendicular to the surface; Multiple insulating layers are respectively arranged between adjacent conductive patterns in the multiple conductive patterns, and the multiple insulating layers extend in the horizontal direction; A channel layer extends in the vertical direction within a channel hole that penetrates the plurality of conductive patterns and the plurality of insulating layers; Multiple charge-capturing patterns are spaced apart from each other inside the channel aperture and are interposed between the multiple conductive patterns and the channel layer; Multiple dummy charge trapping patterns are spaced apart from each other inside the channel aperture and spaced apart from the multiple charge trapping patterns, the multiple dummy charge trapping patterns being interposed between the multiple insulating layers and the channel layer; as well as Multiple barrier dielectric patterns include multiple first pattern portions and multiple second pattern portions. The multiple first pattern portions are respectively arranged between adjacent insulating layers and interposed between multiple conductive patterns and multiple charge-trapping patterns. The multiple second pattern portions surround corresponding portions of the multiple conductive patterns and fill corresponding spaces between the multiple charge-trapping patterns and multiple dummy charge-trapping patterns. Each of the multiple second pattern portions contacts the upper and lower surfaces of a corresponding one of the multiple charge-trapping patterns that are opposite to each other in the vertical direction. The plurality of charge-capturing patterns and the plurality of dummy charge-capturing patterns are formed of the same material.

14. The integrated circuit device according to claim 13, wherein The plurality of charge trapping patterns and the plurality of dummy charge trapping patterns are arranged alternately inside the channel vias along straight lines extending in a direction away from the substrate.

15. The integrated circuit device according to claim 13, wherein The plurality of charge-capturing patterns and the plurality of dummy charge-capturing patterns have the same width in the horizontal direction.

16. An integrated circuit device, comprising: The lower conductive line and the upper conductive line extend parallel to each other in the horizontal direction on the substrate. An insulating layer extends in the horizontal direction between the lower conductive line and the upper conductive line; The channel layer is formed in a channel hole that extends vertically through the lower conductive wire, the upper conductive wire, and the insulating layer. A lower charge trapping pattern is provided in the channel hole, and the lower charge trapping pattern is inserted between the lower conductive line and the channel layer; An upper charge trapping pattern is present in the channel hole, the upper charge trapping pattern is inserted between the upper conductive line and the channel layer, and is spaced apart from the lower charge trapping pattern in the vertical direction; as well as A dummy charge trapping pattern is provided between the insulating layer and the channel layer. The dummy charge trapping pattern is separated from the lower charge trapping pattern by a lower partition space and from the upper charge trapping pattern by an upper partition space. A lower first blocking dielectric pattern is located between the lower conductive line and the channel layer; An upper first blocking dielectric pattern is located between the upper conductive line and the channel layer; A lower second blocking dielectric pattern is located between the lower conductive line and the lower first blocking dielectric pattern. The lower second blocking dielectric pattern fills the lower partition space and contacts the upper and lower surfaces of the lower charge trapping pattern that are opposite to each other in the vertical direction. as well as An upper second blocking dielectric pattern, located between the upper conductive line and the upper first blocking dielectric pattern, fills the upper partition space and contacts the upper and lower surfaces of the upper charge-capturing pattern that are opposite to each other in the vertical direction. The lower charge trapping pattern, the upper charge trapping pattern, and the dummy charge trapping pattern are formed of the same material.

17. An integrated circuit device, comprising: Multiple conductive lines extend on a substrate in a horizontal direction parallel to the surface of the substrate, and the multiple conductive lines overlap each other in a vertical direction perpendicular to the surface. Multiple insulating layers are respectively arranged between adjacent conductive lines in the multiple conductive lines, and the multiple insulating layers extend in the horizontal direction; The channel layer extends vertically in the channel holes that penetrate the plurality of conductive lines and the plurality of insulating layers; Multiple charge trapping patterns are spaced apart from each other inside the channel aperture and are inserted between the multiple conductive lines and the channel layer; Multiple dummy charge trapping patterns are spaced apart from each other inside the channel orifice and are inserted between the multiple insulating layers and the channel layer, the multiple dummy charge trapping patterns being spaced apart from the multiple charge trapping patterns; Multiple first barrier dielectric patterns are respectively arranged between adjacent insulating layers in the multiple insulating layers and interposed between the multiple conductive lines and the multiple charge trapping patterns; A plurality of second blocking dielectric patterns surround corresponding portions of the plurality of first blocking dielectric patterns and corresponding portions of the plurality of conductive lines, and include portions filling corresponding spaces between the plurality of charge-capturing patterns and the plurality of dummy charge-capturing patterns, each of the plurality of second blocking dielectric patterns contacting the upper and lower surfaces of a corresponding one of the plurality of charge-capturing patterns that are opposite to each other in the vertical direction; as well as Tunneling dielectric layer, between the plurality of first barrier dielectric patterns and the channel layer. The plurality of charge-capturing patterns and the plurality of dummy charge-capturing patterns are formed of the same material.

18. A method for manufacturing an integrated circuit device, the method comprising: This forms a structure in which multiple insulating layers and multiple molding layers are alternately stacked on a substrate; Forming a channel hole that penetrates the structure; By removing portions of the plurality of molded layers through the channel holes, a plurality of molding recesses are formed that are connected to the channel holes; A sacrificial layer and an initial dielectric pattern are formed to fill each of the plurality of molded notches; A first barrier dielectric pattern is formed by oxidizing the initial dielectric pattern; A charge storage layer is formed in the channel hole; A tunneling dielectric layer is formed on the charge storage layer in the channel hole; A trench layer is formed on the tunneling dielectric layer in the trench hole; By removing the plurality of molding layers, conductive spaces are formed, each of the conductive spaces being between adjacent insulating layers in the plurality of insulating layers; By removing a portion of the charge storage layer and the sacrificial layer through each of the conductive spaces, a plurality of partition spaces are formed, which divide the charge storage layer into a plurality of charge storage patterns and a plurality of dummy charge storage patterns. A second barrier dielectric pattern is formed, which fills the plurality of partition spaces and covers the inner wall of the corresponding conductive space; as well as A conductive pattern is formed on the second barrier dielectric pattern in the corresponding conductive space.

19. A method for manufacturing an integrated circuit device, the method comprising: This forms a structure in which multiple insulating layers and multiple molding layers are alternately stacked on a substrate; Forming a channel hole that penetrates the structure; By removing portions of the plurality of molded layers through the channel holes, a plurality of molding recesses are formed that are connected to the channel holes; A first barrier dielectric pattern is formed in each of the plurality of molded notches; A charge trapping layer covering the first barrier dielectric pattern is formed in the channel hole; By removing the plurality of molding layers, a conductive space is formed that exposes the first barrier dielectric pattern; By removing a portion of the charge trapping layer via the conductive space, a plurality of partitioned spaces are formed, which divide the charge trapping layer into a plurality of charge trapping patterns and a plurality of dummy charge trapping patterns. A second barrier dielectric pattern is formed, which fills the plurality of spaced spaces and covers the first barrier dielectric pattern in the conductive spaces. as well as Conductive lines are formed in the conductive space.

20. A method for manufacturing an integrated circuit device, the method comprising: This forms a structure in which multiple insulating layers and multiple molding layers are alternately stacked on a substrate; Forming a channel hole that penetrates the structure; By removing portions of the plurality of molded layers through the channel holes, a plurality of molding recesses are formed that are connected to the channel holes; A sacrificial layer and an initial dielectric pattern are formed to fill each of the plurality of molded notches; A charge trapping layer covering the initial dielectric pattern is formed in the channel hole; By removing the plurality of molding layers, conductive spaces are formed that expose the initial dielectric pattern; By removing a portion of the charge trapping layer via the conductive space, a plurality of partitioned spaces are formed, which divide the charge trapping layer into a plurality of charge trapping patterns and a plurality of dummy charge trapping patterns. A first blocking dielectric pattern is formed by oxidizing the initial dielectric pattern via the conductive space; A second barrier dielectric pattern is formed, which fills the plurality of spaced spaces and covers the first barrier dielectric pattern in the conductive spaces. as well as Conductive lines are formed in the conductive space.

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