Capacitor and method for manufacturing the same

Abstract

The present application discloses a capacitor with high dielectric constant and low leakage current and a method for manufacturing the same, wherein the capacitor may include: a first conductive layer, a second conductive layer, a dielectric layer stack between the first conductive layer and the second conductive layer, a dielectric interface layer between the dielectric layer stack and the second conductive layer, and a high work function interface layer between the dielectric interface layer and the second conductive layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2019-0107440, filed on August 30, 2019, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments relate to a semiconductor device, and more particularly, to a capacitor and a method of manufacturing the same. Background Art

[0004] In recent years, improvements in the design and manufacture of highly integrated semiconductor memories have accelerated, resulting in a reduction in unit cell area and operating voltage. This in turn requires the development of an improved capacitor with higher capacitance and lower leakage current. Summary of the invention

[0005] Various embodiments of the present invention are directed to an improved capacitor having a high dielectric constant and a low leakage current for use in a semiconductor device and a method of manufacturing the same.

[0006] Various embodiments of the present invention are directed to an improved memory cell including a capacitor having a high dielectric constant and a low leakage current.

[0007] According to one embodiment, a capacitor may include: a first conductive layer; a second conductive layer; a dielectric layer stack between the first conductive layer and the second conductive layer; a dielectric interface layer between the dielectric layer stack and the second conductive layer; and a high work function interface layer between the dielectric interface layer and the second conductive layer.

[0008] According to one embodiment, a capacitor may include: a first conductive layer; a second conductive layer; a multilayer stack between the first conductive layer and the second conductive layer, wherein the multilayer stack may include: a first tetragonal zirconia layer above the first conductive layer; a second tetragonal zirconia layer above the first tetragonal zirconia layer; an aluminum-doped tetragonal zirconia layer between the first tetragonal zirconia layer and the second tetragonal zirconia layer; an aluminum oxide layer above the second tetragonal zirconia layer; a titanium oxide layer above the aluminum oxide layer; and a carbon-doped zirconium nitride layer above the titanium oxide layer.

[0009] According to one embodiment, a memory cell may include: a buried word line embedded in a substrate; a bit line located at a higher level than the buried word line; a capacitor located at a higher level than the bit line, wherein the capacitor includes: a bottom electrode; a top electrode; a dielectric layer stack between the bottom electrode and the top electrode; a dielectric interface layer between the dielectric layer stack and the top electrode; a high work function interface layer between the dielectric interface layer and the top electrode, wherein the dielectric layer stack includes a zirconium oxide-based material and the high work function interface layer includes a zirconium nitride-based material.

[0010] According to one embodiment, a method for manufacturing a capacitor may include: forming a first conductive layer; forming a dielectric layer stack having a leakage barrier material embedded therein on the first conductive layer; forming a dielectric interface layer on the dielectric layer stack; forming a high work function interface layer on the dielectric interface layer; and forming a second conductive layer on the high work function interface layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a cross-sectional view showing a capacitor according to an embodiment of the present disclosure.

[0012] Figure 2A is schematically shown in Figure 1 A cross-sectional view of an example of a dielectric layer stack used in a capacitor.

[0013] Figure 2B is a more detailed cross-sectional view showing the dielectric layer stack.

[0014] Figure 2C is a detailed cross-sectional view showing a dielectric layer stack according to a comparative example.

[0015] FIG. 3A to FIG. 3D is a cross-sectional view illustrating a method for manufacturing a capacitor according to an embodiment of the present disclosure.

[0016] Figure 4 is a graph describing changes in work function according to the formation of a high work function interface layer.

[0017] Figure 5 is a graph depicting leakage current according to formation of a high work function interface layer.

[0018] Fig. 6A and Figure 6B is a cross-sectional view showing a capacitor according to an embodiment of the present disclosure.

[0019] FIG. 7A to FIG. 7C is a cross-sectional view showing a capacitor according to an embodiment of the present disclosure.

[0020] Figure 8is a cross-sectional view showing a capacitor according to an embodiment of the present disclosure.

[0021] 9A to 9C is a diagram showing a storage unit.

[0022] FIG. 10A to FIG. 10F is a cross-sectional view showing an application example of a capacitor of a memory cell. DETAILED DESCRIPTION

[0023] Various examples and embodiments described herein will be described with reference to cross-sectional views, plan views, and block diagrams as ideal schematic diagrams of the present invention. Therefore, the shapes illustrated can be modified by manufacturing techniques and / or tolerances. Therefore, embodiments of the present invention are not limited to the specific forms shown, but also include changes in shapes produced according to manufacturing processes. The regions shown in the figures have schematic properties, and the shapes of the regions shown in the figures are intended to illustrate specific types of regions of the elements, and are not intended to limit the scope of the present invention.

[0024] The capacitor may include a bottom electrode, a dielectric layer and a top electrode. As the thickness of the dielectric layer decreases, the leakage current may increase. The dielectric constant and the energy band gap (hereinafter referred to as "band gap") of the dielectric layer are inversely proportional to each other. In order to suppress the leakage current, the thickness of the dielectric layer can be increased or a dielectric layer with a low dielectric constant can be used. The increase in the thickness of the dielectric layer and the low dielectric constant of the dielectric layer can increase the electrical thickness of the dielectric layer, i.e., the equivalent oxide thickness (EOT). When the thickness of the dielectric layer is reduced so that the EOT is reduced, the thickness of the reduced dielectric layer becomes less than the minimum thickness required for the crystallization of the dielectric layer, thereby improving the amorphous characteristics. Therefore, although the thickness of the dielectric layer is reduced, the increase in capacitance is limited.

[0025] In addition, the top electrode of the capacitor can be formed in a strong reducing atmosphere. For example, the strong reducing atmosphere may include NH3, SiH x ,GeH x and BH x Since the strong reducing atmosphere causes the loss of oxygen in the dielectric layer, the quality of the dielectric layer may be degraded.

[0026] A dead layer (DL) with a low dielectric constant may exist at the interface between the dielectric layer and the top electrode. The DL may be formed in a reducing atmosphere when depositing the top electrode. In addition, the DL may be formed due to oxidation of the top electrode. The DL may act as an obstacle to reducing the EOT.

[0027] In the following, embodiments are directed to interface engineering that can prevent reduction of a dielectric layer. In addition, embodiments are directed to interface engineering that can increase the dielectric constant of a dielectric layer. In addition, embodiments are directed to interface engineering that can reduce leakage current.

[0028] In the embodiments described below, a high work function interface layer can be formed at the interface between the dielectric layer and the conductive layer. The high work function interface layer can be used as a leakage current barrier, which has a high effective work function (eWF) and a large conduction band offset (CBO). The high work function interface layer can increase the eWF to about 4.7 eV or higher.

[0029] Figure 1 is a cross-sectional view showing a capacitor 100 according to an embodiment. Figure 2A is schematically shown in Figure 1 A cross-sectional view of an example of a dielectric layer stack used in a capacitor. Figure 2B is a more detailed cross-sectional view showing the dielectric layer stack. Figure 2C is a detailed cross-sectional view showing a dielectric layer stack according to a comparative example.

[0030] refer to Figure 1 , the capacitor 100 may include a first conductive layer 110 , a multilayer stack 100M, and a second conductive layer 130 .

[0031] The first conductive layer 110 may include a silicon-containing material, a germanium-containing material, a metal, a metal-containing material, or a combination thereof. The first conductive layer 110 may include a metal, a metal nitride, a metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof. For example, the first conductive layer 110 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), molybdenum, molybdenum oxide, iridium oxide (IrO2), or a combination thereof. In some embodiments, the first conductive layer 110 may include a silicon-containing material. The first conductive layer 110 may include silicon, silicon germanium, or a combination thereof. In some embodiments, the first conductive layer 110 may include a stack of a metal-containing material and a silicon-containing material. The first conductive layer 110 may be referred to as a "bottom electrode" or a "storage node."

[0032] The second conductive layer 130 may include a silicon-containing material, a germanium-containing material, a metal, a metal-containing material, or a combination thereof. The second conductive layer 130 may include a metal, a metal nitride, a metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof. The second conductive layer 130 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), molybdenum, molybdenum oxide, iridium oxide (IrO2), or a combination thereof. The second conductive layer 130 may include silicon (Si), germanium (Ge), germanium silicon (SiGe), or a combination thereof. The second conductive layer 130 may include a Si / SiGe stack, wherein germanium silicon (SiGe) is stacked on silicon (Si). The second conductive layer 130 may include a Ge / SiGe stack, wherein germanium silicon (SiGe) is stacked on germanium (Ge). The second conductive layer 130 may be formed by stacking silicon germanium (SiGe) on a metal nitride. In some embodiments, the second conductive layer 130 may have a structure in which titanium nitride (TiN), silicon germanium (SiGe), and tungsten (W) are sequentially stacked. In some embodiments, the second conductive layer 130 may have a structure in which titanium nitride (TiN), silicon germanium (SiGe), and tungsten nitride (WN) are sequentially stacked. In the present embodiment, the second conductive layer 130 may include a TiN / SiGe stack in which silicon germanium (SiGe) is stacked on titanium nitride (TiN). The second conductive layer 130 may be referred to as a "top electrode" or a "plate node".

[0033] The multilayer stack 100M may include a dielectric layer stack 120D and a dielectric interface layer 120I. The dielectric layer stack 120D may include a multilayer material, a laminated material, an intermixed material, or a combination thereof. The dielectric layer stack 120D may include a high-k material. When used herein, a high-k material refers to a material having a dielectric constant higher than both silicon oxide and silicon nitride. The dielectric layer stack 120D may include a combination of a high-k material and an ultra-high-k material. The dielectric layer stack 120D may include at least one layer of a high-k material and at least one layer of an ultra-high-k material. The dielectric layer stack 120D may include a mixed material of a high-k material and an ultra-high-k material. The ultra-high-k material may have a higher dielectric constant than the high-k material. For example, the high-k material may have a dielectric constant of about 10 or more, while the ultra-high-k material may have a dielectric constant of about 60 or more. The dielectric layer stack 120D may include a metal oxide-based material. The dielectric layer stack 120D may include aluminum oxide, hafnium oxide, zirconium oxide, or a combination thereof. The dielectric layer stack 120D may be directly formed on the first conductive layer 110 .

[0034] The dielectric interface layer 120I may be a material different from the dielectric layer stack 120D. The dielectric interface layer 120I may be used to protect the dielectric layer stack 120D when forming the second conductive layer 130. In addition, the dielectric interface layer 120I may reduce leakage current of the dielectric layer stack 120D.

[0035] The dielectric interface layer 120I may be a material that is reduced before the dielectric layer stack 120D when the second conductive layer 130 is deposited. The dielectric interface layer 120I may serve as a leakage current barrier having a high effective work function (eWF) and a large conduction band offset (CBO). In addition, the dielectric interface layer 120I may not increase the equivalent oxide layer thickness T of the dielectric layer stack 120D. ox .

[0036] The dielectric interface layer 120I may be a material having a high electronegativity. The dielectric interface layer 120I may have a higher Pauling electronegativity than the dielectric layer stack 120D. The dielectric interface layer 120I may include a material having a higher Pauling electronegativity (hereinafter referred to as "electronegativity") than zirconium oxide and hafnium oxide. Materials having a high electronegativity are difficult to oxidize and are easy to reduce. Therefore, the oxygen of the dielectric interface layer 120I but not the dielectric layer stack 120D may be removed. As a result, the dielectric interface layer 120I may prevent the loss of oxygen from the dielectric layer stack 120D.

[0037] The dielectric interface layer 120I may include atoms with high electronegativity, for example, metal atoms, silicon atoms, or germanium atoms. The dielectric interface layer 120I may include titanium (Ti), tantalum (Ta), aluminum (Al), tin (Sn), molybdenum (Mo), ruthenium (Ru), iridium (Ir), niobium (Nb), germanium (Ge), silicon (Si), or a combination thereof. The dielectric interface layer 120I may include a metal oxide-based material, a silicon oxide-based material, or a germanium oxide-based material.

[0038] The dielectric interface layer 120I may include titanium oxide, tantalum oxide, niobium oxide, aluminum oxide, silicon oxide (SiO2), tin oxide, germanium oxide, molybdenum dioxide, molybdenum trioxide, iridium oxide, ruthenium oxide, or a combination thereof. In the present embodiment, the dielectric interface layer 120I may be formed of titanium oxide, which may be referred to as a "titanium (Ti)-based interface layer".

[0039] The multilayer stack 100M may further include a high work function interface layer 140. The high work function interface layer 140 may be formed on the dielectric interface layer 120I. The high work function interface layer 140 may be formed directly on the dielectric interface layer 120I. The high work function interface layer 140 may be located between the dielectric interface layer 120I and the second conductive layer 130. The high work function interface layer 140 may suppress reduction of the dielectric layer stack 120D when the second conductive layer 130 is deposited, and may increase the effective work function between the dielectric layer stack 120D and the second conductive layer 130.

[0040] The dielectric interface layer 120I and the high work function interface layer 140 may be made of different materials. The high work function interface layer 140 may be made of a material deposited by atomic layer deposition (ALD). The high work function interface layer 140 may include a high work function material. The high work function interface layer 140 may include a material that further improves the effective work function compared to when the dielectric interface layer 120I is used. As a result, the present embodiment can further improve the leakage current by the combination of the dielectric interface layer 120I and the high work function interface layer 140.

[0041] The high work function interface layer 140 may include a zirconium-based material. The high work function interface layer 140 may include zirconium nitride (ZrN) or carbon-containing zirconium nitride. The carbon-containing zirconium nitride may include ZrCN. In the carbon-containing zirconium nitride, the effective work function may be adjusted according to the carbon content. The carbon content may be adjusted by controlling the flow rate of the zirconium source material and the flow rate of the reaction gas. A carbon-containing zirconium source may be used as the zirconium source material.

[0042] Zirconium nitride (ZrN) and carbon-containing zirconium nitride as the high work function interface layer 140 can be formed by ALD. For example, zirconium nitride (ZrN) and carbon-containing zirconium nitride can be formed using a zirconium (Zr) source material and a reaction gas. The reaction gas may include NH3. For example, the zirconium source material may include cyclopentadienyl tris (dimethylamino) zirconium CpZr (NME2) 3 (ZAC). ZAC may be a carbon-containing zirconium source material, and carbon-doped zirconium nitride may be deposited using ZAC. The carbon content of the carbon-doped zirconium nitride can be adjusted by the flow rate of the carbon-containing zirconium source material. The ALD for forming zirconium nitride and carbon-doped zirconium nitride may repeat the unit cycle of zirconium source material injection, purging, reaction gas injection and purging several times.

[0043] In the present embodiment, the dielectric interface layer 120I may be a titanium-based interface layer, and the high work function interface layer 140 may be a zirconium-based interface layer. The high work function interface layer 140 may have a thickness less than the dielectric interface layer 120I. The dielectric layer stack 120D may be a zirconium oxide-based material. Each of the dielectric layer stack 120D and the high work function interface layer 140 may include a zirconium-based material. The dielectric layer stack 120D may include a zirconium oxide-based material, and the high work function interface layer 140 may include a zirconium nitride-based material.

[0044] Figure 2A 1 is a schematic diagram of an example of a dielectric layer stack 120D. The dielectric layer stack 120D may include a first dielectric layer 121 and a second dielectric layer 123. The first dielectric layer 121 and the second dielectric layer 123 may have a high dielectric constant of about 40 or more. Each of the first dielectric layer 121 and the second dielectric layer 123 may have a tetragonal crystal structure. The first dielectric layer 121 and the second dielectric layer 123 may be made of the same material. Each of the first dielectric layer 121 and the second dielectric layer 123 may include a zirconium oxide-based material. Each of the first dielectric layer 121 and the second dielectric layer 123 may include zirconium oxide. Each of the first dielectric layer 121 and the second dielectric layer 123 may include tetragonal zirconium oxide. The first dielectric layer 121 and the second dielectric layer 123 may be formed by ALD.

[0045] The dielectric layer stack 120D may also include a first leakage barrier layer 122 and a second leakage barrier layer 124. The first leakage barrier layer 122 and the second leakage barrier layer 124 may be used to suppress leakage current of the dielectric layer stack 120D. Each of the first leakage barrier layer 122 and the second leakage barrier layer 124 may include a high bandgap material. The first leakage barrier layer 122 and the second leakage barrier layer 124 may include a material with a higher bandgap energy than the first dielectric layer 121 and the second dielectric layer 123. The first leakage barrier layer 122 and the second leakage barrier layer 124 may be made of a material different from the first dielectric layer 121 and the second dielectric layer 123. Each of the first leakage barrier layer 122 and the second leakage barrier layer 124 may include a high-k material, but may have a lower dielectric constant than the first dielectric layer 121 and the second dielectric layer 123. In one embodiment, each of the first leakage barrier layer 122 and the second leakage barrier layer 124 may have a higher dielectric constant than silicon oxide (SiO2). Note that the dielectric constant of silicon oxide is about 3.9. For example, each of the first leakage barrier layer 122 and the second leakage barrier layer 124 may be made of aluminum oxide or beryllium oxide. Beryllium oxide may be amorphous. Beryllium oxide may have a wurtzite crystal structure or a rock salt structure. The first leakage barrier layer 122 and the second leakage barrier layer 124 may be formed by ALD. The first leakage barrier layer 122 and the second leakage barrier layer 124 may have a thickness smaller than that of the first dielectric layer 121 and the second dielectric layer 123, so that the reduction in capacitance of the dielectric layer stack 120D may be minimized.

[0046] In another embodiment, each of the first leakage barrier layer 122 and the second leakage barrier layer 124 may have a higher dielectric constant than silicon nitride (Si3N4). Note that silicon nitride has a dielectric constant of about 7.5.

[0047] In some embodiments, the first leakage barrier layer 122 may be very thin and may be embedded in the first dielectric layer 121 or / and the second dielectric layer 123. The first leakage barrier layer 122 may not separate the grains of the first dielectric layer 121 and the second dielectric layer 123. In other words, the first leakage barrier layer 122 may not separate the tetragonal crystal structures of the first dielectric layer 121 and the second dielectric layer 123. The first leakage barrier layer 122 may be manufactured by placing a dopant inside the top surface of the first dielectric layer 121 or the bottom surface of the second dielectric layer 123 to form an extremely thin doping interface.

[0048] For example, when the first dielectric layer 121 and the second dielectric layer 123 include tetragonal zirconia, the first leakage barrier layer 122 may include tetragonal zirconia doped with a dopant. The dopant of the first leakage barrier layer 122 may include aluminum (Al) or beryllium (Be). For example, the first leakage barrier layer 122 may include aluminum-doped tetragonal zirconia or beryllium-doped zirconia.

[0049] The thickness of the first dielectric layer 121 and the second dielectric layer 123 may be adjusted based on the first leakage barrier layer 122. The first leakage barrier layer 122 may have a higher band gap than the first dielectric layer 121 and the second dielectric layer 123. Each of the first dielectric layer 121 and the second dielectric layer 123 may have a band gap energy of about 5.8 eV, and the first leakage barrier layer 122 may have a band gap energy of about 8.8 eV to about 10.6 eV.

[0050] The second leakage barrier layer 124 may be formed between the second dielectric layer 123 and the dielectric interface layer 120I. The second leakage barrier layer 124 may be embedded on the uppermost surface of the second dielectric layer 123. The second leakage barrier layer 124 may be formed of the same material as the first leakage barrier layer 122. For example, the second leakage barrier layer 124 may include aluminum-doped zirconium oxide or beryllium-doped zirconium oxide. Due to the increased band gap energy provided by the first leakage barrier layer 122 and the second leakage barrier layer 124, the thickness of the entire dielectric layer stack may be reduced to improve the capacitance of the capacitor 100 while also improving the leakage barrier properties of the capacitor 100. In some embodiments, the first leakage barrier layer 122 may include aluminum-doped tetragonal zirconium oxide, and the second leakage barrier layer 124 may include aluminum oxide. In some embodiments, the first leakage barrier layer 122 and the second leakage barrier layer 124 are thinner than the first dielectric layer 121 and the second dielectric layer 123.

[0051] As described above, the high band gaps of the first leakage barrier layer 122 and the second leakage barrier layer 124 may suppress the leakage current of the capacitor 100 .

[0052] Figure 2B is a diagram showing the dielectric layer stack 120D in more detail.

[0053] refer to Figure 2B, the dielectric layer stack 120D in which the first leakage barrier layer 122 and the second leakage barrier layer 124 are embedded may be divided into the first dielectric layer 121, the first leakage barrier layer 122, the second dielectric layer 123, and the second leakage barrier layer 124. The first dielectric layer 121, the first leakage barrier layer 122, the second dielectric layer 123, and the second leakage barrier layer 124 may have grains 120G that are not separated but continuous with each other. Each of the first dielectric layer 121, the first leakage barrier layer 122, the second dielectric layer 123, and the second leakage barrier layer 124 may have a tetragonal crystal structure. The first leakage barrier layer 122 may not separate the grains 120G of the first dielectric layer 121 from the grains 120G of the second dielectric layer 123. Compared with the first dielectric layer 121 and the second dielectric layer 123, the first leakage barrier layer 122 and the second leakage barrier layer 124 may have very small thicknesses.

[0054] Each of the first dielectric layer 121 and the second dielectric layer 123 may be undoped tetragonal zirconia not doped with a dopant, and each of the first leakage barrier layer 122 and the second leakage barrier layer 124 may be doped tetragonal zirconia doped with a dopant. The first leakage barrier layer 122 and the second leakage barrier layer 124 may include aluminum or beryllium as a dopant.

[0055] As described above, although each of the first leakage barrier layer 122 and the second leakage barrier layer 124 includes a dopant, each of the first leakage barrier layer 122 and the second leakage barrier layer 124 may not be an oxide layer of the dopant. For example, the first leakage barrier layer 122 and the second leakage barrier layer 124 may not be an aluminum oxide (Al2O3) layer, but aluminum-doped tetragonal zirconium oxide.

[0056] In the present embodiment, the first dielectric layer 121, the first leakage barrier layer 122, the second dielectric layer 123, and the second leakage barrier layer 124 may be a first zirconium oxide layer, a first aluminum-doped zirconium oxide layer, a second zirconium oxide layer, and a second aluminum-doped zirconium oxide layer, respectively. Therefore, the dielectric layer stack 120D may include a "Z-AZ-Z-AZ stack" in which a first zirconium oxide layer, a first aluminum-doped zirconium oxide layer, a second zirconium oxide layer, and a second aluminum-doped zirconium oxide layer are sequentially stacked. In the Z-AZ-Z-AZ stack, "Z" may refer to zirconium oxide, and "AZ" may refer to aluminum-doped zirconium oxide. All materials of the Z-AZ-Z-AZ stack may have a tetragonal crystal structure.

[0057] Figure 2C is a diagram showing a dielectric layer stack 120D′ according to a comparative example.

[0058] refer to Figure 2CThe dielectric layer stack 120D' may include a first dielectric layer 121, an aluminum oxide (Al2O3) layer 122', a second dielectric layer 123, and an aluminum oxide (Al2O3) layer 124'. The grains 120G of the first dielectric layer 121 and the grains 120G of the second dielectric layer 123 may be separated from each other by the aluminum oxide layer 122' (see reference mark "120S"). The grains of the first dielectric layer 121 and the grains of the second dielectric layer 123 may be separated in a vertical direction by the aluminum oxide layer 122'. The aluminum oxide layer 122' may have a relative thickness of Figure 2B The first leakage barrier layer 122 has a large thickness and can be a continuous layer. When the first dielectric layer 121 and the second dielectric layer 123 include zirconium oxide, the dielectric layer stack 120D' can be referred to as a "ZAZA stack". In the ZAZA stack, "Z" can refer to zirconium oxide, and "A" can refer to aluminum oxide.

[0059] The dielectric layer stack 120D according to the present embodiment includes a Z-AZ-Z-AZ stack, while the dielectric layer stack 120D' according to the comparative example includes a ZAZA stack. In the Z-AZ-Z-AZ stack, the grains of the first zirconium oxide layer are not separated from the grains of the second zirconium oxide layer by the aluminum-doped zirconium oxide layer. In contrast, in the ZAZA stack, the grains of the first zirconium oxide layer are separated from the grains of the second zirconium oxide layer by the aluminum oxide layer.

[0060] In the comparative example, when the grains 120G of the first dielectric layer 121 are separated from the grains 120G of the second dielectric layer 123 by the aluminum oxide layer 122', the dielectric constant of the first dielectric layer 121 and the dielectric constant of the second dielectric layer 123 are reduced. When the dielectric constants of the first dielectric layer 121 and the second dielectric layer 123 are reduced, it is impossible to reduce the equivalent oxide layer thickness T ox .

[0061] According to the above Figure 2B , the thickness of the equivalent oxide layer can be reduced while increasing the dielectric constant of the dielectric layer stack 120D in which the first leakage barrier layer 122 and the second leakage barrier layer 124 are embedded. The leakage current of the dielectric layer stack 120D can be suppressed by the first leakage barrier layer 122 and the second leakage barrier layer 124.

[0062] In some embodiments, the second leakage barrier layer 124 may be omitted. Therefore, the dielectric layer stack 120D may include a first dielectric layer 121 and a second dielectric layer 123 in which the first leakage barrier layer 122 is embedded. The dielectric layer stack 120D may include a Z-AZ-Z stack. The materials of the Z-AZ-Z stack may all have a tetragonal crystal structure.

[0063] FIG. 3A to FIG. 3D is a cross-sectional view illustrating a method for manufacturing a capacitor according to an embodiment of the present disclosure.

[0064] like Figure 3A As shown, a first conductive layer 110 may be formed. The first conductive layer 110 may include a metal or a metal-containing material. The first conductive layer 110 may include a metal, a metal nitride, a metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof. The first conductive layer 110 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), molybdenum, molybdenum oxide, iridium oxide (IrO2), or a combination thereof. In the present embodiment, the first conductive layer 110 may be referred to as a "bottom electrode" or a "storage node". The first conductive layer 110 may be formed of ALD titanium nitride (i.e., titanium nitride deposited by ALD).

[0065] The dielectric layer stack 120D may be formed on the first conductive layer 110. The dielectric layer stack 120D may be formed directly on the first conductive layer 110. The dielectric layer stack 120D may be formed with Figure 2A and Figure 2B The dielectric layer stack 120D shown is identical.

[0066] The dielectric layer stack 120D may be deposited by ALD. For example, the prepared substrate having the first conductive layer 110 may be loaded into an atomic layer deposition chamber, and then the dielectric layer stack 120D may be deposited on the first conductive layer 110.

[0067] When the dielectric layer stack 120D is a zirconium oxide-based material, atomic layer deposition of zirconium oxide may be performed. For example, the atomic layer deposition of zirconium oxide may repeat a unit cycle consisting of zirconium source material injection, purge, reaction gas material injection, and purge several times.

[0068] When depositing zirconium oxide, the dielectric layer stack 120D may also be subjected to aluminum source material injection and purge. The atomic layer deposition of the dielectric layer stack 120D may be performed in the order of depositing the first zirconium oxide, forming the first leakage barrier layer, depositing the second zirconium oxide, and forming the second leakage barrier layer. The first zirconium oxide and the second zirconium oxide may be deposited using the same unit cycle. The first leakage barrier layer and the second leakage barrier layer may be formed using the same unit cycle.

[0069] The first zirconium oxide and the second zirconium oxide may be deposited by repeating a unit cycle consisting of zirconium source material injection, purging, reaction gas material injection and purging several times. The first leakage barrier layer and the second leakage barrier layer may be formed by repeating a unit cycle consisting of aluminum source material injection and purging several times. Thus, a dielectric layer stack 120D in which the first leakage barrier layer 122 and the second leakage barrier layer 124 are embedded may be deposited. The dielectric layer stack 120D may be a material in which aluminum is embedded in zirconium oxide.

[0070] like Figure 3B As shown, a dielectric interface layer 120I may be formed on the dielectric layer stack 120D. The dielectric interface layer 120I may be formed directly on the dielectric layer stack 120D. The dielectric interface layer 120I may be deposited by ALD. The dielectric interface layer 120I may include a titanium oxide-based material. The dielectric interface layer 120I may be formed by ALD of titanium oxide. The ALD of titanium oxide may be performed by repeating a unit cycle consisting of titanium source material injection, purging, reactive gas injection, and purging for several times. TiCl4 may be used as a titanium source material, and an oxygen-containing gas may be used as a reactive gas.

[0071] like Figure 3C As shown, the high work function interface layer 140 can be formed on the dielectric interface layer 120I. The high work function interface layer 140 can be formed directly on the dielectric interface layer 120I. The high work function interface layer 140 can be deposited by ALD. The high work function interface layer 140 can include a zirconium-based material. The high work function interface layer 140 can be formed by ALD of zirconium nitride. The ALD of zirconium nitride can be performed by repeating a unit cycle consisting of zirconium source material injection, purging, reaction gas injection and purging for several times. ZAC (CpZr (NME2) 3) can be used as a zirconium source material, and a nitrogen-containing gas can be used as a reaction gas. The nitrogen-containing gas can include NH3. The flow rate of the nitrogen-containing gas or the flow rate of the ZAC can be adjusted to deposit carbon-doped zirconium nitride. The carbon content of the carbon-doped zirconium nitride can be adjusted by the flow rate of the ZAC instead of the flow rate of the nitrogen-containing gas. The flow rate of the nitrogen-containing gas and the number of cycles can help improve the leakage current. For example, when the flow rate of the nitrogen-containing gas increases or the number of cycles of the nitrogen-containing gas decreases, the leakage current of the capacitor may be improved. The multilayer stack 100M may include a dielectric layer stack 120D, a dielectric interface layer 120I, and a high work function interface layer 140 .

[0072] like Figure 3DAs shown in , the second conductive layer 130 can be formed on the high work function interface layer 140. The second conductive layer 130 can be directly formed on the high work function interface layer 140. The second conductive layer 130 may include a metal-containing material. The second conductive layer 130 may include a metal, a metal nitride, a metal carbide, a conductive metal nitride, a conductive metal oxide, or a combination thereof. The second conductive layer 130 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), molybdenum, molybdenum oxide, iridium oxide (IrO2), or a combination thereof. The second conductive layer 130 may have a structure in which titanium nitride (TiN) and silicon germanium (SiGe) are sequentially stacked. When the second conductive layer 130 is formed, the high work function interface layer 140 can prevent the dielectric interface layer 120I and the dielectric layer stack 120D from being reduced. Therefore, oxygen loss of the dielectric layer stack 120D can be prevented.

[0073] In the above-described embodiment, the dielectric layer stack 120D, the dielectric interface layer 120I, and the high work function interface layer 140 may be sequentially stacked between the first conductive layer 110 and the second conductive layer 130. Since the dielectric layer stack 120D includes a zirconium oxide stack in which aluminum is embedded, i.e., a Z-AZ-Z-AZ stack, and the dielectric interface layer 120I and the high work function interface layer 140 include titanium oxide and zirconium nitride, respectively, a “Z-AZ-Z-AZ-T-ZN stack” may be formed between the first conductive layer 110 and the second conductive layer 130. In the Z-AZ-Z-AZ-T-ZN stack, “ZN” may refer to zirconium nitride.

[0074] Figure 4 is a graph describing a change in work function according to the formation of the high work function interface layer 140 . Figure 4 Capacitance / voltage (CV) characteristics are compared and the shift of the flatband voltage is shown. The flatband voltage may depend on the work function. The flatband voltage may be shifted by increasing or decreasing the work function. A high work function may shift the flatband voltage in a positive direction, while a low work function may shift the flatband voltage in a negative direction.

[0075] exist Figure 4 In the embodiment, the ZAZAT stack may refer to a Z-AZ-Z-AZ-T stack, in which the high work function interface layer 140 is omitted and a dielectric layer stack 120D and a dielectric interface layer 120I are stacked. The ZAZATZ stack may refer to a Z-AZ-Z-AZ-T-ZN stack, in which a dielectric layer stack 120D, a dielectric interface layer 120I and a high work function interface layer 140 are stacked.

[0076] refer to Figure 4, it can be seen that in the ZAZATZ stack, the flat band voltage is shifted in the positive direction (see reference mark "PS"), and therefore, the effective work function in the ZAZATZ stack is further improved than that in the ZAZAT stack. The effective work function in the ZAZATZ stack can be further improved by 0.1 eV to 0.2 eV than that in the ZAZAT stack. For example, an effective work function of about 4.6 eV can be obtained by the ZAZAT stack, while an effective work function of about 4.8 eV or higher can be obtained by the ZAZATZ stack.

[0077] Figure 5 is a graph describing the leakage current Cap LKG according to the formation of the high work function interface layer 140. Figure 5 , it can be seen that the leakage current Cap LKG in the ZAZATZ stack is further reduced than the leakage current Cap LKG in the ZAZAT stack. For example, the leakage current Cap LKG in the ZAZATZ stack can be further reduced by about 50% than the leakage current in the ZAZAT stack. In addition, the equivalent oxide thickness T in the ZAZATZ stack ox can be compared to the equivalent oxide thickness T in the ZAZAT stack ox Further reduction (see reference symbol "T ox Zoom”).

[0078] Fig. 6A and Figure 6B is a cross-sectional view showing a capacitor according to an embodiment of the present disclosure.

[0079] refer to Fig. 6A , capacitor 200 can be similar to Figure 1 The capacitor 100 of FIG. 200 may include a first conductive layer 110, a multilayer stack 200M, and a second conductive layer 130. The multilayer stack 200M may include a dielectric layer stack 120, a dielectric interface layer 120I, and a high work function interface layer 140. The dielectric layer stack 120 may include a first dielectric layer 121, a first leakage barrier layer 122, a second dielectric layer 123, and a second leakage barrier layer 124. The first leakage barrier layer 122 and the second leakage barrier layer 124 may be embedded in the dielectric layer stack 120. The high work function interface layer 140 may be located between the dielectric interface layer 120I and the second conductive layer 130.

[0080] The multilayer stack 200M may further include an ultra-high-k layer 220 between the dielectric layer stack 120 and the first conductive layer 110. The ultra-high-k layer 220 may have a higher dielectric constant than the dielectric layer stack 120. The ultra-high-k layer 220 may have a dielectric constant of about 60 or more. The ultra-high-k layer 220 and the dielectric layer stack 120 may include different materials. The ultra-high-k layer 220 may have a tetragonal crystal structure.

[0081] The ultra-high-k layer 220 may include a hafnium oxide-based material. The ultra-high-k layer 220 may include tetragonal hafnium oxide. Tetragonal hafnium oxide refers to hafnium oxide having a tetragonal crystal structure. The bottom surface of the ultra-high-k layer 220 may directly contact the first conductive layer 110, and the top surface of the ultra-high-k layer 220 may directly contact the dielectric layer stack 120. The ultra-high-k layer 220 may have a pure tetragonal crystal structure. The high dielectric constant of the ultra-high-k layer 220 may be obtained by the dielectric layer stack 120. For example, the first dielectric layer 121 of the dielectric layer stack 120 may be used as a seed to promote tetragonal crystallization of the ultra-high-k layer 220.

[0082] The multilayer stack 200M may include a HZ-AZ-Z-AZ-T-ZN stack. In the HZ-AZ-Z-AZ-T-ZN stack, "H" may represent tetragonal hafnium oxide.

[0083] refer to Figure 6B , capacitor 201 can be similar to Fig. 6A The capacitor 200 may include a first conductive layer 110, a multilayer stack 201M, and a second conductive layer 130. The multilayer stack 201M may include a dielectric layer stack 120, a dielectric interface layer 120I, and a high work function interface layer 140. The dielectric layer stack 120 may include a first dielectric layer 121, a first leakage barrier layer 122, a second dielectric layer 123, and a second leakage barrier layer 124. The first leakage barrier layer 122 and the second leakage barrier layer 124 may be embedded in the dielectric layer stack 120. The high work function interface layer 140 may be located between the dielectric interface layer 120I and the second conductive layer 130.

[0084] The multilayer stack 201M may further include a first ultra-high-k layer 221 between the dielectric layer stack 120 and the first conductive layer 110. The first ultra-high-k layer 221 may have a higher dielectric constant than the dielectric layer stack 120. The first ultra-high-k layer 221 may have a dielectric constant of about 60 or more. The first ultra-high-k layer 221 and the dielectric layer stack 120 may include different materials. The first ultra-high-k layer 221 may have a tetragonal crystal structure.

[0085] The first ultra-high-k layer 221 may include a hafnium oxide-based material. The first ultra-high-k layer 221 may include tetragonal hafnium oxide. The bottom surface of the first ultra-high-k layer 221 may directly contact the first conductive layer 110, and the top surface of the first ultra-high-k layer 221 may directly contact the first dielectric layer 121 of the dielectric layer stack 120. The first ultra-high-k layer 221 may have a pure tetragonal crystal structure. The high dielectric constant of the first ultra-high-k layer 221 may be obtained by the dielectric layer stack 120. For example, the first dielectric layer 121 of the dielectric layer stack 120 may be used as a seed to promote tetragonal crystallization of the first ultra-high-k layer 221.

[0086] The multilayer stack 201M may further include a second ultra-high-k layer 222. The second ultra-high-k layer 222 may be embedded in the dielectric layer stack 120. The second ultra-high-k layer 222 may have a higher dielectric constant than the dielectric layer stack 120. The second ultra-high-k layer 222 may have a dielectric constant of about 60 or higher. The second ultra-high-k layer 222 and the dielectric layer stack 120 may include different materials. The second ultra-high-k layer 222 may have a tetragonal crystal structure.

[0087] The second ultra-high-k layer 222 may include a hafnium oxide-based material. The second ultra-high-k layer 222 may include tetragonal hafnium oxide. The top surface of the second ultra-high-k layer 222 may directly contact the second leakage barrier layer 124, and the bottom surface of the second ultra-high-k layer 222 may directly contact the second dielectric layer 123. The second ultra-high-k layer 222 may have a tetragonal crystal structure. The high dielectric constant of the second ultra-high-k layer 222 may be obtained by the dielectric layer stack 120. For example, the second dielectric layer 123 of the dielectric layer stack 120 may be used as a seed to promote tetragonal crystallization of the second ultra-high-k layer 222.

[0088] The multilayer stack 201M may include a HZ-AZ-ZH-AZ-T-ZN stack.

[0089] exist Fig. 6A and Figure 6B In the embodiment, each of the ultra-high-k layer 220, the first ultra-high-k layer 221, and the second ultra-high-k layer 222 may further include a dopant. The dopant may include strontium (Sr), lanthanum (La), gadolinium (Gd), aluminum (Al), silicon (Si), yttrium (Y), zirconium (Zr), niobium (Nb), bismuth (Bi), germanium (Ge), dysprosium (Dy), titanium (Ti), cerium (Ce), magnesium (Mg), or nitrogen (N).

[0090] FIG. 7A to FIG. 7C is a cross-sectional view showing a capacitor according to an embodiment of the present disclosure.

[0091] refer to Fig. 7A , capacitor 300 can be similar to Figure 1The capacitor 100 of FIG. 300 may include a first conductive layer 110, a multilayer stack 300M, and a second conductive layer 130. The multilayer stack 300M may include a dielectric layer stack 320, a dielectric interface layer 120I, and a high work function interface layer 140. The dielectric layer stack 320 may include a first hafnium oxide 321, a first leakage barrier layer 322, a second hafnium oxide 323, and a second leakage barrier layer 324. The dielectric interface layer 120I may include titanium oxide. The high work function interface layer 140 may include zirconium nitride or carbon-doped zirconium nitride.

[0092] Each of the first hafnium oxide 321 and the second hafnium oxide 323 may include a hafnium oxide-based material. Therefore, the dielectric layer stack 320 may include the first hafnium oxide 321, the first leakage barrier layer 322, the second hafnium oxide 323, and the second leakage barrier layer 324. Each of the first leakage barrier layer 322 and the second leakage barrier layer 324 may include aluminum. The first leakage barrier layer 322 and the second leakage barrier layer 324 may be embedded in the hafnium oxide-based material. Each of the first leakage barrier layer 322 and the second leakage barrier layer 324 may include aluminum-doped hafnium oxide. Each of the first hafnium oxide 321 and the second hafnium oxide 323 may have a tetragonal crystal structure.

[0093] The multilayer stack 300M may include a H-AH-H-AH-T-ZN stack. In the H-AH-H-AH-T-ZN stack, "AH" may refer to aluminum-doped hafnium oxide.

[0094] refer to Figure 7B , capacitor 301 can be similar to Fig. 7A The capacitor 300 may include a first conductive layer 110, a multilayer stack 301M, and a second conductive layer 130. The multilayer stack 301M may include a dielectric layer stack 320, a dielectric interface layer 120I, and a high work function interface layer 140. The dielectric layer stack 320 may include a first hafnium oxide 321, a first leakage barrier layer 322, a second hafnium oxide 323, and a second leakage barrier layer 324.

[0095] Each of the first hafnium oxide 321 and the second hafnium oxide 323 may include a hafnium oxide-based material. Therefore, the dielectric layer stack 320 may include the first hafnium oxide 321, the first leakage barrier layer 322, the second hafnium oxide 323, and the second leakage barrier layer 324. Each of the first leakage barrier layer 322 and the second leakage barrier layer 324 may include aluminum. The first leakage barrier layer 322 and the second leakage barrier layer 324 may be embedded in the hafnium oxide-based material. Each of the first leakage barrier layer 322 and the second leakage barrier layer 324 may include aluminum-doped hafnium oxide. Each of the first hafnium oxide 321 and the second hafnium oxide 323 may have a tetragonal crystal structure.

[0096] The multilayer stack 301M may further include a seed layer 331 between the dielectric layer stack 320 and the first conductive layer 110. The seed layer 331 may have a lower dielectric constant than the dielectric layer stack 320. The seed layer 331 may have a dielectric constant of about 40. The seed layer 331 and the dielectric layer stack 320 may include different materials. The seed layer 331 may have a tetragonal crystal structure.

[0097] The seed layer 331 may include a zirconium oxide-based material. The seed layer 331 may include tetragonal zirconium oxide. The bottom surface of the seed layer 331 may directly contact the first conductive layer 110, and the top surface of the seed layer 331 may directly contact the dielectric layer stack 320. The seed layer 331 may have a pure tetragonal crystal structure. For example, the seed layer 331 may be used as a seed to promote tetragonal crystallization of the dielectric layer stack 320. The seed layer 331 may be used as a seed to promote tetragonal crystallization of the first hafnium oxide 321.

[0098] The multilayer stack 301M may include a ZH-AH-H-AH-T-ZN stack.

[0099] refer to Figure 7C , capacitor 302 may be similar to Figure 7B The capacitor 301 of FIG. 302 may include a first conductive layer 110, a multilayer stack 302M, and a second conductive layer 130. The multilayer stack 302M may include a dielectric layer stack 320, a dielectric interface layer 120I, and a high work function interface layer 140. The dielectric layer stack 320 may include a first hafnium oxide 321, a first leakage barrier layer 322, a second hafnium oxide 323, and a second leakage barrier layer 324. Each of the first leakage barrier layer 322 and the second leakage barrier layer 324 may include aluminum. The first leakage barrier layer 322 and the second leakage barrier layer 324 may be embedded in a hafnium oxide-based material. Each of the first hafnium oxide 321 and the second hafnium oxide 323 may have a tetragonal crystal structure. The multilayer stack 302M may further include a first seed layer 331 between the dielectric layer stack 320 and the first conductive layer 110. The first seed layer 331 may have a lower dielectric constant than the dielectric layer stack 320. The first seed layer 331 may have a dielectric constant of about 40.

[0100] The first seed layer 331 and the dielectric layer stack 320 may include different materials. The first seed layer 331 may have a tetragonal crystal structure.

[0101] The first seed layer 331 may include a zirconium oxide-based material. The first seed layer 331 may include tetragonal zirconium oxide. The bottom surface of the first seed layer 331 may directly contact the first conductive layer 110, and the top surface of the first seed layer 331 may directly contact the dielectric layer stack 320. The first seed layer 331 may have a pure tetragonal crystal structure. The first seed layer 331 may be used as a seed to promote tetragonal crystallization of the dielectric layer stack 320. The first seed layer 331 may be used as a seed to promote tetragonal crystallization of the first hafnium oxide 321.

[0102] The multilayer stack 302M may further include a second seed layer 332 embedded in the dielectric layer stack 320. The second seed layer 332 may have a lower dielectric constant than the dielectric layer stack 320. The second seed layer 332 may have a dielectric constant of about 40. The second seed layer 332 may contact the second hafnium oxide 323.

[0103] The second seed layer 332 and the dielectric layer stack 320 may include different materials. The second seed layer 332 may have a tetragonal crystal structure. The first seed layer 331 and the second seed layer 332 may include the same material.

[0104] The second seed layer 332 may include a zirconium oxide-based material. The second seed layer 332 may include tetragonal zirconium oxide. The bottom surface of the second seed layer 332 may directly contact the second hafnium oxide 323, and the top surface of the second seed layer 332 may directly contact the second leakage barrier layer 324. The second seed layer 332 may have a pure tetragonal crystal structure. For example, the second seed layer 332 may be used as a seed to promote tetragonal crystallization of the second hafnium oxide 323.

[0105] As described above, the first seed layer 331 and the second seed layer 332 may serve as seeds promoting tetragonal crystallization of the first hafnium oxide 321 and the second hafnium oxide 323 , respectively.

[0106] The multilayer stack 302M may include a ZH-AH-HZ-AH-T-ZN stack.

[0107] Figure 8 is a cross-sectional view showing a capacitor 400 according to an embodiment of the present disclosure.

[0108] refer to Figure 8 , capacitor 400 may be similar to Figure 1 The capacitor 400 may include a first conductive layer 110, a multilayer stack 400M, and a second conductive layer 130. The multilayer stack 400M may include a dielectric layer 420, a dielectric interface layer 120I, and a high work function interface layer 140. The dielectric layer 420 may include a HZO (HfZrO) structure in which hafnium oxide and zirconium oxide are mixed with each other.

[0109] 9A to 9C is a diagram showing a storage unit 500 . Fig. 9B is along Fig. 9A A cross-sectional view taken along the line A-A'. Fig. 9C is along Fig. 9A Cross-sectional view taken along line BB'.

[0110] The memory cell 500 may include a cell transistor including a buried word line 508, a bit line 514, and a capacitor 600. The capacitor 600 may include a dielectric layer stack, and the dielectric layer stack may include any one of the dielectric layer stacks described in the above embodiments.

[0111] The storage unit 500 is described in detail below.

[0112] An isolation layer 503 and an active area 504 may be formed in the substrate 501. A plurality of active areas 504 may be defined by the isolation layer 503. The substrate 501 may be a material suitable for a semiconductor process. The substrate 501 may include a semiconductor substrate. The substrate 501 may be formed of a silicon-containing material. The substrate 501 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The substrate 501 may include another semiconductor material, such as germanium. The substrate 501 may include a III / V semiconductor substrate, such as a chemical compound semiconductor substrate, such as gallium arsenide (GaAs). The substrate 501 may include a silicon on insulator (SOI) substrate. The isolation layer 503 may be formed in the isolation trench 502 by a shallow trench isolation (STI) process.

[0113] A word line trench 506 may be formed in the substrate 501. The word line trench 506 may also be referred to as a gate trench. A gate dielectric layer 507 may be formed on the surface of the word line trench 506. A buried word line 508 may be formed on the gate dielectric layer 507, which fills a portion of the word line trench 506. The buried word line 508 may also be referred to as a buried gate electrode. A word line capping layer 509 may be formed on the buried word line 508. The top surface of the buried word line 508 may be lower than the top surface of the substrate 501. The buried word line 508 may be a metal material with a low resistivity. The buried word line 508 may be formed by sequentially stacking titanium nitride and tungsten. In some embodiments, the buried word line 508 may be formed only of titanium nitride (TiN).

[0114] A first impurity region 510 and a second impurity region 511 may be formed in the substrate 501. The first impurity region 510 and the second impurity region 511 may be spaced apart from each other by the word line trench 506. The first impurity region 510 and the second impurity region 511 may also be referred to as a first source / drain region and a second source / drain region, respectively. The first impurity region 510 and the second impurity region 511 may include N-type impurities such as arsenic (As) and phosphorus (P). Therefore, the buried word line 508 and the first impurity region 510 and the second impurity region 511 may become a cell transistor. Due to the presence of the buried word line 508, the cell transistor may improve the short channel effect.

[0115] A bit line contact plug 513 may be formed on the substrate 501. The bit line contact plug 513 may be coupled to the first impurity region 510. The bit line contact plug 513 may be located within the bit line contact hole 512. The bit line contact hole 512 may be formed in the hard mask layer 505. The hard mask layer 505 may be formed on the substrate 501. The bit line contact hole 512 may expose the first impurity region 510. The bottom surface of the bit line contact plug 513 may be lower than the top surface of the substrate 501. The bit line contact plug 513 may be formed of polysilicon or a metal material. A portion of the bit line contact plug 513 may have a line width smaller than a diameter of the bit line contact hole 512. A bit line 514 may be formed on the bit line contact plug 513. A bit line hard mask 515 may be formed on the bit line 514. The stacked structure of the bit line 514 and the bit line hard mask 515 may also be referred to as a bit line structure BL. The bit line 514 may have a line shape extending in a direction crossing the buried word line 508. A portion of the bit line 514 may be coupled to the bit line contact plug 513. The bit line 514 may include a metal material. The bit line hard mask 515 may include a dielectric material.

[0116] A bit line spacer 516 may be formed on the sidewall of the bit line structure BL. The bottom of the bit line spacer 516 may extend to be formed on both sidewalls of the bit line contact plug 513. The bit line spacer 516 may include silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the bit line spacer 516 may include an air gap. For example, the bit line spacer 516 may have a nitride-air gap-nitride (NAN) structure, in which the air gap is located between silicon nitrides.

[0117] A storage node contact plug SNC may be formed between adjacent bit line structures BL. The storage node contact plug SNC may be formed in a storage node contact hole 518. The storage node contact plug SNC may be coupled to the second impurity region 511. The storage node contact plug SNC may include a bottom plug 519 and a top plug 521. The storage node contact plug SNC may further include an ohmic contact layer 520 between the bottom plug 519 and the top plug 521. The ohmic contact layer 520 may include a metal silicide. The top plug 521 may include a metal material, and the bottom plug 519 may include a silicon-containing material.

[0118] From a perspective parallel to the bit line structure BL, a plug isolation layer 517 may be formed between adjacent storage node contact plugs SNC. The plug isolation layer 517 may be formed between adjacent bit line structures BL and may provide a storage node contact hole 518 together with the hard mask layer 505.

[0119] The capacitor 600 may be formed on the storage node contact plug SNC.

[0120] FIG. 10A to FIG. 10F It is shown 9A to 9C A cross-sectional view of an application example of capacitor 600 is shown.

[0121] refer to Fig. 10A , the capacitor 611 may include a bottom electrode 601, a multilayer stack 600M and a top electrode 602. The first conductive layer 110 and the second conductive layer 130 of the above-mentioned embodiment may correspond to the bottom electrode 601 and the top electrode 602, respectively. The bottom electrode 601 may be formed in a cylindrical shape. The multilayer stack 600M may be formed between the bottom electrode 601 and the top electrode 602. The multilayer stack 600M may include a dielectric layer stack 603 and a high work function interface layer 604. The dielectric layer stack 603 may correspond to any one of the dielectric layer stacks of the above-mentioned embodiments. For example, the dielectric layer stack 603 may include a zirconium oxide-based material or a hafnium oxide-based material, and the high work function interface layer 604 may include zirconium nitride or carbon-doped zirconium nitride. Although not shown, a dielectric interface layer may be further formed between the dielectric layer stack 603 and the high work function interface layer 604.

[0122] In the following, the FIG. 10B to FIG. 10F The capacitors 612, 613, 614, 615 and 616 shown in FIG. Fig. 10A Detailed description of components and structures identical or similar to capacitor 611 shown in FIG.

[0123] refer to Fig. 10B, the capacitor 612 may include a cylindrical bottom electrode 601, a multilayer stack 600M and a top electrode 602. The capacitor 612 may further include a support member 600S. The support member 600S is a structure for supporting the outer wall of the bottom electrode 601. The support member 600S may include silicon nitride. The support member 600S may have a single support member structure. In some embodiments, a plurality of support members 600S may support the outer wall of the bottom electrode 601. The plurality of support members 600S may be formed into a multilayer horizontal support member structure. The multilayer horizontal support member structure may include two or more support members. For example, a three-layer horizontal support member structure may include: a bottom support member for supporting the bottom outer wall of the bottom electrode 601; an intermediate support member for supporting the intermediate outer wall of the bottom electrode 601; and a top support member for supporting the top outer wall of the bottom electrode 601.

[0124] The multilayer stack 600M may include a dielectric layer stack 603 and a high work function interface layer 604. The dielectric layer stack 603 may correspond to any one of the dielectric layer stacks of the above-described embodiments. For example, the dielectric layer stack 603 may include a zirconium oxide-based material or a hafnium oxide-based material, and the high work function interface layer 604 may include zirconium nitride or carbon-doped zirconium nitride. Although not shown, a dielectric interface layer may be further formed between the dielectric layer stack 603 and the high work function interface layer 604.

[0125] refer to Fig. 10C and Fig. 10D , each of the capacitors 613 and 614 may include a pillar-shaped bottom electrode 601P, a multilayer stack 600M, and a top electrode 602 . Fig. 10D The capacitor 614 shown in the figure may further include a support member 600S. The multilayer stack 600M may include a dielectric layer stack 603 and a high work function interface layer 604. The dielectric layer stack 603 may correspond to any one of the dielectric layer stacks of the above-mentioned embodiments. For example, the dielectric layer stack 603 may include a zirconium oxide-based material or a hafnium oxide-based material, and the high work function interface layer 604 may include zirconium nitride or carbon-doped zirconium nitride. Although not shown, a dielectric interface layer may be further formed between the dielectric layer stack 603 and the high work function interface layer 604.

[0126] refer to Fig.10E and Fig.10F , each of the capacitors 615 and 616 may include a composite pylinder-shaped bottom electrode 601L, a multilayer stack 600M, and a top electrode 602 . Fig.10FThe capacitor 616 shown in the figure may further include a support member 600S. The bottom electrode 601L may have a hybrid structure in which a columnar shape and a cylindrical shape are fused. The composite columnar bottom electrode 601L refers to a hybrid structure of a columnar shape and a cylindrical shape of the bottom electrode 601L. The multilayer stack 600M may include a dielectric layer stack 603 and a high work function interface layer 604. The dielectric layer stack 603 may correspond to any one of the dielectric layer stacks of the above-mentioned embodiments. For example, the dielectric layer stack 603 may include a zirconium oxide-based material or a hafnium oxide-based material, and the high work function interface layer 604 may include zirconium nitride or carbon-doped zirconium nitride. Although not shown, a dielectric interface layer may be further formed between the dielectric layer stack 603 and the high work function interface layer 604.

[0127] According to the attached FIG. 10A to FIG. 10F , the capacitors 611 to 616 may include: bottom electrodes 601, 601P, and 601L; a top electrode 602; a dielectric layer stack 603 between the bottom electrodes 601, 601P, and 601L and the top electrode 602; and a high work function interface layer 604 between the dielectric layer stack 603 and the top electrode 602. The dielectric layer stack 603 may have a tetragonal crystal structure. The dielectric layer stack 603 may include a zirconium oxide-based material or a hafnium oxide-based material. The dielectric layer stack 603 may include zirconium oxide having a tetragonal crystal structure, hafnium oxide having a tetragonal crystal structure, or a combination thereof. The dielectric layer stack 603 may include any one of a Z-AZ-Z (ZrO2-Al doped ZrO2-ZrO2) stack, a Z-AZ-Z-AZ (ZrO2-Al doped ZrO2-ZrO2-Al doped ZrO2) stack, a HZ-AZ-ZH-AZ (HfO2-ZrO2-Al doped ZrO2-ZrO2-HfO2-Al doped ZrO2) stack, a H-AH-H (HfO2-Al doped HfO2-HfO2) stack, and a ZH-AH-HZ (ZrO2-HfO2-Al doped HfO2-HfO2-ZrO2) stack. The high work function interface layer 604 may include a zirconium nitride-based material. A dielectric interface layer (not shown) may be formed between the dielectric layer stack 603 and the high work function interface layer 604. The dielectric interface layer may include titanium oxide.

[0128] As described above, dielectric layer stack 603 and high work function interface layer 604 can be formed, which makes it possible to obtain a capacitor with high dielectric constant and low leakage current. Therefore, a highly integrated dynamic random access memory (DRAM) with improved refresh characteristics and reliability can be manufactured.

[0129] According to an embodiment, a multilayer stack may be applied to a peripheral circuit of a DRAM. For example, a DRAM may include a memory cell ( Fig. 9A The present invention relates to a memory cell region (with reference numeral "500") and a peripheral circuit region including a peripheral transistor, and at least one of the capacitor 600 of the memory cell 500 and the peripheral transistor may include any one of the multilayer stacks in the above-mentioned embodiments. For example, the multilayer stack may include a dielectric layer stack, a dielectric interface layer, and a high work function interface layer, wherein the high work function interface layer may include zirconium nitride or carbon-doped zirconium nitride.

[0130] According to an embodiment, the dielectric layer stack may be applied to a metal-insulator-metal (MIM) capacitor. For example, the MIM capacitor may include a multilayer stack including a first metal electrode, a second metal electrode, and a high work function interface layer formed between the first metal electrode and the second metal electrode, wherein the high work function interface layer may include zirconium nitride or carbon-doped zirconium nitride.

[0131] According to an embodiment, the dielectric layer stack may be applied to an embedded DRAM. For example, the embedded DRAM may include a logic circuit and a capacitor, and the capacitor of the embedded DRAM may include a multilayer stack including a high work function interface layer, wherein the high work function interface layer may include zirconium nitride or carbon-doped zirconium nitride.

[0132] According to an embodiment, a dielectric layer stack may be applied to a three-dimensional (3D) NAND. For example, a 3D NAND may include a columnar channel layer, a word line surrounding the columnar channel layer, and a multilayer stack between the columnar channel layer and the word line, wherein the multilayer stack may include a dielectric layer stack and a high work function interface layer.

[0133] According to an embodiment, a high work function interface layer may be formed using a zirconium nitride-based material, thereby reducing leakage current of a capacitor.

[0134] Although the present invention has been described for specific embodiments, it should be noted that these embodiments are used to describe rather than limit the present invention. In addition, it should be noted that those skilled in the art can realize the present invention in various ways by replacing, changing and modifying without departing from the scope of the present invention defined by the appended claims.

Claims

1. A capacitor, include: a first conductive layer; a second conductive layer; a dielectric layer stack between the first conductive layer and the second conductive layer; a dielectric interface layer between the dielectric layer stack and the second conductive layer; and a high work function interface layer between the dielectric interface layer and the second conductive layer, The dielectric layer stack includes any one of a Z-AZ-Z stack, a Z-AZ-Z-AZ stack, a HZ-AZ-ZH-AZ stack, a H-AH-H stack and a ZH-AH-HZ stack, wherein Z refers to ZrO 2 AZ refers to Al-doped ZrO 2 , H refers to HfO 2 , and AH refers to Al-doped HfO 2 .

2. The capacitor according to claim 1, in, The thickness of the high work function interface layer is less than the thickness of the dielectric interface layer.

3. The capacitor according to claim 1, in, The high work function interface layer includes a material having a higher work function than the dielectric layer stack.

4. The capacitor according to claim 1, in, The high work function interface layer includes zirconium nitride or carbon-doped zirconium nitride.

5. The capacitor according to claim 1, in, The dielectric interface layer includes a material that is more electronegative than the dielectric layer stack.

6. The capacitor according to claim 1, in, The dielectric interface layer includes titanium oxide.

7. The capacitor according to claim 1, in, The dielectric layer stack includes a hafnium oxide-based material or a zirconium oxide-based material.

8. The capacitor according to claim 1, in, The dielectric layer stack comprises: A high-k material having a tetragonal crystal structure; and A leakage barrier material is embedded in the high-k material.

9. The capacitor according to claim 8, in, The leakage barrier material includes aluminum or beryllium.

10. The capacitor according to claim 1, in, The dielectric layer stack comprises: a first high-k material having a tetragonal crystal structure; a second high-k material having a tetragonal crystal structure; and a leakage barrier material disposed between the first high-k material and the second high-k material, The leakage blocking material has a small thickness and is embedded in the first high-k material or the second high-k material, and the small thickness does not separate the grains of the first high-k material from the grains of the second high-k material.

11. The capacitor according to claim 1, in, Each of the dielectric layer stack and the dielectric interface layer includes an oxide-based material.

12. The capacitor according to claim 1, in, Each of the dielectric layer stack and the dielectric interface layer includes a metal oxide based material, and the high work function interface layer includes a zirconium nitride based material.

13. The capacitor according to claim 1, in, The dielectric layer stack includes tetragonal zirconium oxide and aluminum-doped zirconium oxide embedded in the tetragonal zirconium oxide.

14. The capacitor according to claim 1, in, The dielectric layer stack includes tetragonal hafnium oxide and aluminum-doped hafnium oxide embedded in the tetragonal hafnium oxide.

15. A capacitor, include: a first conductive layer; a second conductive layer; and a multilayer stack between the first conductive layer and the second conductive layer; Wherein, the multi-layer stack comprises: a first tetragonal zirconia layer overlying the first conductive layer; a second tetragonal zirconia layer overlying the first tetragonal zirconia layer; an aluminum-doped tetragonal zirconia layer between the first tetragonal zirconia layer and the second tetragonal zirconia layer; an aluminum oxide layer overlying the second tetragonal zirconium oxide layer; a titanium oxide layer over the aluminum oxide layer; and A carbon-doped zirconium nitride layer is above the titanium oxide layer.

16. The capacitor according to claim 15, in, The aluminum-doped tetragonal zirconia layer and the aluminum oxide layer are thinner than the first tetragonal zirconia layer and the second tetragonal zirconia layer.

17. The capacitor according to claim 15, in, The carbon-doped zirconium nitride layer is thinner than the titanium oxide layer.

18. A storage device, include: a buried word line embedded in the substrate; a bit line located at a higher level than the buried word line; and capacitor, located at a higher level than the bit line, Wherein, the capacitor comprises: Bottom electrode; Top electrode; a dielectric layer stack between the bottom electrode and the top electrode; a dielectric interface layer between the dielectric layer stack and the top electrode; and a high work function interface layer between the dielectric interface layer and the top electrode, The dielectric layer stack includes any one of a Z-AZ-Z stack, a Z-AZ-Z-AZ stack, a HZ-AZ-ZH-AZ stack, a H-AH-H stack and a ZH-AH-HZ stack, wherein Z refers to ZrO 2 AZ refers to Al-doped ZrO 2 , H refers to HfO 2 , and AH refers to Al-doped HfO 2 .

19. The storage device according to claim 18, in, The high work function interface layer includes zirconium nitride or carbon-doped zirconium nitride.

20. A method of manufacturing a capacitor, include: forming a first conductive layer; forming a dielectric layer stack having a leakage barrier material embedded therein on the first conductive layer; forming a dielectric interface layer on the dielectric layer stack; forming a high work function interface layer on the dielectric interface layer; as well as forming a second conductive layer on the high work function interface layer, The dielectric layer stack includes any one of a Z-AZ-Z stack, a Z-AZ-Z-AZ stack, a HZ-AZ-ZH-AZ stack, a H-AH-H stack and a ZH-AH-HZ stack, wherein Z refers to ZrO 2 AZ refers to Al-doped ZrO 2 , H refers to HfO 2 , and AH refers to Al-doped HfO 2 .

21. The method according to claim 20, in, The high work function interface layer includes a material having a higher work function than the dielectric layer stack.

22. The method according to claim 20, in, The high work function interface layer is formed of a zirconium nitride based material.

23. The method according to claim 20, in, The high work function interface layer includes zirconium nitride or carbon-doped zirconium nitride.

24. The method according to claim 20, in, The step of forming the high work function interface layer is performed by atomic layer deposition of zirconium nitride.

25. The method according to claim 20, in, The step of forming the high work function interface layer is performed by repeating a unit cycle consisting of zirconium source material injection, purging, reaction gas injection and purging.

26. The method according to claim 25, in, The zirconium source material includes a carbon-containing zirconium source material.

27. The method according to claim 25, in, The reaction gas includes NH 3 .

28. The method according to claim 20, in, The steps of forming the dielectric layer stack, the dielectric interface layer and the high work function interface layer are performed by atomic layer deposition.

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