Semiconductor device

Abstract

Embodiments of the present disclosure relate to a semiconductor device. The semiconductor device has a fault-tolerant buffer that can protect the internal circuit even when the power supply potential becomes 0V. In the semiconductor device, the protection voltage generation circuit 100 generates the larger of the divided voltage and the power supply voltage Vdd as the protection voltage protectv, and the divided voltage is obtained by dividing the voltage padv applied to the pad 4. The first protection circuit 200 for protecting the internal logic circuits 2A and 2B and the output buffer 10, and the second protection circuit 300 for protecting the input buffer 20 operate the protection voltage protectv.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2019-159569, filed on September 2, 2019, including the specification, drawings, and abstract, is incorporated herein by reference in its entirety. Background Art

[0003] The present disclosure relates to semiconductor devices, and more particularly, to a semiconductor device having a high-voltage tolerant input protection circuit (so-called input fault tolerance function).

[0004] Transistors used in semiconductor integrated circuits have become increasingly finer year by year. For this reason, even more transistors for IF (interface) applications are being manufactured, and their tolerance performance is lower than the voltage used in the IF. One of the reasons is that the IF standard itself has not been significantly updated as the manufacturing process has evolved.

[0005] In this case, a fault tolerance buffer is a buffer circuit that allows the amplitude of an input signal to be greater than the power supply voltage of the semiconductor integrated circuit.

[0006] The disclosed technologies are listed below.

[0007] [Patent Document 1] U.S. Patent No. 6150843

[0008] For example, U.S. Patent No. 6150843 (Patent Document 1) discloses an exemplary fault tolerance I / O (input and output) buffer. Summary of the Invention

[0009] As the operation of the conventional fault tolerance buffer shown in Patent Document 1 above, it is assumed that the power supply for driving the semiconductor integrated circuit is active.

[0010] Therefore, when the power supply of the semiconductor integrated circuit is turned off due to power saving requirements, there is a problem that the fault tolerance function does not work.

[0011] According to the description herein and according to the drawings, other problems and novel features will become apparent.

[0012] In the semiconductor device of the embodiment, the fault tolerance buffer is operated by the larger of the divided voltage and the power supply voltage, and the divided voltage is obtained by dividing the voltage applied to the pad for external connection.

[0013] According to the above embodiment, even when the power supply voltage becomes 0V, the fault tolerance buffer can protect the internal circuit. Brief Description of the Drawings

[0014] Figure 1 It is a plan view schematically showing the configuration of the LSI.

[0015] Figure 2A It is the first example diagram showing that the input voltage from the outside is higher than the power supply voltage for driving an IC (Integrated Circuit).

[0016] Figure 2B It is the second example diagram showing that the input voltage from the outside is higher than the power supply voltage for driving an IC (Integrated Circuit).

[0017] Figure 3 It shows Figure 1 a block diagram of the schematic configuration of the fault-tolerant buffer;

[0018] Figure 4 It shows Figure 3 an example circuit diagram of the detailed configuration of the fault-tolerant buffer.

[0019] Figure 5 It is a diagram showing the simulation result of the protection voltage generation circuit.

[0020] Figure 6 It is a diagram showing the operation of the PMOS transistor P200_2 when a high voltage is applied to the pad.

[0021] Figure 7 It is a diagram showing in tabular form the voltage difference between the electrodes of each transistor when the intermediate voltage mid is greater than the power supply voltage Vdd.

[0022] Figure 8 It is a diagram showing in tabular form the voltage difference between the electrodes of each transistor when the power supply voltage Vdd is greater than the intermediate voltage mid.

[0023] Figure 9 It is a circuit diagram showing an example of the configuration of the protection voltage generation circuit in the fault-tolerant buffer of the second embodiment.

[0024] Figure 10 It is a circuit diagram showing an example of the configuration of the protection voltage generation circuit in the fault-tolerant buffer of the third embodiment.

[0025] Figure 11 It is a diagram showing in tabular form the voltage difference between the electrodes of the transistor corresponding to the pad voltage padv when the power supply voltage Vdd is 0V.

[0026] Figure 12 It is a diagram showing the simulation result of the voltage at each node of the circuit C100_1 under the conditions Figure 11 shown.

[0027] Figure 13 It is a diagram showing in tabular form the voltage difference between the electrodes of the transistor corresponding to the protection voltage protectv when the power supply voltage Vdd is 3.3V.

[0028] Figure 14 is a diagram showing the simulation results of the voltage of each node of the circuit C100_1 Figure 13 under the conditions shown.

[0029] Figure 15 is a diagram showing the magnitude of the through-current corresponding to the protection voltage protectv.

[0030] Figure 16 is a circuit diagram showing the configuration of the fault-tolerant buffer according to the fourth embodiment.

[0031] Figure 17 is a diagram showing the current driving ability of the output buffer during normal operation. Detailed Description of the Embodiments

[0032] Hereinafter, each embodiment will be described in detail with reference to the accompanying drawings. As an example of an N-channel transistor, an NMOS (negative-channel metal-oxide semiconductor) transistor is illustrated below. Further, as an example, a PMOS (positive-channel metal-oxide semiconductor) transistor is mentioned as an example of a P-channel transistor. However, the structure of the transistor is not limited to the MOS structure, nor is it limited to the FET (field-effect transistor). Accordingly, in the present disclosure, more generally, an N-channel FET or the like is collectively referred to as an N-type transistor, and a P-channel FET or the like can be collectively referred to as a P-type transistor. Further, when not limited to either the N-type or the P-type, it is simply referred to as a transistor.

[0033] In the following description, the same or corresponding parts are denoted by the same reference numerals, and their descriptions may not be repeated.

[0034] (First Embodiment) (Overall Configuration of the Semiconductor Device) Figure 1 is a plan view schematically showing the configuration of the LSI. Referring to Figure 1 , the LSI (large-scale integration) 1 includes an internal logic circuit 2 disposed on the main surface of the substrate 6, and a plurality of pads 4 disposed on the peripheral portion of its main surface.

[0035] The LSI 1 further includes an interface region 3 disposed between the internal logic region 2 and the plurality of pads 4. The interface region 3 includes a buffer circuit that is used to transmit a signal input from the outside to the pad 4 to the internal logic region 2, or to output a signal from the internal logic region 2 to the outside through the pad 4.

[0036] A fault-tolerant buffer 5 is obtained by adding an internal protection circuit to a buffer circuit. Thus, even when a voltage higher than the power supply voltage is applied to the corresponding pad 4A, the buffer circuit and the internal logic region 2 can be protected. In particular, even when the power supply voltage for driving the LSI 1 is not supplied, the fault-tolerant circuit 5 of the present embodiment is configured to protect the internal logic region 2 of the buffer circuit and the interface region 3.

[0037] (Examples Requiring a Fault-Tolerant Buffer) Figure 2A and Figure 2B are example diagrams illustrating that an input voltage from the outside is higher than the power supply voltage for driving an IC (integrated circuit). Hereinafter, cases where the fault-tolerant buffer 5 is required will be described in detail with reference to FIG. 2.

[0038] Referring to Figure 2A , the IC 501 is mounted on a board 500 provided with a 3.3V power supply (hereinafter referred to as the 3.3V board 500). The IC 501 operates with a power supply voltage of 3.3V. On the other hand, the mounting power supply on the board 530 is the IC 531 with 5V (hereinafter referred to as the 5V board 530). The IC �31 operates with a power supply voltage of 5V. These ICs 501 and 503 with different power supply voltages are interconnected via a signaling line 540.

[0039] In the above configuration, it is necessary to provide a fault-tolerant buffer 505 in the IC 501 with a lower power supply voltage. This is because the high-level voltage of the signal output from the IC 531 is 5V and exceeds the withstand voltage of the IC 501 with a power supply voltage of 3.3V.

[0040] Referring to Figure 2B , a PCI (Peripheral Component Interconnect) standard signal line 540 is connected to the IC 501 mounted on the 3V board 500. Since the voltage level of the PCI standard signal line 540 is determined to be 5V by this standard, it exceeds the withstand voltage of the IC 501 with a power supply voltage of 3.3V. Therefore, the IC 501 needs to be provided with a fault-tolerant buffer 505.

[0041] (Outline of the Fault-Tolerant Buffer) Figure 3 is a block diagram showing a schematic configuration of the fault-tolerant buffer Figure 1 . Referring to Figure 3 , the fault-tolerant buffer 5 includes an output buffer 10, an input buffer 20, a protection voltage generation circuit 100, and protection circuits 200 and 300.

[0042] During the output operation, the output buffer 10 drives an external circuit (not shown) connected to the corresponding pad 4 based on the output signal from the internal logic circuit 2B. The output buffer 10 is provided to improve the current driving ability.

[0043] The input buffer 20 drives the corresponding internal logic circuit system 2A based on the signal externally input to the pad 4 during the input operation. The input buffer 20 is provided to shape the input signal and enhance the current driving ability.

[0044] The protection voltage generation circuit 100 compares the intermediate voltage mid obtained by dividing the voltage padv input to the pad 4 with the power supply voltage Vdd. The protection voltage generator 100 outputs the larger of the intermediate voltage mid and the power supply voltage Vdd as the protection voltage protectv. In the present disclosure, the voltage input to the pad 4 is referred to as the pad voltage padv, and the intermediate voltage mid is also referred to as the divided voltage.

[0045] When a high voltage is applied to the pad 4 (i.e., when the pad voltage padv is greater than the protection voltage protectv), the protection circuit 200 protects the output buffer 10 and the internal logic circuit 2B. The protection circuit 200 uses the protection voltage protectv as the operating power supply. Therefore, even if the power supply voltage Vdd is 0V, the protection circuit 200 can operate.

[0046] When a high voltage is applied to the pad 4 (i.e., when the pad voltage padv is higher than the protection voltage protectv), the protection circuit 300 protects the input buffer 20. The protection circuit 300 uses the protection voltage protectv as the operating power supply. Therefore, even if the power supply voltage Vdd is 0V, the protection circuit 300 can operate.

[0047] (Detailed fault-tolerant buffer configuration) Figure 4 is an example circuit diagram showing Figure 3 the detailed configuration of the fault-tolerant buffer. In Figure 4 , the power supply voltage supplied to the fault-tolerant buffer 5 is referred to as Vdd, and the ground voltage is referred to as Gnd. The node to which the power supply voltage Vdd is applied is called the Vdd node, and the node to which the ground voltage Gnd is applied is called the Gnd node. Figure 4 Each of the internal logic circuits 2A, 2B, 2C in Figure 1 corresponds to

[0048] the internal logic region 2 in . As described above, the pad voltage padv input to the pad 4 can be greater than the power supply voltage Vdd. Further, the operating range of the transistors constituting the fault-tolerant buffer 5 is less than the maximum value of the voltage padv input to the pad 4. Therefore, when the buffer circuit 5 does not have a fault-tolerant function, the following problems occur. First, an abnormal current flows from the pad 4 to the Vdd node through the parasitic diode of the PMOS transistor. Second, since a voltage higher than the withstand voltage is applied to the gate oxide film of the transistor, the reliability of the gate oxide film becomes a problem.

[0049] As will be described in detail below, the fault-tolerant buffer 5 of this embodiment is configured such that the above-described problem does not occur even when the power supply voltage Vdd is 0V. Hereinafter, the configuration and operation of each functional block constituting the fault-tolerant buffer 5 will be described in detail with reference to Figure 4 the configuration and operation of each functional block constituting the fault-tolerant buffer 5 will be described in detail.

[0050] (Configuration and Operation of Protection Voltage Generation Circuit) The protection voltage generation circuit 100 includes an input node IN1, an output node OUT1, a circuit C100_1, and a circuit C100_2.

[0051] The input node IN1 is connected to the corresponding pad 4. The protection voltage generation circuit 100 inputs the pad voltage padv via the input node IN1. Further, the protection voltage generation circuit 100 outputs the generated protection voltage protectv from the output node OUT1. In the following description, the output node OUT1 is also referred to as the protectv node.

[0052] The circuit C100_1 generates an intermediate voltage mid by dividing the pad voltage padv. The intermediate voltage mid is a voltage higher than the ground voltage Gnd (0V) and lower than the pad voltage padv. That is, the intermediate voltage mid always satisfies: Padv ≧ mid ≧ Gnd...(1). In the above equation (1), the equality holds when padv = Gnd = 0V.

[0053] Even when the pad voltage padv is at the maximum voltage, the intermediate voltage mid is set such that the voltage of each electrode of each transistor falls within the operable range, and the voltage between the electrodes of each transistor falls within the rated range. For example, the operation range of the corresponding transistor is set to 4.0V, the maximum value of the pad voltage padv is set to 5.5V, and the voltage division ratio of the circuit C100_1 is set to 0.5. Since the intermediate voltage mid is 5.5 × 0.5 = 2.75V, the intermediate voltage mid falls within the operation range of the transistor.

[0054] Figure 4 The circuit C100_1 includes a resistor element R100_1 and a resistor element R100_2 connected in series between the input node IN1 and the ground node. The intermediate voltage mid is output from the connection node between the resistor element R100_1 and the resistor element R100_2. In the following description, the connection node between the resistor element R100_1 and the resistor element R100_2 (i.e., the node having the intermediate voltage mid) is referred to as the mid node or the resistor voltage division node. In order to reduce the current flowing between the pad 4 and the Gnd node, the resistance values of the resistor element R100_1 and the resistor element R100_2 are preferably 100 kΩ or more.

[0055] The power supply voltage Vdd and the intermediate voltage mid from the circuit C100_1 are input to the circuit C100_2. The intermediate voltage mid falls within the operating range of the circuit C100_2. The circuit C100_2 outputs the larger one of the power supply voltage Vdd and the intermediate voltage mid as the protection voltage protectv. The circuit C100_2 includes, for example, PMOS transistors P100_1 and P100_2.

[0056] The source of the PMOS transistor P100_1 is connected to the mid node, the gate is connected to the Vdd node, and the drain and the back gate are connected to the output node OUT1. The source of the PMOS transistor P100_2 is connected to the Vdd node, the gate is connected to the mid node, and the drain and the back gate are connected to the output node OUT1.

[0057] First, the case where the intermediate voltage mid is greater than the power supply voltage Vdd (mid > Vdd) will be described. Here, the source voltage of the PMOS transistor P100_1 is higher than the gate voltage, and the gate voltage of the PMOS transistor P100_2 is higher than the source voltage. Therefore, the PMOS transistor P100_1 is turned on, and the PMOS transistor P100_2 is turned off. Therefore, the intermediate voltage mid is output from the output node OUT1 as the protection voltage protectv.

[0058] On the other hand, the case where the power supply voltage Vdd is greater than the intermediate voltage mid (Vdd > mid) will be described. Here, the gate voltage of the PMOS transistor P100_1 is greater than the source voltage, and the source voltage of the PMOS transistor P100_2 is greater than the gate voltage. Therefore, the PMOS transistor P100_1 is turned off, and the PMOS transistor P100_2 is turned on. Therefore, the power supply voltage Vdd is output from the output node OUT1 as the protection voltage protectv.

[0059] Figure 5 is a graph showing the simulation results of the protection voltage generation circuit. Figure 5 The time variations of the pad voltage padv, the power supply voltage Vdd, the intermediate voltage mid, and the protection voltage protectv are shown in order from top to bottom. Figure 5 The horizontal axis of the shown graph is the time axis, and the unit is an optional unit (a.u.: arbitrary unit).

[0060] The pad voltage padv varies between 0 V and 5.5 V. The power supply voltage Vdd varies within the range of 0 V to 3.3 V. Assuming that the voltage division ratio of the circuit C100_1 is 0.5, the intermediate voltage mid is equal to 1 / 2 of the pad voltage padv.

[0061] At Figure 5In this case, since the intermediate voltage mid is greater than the power supply voltage Vdd from time t1 to time t3 and after time t4, the protection voltage protectv follows the intermediate voltage mid. That is, protectv = mid. It should be noted that between time t1 and time t2, the power supply voltage Vdd is 0V, but the protection voltage protectv generated by the protection voltage generator 100 is greater than 0V.

[0062] On the other hand, since the power supply voltage Vdd is greater than the intermediate voltage mid between time t3 and time t4, the protection voltage protectv follows the power supply voltage Vdd. That is, protectv = Vdd.

[0063] (Input buffer configuration) Refer to Figure 4 , the input buffer 20 includes, for example, an input node IN11, an output node OUT6, and two cascaded inverters. The input signal padinv is input to the input node IN11 of the input buffer 20 via the pad 4 and the protection circuit 300. A signal outv based on the input signal padinv is output from the output node OUT6 of the input buffer 20 to the internal logic circuit 2A.

[0064] More specifically, the input buffer 20 includes a PMOS transistor P20_1 and an NMOS transistor N20_1 as a pre-stage inverter. The input buffer 20 further includes a PMOS transistor P20_2 and an NMOS transistor N20_2 as a subsequent inverter. These connection relationships will be described below.

[0065] The respective sources of the PMOS transistors P20_1 and P20_2 are connected to the Vdd node. The gates of the PMOS transistor P20_1 and the NMOS transistor N20_1 are connected to the input node IN11. The sources of the NMOS transistors N20_1 and N20_2 are connected to the ground node. The drains of the PMOS transistor P20_1 and the NMOS transistor N20_1 are connected to the gates of the PMOS transistor P20_2 and the NMOS transistor N20_2. In Figure 4 these, these shared nodes are shown as the intermediate node MND2. The drains of the PMOS transistor P20_2 and the NMOS transistor N20_2 are connected to the output node OUT6.

[0066] (Configuration and operation of the protection circuit for the input buffer) The logic signal input from the outside to the pad 4 is sequentially input to the internal logic circuit 2A through the protection circuit 300 and the input buffer 20. The protection circuit 300 is a protection circuit for keeping the voltage between the gate and the source of each transistor constituting the input buffer 20 within the rated range, even when a high voltage is applied to the pad 4.

[0067] The protection circuit 300 includes input nodes IN9, IN10, an output node OUT5, and an NMOS transistor N300_1. The source of the NMOS transistor N300_1 is connected to the pad 4 via the input node IN9. The protection voltage protectv is input to the gate of the NMOS transistor N300_1 through the input node IN10. The drain and the back gate of the NMOS transistor N300_1 are connected to the input node IN11 of the input buffer 20 via the output node OUT5.

[0068] It should be noted that the allowable voltage between the back gate source and the back gate drain is generally greater than the allowable voltage between other electrodes. Therefore, the back gate of the NMOS transistor N300_1 can be connected to the ground node depending on the magnitude of the allowable voltage.

[0069] Next, the operation of the protection circuit 300 will be described. The protection voltage protectv is input to the gate of the NMOS transistor N300_1. Even if the pad voltage padv is higher than the protection voltage protectv, the voltage of the drain of the NMOS transistor N300_1 is limited to be equal to or less than the protection voltage protectv. Specifically, when the threshold voltage of the NMOS transistor N300_1 is Vtn, the drain voltage is limited to at most protectv - Vtn. Therefore, the high-level voltage of the input signal padinv to be input to the input buffer 20 is at most the protection voltage protectv (specifically, protectv - Vtn). Therefore, the voltage difference between the electrodes of each transistor constituting the input buffer 20 can be within the rated range.

[0070] (Output buffer configuration) The output buffer 10 includes input nodes IN5 to IN8, an output node OUT4, a PMOS transistor P10_1, and NMOS transistors N10_1 and N10_2. Hereinafter, these connection relationships will be described.

[0071] The source of the PMOS transistor P10_1 and the gate of the NMOS transistor N10_1 are connected to the input node IN5. The input node IN5 has the protection voltage protectv.

[0072] The back gate of the PMOS transistor P10_1 is connected to the input node IN6. The input node IN6 is connected to the output node OUT2 of the protection circuit 200. In Figure 4 which, the voltages of the input node IN6 and the output node OUT2 are referred to as the back gate voltage pbgv.

[0073] The gate of PMOS transistor P10_1 is connected to input node IN7. The gate control signal pgatev is input from internal logic circuit 2B to input node IN7 through protection circuit 200.

[0074] The drain of PMOS transistor P10_1 and the drain of NMOS transistor N10_1 are connected to output node OUT4. Output node OUT4 is connected to pad 4.

[0075] The source and back gate of NMOS transistor N10_1 and the drain of NMOS transistor N10_2 are connected to intermediate node nmid. The source of NMOS transistor N10_1 is connected to the ground node.

[0076] The gate of NMOS transistor N10_1 is connected to input node IN8. The gate control signal ngatev is input from internal logic circuit 2C to input node IN8.

[0077] (Configuration of the protection circuit for the output buffer) During normal operation, the signal output from internal logic circuit 2B is propagated to pad 4 through protection circuit 200 and output buffer  10. That is, protection circuit 200 is a circuit for transmitting the signal output from internal logic circuit 2B to the gate of PMOS transistor P10_1 during normal output operation.

[0078] On the other hand, when a high voltage is applied to pad 4, protection circuit 200 prevents the high voltage from propagating to internal logic circuit 2B. In addition, when a high voltage is applied to pad 4, protection circuit 200 causes the gate voltage of PMOS transistor P10_1 to follow the pad voltage padv. Therefore, PMOS transistor P10_1 is turned off to prevent abnormal current from flowing from pad 4 to the Vdd node.

[0079] Protection circuit 200 includes, for example, input nodes IN2 to IN4, output nodes OUT2, OUT3, and PMOS transistors P200_1 and P200_2. Protection circuit 200 further includes inverter 210 and transmission gate 220. As Figure 4 shown, inverter 210 includes PMOS transistor P200_5 and NMOS transistor N200_2. Transmission gate 220 includes PMOS transistors P200_3 and P200_4 and NMOS transistor N200_1. These connection relationships will be described below.

[0080] The source of PMOS transistor P200_1, the gate of PMOS transistor P200_2, and the source and back gate of PMOS transistor P200_5 are connected to input node IN2. Further, the gate of NMOS transistor N200_1 is connected to input node IN2. Input node IN2 has a protection voltage protectv.

[0081] The gate of PMOS transistor P200_1, the source of PMOS transistor P200_2, and the gate of PMOS transistor P200_3 are input to input node IN3. Input node IN3 is connected to pad 4.

[0082] The drain and back gate of PMOS transistor P200_1 and the back gates of PMOS transistors P200_2, P200_3, and P200_4 are connected to output node OUT2. The voltage of output node OUT2 is equal to the above-mentioned back gate voltage pbgv.

[0083] The drains of PMOS transistors P200_2 and P200_3 and the gate and drain of PMOS transistor P200_4 are connected to output node OUT3. The drain of NMOS transistor N200_1 is also connected to output node OUT3. The aforementioned gate control signal pgatev is output from output node OUT3.

[0084] The sources of PMOS transistors P200_3 and P200_4 and the source and back gate of NMOS transistor N200_1 are connected to intermediate node MND1. Intermediate node MND1 is further connected to the drain of PMOS transistor P200_5 and the drain of NMOS transistor N200_2. Let prepgatev be the voltage of intermediate node MND1. The source and back gate of NMOS transistor N200_2 are connected to the ground node.

[0085] The gate of PMOS transistor P200_5 and the gate of NMOS transistor N200_2 are connected to input node IN4. The output signal pinv is input to input node IN4 from the internal logic circuit 2B.

[0086] (Operation of the protection circuit for the output buffer) Next, the operation of protection circuit 200 is described. In normal output operation without applying a high voltage to pad 4, PMOS transistor P200_1 is turned on. In this case, the protection voltage protectv (= pbgv) is input to the back gate of PMOS transistor P10_1 through the channel of PMOS transistor P200_1. That is, in normal output operation, PMOS transistor P200_1 is the power supply path for the back gate voltage pbgv of PMOS transistor P10_1.

[0087] When a high voltage is applied to pad 4, the protection voltage protectv (=mid) is input to the source of PMOS transistor P200_1, and the pad voltage padv is input to the gate of PMOS transistor P200_1. Therefore, when padv>protectv, PMOS transistor P200_1 is turned off. Thus, the pad voltage padv flowing through the parasitic diode of PMOS transistor P10_1 can be prevented from reaching the Vdd node through PMOS transistor P200_1.

[0088] In the normal output operation where no high voltage is applied to pad 4, PMOS transistor P200_2 is cut off. On the other hand, when a high voltage is applied to pad 4, as Figure 6 shown, PMOS transistor P200_2 is turned on and supplies the pad voltage padv to the gate of PMOS transistor P10_1.

[0089] Figure 6 is an operation diagram of PMOS transistor P200_2 when a high voltage is applied to the pad. Since the P-type substrate (P-Sub) ground voltage Gnd is provided, it is non-conductive between the P-type substrate and the N-type well (N-Well).

[0090] As Figure 6 shown, the P-type drain (P-Drain) pad voltage padv is supplied, and the protection voltage protectv is input to the gate (Gate). The pad voltage padv is greater than the protection voltage protectv, that is, padv>protectv. Therefore, PMOS transistor P200_2 is turned on, and a channel current flows through the P-channel. Therefore, the voltage (pgatev) of the P-type source (P-Source) becomes substantially equal to the pad voltage padv. Thus, the pad voltage padv is supplied to the gate of PMOS transistor P10_1 that constitutes the output buffer 10. Since the protection voltage protectv is supplied to the source of PMOS transistor P10_1, PMOS transistor P10_1 is cut off.

[0091] In addition, as Figure 6 shown, the parasitic diode between the P-type drain and the N-type well becomes conductive. Therefore, the voltage pbgv of the backgate of PMOS transistor P200_2 follows the pad voltage padv. Specifically, the backgate voltage pbgv is equal to padv - Vtp, where Vtp is the threshold voltage.

[0092] As described above, in padv > protectv, the voltages of the electrodes of PMOS transistors P200_1 and P200_2 are either the pad voltage padv or the protection voltage protectv. Therefore, the voltage difference between any electrodes of each of PMOS transistors P200_1 and P200_2 can be maintained within the rated range.

[0093] Referring again to Figure 4 , transmission gate 220 operates as a conversion circuit that propagates an input signal from internal logic circuit 2B during normal output operation without applying a high voltage to pad 4.

[0094] On the other hand, when a high voltage is applied to pad 4, transmission gate 220 operates as a protection circuit that does not allow the pad voltage padv to surround internal logic circuit 2B. Specifically, in the case of padv > protectv, the pad voltage padv is supplied to the gates of PMOS transistors P200_3 and P200_4. Therefore, PMOS transistors P200_3 and P200_4 are turned off. Since the protection voltage protectv is supplied to the gate of NMOS transistor N200_2, NMOS transistor N200_2 is turned on. However, the source voltage prepgatev of NMOS transistor N200_2 does not rise above the protection voltage protectv. Therefore, the voltage of each electrode of the transistors constituting transmission gate 220 is either the pad voltage padv or the protection voltage protectv. Therefore, the voltage difference between the electrodes of each transistor can also be within the rated range.

[0095] The maximum voltage supplied to the electrodes of PMOS transistor P200_5 and NMOS transistor N200_2 included in inverter 210 is the protection voltage protectv. Therefore, the voltage difference between the electrodes of each transistor constituting inverter 210 falls within the rated range.

[0096] The protection voltage protectv is supplied to the back gate of PMOS transistor P200_5. Here, as described above, the protection voltage protectv can be supplied to intermediate node MND1 through NMOS transistor N200_1. However, the drain-side parasitic diode of PMOS transistor P200_5 is not turned on. Therefore, no abnormal current is supplied to the internal power supply. As long as the protection voltage protectv is supplied to the back gate of PMOS transistor P200_5, other circuits can be used instead of inverter 210.

[0097] (Summary of output buffer protection) The protection of output buffer 10 will be outlined based on the configuration of the above protection circuit 200.

[0098] When a high voltage is applied to the pad 4 (padv > protectv), the pad voltage padv is supplied to the gate of the PMOS transistor P10_1 through the protection circuit 200. Therefore, the PMOS transistor P10_1 is turned off.

[0099] Similar to the PMOS transistor P200_2, the drain of the PMOS transistor P10_1 is provided with the pad voltage padv. Therefore, the voltage (pbgv) of the back gate of the PMOS transistor P10_1 follows the pad voltage padv (specifically, padv - Vtp) through the drain-side parasitic diode.

[0100] Similar to the NMOS transistor N300_1, the protection voltage protectv is supplied to the gate of the NMOS transistor N10_1. Therefore, even if the pad voltage padv is input to the drain of the NMOS transistor N10_1, the voltage of the source of the intermediate node nmid is limited to the protection voltage protectv. Specifically, when the threshold voltage of the NMOS transistor N10_1 is Vtn, the voltage of the intermediate node nmid is limited to protectv - Vtn.

[0101] Therefore, the voltages of the electrodes of the PMOS transistor P10_1 and the NMOS transistor N10_1 become the pad voltage padv or the protection voltage protectv. Therefore, the voltage difference between the electrodes of these transistors can be within the rated range.

[0102] Finally, the voltage of the drain (intermediate node nmid) of the NMOS transistor N10_2 is at most the protection voltage protectv (specifically, protectv - Vtn). Therefore, the voltage differences between the electrodes of the NMOS transistor N10_2 can all be within the rated range.

[0103] (Specific example of the voltage difference between the electrodes of the transistor) Hereinafter, with reference to specific numerical examples, the circuit operation is further illustrated.

[0104] Figure 7 is a diagram showing the voltage differences between the electrodes of each transistor when the intermediate voltage mid is greater than the power supply voltage Vdd in tabular form.

[0105] In Figure 7In this case, the pad voltage padv is set to 5.5V, and the power supply voltage Vdd is set to 0V. When the voltage division ratio of the circuit C100_1 is 0.5, the intermediate voltage mid (= protection voltage protectv) is 2.75V. The threshold voltage Vtn of the NMOS transistor is set to 0.5V, and the threshold voltage Vtp of the PMOS transistor is set to 0.5V. The allowable voltage difference between the electrodes of the transistor should be 4.0V. Since the power supply voltage Vdd is 0V, the output from the internal logic circuit is 0V.

[0106] Figure 7 The symbols used in [[ID=,55]]Figure 4 are the same as those in Figure 7 . The gate-source voltage Vgs, gate-drain voltage Vgd, and drain-source voltage Vds, which are the voltage differences between the electrodes, are shown. In addition, the gate-body voltage Vgb, drain-body voltage Vdb, and source-body voltage Vsb, which are the voltage differences between the electrodes, are shown. As

[0107] Figure 8 shown, the absolute value of the voltage difference between these electrodes is at most 3.25V, which is within the allowable voltage difference range.

[0108] In Figure 8 the pad voltage padv is set to 5.5V, and the power supply voltage Vdd (= protection voltage protectv) is set to 3.3V. Assuming that the voltage division ratio of the circuit C100_1 is 0.5, the intermediate voltage mid is 2.75V. The threshold voltage Vtn of the NMOS transistor is set to 0.5V, and the threshold voltage Vtp of the PMOS transistor is set to 0.5V. The allowable voltage difference between the electrodes of the transistor should be 4.0V. Since the power supply voltage Vdd is 3.3V, the internal logic circuit system is operating. Assuming that the output of the output buffer 10 is in a high impedance state. Figure 8 The symbols used in Figure 7 are the same as those in

[0109] As Figure 8 shown, the voltage difference (absolute value) between the electrodes is at most 3.3V, which is within the allowable voltage difference.

[0110] (Effect of the First Embodiment) In conventional fault-tolerant buffers, the voltage required for the fault-tolerant function is supplied by the power supply voltage Vdd of the LSI. Therefore, the protection of the LSI depends on the state of the power supply, and the fault-tolerant function does not function when the power is cut off. On the other hand, the fault-tolerant buffer of the first embodiment includes a protection voltage generating circuit 100. The protection voltage generating circuit 100 can generate the protection voltage protectv required for the operation of the fault-tolerant buffer by utilizing the voltage supplied to the LSI from an external circuit. Therefore, even if the power supply of the LSI is cut off to save power, the LSI can be protected.

[0111] Second Embodiment In the second embodiment, the configuration of circuit C100_1 in protection voltage generating circuit 100 is modified. Specifically, a voltage divider circuit using a plurality of PMOS transistors is used instead of a voltage divider circuit using a resistor element. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

[0112] (Configuration of Protection Voltage Generation Circuit) Figure 9 1 is a circuit diagram showing a configuration example of a protection voltage generating circuit in the fault-tolerant buffer of the second embodiment. Figure 9 In addition to the protection voltage generating circuit 100 shown in FIG. 1 , the configuration of the fault-tolerant buffer of the second embodiment can be the same as that of the reference Figure 4 The configuration of the circuit C100_2 of the protection voltage generating circuit 100 is the same as that of the first embodiment described above, so the description thereof will not be repeated. Figure 4 The first embodiment described is the same, so its description will not be repeated.

[0113] Figure 9 The circuit C100_1 includes PMOS transistors P100_3 and P100_4 connected in series between the input node IN1 and the ground node. Each of the PMOS transistors P100_3 and P100_4 is diode-connected.

[0114] Specifically, the source and back gate of the PMOS transistor P100_3 are connected to the input node IN1. The gate and drain of the PMOS transistor P100_3 are connected to the mid node. The source and back gate of the PMOS transistor P100_4 are connected to the mid node. The gate and drain of the PMOS transistor P100_4 are connected to the ground node. Figure 4 As depicted, the mid node is connected to the source of the PMOS transistor P100_1 and the gate of the PMOS transistor P100_2 .

[0115] Although Figure 9Two PMOS transistors connected in series are shown, but the number of PMOS transistors connected in series can be changed according to the magnitude of the intermediate voltage mid to be extracted and the power consumption of the PMOS transistor P100_1. In addition, NMOS transistors can be used instead of PMOS transistors, and other types of semiconductor elements can be used.

[0116] Preferably, the device characteristics of the PMOS transistors P100_3 and P100_4 are substantially the same, for example, the L / W ratio. When the pad voltage padv sufficient to turn on each of the PMOS transistors P100_3 and P100_4 is input to the input node IN1, Figure 9 the circuit C100_1 of operates as a state division circuit. In this case, the pad voltage padv is equally divided by the PMOS transistors P100_3 and P100_4. Therefore, the circuit C100_1 operates as a voltage division circuit with a voltage division ratio of 0.5.

[0117] (Effect) By using MOS transistors instead of resistor elements, the effect of reducing the size of the circuit can be achieved.

[0118] More specifically, in Figure 4 the circuit C100_1 of, depending on the absolute values of the resistor elements R100_1 and R100_2, the through current between the input node IN1 and the ground node increases. In order to suppress the penetration current to about several μA at most, the resistance value of the resistor element needs to be about several hundred kΩ to several MΩ. When a resistor element with this resistance value is formed inside the LSI, depending on the process constraints (for example, depending on the sheet resistance value of the resistor), the circuit area increases.

[0119] On the contrary, when MOS transistors are used, since reducing the gate width W is sufficient to narrow the through current, the circuit area does not expand. Therefore, the size of the circuit can be reduced.

[0120] (Third Embodiment) In the third embodiment, an example in which the protection voltage generation circuit of the second embodiment is further modified will be described. Specifically, the number of PMOS transistors included in the voltage division circuit C100_1 is increased, and a switching element for switching between the operation and non-operation of the circuit C100_1 is provided. This will be described in detail below with reference to the drawings.

[0121] (Configuration of the protection voltage generation circuit) Figure 10 is a circuit diagram showing a configuration example of the protection voltage generation circuit in the fault-tolerant buffer of the third embodiment. Except for Figure 10 the protection voltage generation circuit 100 shown, the configuration of the fault-tolerant buffer of the third embodiment is the same as that of the first embodiment described with reference to Figure 4 and thus its description will not be repeated.

[0122] Refer to Figure 10 Figure 10 , the protection voltage generation circuit 100 includes input nodes IN1, IN12, an output node OUT1, a circuit C100_1, and a circuit C100_2. Here, the connection between the input node IN1 and the output node OUT1 and the configuration of the circuit C100_2 are the same as those in the first embodiment described with reference to Figure 4 and thus the description thereof will not be repeated.

[0123] The circuit C100_1 includes PMOS transistors P100_3 to P100_11 and an NMOS transistor N100_1. Hereinafter, these connection relationships will be described.

[0124] First, the PMOS transistors P100_3 to P100_11 are sequentially connected in series between the input node IN1 and the ground node. That is, in two adjacent PMOS transistors, the drain of the high-voltage-side PMOS transistor and the source of the low-voltage-side PMOS transistor are connected to each other. In each of the PMOS transistors P100_3 to P100_6 and P100_8 to P100_11, the gate is connected to the drain, and the back gate is connected to the source. That is, each of the PMOS transistors P100_3 to P100_6 and P100_8 to P100_11 is diode-connected. The gate voltages (= drain voltages) of the PMOS transistors P100_3 to P100_6 and P100_8 to P100_10 are g100_3 to g100_6 and g100_8 to g100_10, respectively.

[0125] In the PMOS transistor P100_7, the gate is connected to the input node IN12, the drain is connected to the mid node, and the back gate is connected to the source. The selection signal protectselect is input to the input node IN12 from the internal logic region 2. The PMOS transistor P100_7 functions as a switching device for turning on and off.

[0126] In the NMOS transistor N100_1, the drain is connected to the mid node, the gate is connected to the input node IN12, and the source and the back gate are connected to the Gnd node. The NMOS transistor N100_1 functions as a switching device for turning on and off.

[0127] (Operation of the protection voltage generation circuit) The operation of circuit C100_1 will be described below. First, the case when the power supply voltage Vdd supplied to the LSI is 0V (i.e., when the power supply is cut off) will be described. In this case, the selection signal protectselect input from the internal logic region 2 is at a low level. Therefore, the NMOS transistor N100_1 is cut off, and the PMOS transistor P100_7 is turned on. Under this condition, as in the first and second embodiments, circuit C100_1 generates an intermediate voltage mid by dividing the pad voltage padv of pad 4. Circuit C100_2 outputs the intermediate voltage mid as the protection voltage protectv from output node OUT1.

[0128] Next, as the power supply voltage Vdd gradually rises from 0, the case where the operation of the LSI is enabled will be described. When the LSI operation is enabled, the internal logic region 2 changes the step signal protectselect from a low level to a high level. Therefore, the NMOS transistor N100_1 is turned on, and the PMOS transistor P100_7 is cut off.

[0129] As a result, the through-current flowing between the input node IN1 and the ground node can be reduced. Further, since the intermediate voltage mid almost becomes 0V, the supply source of the protection voltage protectv can be clearly switched to the power supply voltage Vdd.

[0130] (Specific example of circuit operation) Hereinafter, the operation of circuit C100_1 will be further described with reference to specific numerical examples. Figure 10 of circuit C100_1.

[0131] Figure 11 is a diagram showing in tabular form the voltage differences between the electrodes of the transistors corresponding to the pad voltage padv when the power supply voltage Vdd is 0V. The symbols used in the table are the same as those used in Figure 4 、 7 、10, etc.

[0132] In Figure 11In this case, the pad voltage padv is set to 5.5V, and the power supply voltage Vdd is set to 0V. When the voltage division ratio of the circuit C100_1 is 0.5, the intermediate voltage mid (= protection voltage protectv) is 2.75V. The threshold voltage Vtn of the NMOS transistor is set to 0.5V, and the threshold voltage Vtp of the PMOS transistor is set to 0.5V. The allowable voltage difference between the electrodes of the transistor should be 4.0V. Since the power supply voltage Vdd is 0V, the output from the internal logic circuit is 0V. The select signal protectselect is 0V because the LSI is in a non-operating condition when the power supply voltage Vdd = 0V. The PMOS transistor P100_7 is regarded as a switch, and the voltage difference Vds between the drain and source of this switch is 0V.

[0133] As Figure 11 shown, eight PMOS transistors P100_3 to P100_6, P100_8 to P100_11 are used to divide the 5.5V pad voltage padv. Therefore, the drain-source voltage Vds of each of these transistors is 0.69V. The intermediate voltage mid is obtained by dividing the 5.5V pad voltage padv, and this intermediate voltage mid is equal to 2.75V.

[0134] According to Figure 11 it is obvious that the voltage difference between the electrodes of each transistor is within the allowable voltage difference range.

[0135] Figure 12 is a simulation result graph showing the voltages of each node of the circuit C100_1 under the Figure 11 shown conditions. It should be understood that the voltage of the corresponding node of the circuit C100_1 is determined as the voltage division of the pad voltage padv.

[0136] For example, the voltage g100_3 of the gate and drain of the PMOS transistor P100_3 is determined by the following formula: g100_3 = padv * 7 / 8 = 5.5 * 7 / 8 = 4.81V...(2). The gate voltages of the other PMOS transistors are obtained in the same way.

[0137] Figure 13 is a graph showing in tabular form the voltage differences between the electrodes of the transistors corresponding to the protection voltage protectv when the power supply voltage Vdd is 3.3V. The symbols used in the table are the same as those used in Figure 4 , 7 , 10, etc.

[0138] In Figure 13In this case, the pad voltage padv is 5.5V, and the power supply voltage Vdd ( = protection voltage protectv) is 3.3V. Assuming that the voltage division ratio of circuit C100_1 is 0.5, the intermediate voltage mid is 2.75V. The threshold voltage Vtn of the NMOS transistor is set to 0.5V, and the threshold voltage Vtp of the PMOS transistor is set to 0.5V. The allowable voltage difference between the electrodes of the transistor should be 4.0V. Since the power supply voltage Vdd is 3.3V, the internal logic circuit system is operating. Therefore, the selection signal protectselect becomes a high-level signal.

[0139] As Figure 13 shown, the NMOS transistor N100_1 is in the conducting state, and the PMOS transistors P100_7 to P100_11 are in the cutoff state. The intermediate voltage mid is 0V.

[0140] On the other hand, the PMOS transistors P100_3 to P100_6 connected in series between the input node IN1 and the input node IN12 are turned on. In each of these transistors, the voltage drops by 0.5V, which corresponds to the threshold voltage of the PMOS transistor. As Figure 13 shown, the voltage difference between the electrodes of the PMOS transistor P100_7 is within the allowable operating voltage difference.

[0141] Figure 14 is a simulation result graph showing the voltages of each node of circuit C100_1 under the Figure 13 shown conditions.

[0142] As Figure 14 shown, the gate voltages ( = drain voltages) g100_3 to g100_6 of the PMOS transistors P100_3 to P100_6 change according to the pad voltage padv. These voltages are obtained by dividing the voltage difference between the pad voltage padv ( = 5.5V) and the voltage of the selection signal protectselect ( = 3.3V). The gate voltages ( = drain voltages) g100_8 to g100_10 of the PMOS transistors P100_8 to P100_10 are close to the gate voltage 0V.

[0143] Figure 15 shows a graph of the magnitude of the through-current corresponding to the protection voltage protectv. In Figure 15 it, the pad voltage padv, the through-current when the protection voltage protectv is mid, and the through-current when the protection voltage protectv is Vdd are shown in sequence from top to bottom. The pad voltage padv is at most 5.5V (at time t5).

[0144] When the power supply voltage Vdd = 0V and the select signal protectselect = 0V, Figure 10 the circuit C100_1 in Figure 10 functions as a voltage divider circuit for dividing the pad voltage padv. In this case, the magnitude of the through-current flowing between the input node IN1 and the Gnd node is at most 269 [nA].

[0145] On the other hand, when the power supply voltage Vdd = protectselect = 3.3V, the power supply voltage Vdd is selected as the protection voltage protectev. In this case, the magnitude of the through-current is at most 2.93 [nA], which is reduced to about 1 / 100 compared to the case of Vdd = 0V.

[0146] (Effect) As described above, according to the third embodiment, the operation / non-operation of the voltage divider C100_1 is switched according to the select signal protectselect output from the internal logic region 2. Therefore, it is possible to clearly select the power supply voltage Vdd as the power supply for implementing the fault tolerance function. Further, when the power supply voltage Vdd is selected, the switching PMOS transistor P100_7 provided in the voltage divider C100_1 is controlled to be cut off. Therefore, the through-current flowing through the voltage divider circuit C100_1 can be suppressed.

[0147] (Fourth Embodiment) In the Figure 4 first embodiment shown in Figure 4 , the current driving ability of the PMOS transistor P10_1 constituting the output buffer 10 cannot be determined only by the drain-source voltage Vds of the PMOS transistor P10_1. Since the drain current of the PMOS transistor P10_1 is supplied through the PMOS transistor P100_2, the drain current is also affected by the gate-source voltage Vgs of the PMOS transistor P100_2. Accordingly, as the pad voltage padv changes, the current driving ability of the PMOS transistor P10_1 will also change accordingly.

[0148] To solve the above problems, the fault tolerance buffer of the fourth embodiment further includes a protection circuit 400, and a PMOS transistor P10_2 is added to the output buffer 10. This will be described in detail below with reference to the drawings. Since the configurations of the other fault tolerance buffers are the same as those in the Figure 4 case, the same reference numerals are given to the same or corresponding parts, and their descriptions will not be repeated.

[0149] The protection circuit 400 controls the operation of the output buffer 10. Therefore, the protection circuit 400 can be considered as a part of the configuration of the protection circuit 200.

[0150] (Configuration of the Fault Tolerance Buffer) Figure 16It is a circuit diagram showing the configuration of the fault-tolerant buffer according to the fourth embodiment. Figure 16 The fault-tolerant buffer of Figure 4 is different from the fault-tolerant buffer of

[0151] in that it further includes a protection circuit 400. The protection circuit 400 includes, for example, input nodes IN13, IN14, output node OUT7, PMOS transistor P400_1, and NMOS transistor N400_1. These connection relationships will be described below.

[0152] The select signal protectselect is input from a part of the internal logic region 2 in the internal logic circuit 2D ( Figure 1 ) to the input node IN13. The protection signal protectv is input from the protection voltage generation circuit 100 to the input signal node IN14. In the PMOS transistor P400_1, the gate is connected to the input node IN13, and the source and back gate are connected to the input node IN14. The drain of the PMOS transistor P400_1 is connected to the output node OUT7. In the NMOS transistor N400_1, the gate is connected to the input node IN13, and the source and back gate are connected to the Gnd node. The drain of the NMOS transistor N400_1 is connected to the output node OUT7.

[0153] The PMOS transistor P400_1 and the NMOS transistor N400_1 configured as described above operate as an inverter. Therefore, the select signal protectselectb output from the output node OUT7 is a signal obtained by inverting the logic level of the select signal protectselect input to the input node IN13.

[0154] The output buffer 10 is different from the output buffer 10 of Figure 4 in that it further includes an input node IN15 and a PMOS transistor P10_2. First, these connections will be described.

[0155] The input node IN15 is input the select signal protectselectb by being connected to the output node OUT7 of the protection circuit 400.

[0156] For the PMOS transistor P10_2, the source is connected to the Vdd node, the gate is connected to the input node IN15, and the back gate is connected to the input node IN5. The drain of the PMOS transistor P10_2 is connected to the source of the PMOS transistor P10_1. Different from Figure 4 , the source of the PMOS transistor P10_1 is not connected to the input node IN5.

[0157] (Output buffer operation) Next, forFigure 16 The operation of the output buffer 10 will be described. First, the case where the power supply voltage Vdd is 0 V (i.e., the power supply of the LSI is cut off) will be described. In this case, the selection signal protectselect output from the internal logic circuit 2D becomes low level. Accordingly, the protection circuit 400 outputs a high-level selection signal protectselectb (equal to the protection voltage protectv) from the output node OUT7. Therefore, the protection voltage protectv (> Vdd) is input to the gate of the PMOS transistor P10_2, causing the PMOS transistor P10_2 to be cut off. Therefore, no through path is formed between the drain and source of the PMOS transistor P10_2.

[0158] Next, the normal operation where the power supply voltage Vdd is, for example, 3.3 V will be described. In this case, the internal logic circuit 2D sets the selection signal protectselect to high level. Therefore, the selection signal protectselectb output from the protection circuit 400 via the output node OUT7 becomes low level (0 V). Therefore, since the PMOS transistor P10_2 is turned on, the source voltage of the PMOS transistor P10_1 becomes equal to the power supply voltage Vdd. Therefore, it is possible to prevent the pad voltage padv from affecting the current driving ability of the PMOS transistor P10_1.

[0159] Figure 17 is a diagram showing the current driving ability of the output buffer during normal operation. In Figure 17 the pad voltage padv, the intermediate voltage mid (in the case of Figure 4 ), and the voltage V of the selection signal protectselectb (in the case of Figure 16 ) are shown in order from top to bottom. Further, in Figure 17 the drive current Ipad of the output buffer is shown as a simulation waveform compared with the case of Figure 4 and the case of Figure 16 . Figure 17 The horizontal axis of the graph shown is the time axis, and the unit of the time axis is an arbitrary unit (a.u.: arbitrary unit).

[0160] Referring to Figure 17 , compare the current drive amounts at time t6. In the case of Figure 4 , the current supplied from the output buffer 10 to the pad 4 is 1.54 mA. On the contrary, in the case of Figure 16 , the current supplied from the output buffer 10 to the pad 4 is 1.97 mA. Therefore, it can be seen that in this embodiment, the current driving ability of the PMOS transistor P10_1 is improved.

[0161] (Effect) As described above, in the first embodiment, the power supply path of the protection voltage protectv of the PMOS transistor P10_1 is the same as the path of the output current. Therefore, there is the following problem: the current supply capability of the PMOS transistor P10_1 is affected by the pad voltage padv.

[0162] In contrast, in the output buffer 10 according to the present embodiment, the PMOS transistor P10_2 for overvoltage protection is connected in series with the PMOS transistor P10_1 for current driving. The output current of the PMOS transistor P10_1 is supplied from the Vdd node via the PMOS transistor P10_2. That is, the path of the output current of the output buffer 10 is separated from the power supply path of the protection voltage protectedv. Therefore, the current driving ability of the output buffer 10 can be further improved.

[0163] According to the above configuration, the electrostatic discharge (ESD: Electro-Static Discharge) path and the power supply path of the protection voltage protectv are separated from each other. Therefore, the risk of damage due to ESD can also be reduced.

[0164] Moreover, the fourth embodiment can be combined with each of the second and third embodiments. That is, Figure 16 the circuit C100_1 can be replaced with Figure 9 the circuit C100_1, or can be replaced with Figure 10 the circuit C100_1.

[0165] Although the present invention made by the present inventors has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and needless to say, various modifications can be made without departing from its gist.

Claims

1. A semiconductor device, comprising: A pad; An internal logic circuit operated by a power supply voltage; An output buffer configured to drive an external circuit coupled to the pad based on an output signal from the internal logic circuit; A protection voltage generation circuit configured to output, as a protection voltage, the larger of a divided voltage and the power supply voltage, the divided voltage being obtained by dividing a voltage applied to the pad; And A first protection circuit operated by the protection voltage and configured to protect the internal logic circuit and the output buffer when a voltage greater than the protection voltage is applied to the pad, Wherein the output buffer includes a third P-type transistor having a first electrode and a second electrode, the protection voltage is input to the first electrode, and the second electrode is coupled to the pad, Wherein, when the protection voltage generation circuit outputs the protection voltage, the first protection circuit is configured to supply an output voltage from the internal logic circuit to a control electrode of the third P-type transistor, Wherein, when the voltage greater than the protection voltage is supplied to the pad, the first protection circuit supplies the voltage of the pad to the control electrode of the third P-type transistor, Wherein the protection voltage generation circuit includes: A first generation circuit including a plurality of transistors connected in series in a diode connection between the pad and a ground node to which a ground voltage is applied, the plurality of transistors being configured to output the divided voltage; and A second generation circuit configured to output, to an output node, the larger of the divided voltage and the power supply voltage as the protection voltage, and Wherein the first generation circuit further includes: A first switch disposed between the plurality of transistors and controlled by a control signal from the internal logic circuit; A second switch disposed between a divided voltage node outputting the divided voltage and the ground node and controlled by the control signal, Wherein a state of the second switch is complementary to a state of the first switch.

2. The semiconductor device according to claim 1, Wherein the second generation circuit includes: A first P-type transistor having a first electrode, a second electrode, and a control electrode, the divided voltage is input to the first electrode, the power supply voltage is input to the control electrode, and the second electrode is coupled to the output node; And A second P-type transistor having a first electrode, a second electrode, and a control electrode, the power supply voltage is input to the first electrode, the divided voltage is input to the control electrode, and the second electrode is coupled to the output node.

3. The semiconductor device according to claim 2, Wherein the first generation circuit includes a plurality of resistors connected in series between the pad and the ground node, and a ground voltage is applied to the ground node.

4. The semiconductor device according to claim 2, Wherein the first generation circuit includes a plurality of transistors connected in series in a diode connection between the pad and a ground node to which a ground voltage is applied.

5. The semiconductor device according to claim 1, wherein the first protection circuit includes a fourth P-type transistor having a first electrode, a second electrode, and a control electrode, the first electrode being coupled to the pad, the second electrode being coupled to the control electrode of the third P-type transistor, and the protection voltage being input to the control electrode of the fourth P-type transistor.

6. The semiconductor device according to claim 5, wherein the output buffer includes: a third P-type transistor having a first electrode to which the power supply voltage is input; a fourth P-type transistor having a first electrode and a second electrode, the first electrode being coupled to the second electrode of the third P-type transistor, and the second electrode being coupled to the pad, wherein, when the protection voltage generation circuit outputs the protection voltage, the first protection circuit outputs the output signal from the internal logic circuit to the control electrode of the fourth P-type transistor, wherein the first protection circuit has an inverter operated by the protection voltage, and wherein the inverter outputs an inverted signal to the control electrode of the third P-type transistor, the inverted signal having a logic level opposite to that of the control signal from the internal logic circuit.

7. The semiconductor device according to claim 1, further comprising: an input buffer configured to drive the internal logic circuit based on an input signal input from the pad; and a second protection circuit operated by the protection voltage and configured to protect the input buffer when a voltage greater than the protection voltage is supplied to the pad.

8. The semiconductor device according to claim 7, wherein the second protection circuit includes a first N-type transistor having a first electrode, a second electrode, and a control electrode, the first electrode being coupled to the pad, the second electrode being coupled to an input node of the input buffer, and the protection voltage being input to the control electrode.

9. A semiconductor device, comprising: a pad; an internal logic circuit operated by a power supply voltage; an input buffer configured to drive the internal logic circuit based on an input signal input from the pad; an output buffer configured to drive an external circuit coupled to the pad based on an output signal from the internal logic circuit; a protection voltage generation circuit configured to output, as the protection voltage, the larger of a divided voltage and the power supply voltage, the divided voltage being obtained by dividing the voltage applied to the pad; and a protection circuit operated by the protection voltage and configured to protect the internal logic circuit when a voltage greater than the protection voltage is applied to the pad, wherein the output buffer includes a third P-type transistor having a first electrode and a second electrode, the protection voltage being input to the first electrode, and the second electrode being coupled to the pad. Among them, when the protection voltage generating circuit outputs the protection voltage, the protection circuit is configured to supply the output voltage from the internal logic circuit to the control electrode of the third P-type transistor. Among them, when the voltage greater than the protection voltage is supplied to the pad, the protection circuit supplies the voltage of the pad to the control electrode of the third P-type transistor. Among them, the protection voltage generating circuit includes: A first generating circuit, including a plurality of transistors connected in series between the pad and a ground node to which a ground voltage is applied, and the plurality of transistors are configured to output the divided voltage; and A second generating circuit, configured to output the larger of the divided voltage and the power supply voltage as the protection voltage to an output node, and Among them, the first generating circuit further includes: A first switch, arranged between the plurality of transistors and controlled by a control signal from the internal logic circuit; A second switch, arranged between the divided voltage node outputting the divided voltage and the ground node and controlled by the control signal, Among them, the state of the second switch is complementary to the state of the first switch.

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