FPGA simulation debugging system

Abstract

The present invention discloses an FPGA simulation debugging system, including at least one debugging system, each debugging system including: a control module and multiple debugging modules, and data cascading can be realized between the multiple debugging modules. The present invention can better adapt to different scenarios, especially multi-function and large-scale data debugging, reasonably allocate storage space, processing resources and transmission channels, and improve overall efficiency and performance.

Description

Technical Field

[0001] The invention relates to the field of data communication, and in particular to an FPGA simulation debugging system. Background Art

[0002] With the development of chip technology, SOC is getting bigger and bigger, its functions are getting more and more complex, and its simulation verification in the design stage is becoming more and more important. Therefore, the amount of data collected by the probe is also increasing. This requires a debugging module that can adapt to large-scale multi-module simulation verification data collection and has a large amount of storage space. The current debugging module cannot be flexibly applied to large-scale application scenarios due to limited resources. At the same time, when the probe data difference is large, the storage difference will also increase, resulting in waste of storage space and performance degradation. At the same time, the large difference in the work of the corresponding processing units will also cause uneven resources and low efficiency. Therefore, designing a debugging system that can flexibly allocate data, make full use of storage space and has high processing efficiency is a research direction in the industry. Summary of the invention

[0003] The present invention provides an FPGA simulation debugging system, which solves the problem that the storage resources of the debugging module in the prior art are limited and cannot be flexibly applied to large-scale application scenarios.

[0004] The technical solution adopted by the present invention is: an FPGA simulation debugging system includes at least one debugging system, each debugging system includes a control module and at least one debugging module;

[0005] The control module controls the simulation debugging process of the debugging system, receives the trigger conditions and trigger timings of all trigger modules set by the user, and receives data storage and transmission rules;

[0006] The debugging module interacts with the simulation verification platform according to the trigger conditions and trigger timing to implement the simulation debugging process, and uploads the collected probe data to the control module according to the set data storage and transmission rules, or stores it locally, or sends it to other debugging modules of the debugging system for storage.

[0007] Furthermore, the debugging module includes a probe data receiving submodule connected to the simulation verification platform for collecting probe data, a storage control submodule connected to the probe data receiving submodule, and a local storage submodule connected to the storage control submodule; the storage control submodules of each debugging module of the same debugging system are connected in series through a shared channel.

[0008] Further, the control module receives the trigger information sent by each debugging module according to the trigger condition and makes a judgment, notifies the debugging module to suspend debugging when it meets the user's setting, and transmits the corresponding probe data uploaded by the debugging module to the upper-level device;

[0009] When the debugging module obtains the probe data that meets the trigger condition, it sends the corresponding trigger information to the control module, and controls the clock of the verification platform to pause according to the notification of the control module.

[0010] Furthermore, the trigger condition includes the debugging module transmitting a corresponding section of probe data to the control module according to a specific signal or data in the collected probe data.

[0011] Furthermore, when there are multiple debugging systems, the control modules are connected in series through cascading sub-modules, and the control module of one debugging system serves as the main control, and the control modules of the other debugging systems serve as auxiliary controls. The user sets the trigger conditions and trigger timing of the control modules of each debugging system through the main control. The main control receives the trigger information sent by each auxiliary control according to the trigger conditions and makes a judgment. When it meets the user's settings, the main control processes the corresponding probe data uploaded by the auxiliary control and passes it to the user's corresponding terminal device.

[0012] Further, the control module includes a first data transmission submodule, an external transceiver submodule connected to the first data transmission submodule for uploading data, a first trigger submodule connected to the first data transmission submodule, a control submodule connected to the first trigger submodule and the external transceiver submodule, and a first instruction transmission management submodule connected to the control submodule.

[0013] Further, the debugging module includes a second data transmission submodule connected to the first data transmission submodule and the storage control submodule, a second trigger submodule connected to the storage control submodule and the probe data receiving submodule, and a second instruction transmission management submodule connected to the first instruction transmission management submodule and the second trigger submodule.

[0014] Furthermore, the control module processes the probe data when transmitting the probe data to the user, including compressing the probe data. The control module also includes a first data compression submodule, which is connected to the first data transmission submodule and the external transceiver submodule at the same time.

[0015] Furthermore, a second data compression submodule is provided between the storage control submodule and the second data transmission submodule.

[0016] Compared with the existing technology, this system uses a single control module to collaboratively control multiple debugging modules, which can better adapt to different scenarios, especially multi-functional and large-scale data debugging. It has data sharing and storage management functions, and reasonably allocates storage space, processing resources and transmission channels to improve overall efficiency and performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0018] Figure 1 It is a schematic block diagram of a single debugging system in the present invention.

[0019] Figure 2 It is a schematic block diagram of multiple debugging systems in the present invention. DETAILED DESCRIPTION

[0020] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0021] This application proposes an FPGA simulation debugging system, such as Figure 1 , Figure 2 As shown, the system includes at least one debugging system, and each debugging system includes a control module and at least one debugging module.

[0022] The debugging process of a single debugging system is controlled by the control module of the debugging system. The user controls the simulation debugging process of the debugging system through the control module and sets the trigger conditions and trigger timings of all trigger modules of the debugging system.

[0023] The debugging module interacts with the simulation verification platform under the control of the control module, for example, sending a clock pause signal or collecting probe data. When the user sets the debugging module to cache the probe data in advance, the debugging module stores the collected probe data locally or sends it to other debugging modules of the debugging system for storage according to the user's settings, so that data cascading can be achieved between the debugging modules. When the user sets real-time debugging, the debugging module obtains the corresponding probe data and uploads it to the control module in real time, and no local caching is performed.

[0024] When the debugging module obtains probe data that meets the trigger conditions, it sends the corresponding trigger information to the control module. The trigger information includes the trigger conditions and the trigger data. The trigger conditions include the debugging module passing the corresponding section of probe data to the control module according to the specific signal or data in the collected probe data. If only a single debugging module is triggered, the control module determines whether the trigger data meets the trigger conditions. If it does, it notifies the debugging module to send a signal to the verification platform to pause the clock of the verification platform. At the same time, the debugging module passes the corresponding section of probe data to the control module, and the control module passes it to the upper-level device, such as the main control when multiple debugging systems are cascaded, or the control terminal corresponding to the user.

[0025] When the debugging system has multiple debugging modules, the upper limit of the number of debugging modules of each debugging system is determined by the control module, and different types of debugging modules can be selected according to the debugging situation. The debugging module is responsible for collecting probe data of the verification platform, that is, debugging data.

[0026] Each debugging module has a data cascade channel (i.e., shared channel) for data, which enables high-speed transmission of collected data between debugging systems (also known as cascade boards). When the amount of data in a single debugging module is too large to be fully stored or processed locally, it can be transmitted to the debugging module of the adjacent debugging system through the data cascade high-speed channel for storage and processing.

[0027] Each control module can provide an upload channel to the user's corresponding terminal device. When the system needs to capture and transmit data in real time, multiple control modules can be cascaded to upload simultaneously to avoid the situation where the acquisition rate is greater than the upload rate.

[0028] When there are multiple debugging systems, the control module of one debugging system is used as the main control, and the control modules of other debugging systems are used as auxiliary controls. This is called control cascade, which can realize the coordinated control between different debugging systems. The user sets the trigger conditions and trigger timing of the control modules of each debugging system through the main control. The main control receives the trigger information sent by each auxiliary control according to the trigger conditions and makes a judgment. When it meets the user's settings, the corresponding probe data uploaded by the auxiliary control is processed and transmitted to the user's corresponding terminal device. The control cascade signals mainly include: reset, clock, instruction transmission, and data transmission. The debugging systems cascaded with each other are unified by one control module as the main control, and the other cascaded control modules are used as auxiliary controls. At this time, the main control can coordinate the auxiliary controls through the reset and instruction transmission channels, and the corresponding valid data can also be transmitted to the control module as the main control through the data channel for unified processing and upload. It is also possible to make multiple controls parallelly controlled. At this time, it is mainly through their respective trigger mechanisms. The control modules in the cascaded debugging system each set the trigger mechanism, and each outputs valid data when the trigger is valid. Each control module compares the trigger conditions of each other through the instruction and data channels to select the valid trigger for uploading.

[0029] In the above technical solution, all trigger conditions and specific working forms of the entire simulation debugging system are set by the user through a computer or server, that is, the control module is connected to the PC or server. The trigger process is for the user to set the trigger conditions at various levels or required by the user through the control module, including the judgment basis for the control module or the main control to finally compare and filter the trigger information. The trigger cascade between multiple debugging modules is realized through the control module, that is, after each debugging module is triggered internally, the trigger out (trigger output, i.e., trigger signal) is summarized in the control module for triggercombine detection, that is, detection is performed according to the trigger conditions and trigger timing set by the user, for example, the trigger condition set in the control module is the behavior of two debugging modules triggering at the same time or in a fixed order. That is, the system effective trigger condition is that the debugging module trigger is valid and the trigger between the debugging modules needs to meet a certain timing. When there are multiple debugging systems, the cascade principle between them is the same, and is realized through the trigger out and trigger in of the cascade submodule of the control module (interconnected input and output).

[0030] It can be seen from the above technical solution that the user can set two mechanisms for data storage and transmission through the control module, one is a trigger type and the other is a periodic type.

[0031] There are two types of triggering. One is that the debugging module triggers alone. When the user can complete the task with one debugging module, it is only necessary to set the trigger conditions in the debugging module, that is, the probe data triggers the detection directly in the debugging module, and the data or trigger information that meets the trigger conditions is saved locally or uploaded to the control module (whether it is stored locally or uploaded to the control module is controlled or set by the user through the control module). When multiple debugging modules are used to collect probe data, it may be necessary to integrate all data for trigger detection. At this time, the data or trigger out of each debugging module needs to be summarized in the control module for trigger detection.

[0032] The periodic type is mainly for users to configure the system to collect data within a fixed period.

[0033] If the present invention is used to trigger acquisition of a system with larger functions, and a single debugging system does not meet the requirements, then by connecting the cascade interfaces of the cascade submodules DM_cascade of two debugging systems, when one of the debugging systems meets the trigger condition, in addition to sending a trigger out signal to the debugging module of the debugging system itself, a trigger out signal will also be sent to the adjacent debugging system, thereby realizing cascade collaboration of multiple debugging systems.

[0034] Since the debugging module of each debugging system of the present invention can adopt one debugging module or two or more debugging modules cooperating with each other, and there can be multiple debugging systems at the same time, the number of debugging modules of a single debugging system does not need to be set too much, so that the complexity of a single debugging system is reduced, and the debugging systems using the same type of debugging chips (DebugFpga chips) are all the same, which reduces the difficulty of development, and reduces the difficulty of production and the difficulty and cost of later maintenance. The present invention connects several debugging modules to the control module at the same time to increase the maximum data collection amount and improve the storage space, so as to better adapt to different scenarios, especially multi-functional large-scale data debugging, and there is a data sharing channel between adjacent debugging modules, so that the collected data can be flexibly allocated for storage and processing between modules through this shared channel, so as to achieve the purpose of reasonably and fully utilizing the storage space and hardware processing resources in the system to improve the processing efficiency.

[0035] Specifically, the control module includes a first data transmission submodule, an external transceiver submodule, a first trigger submodule, a control submodule, a first instruction transmission management submodule and a cascade submodule, wherein the first data transmission submodule is connected to all debugging modules to receive data transmitted in the debugging modules, and the first data transmission submodule is connected to the external transceiver submodule, so that the control module processes these data and uploads them through the external transceiver submodule and controls the submodule to receive instruction data from users of the external transceiver module; at the same time, the first data transmission submodule is also connected to the first trigger submodule, and the control module sets the trigger condition of the first trigger submodule. When the data meets the trigger condition, the first trigger submodule sends a trigger signal.

[0036] The first instruction transmission management submodule is connected to the control submodule and is used to transmit configuration and control instructions to the debugging module. When a user instruction is transmitted or a valid trigger occurs locally, the control module sends an instruction to the debugging module via the first transmission management submodule.

[0037] Furthermore, the control submodule is connected to the cascade submodule, and every two debug systems can be cascaded through the cascade submodule. The control module in one debug system serves as the main control module, and the control submodule uniformly performs instruction transmission, coordination and distribution control.

[0038] Furthermore, the control module also includes a first data compression submodule, which is connected to the first data transmission submodule and the external transceiver submodule at the same time. When the amount of data is large, in order to avoid the upload speed of the control module limiting the sorting performance, the data will be compressed at this time, and then compressed by the external transceiver submodule and uploaded to the upper level (PC, etc.) through the transmission channel, and finally converted into a corresponding waveform through graphical processing.

[0039] The control module configures different trigger conditions for the debugging modules respectively through the above-mentioned first instruction transmission management submodule. Each debugging module collects data according to its own trigger information. When a valid trigger is obtained, the trigger information will be transmitted to the control module. The control module performs trigger combine detection. After the set trigger condition is met, the trigger signal is output and returned to the debugging module, and the FPGA used to control the overall clock in the control simulation verification platform is controlled to pause the debugging process; another method is that the control module uniformly performs trigger condition detection on the collected trigger data. After the set trigger detection condition is met, the control module outputs a trigger signal and returns to the debugging module, and the control verification platform pauses the clock.

[0040] The debugging module includes a second data transmission submodule, a storage control submodule, a local storage submodule, a second trigger submodule, a probe data receiving submodule, an instruction transmission management submodule and an instruction output submodule, wherein the probe data receiving submodule is responsible for collecting probe data of the IC simulation verification process; the probe data receiving submodule is connected to the storage control submodule, and the probe data receiving submodule is connected to the local storage submodule to allocate and store the collected data.

[0041] The probe data receiving submodule is connected to the storage control submodule, and the collected probe data is handed over to the storage control submodule for distribution, storage or direct transmission. The storage control submodule is respectively connected to the shared channel module, the local storage submodule, and the second data transmission submodule, so that the storage control submodule can share the probe data with the adjacent debugging module or store it locally or upload it directly to the control module. The storage management submodule can also read data from the local storage submodule and the shared channel module and upload it to the third data transmission module, and further transmit it to the control module for processing. Several debugging modules are connected in series through a shared channel for data cascading, so that the local storage submodule can also be handed over to the shared channel for transmission to the adjacent debugging module, and the storage management submodule in the adjacent debugging module will distribute it. This method can realize the sharing of storage resources and the sharing of processing function unit performance.

[0042] The two debugging systems (Debug systems) can cascade data between the debugging modules on both sides through a shared channel, which greatly expands the storage capacity and allocation flexibility of data. The direction of data transmission by the debugging module is mainly determined and processed by the storage management module. The three directions of data transmission are: local storage, upload to the control module (also called Ctrl module), and transmission to the adjacent debugging module (also called Debug module) through a shared channel. The user sets direct reading or pre-storage, which is controlled by storage management. When the storage space of other objects is not enough, the Debug system suspends the simulation verification platform and transmits storage usage information to the user. The local storage space determines whether the local storage is sufficient by writing memory address information.

[0043] The second instruction transmission management submodule is connected to the second trigger submodule so that the user can set the trigger condition of the second trigger submodule by issuing instructions through the control module. And the first instruction transmission management submodule in the control module is connected to the second instruction transmission management submodule in each debugging module so that the debugging module can receive instructions sent from the control module.

[0044] Furthermore, a second data compression submodule (not shown in the figure) may be provided between the storage control submodule and the second data transmission submodule to compress the data and improve the data upload speed.

[0045] Based on the above debugging system (Debug system), there are trigger sub-modules in the control module and the debugging module, and each trigger sub-module contains trigger input and output interfaces for trigger cascading. The trigger interface of the control module can be used for inter-system cascading (i.e. cascading between Debug systems), and the debugging module is used for internal trigger cascading with the control module. The trigger conditions are uniformly configured by the control module.

[0046] This application has multiple trigger mechanisms, which are suitable for different application scenarios, namely: Multi triggercombine (the control module integrates multiple Debug trigger signals) and multi data Trigger detection (the control module integrates multiple Debug data for trigger detection).

[0047] In a scenario where a user uses multiple debugging modules, for Multi trigger combine, the trigger output signal of each debugging module is aggregated into the control module for detection. When the set trigger detection conditions are met, the control module sends an instruction to the debugging module through the instruction transmission module, and then the instruction output submodule of the debugging module outputs it to the simulation verification platform, which controls the simulation verification platform to perform operations such as clock pause or probe configuration (applied to single-step debugging).

[0048] For multi FPGA data trigger detect, the control module integrates the data of multiple debugging modules for unified trigger detection. When the trigger condition is met, the control module pauses the simulation verification platform clock through the control channel. The data can be uniformly transmitted to the control module for trigger detection. After the set trigger detection conditions are met, the control module controls the verification platform to pause the clock through the control channel.

[0049] When one debug system cannot meet the user's usage requirements, the cascade submodules in the two debug systems are connected. The cascade submodules contain trigger input and output signals, and the master-slave mode is used for cascade control, that is, one control module is the main control module, and the other control module is the auxiliary control module. At this time, the master control module can control and coordinate the slave control module through the reset and instruction transmission channel. When one of the debug systems meets the trigger condition, its master control module will send a trigger output signal to the debug module of the system and also send a trigger signal to the adjacent debug system to achieve multi-system cascade collaboration; the corresponding valid data in the two debug systems can also be transmitted to the main control module through the data channel (shared channel) for unified processing and upload, which can realize high-speed transmission of collected data between debug systems. When the data volume of a single debug system is too large to be completely stored or processed locally, it can be transmitted to the adjacent debug system through the shared channel for storage and processing. Each debug system provides an upload channel. When the system needs to capture and transmit data in real time, it can be cascaded to achieve simultaneous upload of multiple debug systems to avoid the situation where the acquisition rate is greater than the upload rate.

[0050] In other embodiments, multiple controls can also be controlled in parallel. In this case, the control modules each set a trigger mechanism mainly through their own trigger mechanism, and each outputs valid data when the trigger is valid. Each control module compares each other's trigger conditions through the instruction and data channel to select the valid trigger for uploading.

[0051] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. An FPGA simulation debugging system, characterized in that: It includes a plurality of debugging systems, each of which includes a control module and at least one debugging module; The control module controls the simulation debugging process of the debugging system, receives the trigger conditions and trigger timings of all trigger modules set by the user, and receives data storage and transmission rules; The debugging module interacts with the simulation verification platform according to the trigger conditions and trigger timing to implement the simulation debugging process, and uploads the collected probe data to the control module according to the set data storage and transmission rules, or stores it locally, or sends it to other debugging modules of the debugging system for storage; The control modules are connected in series through cascading sub-modules, and the control module of one debugging system serves as the main control, and the control modules of the other debugging systems serve as auxiliary controls. The user sets the trigger conditions and trigger timings of the control modules of each debugging system through the main control, and the main control receives the trigger information sent by each auxiliary control according to the trigger conditions and makes a judgment. When it meets the user's settings, the corresponding probe data uploaded by the auxiliary control is processed and transmitted to the user's corresponding terminal device.

2. The FPGA simulation debugging system according to claim 1, characterized in that: The debugging module includes a probe data receiving submodule connected to the simulation verification platform for collecting probe data, a storage control submodule connected to the probe data receiving submodule, and a local storage submodule connected to the storage control submodule; the storage control submodules of each debugging module of the same debugging system are connected in series through a shared channel.

3. The FPGA simulation debugging system according to claim 1, characterized in that: The control module receives the trigger information sent by each debugging module according to the trigger condition and makes a judgment, notifies the debugging module to suspend debugging when it meets the user's setting, and transmits the corresponding probe data uploaded by the debugging module to the upper-level device; When the debugging module obtains the probe data that meets the trigger condition, it sends the corresponding trigger information to the control module, and controls the clock of the verification platform to pause according to the notification of the control module.

4. The FPGA simulation debugging system according to claim 1, characterized in that: The trigger condition includes the debugging module transmitting a corresponding section of probe data to the control module according to a specific signal or data in the collected probe data.

5. The FPGA simulation debugging system according to any one of claims 1 to 4, characterized in that: The control module includes a first data transmission submodule, an external transceiver submodule connected to the first data transmission submodule for uploading data, a first trigger submodule connected to the first data transmission submodule, a control submodule connected to the first trigger submodule and the external transceiver submodule, and a first instruction transmission management submodule connected to the control submodule.

6. The FPGA simulation debugging system as claimed in claim 5, characterized in that: The debugging module includes a second data transmission submodule connected to the first data transmission submodule and the storage control submodule, a second trigger submodule connected to the storage control submodule and the probe data receiving submodule, and a second instruction transmission management submodule connected to the first instruction transmission management submodule and the second trigger submodule.

7. The FPGA simulation debugging system as claimed in claim 6, characterized in that: The control module processes the probe data when transmitting the probe data to the user, including compressing the probe data. The control module also includes a first data compression submodule, which is connected to the first data transmission submodule and the external transceiver submodule at the same time.

8. The FPGA simulation debugging system as claimed in claim 6, characterized in that: A second data compression submodule is also provided between the storage control submodule and the second data transmission submodule.

Images