Semiconductor substrate and method for forming embedded substrate

Abstract

The present invention provides a semiconductor substrate, comprising: an open area; a first buried area in which a chip is buried and surrounded by the open area; a plurality of first conductive pillars, which penetrate the open area and are arranged around the first buried area; and conductive wires, wherein the plurality of first conductive pillars are connected in series through the conductive wires to form a needle-wire structure surrounding the first buried area. The present invention provides a method for forming a buried substrate in another aspect. The purpose of the present invention is to at least improve the strength of the semiconductor substrate.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor substrate and a method for forming an embedded substrate. Background Art

[0002] In an embedded substrate, the thermal expansion coefficients of the filling material and the semiconductor unit (eg, chip) in the substrate are quite different (eg, the thermal expansion coefficient of the filling material is 25-40; the thermal expansion coefficient of the semiconductor unit is 12-15), which can easily cause the substrate to warp.

[0003] When forming a semiconductor packaging structure, the warping of the substrate will affect its subsequent processes. For example, the subsequent fan-out structure cannot be aligned with the active device in the substrate, and there is an offset between the two layers, which reduces the product yield. Summary of the invention

[0004] In view of the problems existing in the related art, an object of the present invention is to provide a semiconductor substrate and a method for forming a buried substrate, so as to at least improve the strength of the semiconductor substrate.

[0005] To achieve the above-mentioned objectives, the present invention provides a semiconductor substrate, comprising: an empty area; a first buried area in which a chip is buried and surrounded by the empty area; a plurality of first conductive pillars, which penetrate the empty area and are arranged around the first buried area; and conductive wires, wherein the plurality of first conductive pillars are connected in series through the conductive wires to form a needle-wire structure surrounding the first buried area.

[0006] According to an embodiment of the present invention, the semiconductor substrate includes a plurality of first buried regions arranged in an array, and each of the first buried regions is surrounded by a corresponding stitch structure.

[0007] According to an embodiment of the present invention, the conductive wires include: a first group of connecting wires and a second group of connecting wires, which are respectively located on the upper surface and the lower surface of the open area and aligned with each other in the longitudinal direction, the first group of connecting wires connects the upper ends of multiple first conductive pillars in series, and the second group of connecting wires connects the lower ends of multiple first conductive pillars in series.

[0008] According to an embodiment of the present invention, the shape formed by the stitch structure is the same as the shape of the first embedded area.

[0009] According to an embodiment of the present invention, a plurality of first conductive pillars are arranged around the first buried region at the same intervals.

[0010] According to an embodiment of the present invention, the outer circumference of each first conductive pillar is spaced apart from the first buried region.

[0011] According to an embodiment of the present invention, bonding pads are disposed at the upper end and the lower end of each first conductive column.

[0012] According to an embodiment of the present invention, the upper surface of the bonding pad at the upper end of the first conductive pillar is lower than the top surface of the sealing layer covering the chip in the first buried area, and is higher than the top surface of the open area.

[0013] According to an embodiment of the present invention, it further includes a plurality of second conductive pillars spaced apart from the chip, wherein the second conductive pillars penetrate through the sealing layer covering the chip in the first buried region.

[0014] According to an embodiment of the present invention, the number of the plurality of second conductive pillars is 5, 4 of which are respectively arranged at the corners of four sides of the first buried region, and the fifth is arranged at the center of the first buried region.

[0015] According to an embodiment of the present invention, upper and lower ends of each second conductive column are respectively provided with bonding pads located on the upper surface and the lower surface of the sealing layer.

[0016] According to an embodiment of the present invention, a thermal expansion coefficient of the first embedded region is not greater than 20.

[0017] According to an embodiment of the present invention, a double-layer conductive block is embedded in the empty area, and the double-layer conductive block is arranged around the needle and line structure.

[0018] According to an embodiment of the present invention, a redistribution structure is disposed above the open area and the first buried area, and the redistribution structure is electrically connected to the chip in the first buried area.

[0019] According to an embodiment of the present invention, it further includes: a trace structure located below the open area and the first buried area, and the trace structure electrically connects the chip in the first buried area.

[0020] On the other hand, an embodiment of the present invention provides a method for forming an embedded substrate, comprising: forming a plurality of needle-wire structures arranged in a ring shape in a resin core layer; forming a through opening in an area surrounded by each needle-wire structure; filling a chip and a sealing layer covering the chip in each through opening to form a plurality of embedded areas, wherein each needle-wire structure comprises a conductive wire and a plurality of first conductive pillars penetrating the resin core layer, and the plurality of first conductive pillars are connected in series through the conductive wire.

[0021] According to an embodiment of the present invention, after forming a plurality of buried regions, a plurality of second conductive pillars separated from the chip are formed in the sealing layer in each buried region.

[0022] According to an embodiment of the present invention, an upper bonding pad and a lower bonding pad are formed at the upper end and the lower end of each second conductive column, respectively. The upper bonding pad and the lower bonding pad are located on the upper surface and the lower surface of the sealing layer, respectively.

[0023] According to an embodiment of the present invention, before forming a plurality of needle and wire structures, a plurality of double-layer copper blocks are formed in the resin core layer, and when forming a through opening, the double-layer copper blocks located within the area surrounded by each needle and wire structure are removed, and the double-layer copper blocks located outside the surrounded area are retained.

[0024] According to an embodiment of the present invention, the hole opened when forming the first conductive pillar is formed by mechanical drilling.

[0025] According to an embodiment of the present invention, the embedded areas correspond to the needle and thread structures one by one, and one needle and thread structure surrounds one embedded area.

[0026] The beneficial technical effects of the present invention are:

[0027] The present application solves the warping problem of the semiconductor substrate and improves the strength of the semiconductor substrate by using a needle-wire structure to surround the empty area in which the chip is embedded. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 8 A process diagram of forming a semiconductor substrate according to an embodiment of the present application is shown, wherein: Figures 1 to 6A , Figures 7 and 8 is a cross-sectional view, Figure 6B This is a top view.

[0029] Fig. 9 A cross-sectional view of a semiconductor substrate according to another embodiment of the present application is shown.

[0030] Fig.10 A top view of a semiconductor substrate according to an embodiment of the present application is shown, wherein a plurality of buried regions are shown.

[0031] Fig.11 A top view of a semiconductor substrate according to an embodiment of the present application is shown, wherein a single buried region is shown.

[0032] Figure 12 to Figure 14 A cross-sectional view showing a process of connecting a semiconductor substrate to a fan-out structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to better understand the spirit of the embodiments of the present application, some preferred embodiments of the present application are further described below.

[0034] The embodiments of the present application will be described in detail below. In the full text of the present application specification, the same or similar components and components with the same or similar functions are represented by similar reference numerals. The embodiments of the accompanying drawings described herein are illustrative, graphical, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be interpreted as limiting the present application.

[0035] As used herein, the terms "substantially," "substantially," "essentially," and "about" are used to describe and illustrate small variations. When used in conjunction with an event or circumstance, the terms may refer to instances where the event or circumstance occurred exactly as well as instances where the event or circumstance occurred very approximately. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two values ​​may be considered “substantially” the same if the difference between them is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%).

[0036] In this specification, unless otherwise specified or limited, relative terms such as "central", "longitudinal", "lateral", "front", "rear", "right", "left", "inner", "outer", "lower", "higher", "horizontal", "vertical", "above", "below", "above", "below", "top", "bottom" and their derivative terms (such as "horizontally", "downwardly", "upwardly", etc.) should be interpreted as referring to the directions described in the discussion or depicted in the drawings. These relative terms are only used for convenience of description and do not require that the present application be constructed or operated in a specific direction.

[0037] In addition, sometimes amounts, ratios and other numerical values ​​are presented in range format herein. It should be understood that such range format is for convenience and brevity, and should be flexibly understood to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or sub-ranges encompassed within the range, as if each numerical value and sub-range were explicitly specified.

[0038] Furthermore, for ease of description, “first”, “second”, “third”, etc. may be used herein to distinguish different components in one figure or a series of figures. “First”, “second”, “third”, etc. are not intended to describe the corresponding components.

[0039] See also Figure 1 and Figure 2 A resin core layer 11 is provided, and conductive blocks 108 are arranged on the upper and lower surfaces of the resin core layer 11. In an embodiment, the conductive blocks 108 are copper blocks electroplated on the resin core layer 11, and the thickness of the conductive blocks 108 is 50 μm.

[0040] See also Figure 3 , the conductive block 108 is patterned. The patterning step preliminarily defines the buried area 20 and the open area 10 surrounding the buried area 20. In an embodiment, the buried area 20 will be embedded with a chip 12, and there is no active device in the open area 10. The use of the conductive block 108 enhances the strength of the open area 10.

[0041] See also Figure 4 , a lamination step is performed using additional material for forming the resin core layer 11 and a conductive material 109 for forming the conductive block 108 , wherein the resin core layer 11 is filled around the conductive block 108 .

[0042] See also Figure 5 Holes are drilled in the conductive material 109, the resin core layer 11, and the conductive block 108, and filled with additional conductive material 109 to form the first conductive column 14. The conductive material 109 on the upper and lower surfaces of the resin core layer 11 is patterned to form bonding pads 161 and 162 located at the upper and lower ends of the first conductive column 14, respectively.

[0043] See also Fig. 6A and Figure 6B , Figure 6B FIG. 1 is a top view, in which the area surrounded by the first conductive pillar 161 is hollowed out to form a through opening 13. Fig. 6A Only two adjacent conductive pillars 14 and the through openings 13 they surround are shown. Figure 6B A plurality of through openings 13 surrounded by a plurality of stitch structures 18 including conductive pillars 14 are shown.

[0044] See also Figure 7 , the chip 12 is placed in the through opening 13 , and the through opening 13 is filled with a sealing layer 22 .

[0045] See also Figure 8, an opening is formed in the sealing layer 22 around the chip 12, and a conductive material is filled to form a second conductive column 24 located in the sealing layer. The conductive material can be arranged on the upper and lower surfaces of the sealing layer 22, and further patterned to form bonding pads 261 and 262 located at the upper and lower ends of the second conductive column, respectively, to form the semiconductor substrate 100 of the present application, wherein the semiconductor substrate 100 is an embedded substrate. In an embodiment, the conductive material used for the second conductive column 24 and the bonding pads 261 and 262 is copper, and its thermal expansion coefficient is about 16.5. Before adding the second conductive column 24 and the bonding pads 261 and 262, the thermal expansion coefficient of the embedded area 20 is about 20-25. By adding the second conductive column 24 and the bonding pads 261 and 262, the thermal expansion coefficient of the entire embedded area 20 can be adjusted to less than 20. By adjusting the thermal expansion coefficient of the embedded area 20, and using the needle-wire structure 18 and the conductive block 108, the overall warping of the semiconductor substrate 100 can be controlled to be less than 1 mm.

[0046] See also Fig. 9 , shows a semiconductor substrate 900 according to another embodiment of the present application, wherein the sealing layer 22 is also located below the chip 12 .

[0047] Fig.10 and Fig.11 1 shows a top view of a semiconductor substrate 100 according to an embodiment of the present application, wherein: Fig.10 A top view including a plurality of buried regions 20 is shown, Fig.11 A partial view of the semiconductor substrate 100 is shown, in which only a single buried region 20 is shown. By using the pin-wire structure 18 to surround the empty region 10, the empty region 10 is fixed, thereby reducing the warpage problem of the semiconductor substrate 100. In an embodiment, the buried region 20 occupies an area of ​​about 1 / 3 of the entire semiconductor substrate 100.

[0048] See also Fig.12 , providing a redistribution structure 103 and an adhesive layer 104 located on the bottom surface of the redistribution structure 103.

[0049] See also Fig.13 The redistribution structure 103 is bonded to the Fig. 9 The adhesive layer 104 covers the buried region 20 and the open region 10.

[0050] See also Fig.14 The redistribution structure 103 is electrically connected to the semiconductor substrate 900 using a through hole 105 . The redistribution structure 103 is a fan-out structure. In an embodiment, the through hole is electrically connected to the second conductive pillar 24 of the buried region 20 .

[0051] The present invention provides a semiconductor substrate 100, comprising: an empty area 10; a first buried area 20 in which a chip 12 is buried and surrounded by the empty area 10; a plurality of first conductive pillars 14, which penetrate the empty area 10 and are arranged around the first buried area 20; and a conductive line 15, wherein the plurality of first conductive pillars 14 are connected in series through the conductive line 15 to form a needle-wire structure 18 surrounding the first buried area 20. In an embodiment, the semiconductor substrate 100 comprises a plurality of first buried areas 20 arranged in an array, and each first buried area 20 is respectively surrounded by a corresponding needle-wire structure 18. In an embodiment, the conductive line 15 comprises: a first group of connecting wires 151 and a second group of connecting wires, which are respectively located on the upper surface and the lower surface of the empty area 10 and are aligned with each other in the longitudinal direction, the first group of connecting wires 151 connects the upper ends of the plurality of first conductive pillars 14 in series, and the second group of connecting wires connects the lower ends of the plurality of first conductive pillars 14 in series. In an embodiment, the shape formed by the needle-wire structure 18 is the same as the shape of the first buried area 20. In an embodiment, a plurality of first conductive pillars 14 are arranged around the first buried area 20 in the same spacing manner, that is, the spacing between two adjacent first conductive pillars 14 connected by the conductive line 15 is constant. In an embodiment, the outer peripheral surface of each first conductive pillar 14 is spaced apart from the first buried area 20. In an embodiment, bonding pads 161 and 162 are respectively provided at the upper end and the lower end of each first conductive pillar 14. In an embodiment, the upper surface of the bonding pad 161 at the upper end of the first conductive pillar 14 is lower than the top surface of the sealing layer 22 covering the chip 12 in the first buried area 20, and is higher than the top surface of the open area 10. In an embodiment, a plurality of second conductive pillars 24 spaced apart from the chip 12 are further included, and the second conductive pillars 24 penetrate the sealing layer 22 covering the chip 12 in the first buried area 20. In an embodiment, the number of the plurality of second conductive pillars 24 is 5, of which 4 are respectively arranged at the four corners of the first buried area 20, and the fifth second conductive pillar 24 is arranged in the center of the first buried area 20. In the embodiment, the upper and lower ends of each second conductive column 20 are respectively provided with bonding pads 261 and 262 located on the upper surface and the lower surface of the sealing glue layer 22. In the embodiment, the thermal expansion coefficient of the first buried area 20 is not greater than 20. In the embodiment, a double-layer conductive block 108 is embedded in the empty area 10, and the double-layer conductive block 108 is arranged around the needle-line structure. In the embodiment, a redistribution structure 103 is also included, which is arranged above the empty area 10 and the first buried area 20, and the redistribution structure 103 is electrically connected to the chip 12 in the first buried area 20. In the embodiment, a trace structure is also included, which is located below the empty area 10 and the first buried area 20, and the trace structure is electrically connected to the chip 12 in the first buried area 20.

[0052] On the other hand, an embodiment of the present invention provides a method for forming an embedded substrate, comprising: forming a plurality of loop-arranged needle and wire structures 18 in a resin core layer 11; forming a through opening 13 in an area surrounded by each needle and wire structure 18; filling a chip 12 and a sealing layer 22 covering the chip 12 in each through opening 13 to form a plurality of embedded areas 20, wherein each needle and wire structure 18 comprises a conductive wire 15 and a plurality of first conductive pillars 14 penetrating the resin core layer, and the plurality of first conductive pillars 14 are connected in series through the conductive wire 15. In an embodiment, after forming the plurality of embedded areas 20, a plurality of second conductive pillars 24 separated from the chip 12 are formed in the sealing layer 22 in each embedded area 20. In an embodiment, an upper bonding pad 261 and a lower bonding pad 262 are formed at the upper end and the lower end of each second conductive pillar 24, respectively, and the upper bonding pad and the lower bonding pad are located on the upper surface and the lower surface of the sealing layer 22, respectively. In an embodiment, before forming a plurality of needle and wire structures 18, a plurality of double-layer copper blocks 108 are formed in the resin core layer 11. When forming the through opening 13, the double-layer copper blocks 108 located within the area surrounded by each needle and wire structure 18 are removed, and the double-layer copper blocks 108 located outside the surrounded area are retained. In an embodiment, the holes opened when forming the first conductive column 14 are formed by mechanical drilling. In an embodiment, the embedded area 20 corresponds to the needle and wire structure 18 one by one, and one needle and wire structure 18 surrounds one embedded area 20.

[0053] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor substrate, characterized in that: include: The open area is embedded with conductive blocks; A first embedded area in which a chip is embedded, surrounded by the open area, wherein the first embedded area has a through opening and a sealing layer located in the through opening for covering the chip; A plurality of first conductive pillars, penetrating the open area and the conductive block, wherein the plurality of first conductive pillars are arranged around the first buried area; as well as A conductive line, through which the plurality of first conductive pillars are connected in series to form a needle-line structure surrounding the first buried area; The sealing layer passes through the through opening and is surrounded by the needle-wire structure, and the top surface of the sealing layer is higher than the upper surface of the first conductive column in the needle-wire structure.

2. The semiconductor substrate according to claim 1, characterized in that The semiconductor substrate includes a plurality of the first buried regions arranged in an array, and each of the first buried regions is surrounded by a corresponding stitch structure.

3. The semiconductor substrate according to claim 1, characterized in that The conductive wire comprises: The first group of connection lines and the second group of connection lines are respectively located on the upper surface and the lower surface of the open area and are aligned with each other in the longitudinal direction. The first group of connection lines connects the upper ends of the plurality of first conductive pillars in series, and the second group of connection lines connects the lower ends of the plurality of first conductive pillars in series.

4. The semiconductor substrate according to claim 1, characterized in that An outer peripheral surface of each of the first conductive pillars is spaced apart from the first buried region.

5. The semiconductor substrate according to claim 3, characterized in that The empty area is embedded with double layers of the conductive blocks, A bonding pad is disposed at the upper end and the lower end of each of the first conductive pillars, and each of the first conductive pillars penetrates through the double-layer conductive blocks.

6. The semiconductor substrate according to claim 1, wherein Also includes: A plurality of second conductive pillars are spaced apart from the chip, wherein the second conductive pillars penetrate through a sealing layer in the first buried area that covers the chip.

7. The semiconductor substrate according to claim 1, characterized in that Also includes: A redistribution structure is disposed above the open area and the first buried area, and the redistribution structure is electrically connected to the chip in the first buried area.

8. The semiconductor substrate according to claim 1, wherein Also includes: A trace structure is located below the open area and the first buried area, and the trace structure is electrically connected to the chip in the first buried area.

9. A method for forming a buried substrate, characterized in that: include: forming a plurality of loop-shaped needle and wire structures in the resin core layer, and forming a plurality of embedded conductive blocks; forming a through opening in the area surrounded by each of the stitch structures; Filling each through opening with a chip and a sealing layer covering the chip to form a plurality of buried areas, Wherein, each of the needle-wire structures comprises a conductive wire and a plurality of first conductive posts penetrating the resin core layer and the conductive block, and the plurality of first conductive posts are connected in series through the conductive wire; The sealing layer passes through the through opening, and the top surface of the sealing layer is higher than the upper surface of the first conductive column in the needle-wire structure.

10. The method for forming a buried substrate according to claim 9, characterized in that: After forming the plurality of buried regions, a plurality of second conductive pillars separated from the chip are formed in the sealing layer in each of the buried regions.

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